201019068 九、發明說明： 、 【發明所屬之技術領域】 本發縣有-槪善鱗目雜 法 裝置.，特別是提胃PFC的效率同時 之控财法與 界常用的CRM/CCM兩種PFC 功率輸出，以解決業201019068 Nine, invention description: [Technical field of invention] This county has a 槪 鳞 鳞 杂 杂 . . , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Power output to solve the industry
在-定負載以下也能與種的優f達到麗 大功率的輪出。 樣的巧效率又可以有CCMPFC 【先前技術】 ❹ 由於切換式電源產品的普及化，同時因保 於切換式鶴W雜要求加裝轉时= 來越高’因此PFC身為電源供應器的-部份 ^ ι的效率，而且效率的要求也不同於以往只看 目^上的負載都要能達到侧電源產品的 HZ PFC為邊界操作模式，具有簡單效率高的優點，夂不 的問題。(:麵為連續導通操作模式，具有大功率輸Under the fixed load, the superiority of the species can also be achieved. CCMPFC [Previous Technology] ❹ Due to the popularization of switching power supply products, and because of the need to switch to the crane type, the higher the speed is, the higher the 'PFC is the power supply'. Part of the efficiency of the ι, and the efficiency requirements are different from the HZ PFC that can only achieve the side power supply product as the boundary operation mode. It has the advantages of simple efficiency and high efficiency. (: The surface is in continuous conduction mode with high power loss
一定負載以下效率都會偏低，目前的PFC控制IC不是CRM就是CCM 的控制方式，無法兩著兼顧，以下將介紹目前pFC相闞控制器所 使用之習知技術。 第1圖為習知技術之臨界模式CRMpfc的電感電流之波形圖。 從電流波形可以明白了解，CRM PFC的開關驅動信號在電感電流達 到零的瞬間主開關工作接近零電壓時才開，這樣的工作方式可以 令主開關工作接近零電壓(ZVS)與零電流(ZCS)切換，使得CRM PFC的效率較CCMPFC的效率高，開關關閉的點由内部的控制信號 與電感電流相同時才關閉，所以CRM PFC在工作時，隨著輸入電 壓以及輸出負載的變動開關驅動信號會依據輸出電壓以及輸出負 201019068 載的變動進行控制，也因此關驅動信號會改變扁盘 期’所以當負載越來越大時’輸入電感電流會越 ’驅 ^ 頻率會越來越低，所以如果要設計更大的輸 ° *3 ^ CRM ρρί 從第技術定頻模式CCMPFC的典型電感電流波形。 從第2圖中明白的說明CCM PFC的電感電流操作在連續模式The efficiency below a certain load will be low. The current PFC control IC is not a CRM or CCM control method. It cannot be considered at the same time. The following describes the conventional techniques used by the current pFC phase-lock controller. Figure 1 is a waveform diagram of the inductor current of the critical mode CRMpfc of the prior art. It can be understood from the current waveform that the switch drive signal of the CRM PFC is turned on when the main switch operates close to zero voltage at the moment when the inductor current reaches zero. This mode of operation can make the main switch work close to zero voltage (ZVS) and zero current (ZCS). Switching, the efficiency of the CRM PFC is higher than that of the CCMPFC. The switch is turned off when the internal control signal is the same as the inductor current. Therefore, when the CRM PFC is working, the switch drive signal changes with the input voltage and the output load. It will be controlled according to the output voltage and the change of the output negative 201019068, and therefore the drive signal will change the flat panel period. So when the load is getting larger, the input inductor current will be lower and the frequency will be lower and lower. If you want to design a larger input ° *3 ^ CRM ρρί from the technical constant frequency mode CCMPFC typical inductor current waveform. The inductor current operation of the CCM PFC is explained in Figure 2 in continuous mode.
感的電流漣波較CRMPFC之電感電流漣波小數倍，作是相針 PFC的主_會工作在硬切換的開關模式，效率相= 的效率低。由於CCM PFC是以固㈣率方式操作，如第4 型應用電路中，可以看出一般CCM PFC之工作頻率由控制ic外部 零件設定其工作頻率’不因輸入電愿與負載變動而改變，有部份 市售1C為内建固定頻率或加入少許擾頻以降低EMI干擾因為其 工作頻率與輸入電壓與負载變動無關，因此相對於CRM PFC ϋ 電壓切換的特性下，其效率相對較低，但是在大功率輸出時設計 上較簡單ΕΜΙ干擾也較低。 第5圖為CRM狀態時序圖。第5圖（Α)為Ζα)信號波形圖。 心可取自PFC上M0SFET之Vds，也可取自PFC抗流線圈（ch〇ke) ❹上之輔助繞組作為ZCD之信號。此信號自高電位至低電位有一衰 減期，1為零電流控制點。第5圖（B)為pFC之凝動信號％波形 圖。ZCD自低電位至高電位時〜自高電位至低電位，但ZCD自高 電位至低電位時須ZCD衰減至〇，然後Vgs才自低電位至高電位。 因驅動信號Vgs之頻率受ZCD衰減速度之影響，故剛好可使pfc之 主開關工作在零電塵(ZVS)零電流(ZCS)切換。第5圖（C)IZCD 檢知器之輸出信號波形圖。此輸出信號於ZCD衰減至零電流控制 點Vz時自高電位至低電位。 第6圖為CCM狀態時序圖。第6圖（A)為PFC之驅動信號Vgs 波形圖。因驅動信號Vgs之頻率為固定頻率，故第6圖（B) pfc之 201019068 之ί信號為落後PFC之驅動信號Vgs。第6圖（C) 為PFC之振於之波形圖。最高電位等於^ 圏（C) ΐΐϊϋί ’目前業界所湖之方式多為跳壓的方ϊ 無更好的解決方法，對於切換#雷浪相ϋ工> Ο 又不增加成本，是非常難的換式電雜應器而s，^輕載效率 理，先前技術之缺點，提出一種簡單且設計合 控制的優點=ΐ^ϊί’。且有效改善上述缺失結合兩㈣ 【發明内容】 ,· . 4 明ί目的在提供一種結合CRM以及CCM兩種PFC控制方 ^的，Γ點之PFC控制方法與裝置，藉由控制CRM PFC之控制方式The sensed current ripple is a few times smaller than the CRMPFC's inductor current ripple. As the phase pin PFC, the main _ will work in the hard-switching mode, and the efficiency phase = low efficiency. Since the CCM PFC operates in a solid (four) rate mode, as in the Type 4 application circuit, it can be seen that the operating frequency of the general CCM PFC is set by the control ic external part whose operating frequency is not changed by the input power and load variation. Some commercially available 1Cs are built-in fixed frequencies or add a little scramble to reduce EMI interference because their operating frequency is independent of input voltage and load variation, so the efficiency is relatively low compared to CRM PFC ϋ voltage switching characteristics, but The design is simpler and the interference is lower at high power output. Figure 5 is a CRM status timing diagram. Figure 5 (Α) is a signal waveform of Ζα). The heart can be taken from the Vds of the M0SFET on the PFC, or from the auxiliary winding of the PFC choke coil (ch〇ke) as the ZCD signal. This signal has a decay period from high potential to low potential, and 1 is a zero current control point. Figure 5 (B) is a % waveform diagram of the condensing signal of pFC. ZCD from low to high ~ from high to low, but ZCD from high to low when ZCD decays to 〇, then Vgs from low to high. Since the frequency of the drive signal Vgs is affected by the ZCD decay rate, the main switch of the pfc can be operated in zero-dust (ZVS) zero current (ZCS) switching. Figure 5 (C) Waveform of the output signal of the IZCD detector. This output signal goes from high to low when ZCD decays to zero current control point Vz. Figure 6 is a CCM status timing diagram. Fig. 6(A) is a waveform diagram of the driving signal Vgs of the PFC. Since the frequency of the driving signal Vgs is a fixed frequency, the signal of 201019068 of Fig. 6(B) pfc is the driving signal Vgs of the trailing PFC. Figure 6 (C) is a waveform diagram of the vibration of the PFC. The highest potential is equal to ^ 圏(C) ΐΐϊϋί 'The current method of the lake in the industry is mostly the method of jumping pressure. There is no better solution. For the switch #雷浪相ϋ工> Ο It is very difficult to increase the cost. Switching electrical hybrids and s, ^ light load efficiency, the shortcomings of the prior art, proposed a simple and design and control advantages = ΐ ^ ϊ ί '. And effectively improve the above-mentioned missing combination two (four) [invention content], · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · the way
’以CM脱的控制觀念將其零電流檢測的 加人CCMPFC的頻率控制，同步改變ccmpfc的工作頻 ί ϋί動信號的動作，使得CCM PFC的PFC縣動信號與CRM pFC ，同時又不影響原來ccm pfc的控制穩定度，由 在輕載時，切換頻率高，當負載越來越重時，切換頻 越低，所以“_時，此發明之方法會使肌的切換頻 ，會由ZCD信號所控制’常負載重至比例以上，由於切換頻 二，至原本CCM PFC所設定的最低頻率時，切換頻率就由所設定 f f低頻率決^，此時PFC會操作在CCM模式，因此達成提高PFC 輕載效率，同時又達成大功率輸出之PFC。'With the control concept of CM off, the frequency control of the CCMPFC with its zero current detection, synchronously change the action of the ccmpfc's working frequency ί 动 动, so that the CFC PFC PFC county dynamic signal and CRM pFC do not affect the original Ccm pfc control stability, from light load, the switching frequency is high, when the load is getting heavier, the switching frequency is lower, so "_, the method of the invention will make the muscle switching frequency, will be ZCD signal The controlled 'normal load is more than the ratio. Because the frequency is switched to the lowest frequency set by the original CCM PFC, the switching frequency is determined by the set ff low frequency. At this time, the PFC will operate in the CCM mode, so the improvement is achieved. PFC Light duty efficiency, while achieving a high power output PFC.
本發明之次一目的在提供一種多模式操作之功率因素修正器 之^制卞法與裝置’此方法可適用於高效率之應用，昇壓式架構 或返驰式之架構皆可利用此控制方式來達成高效率，特別是在PFC 201019068 的應用上提高PFC的效率同時可以做大功率輸出，此發明解決 業界常用的CRM/CCM兩種PFC的缺點，同時結合兩種的優點^ PFC在極輕載與空載時會目PFC之振盪器會受限振盡器的最高頻 之限制，所以PFC在極輕載與空載時會進入叢發模式 Mode)，其空載損耗比CCM PFC低更多，且pFC在一定 也能與CRM PFC —樣的高效率又可以有CCM PFC大功率的輸出。 本發明之再一目的在提供一種多模式操作之功率因素修正 之控制方法與裝置，利用傳統CRM PFC的零電流檢知之方^ e ❹ 同步信號用以控制CCM PFC之振盪器使得pfc的控制方式^不因 負载了有不同的狀態在半载之下可以設計為CRM模忍J在= 頻率級CCM贼’當貞載㈣增加，娜頻率會輔 切換頻率時’ PFC則操作在心 ，s PFC操作在CCM模式時，零電流檢知信酬會被 步PFC之振璗器，使零電流檢知信號不再影響⑽模式之操A second object of the present invention is to provide a power factor corrector and method for multi-mode operation. This method can be applied to high efficiency applications, and the boost architecture or the flyback architecture can utilize this control. Ways to achieve high efficiency, especially in the application of PFC 201019068 to improve the efficiency of PFC and can do high power output, this invention solves the shortcomings of the two commonly used CRM/CCM PFCs in the industry, and combines the advantages of the two ^ PFC in the pole At light load and no load, the PFC oscillator will limit the maximum frequency of the vibrator, so the PFC will enter the burst mode Mode at very light load and no load, and its no-load loss is lower than CCM PFC. More, and pFC can also be as efficient as CRM PFC and can have CCM PFC high power output. Still another object of the present invention is to provide a control method and apparatus for power factor correction of multi-mode operation, using a zero current detection of a conventional CRM PFC, a synchronization signal for controlling a CCM PFC oscillator to control a pfc ^Do not have different states due to load. Under half load, it can be designed as CRM mode tolerant J in = frequency level CCM thief 'When load (four) increases, Na frequency will be auxiliary switching frequency 'PFC operates in heart, s PFC operation In the CCM mode, the zero current detection of the reward will be stepped by the PFC oscillator, so that the zero current detection signal no longer affects the operation of the (10) mode.
為達成上述目的及其他目的，本發明之第一觀點在教導一 i模式功率因素修正器之控制方法，在-定負載以下使功：因J ⑽界模式（Critieal喊_的控制方法動作： 巧南效率；在一定的負載之上使PFC以找模式（Continue Cc^UCtl〇n made，αΜ)馳制方法動仙得大功雜出， 2汽=:;3麼架構電路所產生的零電流檢知信號做為 麵人’當零電流檢知信號由高電位下降至零 键之檢知參考點時，零電流檢知器之㈣會由高電位改 魏，因此改變 奘署本觀點在教導一種多模式功率因素修正器之控制 一個疋頻模式功_素修正器電路，該定頻模式神因素修正= 201019068 電路具有一個電壓迴路誤差放大器，其輸出連至一個乘法器；一 個平方電路之輸出亦連至該乘法器，該乘法器之輸出連至一個電 流迴路誤差放大器，該電流迴路誤差放大器之輸出連至一個比較 器之負輸入；一個振盪器，其輸入為鑛齒波，此錯齒波亦連至該 比較器之正輸入；一個正反器，該比較器之輸出連至輸出連至該 正反器之R輸入’該振盪器之輸出連至該正反器之S輸入；一個 及閘，該正反器之Q輸出連至該及閘之一個輸入；一個反向器， 該振盪器之輸出亦連至該反向器之輸入，該反向器之輸出連至該 及閘之另一輸入’該及閘之輸出為功率因素修正器之軀動信號； ❹其特徵在於：一個零電流檢知器，該正反器之輸出連至該零電流 檢知器之控制以控制輸出與否，作為零電流檢知輸出控制信號； 該零電流檢知器之輸入為ZCD信號，此ZCD信號可取自自pfc上 電晶體(M0SFET)之VDS，也可取自pfc抗流線圈（ch〇ke)上之輔 助繞組作為ZCD之信號；該零電流檢知器之輸出連至該振盪器之 輸入，控制輸出鋸齒波的放電點，作為零電流同步信號用以同步 鑛齒波使PFC上電晶體(M0SFET)之VGS之驅動信號能在電晶艎 (M0SFET)之VDS為零時才驅動PFC上電晶體(M〇SFET)達成 (ZVS)切換之動作。 本發明之以上及其他目的及優點參考以下之參照圖示及最佳 w 實施例之說明而更易完全瞭解。 【實施方式】 第7圖為此發明工作在CRM狀態之時序圖。第7圓（A)為ZCD 信號波形圖。ZCD可取自PFC上電晶體(M0SFET)之Vds，也可取自 PFC抗流線圈（choke)上之輔助繞組作為ZCD之信號）此信 電位至低電位有一衰減期’ 1為零電流控制點。第7圖（B) fc 之驅動信號VGS波形圖。ZCD自低電.位至高電位時Vcs自高電位 電位，但ZCD自高電位至低電位時須ZCD衰減至〇，然後v自 低電位至局電位。因驅動信號vGS之頻率受ZCD衰減速度之影響， 201019068 故剛好可使PFC之主開關工作在零電壓(zvs)零電流(zcs)切換。 第7圖（C)為ZCD檢知器之輸出信號波形圖。此輸出信號於zcd 哀減至零電流控制點Vz時自尚電位至低電位。第7圖（d)為ρρς之 振蘯器波形’當ZCD檢知器輸出自低電位至高電位時，pfS之振盡 ^立即放電，此放電之電壓點稱為Vs，PFC之振盪器波形未達振盪 器之v+之比較電位振盪器便放電，PFC之振盪頻率因此改變，也同 時改變PFC之驅動信號VGS。使得定頻PFC的振重器工作在變頻的 方式，第7圊（E)為ZCD信號使用脈波方式時，其同步振盪器的方 式則改為將脈波注入振蘯器之輸出鑛齒波之頂點電壓加上脈波， 提早達到上比較點VH時，才開始放電至下比較點yl，因此改變了 原來振盪的頻率，如同CRM PFC相同的工作方式，但是此發明的 方式不同於傳統的CRM PFC的控制方式。 第8圖為此發明工作在CCM狀態之時序圖第8圖（a)為pfc =CD之波形圖。因為當PFC的負載大於CRM之負載設計時，zc]) ΐίί雜驅動信號V"，故第8圖⑻PFC之驅動信號&信號 為領先PFC電晶體(M0SFET)之VdS。第8圖（C)為ZCD檢知器信號 輸出。此信號在PFC驅動信號Vgs信號為高電會位時，即立刻將 ZCD檢知器信號輸出之電位不可被ζα)信號改變。因此不In order to achieve the above and other objects, the first aspect of the present invention teaches an i-mode power factor corrector control method that performs work below a fixed load: due to the J (10) bound mode (Critieal shouting _ control method action: skillful South efficiency; above a certain load, the PFC is looking for the mode (Continue Cc^UCtl〇n made, αΜ). The method of making a move is very good, 2 steam =:; 3, the zero current detection generated by the architecture circuit Knowing the signal as a face-to-face when the zero-current detection signal drops from the high potential to the zero-check detection reference point, the zero-current detector (4) will change from high potential to Wei, so changing the view is teaching a kind The multi-mode power factor corrector controls a frequency-frequency mode power-based modifier circuit, and the fixed-frequency mode god factor correction = 201019068 The circuit has a voltage loop error amplifier whose output is connected to a multiplier; the output of a square circuit is also Connected to the multiplier, the output of the multiplier is coupled to a current loop error amplifier, the output of which is coupled to the negative input of a comparator; an oscillator that loses For the ore wave, the wrong tooth wave is also connected to the positive input of the comparator; a flip-flop, the output of the comparator is connected to the R input of the output connected to the flip-flop, the output of the oscillator is connected to the S input of the flip-flop; a gate, the Q output of the flip-flop is connected to an input of the gate; an inverter, the output of the oscillator is also connected to the input of the inverter, the reverse The output of the device is connected to the other input of the gate and the output of the gate is the body motion signal of the power factor corrector; the characteristic is: a zero current detector, the output of the flip-flop is connected to the zero The current detector is controlled to control the output or not as a zero current detection output control signal; the input of the zero current detector is a ZCD signal, and the ZCD signal can be taken from the VDS of the pfc upper transistor (M0SFET). It can also be taken from the auxiliary winding on the pfc anti-current coil (ch〇ke) as the signal of ZCD; the output of the zero current detector is connected to the input of the oscillator, and the discharge point of the output sawtooth wave is controlled as zero current synchronization. The signal is used to synchronize the mineral tooth wave to drive the VGS of the PFC upper transistor (M0SFET). The signal can drive the PFC upper transistor (M〇SFET) to achieve the (ZVS) switching action when the VDS of the transistor (M0SFET) is zero. The above and other objects and advantages of the present invention are referred to the following reference figures and most The description of the embodiment of the invention is more fully understood. [Embodiment] Fig. 7 is a timing chart for the CRM state of the invention. The seventh circle (A) is a waveform diagram of the ZCD signal. The ZCD can be taken from the PFC on the transistor ( The Vds of M0SFET) can also be taken from the auxiliary winding on the PFC choke as the signal of ZCD. This signal has a decay period of 1 to zero current control point. Figure 7 (B) Waveform of the drive signal VGS of fc. ZCD is low-voltage. Vcs is at a high potential from high potential, but ZCD is attenuated to 〇 from high to low, and then v is from low to local. Since the frequency of the drive signal vGS is affected by the ZCD decay rate, 201019068 is just enough to make the PFC main switch operate at zero voltage (zvs) zero current (zcs) switching. Figure 7 (C) is a waveform diagram of the output signal of the ZCD detector. This output signal goes from potential to low when zcd drops to zero current control point Vz. Figure 7 (d) is the oscillator waveform of ρρς' When the ZCD detector output is from low to high, the pfS is immediately discharged. The voltage of this discharge is called Vs, and the waveform of the PFC oscillator is not. The comparator potential oscillator of the v+ is discharged, and the oscillation frequency of the PFC is changed, and the driving signal VGS of the PFC is also changed. The vibrator of the fixed frequency PFC is operated in the frequency conversion mode. When the 7th (E) is the ZCD signal using the pulse wave mode, the synchronous oscillator mode is changed to the pulse wave injected into the output of the vibrator. The vertex voltage plus the pulse wave, when it reaches the upper comparison point VH, starts to discharge to the lower comparison point yl, thus changing the frequency of the original oscillation, like the same working mode of the CRM PFC, but the invention is different from the conventional method. CRM PFC control method. Figure 8 is a timing diagram of the invention in the CCM state. Figure 8 (a) is a waveform diagram of pfc = CD. Because the load of the PFC is greater than the load design of the CRM, the drive signal & Figure 8 (C) shows the ZCD detector signal output. When the PFC drive signal Vgs signal is in the high power position, the signal can immediately change the potential of the ZCD detector signal output by the ζα) signal. Therefore no
LFC 之放電電位點。第8圖⑻為PFC之振蘯器之波形 圖丄最局電位等於V+。所以PFC之振|器之頻率都不會被改變也 不會受ZCD信號影響而干擾了原來CCM PFC的控制樺定。 第9圖顯示多模式操作之功率因素修正器之控制方 f。第9圖主要由一個定麵式功率因素修正器電路911，定頻相 因素修正器電路911具有一個電壓迴路誤差放大器顚其 H至-讎法n咖個平方電路搬之輸出亦連至乘法^ 政组1法9〇3之輸出連至—個電流迴路誤差放大器904，電流迴 路誤差放大器904之輸出連至一個比較器9〇5之負輸入；一個 盪器906，其輸出為錯齒波，此鋸齒波亦連至比較器9〇5之正 入;-個正反器，比較器之輸出連至正反器撕之段) 201019068 振，器906之輸出連至正反器9〇7之8輸入；一個及問9〇9, 正反 ® 之Q輸出連至及閘909之一個輸入；一個反向器908，振盪 ，90=之輸出亦連至反向器9〇8之輸入，反向器9〇8之輸出連至 =909之另一輸入’及閘9〇9之輸出為功率因素修正器之躺動 5正反器907的輸出910做為零電流檢知器911之零電流檢 913,零電流檢知器911之細912做為振i器906的控制 。零電流檢知器911之輸入為ZCD。正反器907所產生的 ^電k檢知信號913做為零電流檢知器914之控纖入，當零電 檢知信號913由高電位下降至零·檢知器914之檢知參考點 ❹電流檢知器914之輸出912會由高電位改變為低電位 此零電流檢知器之檢知為負緣觸發’其輸出由高電位變化 至低電位’也可以改為由低電位變化至高電位，也能用脈波方式 ，振mu的方式的控制魏需求，此輸出會使振盪器的輸出鑛齒 波立即放電（此點在此稱Vs)改變其原來會達到上比較點VH時，才 電至下比較點VL，因此改變了原來振触鮮。使用脈波 方式時，其同步振盈器的方式則改為將脈波注入振盡器之輸出鑛 齒波之頂點電壓加上脈波，提早達到上比較點VH時，才開始放電 至下比較點VL，因此改變了原來振盡的頻率。 當^盪器的鋸齒波放電至VL點時，PFC之PWM驅動信號會立 即輸出尚電位，而振盪器之鑛齒波會開始線性充電，至下一次的 同步信號纽變放電_間點(Vs)，如果沒同步信號來改變則會 f原來振盪器的VH來決定其工作鮮^當pFC之駆動信號為 尚電位時二零電流檢知器輸出之同步信號會被關閉，直到pFc之 PWM驅動知號為低電位時，才能再次啟動零電流檢知器之輸出。如 此的操作方式便可以使原來CCM PFC的控制可以操作在CRM的模 式進而使整個PFC可以依據需求設計在所需要的負載下操作在 CRM模式在-定的負載以上操作在C(1模式，如此便達成可高效 率與大功率輸出之功率因素修正器，此方式亦可用在非pFC的應 用上。 *' 201019068 * 藉由以上較佳之具體實施例之詳述，係希望能更加清楚插述 本創作之特徵與精神，而並非以上述所揭露的較佳具體實例來對 本發明之範疇加以限制。相反的，其目的是希望能涵蓋各種改變 及具相等性的安排於本發明所欲申請之專利範_内。 【圖式簡單說明】 第1圖（習知技術）臨界模式CRM PF(^電感電流之波形圖。 第2圖（習知技術）定頻模式CCM pFC的典型電感電流波形。 第3圖CRM PFC之典型應用電路。 ❹第4圖CCM PFC的典型應用電路。 第5圖為CRM狀態時序圖； 第5圖（A)為ZCD信號波形圖； 第5圖（B)為PFC之驅動信號VGS波形圖； 第5圖（C)為ZCD檢知器之輸出信號波形圖； 第6圖為CCM狀態時序圖； 第6圖（A)為PFC之驅動信號VGS波形圖； © 第6圖（B)為PFC之主開關之VDS波形圖； 第6圖（〇為？?(：之振盪器之波形圖。 第7圖為本發明之CRM狀態時序圖； 第7圖（A)為ZCD信號波形圖； 第7圖（B)為PFC之驅動信號VGS波形圖； 第7圖(C)為ZCD檢知器之輸出信號波形圖； 第7圖（D)為PFC之振盪器之波形圖； 第7圖（E)為PFC之振盪器之波形圖。 12 201019068 第8圖為本發明之CCM狀態時序圖； 第8圖（A)為ZCD信號波形圖； 第8圖（B)為PFC之驅動信號VGS波形圖； 第8圖（C)為ZCD檢知器之輸出信號波形圖； 第8圖（D)為PFC之振盪器之波形圖。 第9圖顯示多模式操作之功率因素修正器之控制方法與裝置 【主要元件符號說明】 903乘法器 905比較器 907正反器 909正反器 ❹901電壓迴路誤差放大器9〇2平方電路 912零電流檢知器914 913零電流檢知信號 之輪出 904 電流迴路誤差放大器 906 振盪器 908 反向器 910 正反器907的輸出 914零電流檢知器 13The discharge potential point of the LFC. Figure 8 (8) shows the waveform of the vibrator of the PFC. The most local potential is equal to V+. Therefore, the frequency of the PFC's vibration device will not be changed and will not be affected by the ZCD signal and interfere with the control of the original CCM PFC. Figure 9 shows the controller f of the power factor corrector for multi-mode operation. Figure 9 is mainly composed of a fixed-face power factor corrector circuit 911. The fixed-frequency phase factor corrector circuit 911 has a voltage loop error amplifier, and its H to - 雠 method is evenly connected to the multiplication method. The output of the political group 1 method 9〇3 is connected to a current loop error amplifier 904, the output of the current loop error amplifier 904 is connected to the negative input of a comparator 9〇5; a swing 906 whose output is a wrong tooth wave, The sawtooth wave is also connected to the positive input of the comparator 9〇5; a positive and negative inverter, the output of the comparator is connected to the section of the flip-flop of the flip-flop) 201019068, the output of the oscillator 906 is connected to the flip-flop 9〇7 8 inputs; one and ask 9〇9, the Q output of the positive and negative® is connected to one input of the gate 909; one inverter 908, the oscillation, the output of 90= is also connected to the input of the inverter 9〇8, The output of the transmitter 9〇8 is connected to the other input of 909 and the output of the gate 9〇9 is the output of the power factor corrector. The output 910 of the flip-flop 907 is zero current of the zero current detector 911. Check 913, the fine 912 of the zero current detector 911 is used as the control of the oscillator 906. The input of the zero current detector 911 is ZCD. The electric k detection signal 913 generated by the flip-flop 907 is made into the control of the zero current detector 914. When the zero electric detection signal 913 is lowered from the high potential to zero, the detection reference point of the detector 914 The output 912 of the ❹ current detector 914 will change from a high level to a low level. The detection of the zero current detector is a negative edge trigger 'its output changes from a high potential to a low potential' can also be changed from a low potential to a high level. The potential can also be controlled by the pulse wave mode and the mode of the vibration mu. This output causes the output of the oscillator to immediately discharge the ore wave (this point is called Vs) and it will change to the upper comparison point VH. Only when the electricity is compared to the lower point VL, the original vibration is changed. When using the pulse wave mode, the mode of the synchronous vibrator is changed to the pulse wave injected into the peak of the output orthodontic wave of the vibrating device, and the pulse wave is added. When the upper comparison point VH is reached early, the discharge is started until the next comparison. Point VL, thus changing the frequency of the original vibration. When the sawtooth wave of the oscillator is discharged to the VL point, the PWM drive signal of the PFC will immediately output the potential, and the ore wave of the oscillator will start to linearly charge until the next sync signal is changed to the discharge point (Vs). If there is no synchronization signal to change, then the original oscillator's VH will determine its operation. When the pFC's sway signal is still potential, the synchronization signal output from the 20 current detector will be turned off until the PWM drive of pFc When the know signal is low, the output of the zero current detector can be started again. This way of operation allows the original CCM PFC control to operate in the CRM mode so that the entire PFC can be designed to operate under the required load according to the requirements. The CRM mode operates above the fixed load in C (1 mode, so A power factor corrector capable of high efficiency and high power output is achieved, which can also be used in non-pFC applications. *' 201019068 * By the detailed description of the preferred embodiment above, it is hoped that the present invention can be more clearly explained. The features and spirit of the invention are not limited by the preferred embodiments disclosed above. Instead, the purpose is to cover various modifications and equivalents of the patents claimed in the present invention. Fan_内。 [Simplified Schematic] Figure 1 (Preferred Technology) Critical Mode CRM PF (^Inductor Current Waveform. Figure 2 (General Technology) Constant Frequency Mode CCM pFC Typical Inductor Current Waveform. 3 Figure CRM PFC typical application circuit. ❹ Figure 4 CCM PFC typical application circuit. Figure 5 is CRM state timing diagram; Figure 5 (A) is ZCD signal waveform diagram; Figure 5 (B) is P FC drive signal VGS waveform diagram; Figure 5 (C) is the output signal waveform diagram of ZCD detector; Figure 6 is CCM state timing diagram; Figure 6 (A) is PFC drive signal VGS waveform diagram; Fig. 6(B) is a VDS waveform diagram of the main switch of the PFC; Fig. 6 is a waveform diagram of the oscillator of the present invention. Fig. 7 is a timing chart of the CRM state of the present invention; Fig. 7 (A) ) is the ZCD signal waveform diagram; Figure 7 (B) is the PFC drive signal VGS waveform diagram; Figure 7 (C) is the output signal waveform diagram of the ZCD detector; Figure 7 (D) is the PFC oscillator Figure 7 (E) is a waveform diagram of the PFC oscillator. 12 201019068 Figure 8 is a CCM state timing diagram of the present invention; Figure 8 (A) is a ZCD signal waveform diagram; Figure 8 (B) ) is the PGS drive signal VGS waveform diagram; Figure 8 (C) is the output signal waveform diagram of the ZCD detector; Figure 8 (D) is the waveform diagram of the PFC oscillator. Figure 9 shows the multi-mode operation Power factor corrector control method and device [main component symbol description] 903 multiplier 905 comparator 907 positive and negative device 909 forward and reverse device 901 voltage loop error amplifier 9 〇 2 square Zero-current detector 912 is 914,913 zero current detector wheel 904 signals the current loop error amplifier 906 oscillator 908 output of the inverter 910 in the flip-flop 907 914 zero current detector 13