TW201017828A - Fabrication method of non-volatile memories with layers of molybdenum-based nano-crystals - Google Patents

Fabrication method of non-volatile memories with layers of molybdenum-based nano-crystals Download PDF

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TW201017828A
TW201017828A TW97141195A TW97141195A TW201017828A TW 201017828 A TW201017828 A TW 201017828A TW 97141195 A TW97141195 A TW 97141195A TW 97141195 A TW97141195 A TW 97141195A TW 201017828 A TW201017828 A TW 201017828A
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layer
molybdenum
volatile memory
film
memory element
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TW97141195A
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Jian-Yang Lin
Ting-Chang Chang
Sheng-Chi Chen
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Univ Nat Yunlin Sci & Tech
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Abstract

This present invention is a manufacturing method of nonvolatile memories with Molybdenum-based nano-crystals. The manufacturing method includes the steps of forming a tunneling barrier oxide on the substrate, forming a Mo-Si thin film with Molybdenum-based nano-crystals, forming a control dielectric, and forming two electrodes on the surfaces of the substrate and the control dielectric, respectively. The formed Molybdenum-based nano-crystals could be Molybdenum or Molybdenum silicides. The Molybdenum-based nano-crystals are used as charge storage in the nonvolatile memories.

Description

201017828 九、發明說明: 【發明所屬之技術領域】 本發明是關於一種奈米晶體的製造方法,尤其β , 一種具有鉬奈米晶體之非揮發性記憶元件的製關於 【先前技術】 ' ° ❹201017828 IX. Description of the Invention: [Technical Field] The present invention relates to a method for producing a nanocrystal, in particular, β, a non-volatile memory element having molybdenum nanocrystals. [Prior Art] '° ❹

記憶體依所存入的資料是否會受「供電」的影響,。 分為揮發性記憶體(Vo丨at丨丨e mem〇ry)及非揮發性^己传^ (Nlon-vo丨atUe memory)等兩大類。所謂的揮發性記憶體β 指記憶體㈣㈣須仰賴持續性的電源供應才能維持和: 有;相對的,非揮發性記憶體即使遇到了電源中斷,' °内 部記憶體之資料仍得以保持一段报長的時間。日常生活中 常見的電腦其内部的動態隨機存取記憶體(dram)與靜雜 隨機存取記憶體(SRAM)就是屬於揮發性記憶體,其他像; 讀記憶趙(ROM)、可程式唯讀記憶體(EpR〇M)與快閃吃憶 體(Flash Memory)則是屬於非揮發性記憶體。 °心 請參考第十一圖,快閃記憶體(9〇)的原理是使用多晶 石夕的浮停閘極(F丨。ating Gate)(91)作為電荷儲存單元。= 電子由通道(92)注人儲存於浮停閘(91)後,元件臨界電^ 將會改變。非揮發性記憶體邏輯的M叫便是由不同臨界 電廢所定義。雖然傳統的快閃記憶趙_元件已經廣泛地 在商業上量產’但仍有許多不可避免之特性方面上的限制 要來面對。其中最重要的一項限制便是它的垂直堆疊式处 構在尺寸縮減上的限制,尤其是近年來對於元件尺寸料 上所面對的穿随氧化層隨之縮減的挑戰。由於浮停閉極㈣ 201017828 效電晶體通道之間的二氧化矽(93)能障很薄,因此二 #化石夕(93) f要很好的品f才能破保良好浮停閘極(叫絕 ^關鍵、。不幸地’由於結構上不完美的缺陷和原子鍵結 .:不可避免的材料問題,這些缺陷的材料中,其漏電流 =而使得原本儲存在浮停間極(91)的電荷順著路徑進入 般常見的解決方法增加絕緣能障的厚度來避免漏 停Γ更厚的漏電荷能障反而減緩了電子在進入 ❹數)間的傳輸,導致電子寫入與抹除的次 速度,穿=。而要改善浮停閉極(91)元件寫入與抹除的 才能達到,在:層的厚度必須降低,其必須低於2.5奈米 抹广1壓:於1。伏之下時有·寫人與 絕緣能力確保資料的:,穿隨氧化層必須提供更佳的 能確保資料的正確性達::耐久'並於外界擾動下仍 變薄時,資訊的佯广之久。當穿隧氧化層的厚度 緣性固辦得二改善予但會衰減’而當厚度增加時,絕 ❹度與可靠度之間,二==將會降低1此權衡於速 此外’若氧化層的厚度不文:控制於8〜11奈米之間。 直無法獲得改善。A / '°、作電壓與記憶體速度將- 為了克服傳統快閃記揞 改善的方式被提出,〜化V(氮== 咸限制’兩種 體非揮發性記憶體元::=:(_) 二。己億體元件(95)當穿隨氧 二二米 良好的資料保存…降低功率消耗。):耐 == 6 201017828 便是非揮發性記憶體的一項很重要的可靠度參數。因非揮 發性此憶體的耐操性(enduranGe)表示在經過週期性反覆寫 入,後,仍㉜明確的擁有資料的辨別性;而保存性㈣鳴η) ,貝J &述再經過一次寫入後’特定溫度下储存資料與恢復資 料的能力。 #。對於奈米晶體記憶體(95)而言,從側面路徑造成的電 荷損失可由奈米晶體(952)周圍的氧化絕緣層(953)來抑 〇制,相對於傳統浮停閘記憶體元件,此元件展現出更佳的 =荷储存特性。因為奈米晶體(952)中電荷是以分散式的儲 存,故所有儲存電荷不會因少數漏電路徑而損失,其可以 改善傳統快閃記憶體元件尺寸限制而仍保存基本記憶特性 的方法便是以分散式電荷儲存來取代。典型的研究是使用 半導體(石夕或鍺)奈米晶體(952)來縮減穿隨氧化層的厚度而 不會喪失其可靠度並且還能夠減少操作電壓。奈米晶體非 揮發性,憶體第-次簡介於1990年代。在此記憶體元件 ❹中’電何不再是由傳統多晶梦層储存電荷,取而代之的則 是利用分散式彼此互相絕緣的結晶體或奈米晶體(952)來儲 f電荷。每一晶體一般都只有少量的電荷儲存;所有奈米 晶體(952)裡面的電子控制著記憶體電晶體的導電性。 一金屬奈米晶體的優點引起許多注意。比起半導體的奈 米晶體,金屬奈米晶體具有低功率損失、高密度、更強的 通道叙σ更佳的尺寸縮減度與高功函數之設計元件的自 由度。藉由在氧化層上沉積一層薄膜,再經由快速熱退火 後便自我析出成奈米晶體並可整合在丁元件上, 7 201017828 l疋由於表面旎量纟高溫退火下減少以致於驅使金屬薄膜 熱凝聚成為奈米晶體於通道氧化層上。相較於半導體晶體 兄隐體金屬奈米晶體記憶體顯現出幾項優點:)與導 5道有較強的輕合性(2)更佳的尺寸縮減性(3)在費米 能階上有更高的態位密纟⑷由於载子侷限有更低的能量 擾動⑼高功率函數有更大的設計自由度來最佳化元件特Whether the memory is affected by the "power supply" depends on whether the data is stored. It is divided into two categories: volatile memory (Vo丨at丨丨e mem〇ry) and non-volatile ^Nong-^ (Nlon-vo丨atUe memory). The so-called volatile memory β refers to the memory (4) (4) depends on the continuous power supply to maintain and: Yes; relatively, non-volatile memory even if the power supply is interrupted, ' ° internal memory data can still be kept Long time. The internal dynamic random access memory (dram) and static random access memory (SRAM) of computers commonly used in daily life belong to volatile memory, other images; read memory Zhao (ROM), programmable read only Memory (EpR〇M) and Flash Memory are non-volatile memories. ° Heart Please refer to the eleventh figure. The principle of flash memory (9〇) is to use the floating gate (F丨.ating Gate) (91) of polycrystalline stone as the charge storage unit. = After the electron is stored in the channel (92) and stored in the floating gate (91), the component critical voltage will change. The M-call of non-volatile memory logic is defined by different critical electrical waste. Although the traditional flash memory _ components have been widely commercially available in mass production, there are still many inevitable limitations in terms of features to be faced. One of the most important limitations is the reduction in size reduction of its vertically stacked structure, especially in recent years, as the wear-and-see oxide layer faced on component sizes has shrunk. Due to the floating stop (4) 201017828, the bismuth dioxide (93) energy barrier between the transistor channels is very thin, so the ##石石(93) f is a good product to break the good floating gate. ^Key, unfortunately 'due to structural imperfections and atomic bonding.: Inevitable material problems, the leakage current of these defective materials = the charge originally stored in the floating terminal (91) Follow the path to enter a common solution to increase the thickness of the insulation barrier to avoid leakage and thicker leakage charge energy barriers, but slow down the transmission of electrons into the number of turns, resulting in the secondary speed of electronic writing and erasing , wear =. To improve the writing and erasing of the floating-stop closed-pole (91) component, the thickness of the layer must be reduced, which must be less than 2.5 nm. Under the volts, there are people who write and protect the data: the wearer must provide better information to ensure the correctness of the data:: Durable' and when the external disturbance is still thin, the information is wide. as long as. When the thickness of the tunneling oxide layer is fixed, it will be improved, but it will be attenuated. When the thickness is increased, between the absolute degree and the reliability, the second == will be reduced by 1. This trade-off is faster. The thickness is not text: controlled between 8~11 nm. Straight can't be improved. A / '°, voltage and memory speed will be - in order to overcome the traditional flash flash improvement method is proposed, ~ V (nitrogen == salty limit 'two kinds of non-volatile memory elements::=:(_ 2. Two hundred million body components (95) when wearing good data with oxygen two meters to save ... reduce power consumption.): resistance == 6 201017828 is a very important reliability parameter of non-volatile memory. Because of the non-volatile endurance Ge (enduranGe), after repeated periodic writing, it is still clear that 32 has the discriminative possession of the data; and the preservative (four) η), the shell J & The ability to store data and recover data at a specific temperature after a write. #. For the nanocrystal memory (95), the charge loss caused by the side path can be suppressed by the oxidized insulating layer (953) around the nanocrystal (952), compared to the conventional floating gate memory element. The component exhibits better = load storage characteristics. Because the charge in the nanocrystal (952) is stored in a decentralized manner, all stored charges are not lost due to a small number of leakage paths, which can improve the size limitations of conventional flash memory components while still retaining the basic memory characteristics. Replaced by decentralized charge storage. A typical study is to use a semiconductor (Silver or yttrium) nanocrystal (952) to reduce the thickness of the pass-through oxide layer without losing its reliability and also to reduce the operating voltage. The nanocrystals are non-volatile, and the first-time introduction of the nano-crystals was in the 1990s. In this memory component, it is no longer that the charge is stored by the conventional polycrystalline dream layer, but instead the crystals or nanocrystals (952) which are dispersed in each other are used to store the f charge. Each crystal typically has a small amount of charge storage; the electrons in all nanocrystals (952) control the conductivity of the memory transistor. The advantages of a metal nanocrystal cause a lot of attention. Compared to nanocrystals of semiconductors, metallic nanocrystals have low power loss, high density, better channel size, better dimensional reduction and high work function design component freedom. By depositing a thin film on the oxide layer, and then self-precipitating into nanocrystals through rapid thermal annealing, and can be integrated on the D-component, 7 201017828 l疋 is reduced by surface 纟 纟 high temperature annealing to drive the heat of the metal film Condensation becomes a nanocrystal on the channel oxide layer. Compared with the semiconductor crystal brother stealth metal nanocrystal memory, it shows several advantages:) It has strong lightness with the guide 5 channel (2) Better size reduction (3) On the Fermi level There is a higher state density (4) because of the lower energy perturbation of the carrier (9) The high power function has greater design freedom to optimize the component.

金屬奈米晶體不會承受來自開極的跨壓,這表示由控 :閘極給的電壓將跨於穿隧氧化層與控制氧化層上因而獲 得此項好處°由於高密度狀態的金屬奈米晶體對於費米能 階因々木物導致的波動具有更多免疫能力。金屬奈米晶體 傾向更加均勻儲存電荷的一致性’因此控制臨界電壓vth 在更窄的範圍Θ。較寬範圍可利用的功函數提供更佳設計 :由f於權衡寫人/抹除和電荷保存性上,這是因為功函數 衫響者電荷健存在位勢井的深度和可利用的狀態密度於基 板穿隨下^藉由橫列於電龍存時⑪能隙與抹除時導電帶 邊緣之間的奈米晶體f米能階,在报薄的穿隨氧化層下仍 可得到較大的J /1 g,programming/Jg,retenti〇n 比值,因為寫入是 由穿随電子從石夕基板進入奈米晶冑’因此總是可以找到可 利用態位穿隧進入’並且能夠有近似於當時的抹除電流密 .能1¾故金屬奈米晶體可快速寫入和抹除及同時具有 的=貝料保存性。金屬奈米晶體也能夠縮減奈米晶體的 尺寸達到夠好的記憶特性。為了確保庫倫相斥效應下單電 子或少數電子記憶體特性,較小的奈米晶體是必須的,然 201017828 而對於半導體奈米晶體與塊材的相比,由於多維的載子偈 限效應使得奈米晶體的能隙較寬’也就減少了有效的位勢 井深而必須犧牲電荷保存性。這種效應對於金屬奈米晶體 影響是非常微小的,因其有上千個導電帶電子在奈米晶體 中甚至在電荷中性態位裡。故對於金屬奈米晶體尺寸之費 米能階的增加是很小的。 雖然目前的金屬奈米晶體略有功效,但是目前選用的 金屬材料若不是成本太高(如Ag、Pt),就是熱穩定性不佳, 使金屬材料無法應用於CMOS(互補式MOSFET)之源/汲極 (S/D)離子植入製程所需的高溫1〇〇〇它下活化,或是功函 數不佳,使其可儲存的態位密度較少、電荷保存特性不佳, 形成選材使用上的困擾。 【發明内容】 功函數的 ’解決前 為了解決前述金屬晶體高成本、熱穩定性、 問題, 問題,本發明係採用鉬金屬作為金屬晶體的材料 Θ述的問題。The metal nanocrystal does not withstand the cross-voltage from the open pole, which means that the voltage given by the gate will cross the tunneling oxide layer and the control oxide layer to obtain this benefit. Due to the high density state of the metal nano The crystal has more immunity to fluctuations in the Fermi level due to eucalyptus. Metal nanocrystals tend to store charge uniformity more uniformly' thus controlling the threshold voltage vth to be narrower. A wider range of available work functions provides a better design: by weighing the trader/erase and charge preservability, this is because the work function of the power function is the depth of the well and the available state density. The nano-crystal f-meter energy level between the 11-gap between the energy gap and the edge of the conductive strip during erasing can be obtained by the substrate. J /1 g, programming / Jg, retenti〇n ratio, because the writing is made by wearing electrons from the Shixi substrate into the nanocrystalline crystals 'so can always find the available state of the tunnel into the ' and can have an approximation At that time, the current is erased. The metal nanocrystal can be quickly written and erased and has the same conservatory property. Metal nanocrystals are also capable of reducing the size of the nanocrystals to achieve good memory characteristics. In order to ensure the single electron or a few electronic memory characteristics under the Coulomb repulsion effect, smaller nanocrystals are necessary, but 201017828 and compared to semiconductor nanocrystals and bulk materials, due to the multi-dimensional carrier limit effect The wide band gap of the nanocrystals reduces the effective potential well depth and must sacrifice charge retention. This effect is very small for metallic nanocrystals because it has thousands of conduction band electrons in the nanocrystals and even in the charge neutral state. Therefore, the increase in the Fermi level of the metal nanocrystal size is small. Although the current metal nanocrystals have a slight effect, the metal materials currently selected are not too expensive (such as Ag, Pt), but the thermal stability is not good, so that the metal materials cannot be applied to the source of CMOS (complementary MOSFET). The high temperature required for the /dole (S/D) ion implantation process is activated under it, or the work function is not good, so that it can store less state density and poor charge retention characteristics. Trouble with use. SUMMARY OF THE INVENTION Before the solution of the work function In order to solve the aforementioned problems of high cost, thermal stability, and problems of the metal crystal, the present invention employs molybdenum metal as a material of the metal crystal.

介質層表面之電極。 ’本發明係提供一種具有鉬奈米晶 意元件’其包含一基板,依序成形 曼、一包含複數個鉬奈米晶體之鉬 ,以及兩個分別形成於基板及控制The electrode on the surface of the dielectric layer. The present invention provides a molybdenum nanocrystalline element which comprises a substrate, sequentially formed, a molybdenum containing a plurality of molybdenum nanocrystals, and two respectively formed on the substrate and controlled

非晶半導體基材、 '、為一單晶半導體、多晶半導體基材、 摻雜施授子之半導體基材、單元半導體 201017828 基材或多元半導體基材。 之鉬金 其中’該鉬矽薄膜内的各鉬奈米晶體可為析出 屬或鉬矽化合物。 非揮發性 穿隧阻障 其中,該控制介質層為氮化物或氧化物薄膜 本發明再提供—種具有翻奈米晶體結構層的 記憶元件之製造方法,其步驟包含: 形成穿隧障壁層’於一半導體基材上形成_ 層;The amorphous semiconductor substrate, ', is a single crystal semiconductor, a polycrystalline semiconductor substrate, a doped donor semiconductor substrate, a unit semiconductor 201017828 substrate or a multi-component semiconductor substrate. Molybdenum gold wherein each of the molybdenum nanocrystals in the molybdenum-ruthenium film may be a precipitated or molybdenum-rhenium compound. Non-volatile tunneling barrier wherein the control dielectric layer is a nitride or oxide film. The invention further provides a method for fabricating a memory element having a nanocrystalline crystal structure layer, the steps comprising: forming a tunnel barrier layer Forming a layer on a semiconductor substrate;

形成鉬矽薄膜 層; 於該穿隧阻障層上鍍製—鉬發薄膜 *形成控制介電層,於該箱石夕薄膜層上銀製-控制介電 薄膜; 析成銷奈米晶體,係於完成鍍製控制介電薄膜之前或 之後對該銦石夕薄膜執行一翻奈米晶體析出製程 薄膜㈣成複數㈣mm ^翻石夕 ❹蚀制裝作電極’係分別於該半導體基材以及該控制介電層 銀製一電極。 一其該形成穿隧障壁層步驟係以一物理氣相沉積或 一化學氣相沉積裝置鍍製該半導體基材之氧化物或氮化 物。 其中,該形成鉬矽薄膜步驟係以一物理氡相沉積或一 化學亂相沉積裝置將一鉬矽化合物形成於該穿隧障壁層。 其中,該形成控制介電層步驟係以一物理氣相沉積或 化子氣相沉積裝置將一氧化物或氮化物薄膜形成於該鉬 201017828 矽薄膜表面。 其中,該後處理製程係為一快速熱退火製程。 藉此,本發明所使用的鉬矽薄膜經過後處理之後,可 以有效形成翻奈米晶體作為非揮發性記憶體儲存載子的用 途,由於鉬奈米晶體係包覆於矽的氧化物之間,造成奈米 '晶體間有較佳的隔離效果,避免過多漏電路徑的產生不/ 【實施方式】Forming a molybdenum-ruthenium film layer; depositing a molybdenum film on the tunneling barrier layer* to form a control dielectric layer, and performing a silver-controlled dielectric film on the box film layer; forming a pin nanocrystal, Performing a nanometer crystal precipitation process film (4) into a plurality of (four) mm ^ 石 ❹ 制 制 电极 电极 分别 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前 之前Control the dielectric layer to make an electrode of silver. The step of forming the tunnel barrier layer is to deposit an oxide or nitride of the semiconductor substrate by a physical vapor deposition or a chemical vapor deposition apparatus. Wherein, the step of forming a molybdenum-ruthenium film is formed by depositing a molybdenum-bismuth compound into the tunnel barrier layer by a physical germanium deposition or a chemical disorder deposition apparatus. Wherein, the step of forming the control dielectric layer forms an oxide or nitride film on the surface of the molybdenum 201017828 tantalum film by a physical vapor deposition or a chemical vapor deposition apparatus. The post-treatment process is a rapid thermal annealing process. Thereby, the molybdenum tantalum film used in the present invention can be effectively formed into a non-volatile memory storage carrier after being post-treated, since the molybdenum nanocrystal system is coated between the oxides of the tantalum , causing better isolation between the crystals of the nano crystals, avoiding the generation of excessive leakage paths. [Embodiment]

請參考第一圖以及第二A〜二E圖,其為本發明之具 有鉬奈米晶體結構層的非揮發性記憶元件及其製造方法的 較佳實施例’纟中’該具有_奈米晶體結構層的非揮發性 記憶體的製造方法包含步驟:形成穿隧障壁層〇〇)、形成 鉬矽薄膜(20)、形成控制介電層(3〇)、析成鉬奈米晶體_ 以及製作電極(50)。 該形成穿隧障壁層(10)步驟中,請參閱第二A圖所示, 係為選取一半導體基材(8〇),其經過標準清洗製程除去表 面雜質、污染物或原生氧化層(Native 〇xjde Layer)之後, 利用-薄膜成長裝置於該半導艘基材_完成清洗的表面 形成一穿隧障壁層(81)。該半導體基材(8〇)可 元、單晶或多晶或非晶之半導體基材(如矽基材或為三五族 化合物半導體基材,如耗鎵);所謂的標準清洗製程可為 - RCA標準製程;所謂之薄膜成長裝置可為—物理氣相 沉積(PVD、sputter··.等)或—化學氣相沉積之裝置(如 PECVD、ThermalCVD、ApcvD等);該穿随障壁層㈣ 11 201017828 係為可形成載子(電子、電洞…等)躍遷或穿隧阻障效果的 非導電性膜層,其可為該半導體基材(80)的氧化物、氮化 物…等。本較佳實施例係採用單晶(1〇〇)的p型矽晶圓作為 ,該半導體基材(80),其經過標準的RCA清洗後,該半導體 基材(8〇)經過熱氧化處理在常壓化學氣相沉積(APCVD)爐 嘗/几積5奈米的矽氧化層而為該穿隧障壁層(81)。 該形成錮矽薄膜(20)步驟,請參閱第二B圖所示,基 於金屬奈米晶體選擇較高功函數會造成較深的位勢井 (potential wan),可增加資料保存時間而不會犧牲載子注 入效率。而更尚的能態密度(Dens丨ty 〇f state)使得金屬奈 米晶體記憶體可儲存較多的資料。因此,可以選擇高功函 數的金屬材料來製造奈米晶體。而鉬(Mo,molybdenum) 具有尚恤熱穩定性、高功函數(w〇rk functi〇n)且為半導體 工業常用的材料等優點,故選用鉬作為非揮發性記憶元件 的奈米晶體。為了讓鉬最後能夠形成奈米晶體以用於儲存 載子,於本步驟(2〇)中,可利用各種物理或化學氣相沉積 之製程及裝置(CVD、PVD)進行鍍膜,例如利用雙電子搶 (Dual E-Gun)以相同或不同的鍍率共同蒸鍍鉬、矽材料於 該穿隧障壁層(81)之表層,或者將鉬·矽合靶以各種濺鍍方 式(直〃IL、父流、脈衝、磁控、離子輔助、電漿輔助…等) 鍵製於該穿隧障壁層(81)。本實施例採用直流濺鍍方式, 在通入所需之製程氣體(例如:Ar : 24sccm,〇2 : 2 seem) 及控制腔内壓力於數個mtorr(例如:7.6mt〇r「以下)之製程 環境下,利用鉬矽化物(MoSid以及矽靶分別施予4〇及 12 201017828 50Watt(使鉬與矽的比例約為一比三)沉積約5-1 〇奈米的一 鉬矽化合物薄膜(82)於該穿隧障壁層(81 )上。 該形成控制介電層(30)步驟中,請參閱第二c圖所示, .係可以如前所述的物理或化學氣相沉積方式形成一控制介 電層(83)於該鉬矽化合物薄膜(82)表面,該控制介電層(83) 可為氮化物、氧化物等,本較佳實施步驟係以電漿輔助化 學氣相沉積(PECVD)之裝置,在環境溫度於3〇〇〇c左右進 行材質為氧化矽的控制介電層(83),本較佳實施例之該控 制介電層(83)之厚度約於30nm。 該析成翻奈米晶體(40)步驟,請參閱第二〇圖所示, 為了讓該鉬矽化合物薄膜(82)内析出複數個鉬奈米晶體 (821)以為非揮發性s己憶體元件之懸浮閘,可利用各種退火 或加熱(快速熱退火Rapid Therma丨Annea丨jng(RTA)、雷 ^退火、&爐管退火…等)的方式,在非反應氣體或反應氣體 (氮氣、氬氣、氧氣...等)的環境下,將已完成前述步驟的 •非揮發性記憶元件整體或該鉬矽化合物薄膜(82)進行加 …、使該鉬矽化合物薄膜(82)析出該鉬奈米晶體(821)。本 較佳實施步驟採用RTA的方式’在刪t左右進行熱退火, -退火時間為60秒’所析出的該翻奈米晶體(82 ^)尺寸約 於 5nm。 進一步地,本步驟(40)亦可於完錢形成控制介電 (30)步驟之前進行’換言之’係於完成該形 步驟後,直接對所完成之劫_ 4 ^ 厅成之該鉬矽化合物薄膜(82)進行該 奈米晶體(8 21)之析出制兹 析I稳,例如以雷射退火(Lai 13 201017828 eal>ng)方式對該翻石夕化合物薄膜進行析出製程。 前述lit電極(5Q)步驟中,請參閱第二E圖所示,係於 導電金屬元t後1用前述的物理或化學氣相沉積或其他 步電錢、元素置換、塗佈…等)在完成前述 ㈣後的該控制介電層(83)之表面及該半導體基材(8〇)之 ❹ &面分別形成導電電極層㈣,本較佳實施例之導電電極 層(84)利用熱阻絲蒸錢系統(τ|ι_3| c〇ater)在非揮發性 記憶體^成品之兩面鑛上銘電極。另夕卜’在本步驟(50)的 過程’若有需要對該導電電極層(84)進行電路佈局規劃, 則可以利用光微影製程或金屬㉟罩製程將該導電電極層(84) 形成特定圖形或電路。 為了證實前述步驟所完成的非揮發性記憶體之各種效 果’分別請參考第三〜十圖; 第二圖為析成鉬奈米晶體(4〇)步驟完成後之穿透式電 子顯微鏡(TEΜ)之照相結果,由複數個鉬奈米晶體(82彳)析 出於該鉬矽化合物薄膜(82)可知,本較佳實施例之退火方 法確實能夠有效析出形成該鉬奈米晶體(821)。 第四Α圖以及第四Β圖為在不同退火溫度下(步驟 40) ’該非揮發性記憶元件之電容-電壓的記憶視窗電性圖, 可發現在退火溫度900度下其記憶視窗較退火溫度8〇〇度 下來的大。 第五A圖以及第五B圖’分別為鉬元素3〇f軌域(第五 A圖)和氧元素(第五b圖)1s軌域在原生(As-deposited)、 退火溫度800度和900度(執行步驟40之後)的XPS分析 14 201017828 圖’在鉬3cf軌域中可觀察到隨著退火溫度的上升其訊號 從含有些Mo-Ο和M〇訊號漸漸被還原成M〇訊號。這個 現象使得在退火900度時造成其記憶視窗較大。同樣地, . 從氧1s軌域中可觀察到隨著退火溫度的上升其3ί〇χ訊號 漸漸向束缚能大的方向移動,而當退火到9〇〇度時,則是 為一個鍵結較好的Si〇2訊號。所以可推測大部份的矽很容 易和氧鍵結成Si〇2並包覆在鉬奈米晶體周圍,造成奈米晶 ❹體間有較佳的隔離效果,避免過多漏電路徑的產生。從以 上的XPS分析可發現在高溫退火9〇〇度後,其奈米晶體 利用金屬鉬來進行儲存機制,同時也使的氧化矽的品質變 好。在電荷保存時間方面,利用閘極電壓1 〇伏特5秒下 測試其特性,能發現在退火900度後其電荷保存時間到十 年時還剩下67〇/〇,明顯較退火800度後電荷保存時間剩下 41 %來的好,如第六圖所示。 第七A、B圖為本較佳實施例在耐操度(endu「ance)方 面,利用閘極電壓5伏特10微秒下測試其特性,發現在 退火900度後其耐操度到! 〇6次約剩下54%的電荷明顯 較退火800度後的好。根據電荷保存時間和耐操度能發 現在退火900度後特性變好。其原因可能是由於氧化矽的 品質提升’使得電荷比較不易逃脫,整個特性獲得改善。 進一步地,該析成鉬奈米晶體(40)步驟亦可包含其他 不同的半導體製程處理方式,讓非揮發性記憶元件可以獲 得不同的效果,例如電漿處理(piasma treatment )等且 在執行電漿處理製程時,可以通入不同的氣體,例如氨氣。 15 201017828 本發明之另一較佳實施例係在完成熱退火製程之後,再利 用電漿輔助化學氣相沉積系統(PECVD)在通入3〇〇sccm氨 氣和氫氣在1〇〇瓦功率環境下處理3〇分鐘左右,使用電 •漿乜補漏電路徑與缺陷,以下分述經過電漿處理後的各種 結果。 凊參可第八A、B圖,其為鉬奈米晶體於氧化矽中有 無、,.里過氨電漿處理的電容.電壓特性圖比較,可發現在閉極 ❹電麼於1 0V至-1 〇v掃描時,經過處理後其記憶視窗明顯 較未處理前來的小。但如第九圖所示,經過氨電漿處理後 其電荷保存特性可到十年時還剩下85%的電荷,明顯較未 處理前到十年時剩下67%的電荷的特性優異。另外,在漏 電流特性方面,在做完氨電漿處理後整個漏電流明顯下 降,如第十圖所示。 【圖式簡單說明】 0 第一圖為本發明較佳實施例之流程圖。 第二圖為本發明較佳實施例之流程步驟示意圖。 第三圖為本發明較佳實施例之穿透式電子顯微鏡照相 圖0 第四A、B圖為本發明較佳實施例之電容·電壓特性圓。 第五A、B圖為本發明較佳實施例之鉬矽化合物薄膜 之X射線光子能譜(XPS)圖。 第六圖為本發明較佳實施例之電荷保存時間量測結果 16 201017828 第七A、B @為本發明較佳實施 财操度量測結果示意圖。 之非揮發性 第八A、B圖為本發明較佳實施 容-電壓特性圖。 紙电水處 記憶體 理的電 圖 圖 第九圖為本發明較佳實施例之 子将性量洌結果 第十圖為本發明較佳實施例之電荷保存特 ❹ 性量測結果 第十一圖為習用之一 非揮發性記憶體結構示意圖 第十二圖為習用之一奈米晶體記憶體結構示意圖 【主要元件符號說明】 (8〇)半導體基材 (81)穿隧障壁層 (8 2)翻石夕化合物薄膜 (821)翻奈米晶體 (83) 控制介電層 (84) 導電電極層 (90) 快閃記憶體 (91) 浮停閘極 (92) 通道 (93) 二氧化矽 (9 5)奈米晶體記憶體元件 (951)穿隧氧化層 17 201017828 (952) 奈米晶體 (953) 氧化絕緣層Please refer to the first figure and the second A to IIE drawings, which are non-volatile memory elements having a molybdenum nano crystal structure layer and a preferred embodiment thereof. The method for manufacturing a non-volatile memory of a crystal structure layer includes the steps of: forming a tunnel barrier layer, forming a molybdenum-ruthenium film (20), forming a control dielectric layer (3〇), and forming a molybdenum nanocrystal _ and An electrode (50) is fabricated. In the step of forming the tunnel barrier layer (10), as shown in FIG. 2A, a semiconductor substrate (8〇) is selected, which is subjected to a standard cleaning process to remove surface impurities, contaminants or native oxide layers (Native). After 〇xjde Layer), a tunnel barrier layer (81) is formed on the semi-conductive substrate _ the surface to be cleaned by the film growth apparatus. The semiconductor substrate (8 Å) can be a monocrystalline, single crystal or polycrystalline or amorphous semiconductor substrate (such as a germanium substrate or a tri-five compound semiconductor substrate, such as gallium-consuming); the so-called standard cleaning process can be - RCA standard process; the so-called film growth device can be - physical vapor deposition (PVD, sputter · ·, etc.) or - chemical vapor deposition devices (such as PECVD, ThermalCVD, ApcvD, etc.); the wear barrier layer (4) 11 201017828 is a non-conductive film layer capable of forming a carrier (electron, hole, etc.) transition or tunneling barrier effect, which may be an oxide, a nitride, or the like of the semiconductor substrate (80). In the preferred embodiment, a single crystal (1 Å) p-type germanium wafer is used as the semiconductor substrate (80), which is subjected to thermal oxidation treatment after being cleaned by standard RCA. The tunneling barrier layer (81) is a layer of 5 nm tantalum oxide layer in an atmospheric pressure chemical vapor deposition (APCVD) furnace. The step of forming the ruthenium film (20), as shown in the second B diagram, selecting a higher work function based on the metal nanocrystal will result in a deep potential wan, which can increase the data retention time without sacrificing Carrier injection efficiency. The more Dens丨ty 〇f state allows the metal nanocrystal memory to store more data. Therefore, a high work function metal material can be selected to produce a nanocrystal. Molybdenum (Mo, molybdenum) has the advantages of thermal stability, high work function and materials commonly used in the semiconductor industry. Therefore, molybdenum is used as a nanocrystal of non-volatile memory elements. In order to allow molybdenum to finally form nanocrystals for storage of carriers, in this step (2), various physical or chemical vapor deposition processes and devices (CVD, PVD) can be used for coating, for example, using two electrons. Dual E-Gun co-deposits molybdenum and tantalum materials on the surface layer of the tunnel barrier layer (81) at the same or different plating rates, or uses various sputtering methods for the molybdenum/ruthenium target (straight 〃IL, Parent flow, pulse, magnetron, ion assist, plasma assist, etc.) are bonded to the tunnel barrier layer (81). In this embodiment, DC sputtering is used to pass the required process gas (for example, Ar: 24 sccm, 〇 2 : 2 seem) and the pressure in the control chamber to several mtorr (for example, 7.6 mt 「r or less). In the process environment, a molybdenum telluride compound (MoSid and ruthenium target were respectively applied to 4〇 and 12 201017828 50Watt (the ratio of molybdenum to niobium was about one to three) to deposit a 5-1 〇 nanometer-aluminum ruthenium compound film ( 82) on the tunnel barrier layer (81). In the step of forming the control dielectric layer (30), please refer to the second c diagram, which can be formed by physical or chemical vapor deposition as described above. A control dielectric layer (83) is on the surface of the molybdenum-ruthenium compound film (82), and the control dielectric layer (83) may be a nitride, an oxide, etc., and the preferred embodiment is plasma-assisted chemical vapor deposition. The device (PECVD) has a control dielectric layer (83) made of yttrium oxide at an ambient temperature of about 3 〇〇〇c. The thickness of the control dielectric layer (83) of the preferred embodiment is about 30 nm. The step of crystallizing the nanocrystal (40), as shown in the second figure, in order to make the molybdenum compound A plurality of molybdenum nanocrystals (821) are precipitated in the film (82) as a suspension gate of the non-volatile simon element, and various annealing or heating can be utilized (rapid thermal annealing Rapid Therma丨Annea丨jng (RTA), Ray ^ Annealing, & furnace annealing, etc., in the environment of non-reactive gas or reaction gas (nitrogen, argon, oxygen, etc.), the non-volatile memory element that has completed the above steps as a whole or The molybdenum ruthenium compound film (82) is subjected to addition, and the molybdenum ruthenium compound film (82) is precipitated into the molybdenum nanocrystal (821). The preferred embodiment uses the RTA method to perform thermal annealing at about t. The nanocrystalline crystal (82^) precipitated at an annealing time of 60 seconds is about 5 nm. Further, this step (40) can also be performed in the 'in other words' section before the control dielectric (30) step is completed. After the completion of the step, the nanocrystalline crystal (82) is directly deposited on the finished molybdenum ruthenium compound film (82), for example, by laser annealing (for example, by laser annealing) Lai 13 201017828 eal>ng) way to the film In the step of the lit electrode (5Q), please refer to the second E diagram, after the conductive metal element t, 1 using the aforementioned physical or chemical vapor deposition or other step money, element replacement, coating... And forming a conductive electrode layer (4) on the surface of the control dielectric layer (83) after the completion of the foregoing (4) and the surface of the semiconductor substrate (8), and the conductive electrode layer (84) of the preferred embodiment Using the heat-resistance wire steaming system (τ|ι_3| c〇ater) on the two sides of the non-volatile memory ^ finished product. In addition, in the process of this step (50), if it is necessary to perform circuit layout planning on the conductive electrode layer (84), the conductive electrode layer (84) may be formed by a photolithography process or a metal 35 mask process. Specific graphics or circuits. In order to confirm the various effects of the non-volatile memory completed in the previous steps, please refer to the third to tenth views respectively; the second figure is the transmission electron microscope after the completion of the step of forming a molybdenum nanocrystal (4〇) (TEΜ) As a result of the photographic process, it is known that the plurality of molybdenum nanocrystals (82 Å) are precipitated from the molybdenum ruthenium compound film (82), and the annealing method of the preferred embodiment can effectively precipitate the molybdenum nanocrystals (821). The fourth and fourth maps are memory-electrical diagrams of the capacitance-voltage of the non-volatile memory element at different annealing temperatures (step 40). It can be found that the memory window has an annealing temperature at an annealing temperature of 900 degrees. 8 big down. The fifth A map and the fifth B graph are respectively the molybdenum element 3〇f orbital (fifth A picture) and the oxygen element (fifth b picture) 1s orbital domain in the as-deposited, annealing temperature of 800 degrees and XPS analysis of 900 degrees (after performing step 40) 201017828 Figure 'In the molybdenum 3cf trajectory, it can be observed that as the annealing temperature increases, the signal is gradually reduced from the Mo-Ο and M〇 signals to the M〇 signal. This phenomenon causes a large memory window when it is annealed at 900 degrees. Similarly, it can be observed from the oxygen 1s orbital domain that as the annealing temperature increases, the 3ί〇χ signal gradually shifts toward the binding energy, and when it is annealed to 9 degrees, it is a bond. Good Si〇2 signal. Therefore, it is presumed that most of the ruthenium is easily bonded to the oxygen-bonded Si〇2 and coated around the molybdenum nanocrystals, resulting in better isolation between the nanocrystalline bodies and avoiding excessive leakage paths. From the above XPS analysis, it was found that after annealing at a high temperature of 9 deg., the nanocrystals were made of metal molybdenum for storage, and the quality of yttrium oxide was also improved. In terms of charge retention time, the characteristics of the gate voltage were measured using a gate voltage of 1 volt volt for 5 seconds. It can be found that after annealing at 900 degrees, the charge retention time remains at 67 〇/〇 after ten years, which is significantly higher than that after annealing at 800 degrees. The remaining 41% of the save time is good, as shown in the sixth picture. The seventh and fourth graphs of the present embodiment are tested for their endurance in terms of endurance, using a gate voltage of 5 volts at 10 microseconds, and found that the resistance is up to 900 degrees after annealing. The charge of about 54% of the 6 times is obviously better than that of 800 degree after annealing. According to the charge retention time and the resistance, it can be found that the characteristics become better after annealing at 900 degrees. The reason may be due to the improved quality of yttrium oxide. It is not easy to escape, and the whole characteristics are improved. Further, the step of forming a molybdenum nanocrystal (40) may also include other different semiconductor processing methods, so that non-volatile memory elements can obtain different effects, such as plasma processing. (piasma treatment), etc., and when performing a plasma treatment process, different gases, such as ammonia, may be introduced. 15 201017828 Another preferred embodiment of the present invention utilizes plasma assisted chemistry after completion of the thermal annealing process. The vapor deposition system (PECVD) is treated with 3 〇〇 sccm of ammonia gas and hydrogen gas in a power environment of 1 watt for about 3 minutes, using electric and slurry to compensate for leakage paths and defects. Various results after plasma treatment. The ginseng can be the eighth and fourth graphs, which are the presence or absence of molybdenum nanocrystals in yttrium oxide, and the capacitance of the ammonia plasma treatment. Comparison of voltage characteristics can be found in When the plasma is turned from 10 V to -1 〇v, the memory window is obviously smaller than that of the untreated one. However, as shown in the ninth figure, the charge storage characteristics after ammonia plasma treatment can be By the end of ten years, 85% of the charge is left, which is significantly better than the 67% of the charge remaining from the untreated to ten years. In addition, in terms of leakage current characteristics, the entire leakage current after the ammonia plasma treatment is completed. The first figure is a flow chart of a preferred embodiment of the present invention. The second figure is a schematic flow chart of a preferred embodiment of the present invention. Transmissive Electron Microscope Photograph of the Preferred Embodiment of the Invention FIG. 4A and B are diagrams showing a capacitor/voltage characteristic circle according to a preferred embodiment of the present invention. FIGS. 5A and B are diagrams showing molybdenum according to a preferred embodiment of the present invention. X-ray photon spectroscopy (XPS) image of bismuth compound film. The charge storage time measurement result of the preferred embodiment 16 201017828 The seventh A, B @ is a schematic diagram of the financial measurement measurement result of the preferred implementation of the present invention. The non-volatile eighth and fourth diagrams are the preferred embodiments of the present invention. - Voltage characteristic diagram. Electrogram of memory material at paper electro-hydraulic ninth diagram is a sub-graph of the preferred embodiment of the present invention. The tenth figure is a charge-preserving characteristic measurement according to a preferred embodiment of the present invention. Results Figure 11 is a schematic diagram of one of the non-volatile memory structures used in the twelfth. Figure 12 is a schematic diagram of the memory structure of one of the nano crystals. [Main component symbol description] (8〇) Semiconductor substrate (81) tunneling barrier Layer (8 2) Turning Compound Film (821) Turning Nano Crystal (83) Control Dielectric Layer (84) Conductive Electrode Layer (90) Flash Memory (91) Floating Gate (92) Channel (93 ) cerium oxide (9 5) nanocrystal memory element (951) tunneling oxide layer 17 201017828 (952) nanocrystal (953) oxidized insulating layer

Claims (1)

201017828 十、申請專利範圍·· 的非揮發性記憶元件, 1·一種具有鉬奈求晶體結構層 其包含: 一基板; 一穿隧障壁層 一鉬矽薄膜, 數個鉬奈米晶體; ,其形成於該基板表面; 其形成於該穿隧障壁層表面,其包含複201017828 X. The non-volatile memory component of the patent application scope, 1. A crystal structure layer having a molybdenum nanocrystal comprising: a substrate; a tunneling barrier layer-a molybdenum-ruthenium film, and a plurality of molybdenum nanocrystals; Formed on the surface of the substrate; formed on the surface of the tunnel barrier layer, including 一控制介質層,其形成於該鉬矽薄膜表;以及 二分別形成於基板及控制介質層表面之電極。 2.如申請專利範圍帛!項所述之具有鉬 :層的非揮發性記憶元件,該基板係為一單::: 體基材 '非晶半導體基材、摻雜施授體:半導:體: 早7L半導體基材或多元半導體基材。 體結 晶體 槿恳 申請專利_ 1項所述之具有銷奈米晶 π的非揮發性記憶元件,該鉬矽薄膜内的各翻奈米 可為析出之鉬金屬或鉬矽化合物。 項所述之具有鉬奈米晶體結 該控制介質層為氮化物或氧化 4.如申請專利範圍第 構層的非揮發性記憶元件, 物薄膜。 5.如申請專利範圍第13戈2或3或4項所述之具有 τ'米日日幾結構層的非揮發性記憶元件,其中. 該控制介質層為矽氧化物薄膜; 該基材為Ρ型矽基板;以及 該電極為鋁材質電極層。 19 201017828 6 ·如申請專利範圍第5 構層的非揮發性記憶元件,其中: 該控制介質層為厚度為30奈米;以及 該翻石夕薄臈厚度為5至1〇奈米。 項所述之具有鉬奈米晶體結 種具有鉬奈米晶體矣 構層的非揮發性記憶元件 之製造方法,其步驟包含: 形成穿隨障壁層,於一半導體基材上形成-穿隧阻障 層; ❹ 層; 形成銦矽薄骐,於該㈣阻障層上鍍製一钥石夕薄 膜 形成控制介電層 薄膜; 於該鉬矽薄膜層上鍍製一控制介電 析成銘奈米晶ϋ,係於完成銀製控制介電薄膜之前或 =後對該㈣薄膜執行一錮奈米晶體析出製程,使該㈣ 薄膜内形成複數個鉬奈米晶體;以及a control dielectric layer formed on the molybdenum tantalum film sheet; and two electrodes respectively formed on the substrate and the surface of the control medium layer. 2. If you apply for a patent scope! The non-volatile memory element having a molybdenum: layer, the substrate is a single::: body substrate 'amorphous semiconductor substrate, doped donor body: semi-conductive body: body: 7L early semiconductor substrate Or a multi-component semiconductor substrate. Body No. Crystal 槿恳 A non-volatile memory element having a nanocrystalline π as described in claim 1, wherein each of the nanometers in the molybdenum tantalum film may be a precipitated molybdenum metal or molybdenum ruthenium compound. The invention has a molybdenum nanocrystal junction. The control dielectric layer is nitride or oxidized. 4. A non-volatile memory element, as described in the patent application. 5. A non-volatile memory element having a τ'm-day structural layer as described in claim 13 or 2 or 4, wherein the control medium layer is a tantalum oxide film; a crucible type substrate; and the electrode is an aluminum electrode layer. 19 201017828 6 • A non-volatile memory element as claimed in the fifth aspect of the patent application, wherein: the control medium layer has a thickness of 30 nm; and the turnstone has a thickness of 5 to 1 nm. The method for manufacturing a non-volatile memory element having a molybdenum nanocrystal crystal having a molybdenum nanocrystal layer, wherein the step comprises: forming a via barrier layer to form a tunneling resistance on a semiconductor substrate a barrier layer; a germanium layer; forming an indium tantalum thin tantalum, and plating a key film on the (four) barrier layer to form a control dielectric layer film; plating a controlled dielectric layer on the molybdenum tantalum film layer a wafer crystallizing process for performing a nanocrystalline crystal precipitation process on the (four) film before or after the completion of the silver controlled dielectric film, so that a plurality of molybdenum nanocrystals are formed in the (4) film; 製作電極,係分別於該半導體基材以及該控制介電層 鍍製一電極》 8.如申請專利範圍第7項所述之具有鉬奈米晶體結 構層的非揮發性記憶元件之製造方法,該形成穿隧障壁層° 步驟係以一物理氣相沉積或一化學氣相沉積裝置鍍製該^ 導體基材之氧化物或氮化物。 9 .如申請專利範圍第7項所述之具有鉬奈米晶體幹 構層的非揮發性記憶元件之製造方法,該形成鉬妙薄膜: 驟係以一物理氣相沉積或一化學氣相沉積裝置將—翻 '夕化 201017828 合物形成於該穿隧障壁層。 10.如申請專利範圍第7項所述之具有銦奈米晶體社 構層的非揮發性記情袢 、’° 4 法,該形成控制介電層 步驟係以一物理翁夫曰、,拉_ + 礼相'儿積或一化學氣相沉積裝置將一氧化 物或氮化㈣膜形成於㈣㈣料面。 11 .如申請專利範圍第7項所述之具有钥奈米晶體結 構層的非揮發性記憶元件之製 ^ _ 忭心表4方法,該製作電極係採用 物理氣相沉積製程。 12 _如以專利範圍第7項所述之具有铜奈米晶體杜 構層的非揮發性記憶元件之製造方法,該後處料 —快速熱退火製程。 你為 、13·如巾請專利範圍第8或9或⑺或彳彳或12項所 述之具有钥奈米晶體結構層的非揮發性記憶元件之製造方 法,該形成穿随障壁層步驟係先以一標準清洗製程處理該 半導體基材後,再形成該穿隧阻障層。 14.如申請專利範圍第8或9或1〇或^或12項所 述之具有翻奈米晶體結構層的非揮發性記憶元件之製造方 法,其中: 形成該穿隧阻障層係以一電衆輔助氣相沉積或一熱爐 管化學氣相沉積製程,通入氧氣或氮氣形成該 美 的氧化物或氮化物層;以及 土材 該形成鉬矽薄膜係利用雙電子搶分別蒸鍍鉬、矽靶 村,或利用減鑛方式將翻石夕複合乾鍍製於該穿随阻障層表 面。 21 201017828 =·如申請專利範” 14項所述之具有㈣米晶體 'Γ構層的非揮發性記憶元件之製造方法,纟中該快速熱退 火製程溫度介於800〜900度。 16.如申請專利範圍第15項所述之具有翻奈米晶體 結構層的非揮發性記憶元件之製造方法,該析成銷奈米晶 沉m + 乂電漿輔助化學氣相 '儿積方式’在通人氨氣或氫氣或氮氣切境下,對 ❹ 姻石夕薄膜層之半導體基材進行電漿處理。 u 十一、囷式: 如次頁。 ❹ 22An electrode is formed by plating an electrode on the semiconductor substrate and the control dielectric layer respectively. 8. A method for manufacturing a non-volatile memory element having a molybdenum nanocrystal structure layer according to claim 7 of the patent application, The step of forming a tunnel barrier layer is performed by plating a oxide or nitride of the conductor substrate by a physical vapor deposition or a chemical vapor deposition apparatus. 9. The method for producing a non-volatile memory element having a molybdenum nanocrystal dry layer as described in claim 7, wherein the molybdenum film is formed by a physical vapor deposition or a chemical vapor deposition The device forms a layer of the tunneling barrier layer. 10. The non-volatile enthalpy, '° 4 method having a layer of indium nanocrystals as described in claim 7 of the patent application scope, wherein the step of forming the control dielectric layer is a physical Wengfu, pull _ + The ritual 'or product or a chemical vapor deposition device forms a film of oxide or nitride (4) on the (4) (iv) material plane. 11. The method of manufacturing a non-volatile memory element having a key crystal structure layer as described in claim 7 of the patent application, wherein the electrode is formed by a physical vapor deposition process. 12 _ A method for producing a non-volatile memory element having a copper nanocrystal layer as described in claim 7 of the patent, which is a rapid thermal annealing process. You are a method for manufacturing a non-volatile memory element having a key crystal structure layer as described in claim 8 or 9 or (7) or 彳彳 or 12, which is a stepper layer forming step. After the semiconductor substrate is processed by a standard cleaning process, the tunneling barrier layer is formed. 14. The method of manufacturing a non-volatile memory element having a nanocrystalline crystal structure layer according to claim 8 or 9 or 1 or 2 or 12, wherein: forming the tunneling barrier layer is Electric auxiliary vapor deposition or a hot tube chemical vapor deposition process, forming oxygen or nitrogen to form the beautiful oxide or nitride layer; and the soil material to form a molybdenum tantalum film by using two electrons to separately vapor deposit molybdenum,矽 target village, or use the method of reducing ore to dry the composite composite plating on the surface of the barrier layer. 21 201017828 = · As described in the patent application, the method for manufacturing a non-volatile memory element having a (four) meter crystal 'Γ structure layer, as described in Item 14 of the present invention, wherein the rapid thermal annealing process temperature is between 800 and 900 degrees. The method for manufacturing a non-volatile memory element having a nanocrystalline crystal structure layer according to claim 15 of the patent application, wherein the precipitation nano crystal sinking m + 乂 plasma assisted chemical vapor phase Under the condition of human ammonia or hydrogen or nitrogen, the semiconductor substrate of the 石石石膜 layer is subjected to plasma treatment. u 十一, 囷: as the next page. ❹ 22
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