TW201017769A - Transistor structure with suspension type nano-channel and the manufacturing method thereof - Google Patents

Transistor structure with suspension type nano-channel and the manufacturing method thereof Download PDF

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Publication number
TW201017769A
TW201017769A TW097139994A TW97139994A TW201017769A TW 201017769 A TW201017769 A TW 201017769A TW 097139994 A TW097139994 A TW 097139994A TW 97139994 A TW97139994 A TW 97139994A TW 201017769 A TW201017769 A TW 201017769A
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Taiwan
Prior art keywords
channel
substrate
layer
suspended
nanowire channel
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Application number
TW097139994A
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Chinese (zh)
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TWI380376B (en
Inventor
hong-zhi Lin
Jun-Rong Su
Xing-Hui Xu
Guan-Zhang Li
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Univ Nat Chiao Tung
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Priority to TW097139994A priority Critical patent/TW201017769A/en
Priority to US12/314,796 priority patent/US7977755B2/en
Priority to JP2008323971A priority patent/JP4934662B2/en
Publication of TW201017769A publication Critical patent/TW201017769A/en
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Publication of TWI380376B publication Critical patent/TWI380376B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/813—Of specified inorganic semiconductor composition, e.g. periodic table group IV-VI compositions
    • Y10S977/814—Group IV based elements and compounds, e.g. CxSiyGez, porous silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

This invention discloses a transistor structure with suspension type nano-channel and the manufacturing method thereof. It comprises a substrate; a side gate electrode located on the substrate; a dielectric layer covering the substrate and side gate; a suspension type nano-channel located on the sides of side gate having a gap with the dielectric layer; and a source electrode and a drain electrode which are arranged on the dielectric layer and on two sides of the suspension type nano-channel. By the adsorption or separation on the suspension type nano-channel by the electrostatic force of side gate, it can rapidly change the thickness of equivalent side gate dielectric layer so as to cause fast switching or changing the channel threshold voltage of components in the on-off state.

Description

201017769 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種電晶體結構與製造方法，特別是指一種具懸浮式奈 米通道之電晶體結構與其製造方法。 【先前技術】 根據理論’一般元件之次臨界擺幅度（subthresh〇id swing，SS)之最佳 值為60mv/deCade。然而，為使元件有更佳的次臨界擺幅度，而使元件在開 ❹關間具有更大的電流開關比，有微機電（MEMS)結合金氧半場效電晶體 之懸浮閘極電晶想（suspendedgateMOSFET，SG-MOSFET)之結構因應而 生，其懸浮閘極結構提供了可調變之閘極電容，使其之次臨界擺幅度可突 破理論之_ (可至數個mv/deeade) ’細其賴電的結構，使元件的規 模提升許多（為數個微米至數十微米），亦因規模較大，使其在閉極懸浮使 用之钮刻製程也因此有較高難度。 在 N. Abele et al.，IT MEMS Memory Based on Suspended (Jate MOSFET，，，in ❿IEDM，(20〇6)之文獻中曾提出一種利用平面結構與微機電製程，其以乾式選 擇性餘刻去除-犧牲介電層使形成一氣隙於閘極與通道之間的微機電記憶 體’但在此文獻中懸浮部份是閘極，此外由於是使用平面結構，因此在形 成氣麵触相當^肖，且触赋選雜·m方絲断侧再者， 此-文獻中因考慮犧牲介電層氣__難易度，所形成的氣隙厚度相當 厚(>2〇0_，因此需相當高的操作電麼。 再者，中華民國專利公告號以綱之專利文獻中揭露以一種低成本及 可大量製作石夕奈米線之方法，其係將一碎基底以敏化液與活化液進行催化 201017769 處理，使反應金屬原子吸附在該矽基底表面，再將處理後之矽基底浸泡於 一無電鍍酸性鍍液中進行無電鍍沈積，以於矽基底上電鍍沉積出一層含有 催化金屬微粒之金屬層，隨後將此一碎基底置入高溫爐管中，於高溫下催 化金屬微粒與矽基底表面之矽原子在高溫下於金屬/石夕基底界面處熔融形成 液態的矽化物合金，而後透過固態-液態-固態(s〇lid_liquid_s〇lid SLS)化學合 成製程以藉由溫度梯度之變化，促使矽·矽鍵因觸媒效應重新組合排列而堆 疊成矽奈米線。此專利雖能大量製備矽奈米線，但未來在製作電晶體元件 © 時仍會遭遇對準之問題，並且有殘留催化金屬污染疑慮。 在 X. L. Feng et al.，“Very High Frequency Siiic〇n Nan〇wire Electmmechanical Resonators，” Nan〇 Lett，v〇1 7, pp 1953 1959 (2〇们^ 獻為利用氣態·液態-固態(vapor_liquid_s〇lid，心)方式，形成懸浮奈米線之 元件’並研究其振i特性以評估作為振盈器之可行性。此方式主要屬於實 驗室的技術手段’基本上難以準確地定位與對準奈米線之位置，因此在應 用上並不適合於產品的量產。此外，結構本身僅具s_e和她兩電極， 〇 屬於被動元件。 有鑑於對更優良微機電金氧半元件需求的存在，本發明遂針對上述習 知技術之缺失’提出一種勒新且低電壓下即可操作之具懸浮式奈来通道之 電曰a體結構與製4：方法，以有效簡化製程步砸降低成本。 【發明内容】 本發明之主要目的在提供—種具财式奈米通道之電⑽結構與製造 方法’其係利用現有半導趙製程和設備相容之技術，在成本低和步驟簡易 201017769 之製程下’來絲再雜高且可量產化之電晶體結構。 方法本ΓΓΓ目的输—娜輸峨增體結構與製造 門…、糾靜電力_浮式奈米線通道之侧’可達職速改變等效側 2介電層厚度之目的，進而可_於_元件，提升開航件之電流開 本發明之又-目的在提供—種紐料奈料道之電晶體結構與製造 方法，其__極_施赠電力於奈錄通道上，可產纽附或排斥 ©之效果，藉此可改變_極之等效介電層厚度，而_改變通道之起始電 壓，因此，可應用於記憶體元件之運作。 依照本發明提供-種具懸浮式奈米通道之電晶體結構，其包含有一基 底；一位於基底上的側閘極；一覆蓋於基底與側開極上的介電層；一位於 側閘極之側邊的餅式奈树通道，其與介電層間具有—氣隙；以及一源 極電極與-汲極電極’其係設置於介電層上且分設於懸浮式奈米線通道的 兩端。 © 舰本剌之_種賤轉奈細叙電晶體結構之觀方法步驟， 其包含有提供-絲；祕底场成―則極；__與基絲面上依 序形成-介電層與-犧牲層；於犧牲層上形成一多晶石夕層並進行源級極離 子佈植；對多晶石夕層進行圖案化製程，以在侧閘極側壁上形成一奈米線通 道，與在犧牲層上形成分设於奈米線兩端之一源極電極與一波極電極；以 及移除自_電極、麵電極與奈鱗麟Μ犧牲層，以使奈米線通道 成為懸浮狀態。 201017769 底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術内 容、特點及其所達成之功效。 【實施方式】 清參閲第1圖，其係本發明實施例之具懸浮式奈米通道之電晶體的結 構示意圖。如_示，本發明之具鮮式奈米通道之電晶體H)包含有一基 底12 ’其上有一作為絕緣層的熱氧化層14 ;熱氧化層14之表面有一側閘 極16 ’· 一覆蓋於側閘極16與熱氧化層14上的介電層2〇 ;至少一位於侧閘 ©極16之側邊上的懸浮式奈米線通道a，其與介電層間具有一氣隙^ ; 以及-源極電極24與一汲極電極％，其係設置於介電層上且分設於懸 浮式奈米線通道22的兩端。 、述之基底可以;^夕基底，側閘極之材質為多晶♦，而源極電極 24無極電極26之材f是經過源極/祕離子佈植後的多_。懸浮式奈 米線通道22之結晶態可以是多晶或者經過低溫再結晶技術處理後之單晶。 介電層之材質係可為氮化矽或者氧化矽。 ❹ 此外，源極電極24與祕電極26之底面更具有一犧牲層28，以作為 與介電層之接面。 接續’係針對上述本發明之具懸浮式奈米通道之電晶體結構之製作流 程進行說明。 請-併參閲第2〜6圖’其係本發明之具懸浮式奈米通道之電晶體結構 的装作流程示意圖。首先如第2圖所示’提供一硬基底12，並神基底Ο 上依序形成-作為絕緣層之熱氧化層14，與_多_層15 ;接續如第3圖 201017769 所不，對多晶石夕層15進行圖案化製程，以定義出侧閘極（side-gate)結構 16 ’再如第4圖所示’再於頂表面上依序沉積一介電層2〇、一與介電層扨 具有不同钱刻選擇比的犧牲層28與一多晶石夕層3〇 ;然後對多晶石夕層 進行源極離子输與錄離子舰，再個微影與非等向性侧在側間極 關壁之犧牲層Μ上形成奈㈣通道22 時定義出位於犧牲層π上的 源極電極24與及極電極26結構，如第5圖所示；最後，利用選擇性侧 的方式，來侧掉自源極、祕電極24、26與奈求線通道22顯露出的犧 ©牲層28 ’以使奈米線通道22成為懸浮狀態，而獲得如第6圖所示之具懸浮 式奈米通道之電晶體結構1〇。 更者，可棚低溫再結晶技術㈣浮式奈米線通道之結晶狀態由多晶 態轉變為高品質的單晶態，以提升操作時通道之可靠性。 由上述製造方法步驟可發現本發明依現有半導體製造方法和與現有半 導體設備相容之技術，利用與蝕刻閘極邊襯相同之方法，以非等向性餘刻 多轉’並調整__，使其_至奈鱗級，顧極兩側形成邊概狀 ©多晶秒奈米線通道，藉由触刻條件調控奈米線通道尺寸至1〇〇啦（奈米） 以下，且在成本低和步驟簡易之製造方法下，完成重複性高且可量產化之 懸浮式奈米線通道元件製作《•因此本發明之具懸浮式奈米線通道之電晶體 結構結構與製造’可以解決現今奈米線電子元件製作不易或需高成本和高 技術門檻之問題。 請參閱第7麟示’在本發明之賤浮式奈米通道之電晶體結構中， 由於奈米線通道躲浮之結構’因此，删齡懸浮式奈米線通道間除 201017769 、…層、卜另存在層空氣作為介電質。利用湖極電壓施以靜電力於懸 浮式’丁、米線通道上，可產生崎或排斥之效果，藉此可改變侧極之等效 介電層厚度’而達到改變通道之起始電壓，因此，可應用於記憶體元件之 運作。 再者本案發明之具懸浮式奈米通道之電晶體結構亦可應用於開關元 件之操作’其主要原因是靜電力對懸浮式奈米線通道之作用，可達到快速 變等效側祕介電層厚度之目的，躺使元件在開關狀態上快速切換， ©亦因等效於側閘極介電層厚度改變，而提升元件之電流開關比。 鑑此，本發明之具懸浮式奈米線通道之電晶體在操作時會由於閘靜電 力的作用如果疋吸引力的話，懸浮奈米線通道會被吸近接觸間極侧壁上 的閉介電層’斥力齡分離鱗奈親通道，在條上會呈現兩種不同的 邏輯態’如第7 @所tf。因此’本㈣之結構可祕關元件或記憶體元 件之應用。 •综上所述’本發明提出一種具懸浮式奈米通道之電晶體結構與製造方 ©法’其係現有半導體製程和設備相容之技術，在成本低和步驟簡易之 製故方法下’完成重複性高且可量產化之具懸浮式奈米通道之電晶體結 構。再者，本發明為微機電結合電晶趙之結構，其側閘極電容為可變電容， 在讀關閉狀態時，因空氣介電層之存在，可使元件關閉電流極低，進而 使功率消耗降低’而可於低電壓操作環境下運作，並提高元件的可靠度。 唯以上所述者，僅為本發明之較佳實施例而已，並非用來限定本發明 實施之範圍。故即凡依本發明申請範圍所述之特徵及精神所為之均等變化 201017769 或修飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 第1圖係本發明之具懸浮式奈米通道之電晶體的結構示意圖。 第2〜6圖係本發明之具懸浮式奈米通道之電晶體結構的製作流程示意圖。 第7圖係本發明之具懸浮式奈米通道之電晶體的電性圖。 【主要元件符號說明】 10具懸浮式奈米通道之電晶體 ❹ 12基底 14熱氧化層 15多晶矽層 16側閘極 20介電層 22懸浮式奈米線通道 24源極電極 〇 26源極電極 28犧牲層[Technical Field] The present invention relates to a crystal structure and a manufacturing method, and more particularly to a crystal structure having a suspended nanochannel and a method of fabricating the same. [Prior Art] According to the theory, the optimum value of the sub-threshold swing (SS) of the general component is 60 mv/deCade. However, in order to make the component have a better sub-critical swing amplitude and make the component have a larger current switching ratio between the opening and closing, there is a micro-electromechanical (MEMS) combined with a gold-oxygen half-field effect transistor. The structure of the (suspended gateMOSFET, SG-MOSFET) is due to its structure, and its floating gate structure provides a variable gate capacitance, so that its sub-threshold amplitude can break through the theory _ (can be several mv/deeade) The structure of the electric system makes the size of the components much larger (several micrometers to tens of micrometers), and because of its large scale, it is also more difficult to make the button engraving process in the closed-pole suspension. In N. Abele et al., IT MEMS Memory Based on Suspended (Jate MOSFET,,, in ❿ IEDM, (20〇6), a planar structure and microelectromechanical process has been proposed, which is removed by dry selective etching. - sacrificing the dielectric layer to form an air gap between the gate and the channel of the microelectromechanical memory 'but in this document the suspension part is the gate, and in addition to the use of a planar structure, the formation of the gas surface is quite In addition, the thickness of the air gap formed by the dielectric layer is relatively thick (>2〇0_, so it needs to be quite high) Furthermore, the Patent Publication No. of the Republic of China discloses a low-cost and mass-produced method for the production of a Shih Nai line by using a sensitizing solution and an activation solution. Catalyzing 201017769, the reaction metal atoms are adsorbed on the surface of the crucible substrate, and the treated crucible substrate is immersed in an electroless plating bath for electroless deposition to deposit a layer of catalytic metal particles on the crucible substrate. Metal layer Subsequently, the crushed substrate is placed in a high-temperature furnace tube, and at a high temperature, the ruthenium atoms on the surface of the ruthenium metal substrate and the ruthenium substrate are melted at a high temperature at a metal/stone substrate to form a liquid bismuth alloy, and then passed through a solid-liquid state. - Solid state (s〇lid_liquid_s〇lid SLS) chemical synthesis process to promote the stacking of tantalum nanowires by recombination of the 矽·矽 bond due to the catalytic effect by the change of temperature gradient. This patent can prepare a large amount of 矽 nanometer. Wire, but there will still be problems with alignment in the future when making the transistor component ©, and there are concerns about residual catalytic metal contamination. In XL Feng et al., “Very High Frequency Siiic〇n Nan〇wire Electm Mechanical Resonators,” Nan〇 Lett, v〇1 7, pp 1953 1959 (2 we ^ to use the vapor-liquid_s〇lid (heart) method to form the element of the suspended nanowire' and study its vibration characteristics to evaluate as vibration The feasibility of the device. This method is mainly related to the technical means of the laboratory 'it is basically difficult to accurately locate and align the position of the nanowire, so it is not suitable for the product in application. In addition, the structure itself has only s_e and her two electrodes, and 〇 is a passive component. In view of the existence of a demand for a finer micro-electromechanical gold-oxygen half-element, the present invention proposes a kind of leap against the above-mentioned shortcomings of the prior art. The new and low-voltage operation of the suspension type Nylon channel can be operated to reduce the cost by effectively simplifying the process steps. [Summary of the Invention] The main object of the present invention is to provide a tool The structure and manufacturing method of the financial nano-channels are based on the existing semi-conductor technology and equipment compatibility technology. Under the low cost and simple steps of 201017769, the wire is noisy and can be mass-produced. Crystal structure. The purpose of this invention is to increase the structure and manufacture of the door, and to correct the electrostatic force _ the side of the floating nanowire channel can reach the speed of the equivalent side of the dielectric layer thickness, and then _ component, the current of the lifting part is opened. The purpose of the invention is to provide a crystal structure and manufacturing method of the kind of material, and the __ pole_supplied electric power on the nai channel, can be produced Or reject the effect of ©, thereby changing the thickness of the equivalent dielectric layer of _ pole, and _ changing the starting voltage of the channel, and therefore, can be applied to the operation of the memory element. According to the present invention, there is provided a transistor structure having a suspended nanochannel comprising a substrate; a side gate on the substrate; a dielectric layer covering the substrate and the side opening; and a side gate a side cake nai channel with an air gap between the dielectric layer; and a source electrode and a drain electrode are disposed on the dielectric layer and are respectively disposed on the suspended nanochannel end. © Shipen 剌 _ 贱 贱 奈 奈 奈 叙 叙 叙 叙 叙 叙 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; a sacrificial layer; forming a polycrystalline layer on the sacrificial layer and performing source-level polar ion implantation; patterning the polycrystalline layer to form a nanowire channel on the sidewall of the side gate, A source electrode and a wave electrode disposed at two ends of the nanowire are formed on the sacrificial layer; and the self-electrode, the surface electrode and the sacrificial layer of the N. sylvestris are removed to make the nanowire channel in a suspended state. 201017769 The following is a detailed description of the specific embodiments, and it is easier to understand the purpose, technical contents, features and effects of the present invention. [Embodiment] Referring to Fig. 1, there is shown a schematic view showing the structure of a transistor having a suspended nanochannel according to an embodiment of the present invention. As shown in the figure, the transistor H) of the present invention having a fresh nanochannel includes a substrate 12' having a thermal oxide layer 14 as an insulating layer thereon; and a surface of the thermal oxide layer 14 having a side gate 16'. a dielectric layer 2 on the side gate 16 and the thermal oxide layer 14; at least one floating nanochannel channel a on the side of the side gate © pole 16 having an air gap between the dielectric layer and the dielectric layer; a source electrode 24 and a drain electrode % are disposed on the dielectric layer and are disposed at both ends of the suspended nanowire channel 22. The base can be described; the base of the eve, the material of the side gate is polycrystalline ♦, and the material f of the source electrode 24 of the electrodeless electrode 26 is more than _ after being implanted by the source/secret ion. The crystalline state of the suspended nanowire channel 22 can be polycrystalline or single crystal treated by low temperature recrystallization. The material of the dielectric layer may be tantalum nitride or tantalum oxide. Further, the source electrode 24 and the bottom surface of the secret electrode 26 further have a sacrificial layer 28 as a junction with the dielectric layer. The continuation is directed to the production process of the transistor structure having the suspended nanochannel of the present invention described above. Please also refer to Figures 2 to 6 for a schematic diagram of the fabrication process of the crystal structure of the suspended nanochannel of the present invention. First, as shown in Fig. 2, 'providing a hard substrate 12, and sequentially forming on the substrate -, as the thermal oxide layer 14 of the insulating layer, and _ multi_layer 15; continuing as shown in Fig. 3, 201017769, The spar layer 15 is patterned to define a side-gate structure 16' and then as shown in FIG. 4, a dielectric layer 2, a layer and a dielectric layer are sequentially deposited on the top surface. The electric layer 扨 has different sacrificial layers 28 and a polycrystalline layer 3 〇; then the source ion transport and the recording ion ship, and the lithography and anisotropic side of the polycrystalline layer The formation of the source electrode 24 and the electrode electrode 26 on the sacrificial layer π is defined when the naphthalene channel 22 is formed on the sacrificial layer 侧 of the side interpole wall, as shown in FIG. 5; finally, the selective side is utilized. In a manner, the sacrificial layer 28' exposed from the source, the secret electrode 24, 26 and the nematic line channel 22 is removed, so that the nanowire channel 22 is suspended, and the device shown in Fig. 6 is obtained. The crystal structure of the suspended nanochannel is 1〇. In addition, the low-temperature recrystallization technology can be used. (4) The crystalline state of the floating nanowire channel changes from polycrystalline to high-quality single crystal to improve the reliability of the channel during operation. From the above manufacturing method steps, it can be found that the present invention is based on the existing semiconductor manufacturing method and the technology compatible with the existing semiconductor device, using the same method as etching the gate lining, and using the non-isotropic repetitive multi-turn 'and adjusting __, Make it _ to the Nylon level, form a side profile on both sides of the pole pole © polycrystalline seconds nanowire channel, adjust the size of the nanowire channel to 1 〇〇 (nano) by the etch conditions, and at the cost Under the low and easy-to-step manufacturing method, the fabrication of a suspended nanowire channel element with high reproducibility and mass production is completed. Therefore, the transistor structure and manufacturing of the suspended nanowire channel of the present invention can be solved. Today's nanowire electronic components are not easy to manufacture or require high cost and high technology thresholds. Please refer to the 7th Lin's 'in the crystal structure of the floating nanochannel of the present invention, due to the structure of the nanowire channel escaping', therefore, in addition to the 201017769, ... layer, There is another layer of air as a dielectric. Using the voltage of the lake pole to apply electrostatic force to the suspension type 'small, rice noodle channel, the effect of sacrificing or repelling can be generated, thereby changing the thickness of the equivalent dielectric layer of the side pole to achieve the change of the initial voltage of the channel. Therefore, it can be applied to the operation of a memory element. Furthermore, the transistor structure with the suspended nanochannel invented in the present invention can also be applied to the operation of the switching element. The main reason is that the electrostatic force acts on the suspended nanowire channel, and the fast variable equivalent side dielectric can be achieved. For the purpose of layer thickness, the component is quickly switched in the switching state, and the current switching ratio of the component is also increased due to the equivalent thickness change of the side gate dielectric layer. In view of the above, the transistor with the suspended nanowire channel of the present invention may be attracted by the electrostatic force of the gate, and the suspended nanowire channel will be attracted to the closed side wall of the contact. The electric layer 'rejects the age to separate the scales and the pro-channel, and presents two different logic states on the strip' such as the 7th @tf. Therefore, the structure of (4) can be used for secret components or memory components. • In summary, the present invention provides a technique for fabricating a semiconductor structure and equipment that is compatible with existing semiconductor processes and equipment, and is based on a low cost and simple method of fabrication. A highly reproducible and mass-produced crystal structure with a suspended nanochannel is completed. Furthermore, the present invention is a structure of a microelectromechanical combined with an electro-optical structure, wherein the side gate capacitance is a variable capacitance, and in the read-off state, due to the presence of the air dielectric layer, the component closing current is extremely low, thereby making power consumption. Reduced to operate in a low voltage operating environment and improve component reliability. The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, any changes in the characteristics and spirit of the invention described in the scope of the present application are intended to be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a transistor having a suspended nanochannel of the present invention. 2 to 6 are schematic views showing the manufacturing process of the transistor structure having the suspended nanochannel of the present invention. Figure 7 is an electrical diagram of a transistor having a suspended nanochannel of the present invention. [Main component symbol description] 10 floating nanochannel transistor ❹ 12 substrate 14 thermal oxide layer 15 polysilicon layer 16 side gate 20 dielectric layer 22 suspended nanowire channel 24 source electrode 〇 26 source electrode 28 sacrificial layer

Claims (1)

201017769 十、申請專利範園： 1· 一種具懸浮式奈米線通道之電晶體結構，其包含有： 一基底； 一側閘極’其係位於該基底上； 一介電層，其係覆蓋於該基底與該側閘極上； 式奈_通道’其係位於該側_之側邊’且與該介電層間具有 一氣隙；以及 ' Ο —雜電極與—祕電極’其餘置魏介電層上且分設_懸浮式奈 米線it道的兩端。 ’、 2. 如申請專利範圍第i項所述之具懸浮式奈米線通道之電晶體結構，其中 該源極電極與該汲極電極之底面各具有—犧牲層，以與該介電層接面 3. 如申請專利範圍第2項所述之具懸浮式奈米線通道之電晶體雜，射 該犧牲層與該介電層間具有不同蝕刻選擇比。 4. 如申請專利細第丨項所述之具鮮式奈鱗通道之電晶體結構，其中 Q 該基底表面具有一絕緣層。 5. 如申請專概圍第丨項所述之韻浮式奈鱗通道之電晶體結構，其中 該介電層之材質係為統械者氧化矽。 6. 如中請專利範圍第！項所述之具懸浮式奈米線通道之電晶體結構其中 該懸浮式奈米線通道之結晶態為單晶石夕或者多晶石夕。 7. 如申轉利範圍第丨項所述之具财式奈米線通道之電晶體結構，其中 該基底為發基底。 8. 如申請專概圍第〖項職之具鮮式奈米線通道之電晶體結構，其係 12 201017769 應用於記憶體元件的操作或開關元件。 9. 如申請專利範園第！項所述之具懸浮式奈米線通道之電晶體結構其中 該懸浮式奈米線通道之尺寸為100奈米以下。 10. -種具懸浮式奈来線通道之電晶體結構的製造方法，其包含有下列步驟: 提供一基底； 於該基底上形成一側閘極； 於該側閘極與該基底表面上依序形成—介電層與—犧牲層； © 於該犧牲層上形成一多晶梦層並對該多晶石夕;t進行源/没極離子佈植； 對該多㈣層進行圖案化製程，以在該側_之側壁上形成—奈米線通 道，與在該介電層上戰分設於該奈雜兩狀—雜電極與一汲極 電極；以及 移除該不米線通道與該閘極間所夹之該犧牲層，以使該奈求線通道成為 一懸浮狀態之奈米線通道。 ❾u·如巾料利範1G項所狀具财式絲料道之電晶體結構的製 化方法，其中對該多晶石夕層進行目案化製程的步驟包含有郷與非等向 性餘刻。 12·如申請專利細第1G項所述之具懸浮式奈米線通道之電晶體結構的製 造方法，其中該移除該犧牲層的步__選擇性钱刻。 13=申請專利範圍第10項所述之具懸浮式奈米躲道之電晶體結構的裝 迨方法，其中該基底表面覆蓋有—絕緣層。 申明專魏sisn項所狀具料式奈米麟道之m结構的製 13 201017769 造方法，其中於該基底上形成一側閘極的步驟更包含有： 於該絕緣層上形成一側閘極多晶矽層；以及 對該側閘極多晶石夕層進行圖案化，以定義出該側閑極結構。 15·如申請專利範圍第10項所述之具懸浮式奈来線通道之電晶體結構的製 造方法，其中該介電層之材質係為氮化矽或氧化矽。 16.如中請專利範圍第1()項所述之浮式奈㈣通道之電晶體結構的製 造方法，其中該基底為矽基底。 ^ 17._請專鄕圍第H)項所述之㈣料奈鱗通道之電晶體結構的製 造方法，其更可雌奈雜通道輯低溫___，以使該奈米線 通道成為單晶結構。 丨8.如申請專郷圍第H)項所述之具懸浮式奈米線通道之電晶體結構的製 造方法，其中該奈米線通道之尺寸為1〇〇奈米以下。201017769 X. Patent application garden: 1. A crystal structure with a suspended nanowire channel, comprising: a substrate; one gate is located on the substrate; and a dielectric layer is covered On the substrate and the side gate; the type of channel is located on the side of the side _ and has an air gap between the dielectric layer; and the 'Ο--electrode and the secret electrode' are left with Wei dielectric On both layers, the two ends of the _suspension nanowire is used. ' 2. The crystal structure having a suspended nanowire channel as described in claim i, wherein the source electrode and the bottom surface of the drain electrode each have a sacrificial layer to interact with the dielectric layer The junction 3. The transistor of the suspension type nanowire channel described in claim 2 has a different etching selectivity ratio between the sacrificial layer and the dielectric layer. 4. The crystal structure having a fresh nuclei channel as described in the patent application, wherein the surface of the substrate has an insulating layer. 5. For the application of the crystal structure of the rhyme-type nano-scale channel described in the above section, wherein the material of the dielectric layer is the cerium oxide of the implementer. 6. Please ask for the scope of patents! The crystal structure of the suspended nanowire channel is characterized in that the crystalline state of the suspended nanowire channel is single crystal or polycrystalline. 7. The crystal structure of a fatty nanowire channel as described in the third paragraph of the invention, wherein the substrate is a hair substrate. 8. If you apply for the special structure of the crystal structure of the fresh-type nanowire channel, it is applied to the operation or switching elements of the memory component. 9. If you apply for a patent Fanyuan! The transistor structure of the suspended nanowire channel is characterized in that the size of the suspended nanowire channel is less than 100 nm. 10. A method of fabricating a transistor structure having a suspended nanowire channel, comprising the steps of: providing a substrate; forming a gate on the substrate; and forming the gate on the side of the substrate Forming a dielectric layer and a sacrificial layer; forming a polycrystalline dream layer on the sacrificial layer and performing source/dice ion implantation on the polycrystalline stone; t patterning the multi (four) layer Forming a nanowire channel on the side wall of the side, and disposing on the dielectric layer on the nano-dipole-diffusion electrode and a drain electrode; and removing the non-rice channel The sacrificial layer is sandwiched between the gates to make the nematic line channel a nanowire channel in a suspended state. ❾u· For example, the method for preparing a crystal structure of a financial type wire material in the 1G item of the towel material, wherein the step of performing the meshing process on the polycrystalline stone layer includes the enthalpy and the non-isotropic remnant . 12. A method of fabricating a transistor structure having a suspended nanowire channel as described in claim 1G, wherein the step of removing the sacrificial layer is selective. 13 = A method of mounting a crystal structure having a suspended nano-aidway according to claim 10, wherein the surface of the substrate is covered with an insulating layer. Declaring a method for forming a m-structure of a nano-synthesis of the sisn article of the general sisn article, wherein the step of forming a gate on the substrate further comprises: forming a gate on the insulating layer a polysilicon layer; and patterning the side gate polysilicon layer to define the side idler structure. 15. A method of fabricating a transistor structure having a suspended Neil channel as described in claim 10, wherein the dielectric layer is made of tantalum nitride or hafnium oxide. 16. A method of fabricating a transistor structure of a floating nematic (four) channel as described in paragraph 1 () of the patent application, wherein the substrate is a germanium substrate. ^ 17._Please refer to the method for manufacturing the crystal structure of the (n) Nylon channel described in item H), which can be used to make the nanowire channel a single crystal. structure.丨 8. The method for manufacturing a crystal structure having a suspended nanowire channel as described in item H), wherein the size of the nanowire channel is less than 1 nanometer.
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