.201017391 九、發明說明： 【發明所屬之技術領域】 , 本發明係關於一種供電控制電路，尤指一種對電腦 •部件進行供電之控制電路。 【先前技術】 電源是電腦之功率部件，電腦中每個部件之電能來 源都是依靠電源，電源是保證電腦硬體正常運作最基本 之前提，因此供電電源之穩定性與可靠性對電腦各部件 ❹之正常工作將有著直接之關鍵性之影響。.201017391 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a power supply control circuit, and more particularly to a control circuit for supplying power to a computer component. [Prior Art] The power supply is the power component of the computer. The power source of each component in the computer depends on the power supply. The power supply is the most basic to ensure the normal operation of the computer hardware. Therefore, the stability and reliability of the power supply are on the computer components. The normal work of ❹ will have a direct and critical impact.
電腦部件如滑鼠、鍵盤等USB設備之傳統供電電路 中，當電腦從一狀態轉換到另一狀態如從軟體關機狀態 轉換到電腦正常工作狀態後，由於與電腦之Ατχ電源二 連接之電源狀態訊號需經過1〇〇_4〇〇毫秒之延時才能從 低電平變為高電平，而電源狀態訊號為高電平後給USB 設備供電之電壓才會達到穩定，故在電源狀態訊號從低 電平轉換為高電平時，給USB設備供電之電壓會出現從 © —電壓跳變為另一電壓之不穩定現象，由此可引起USB 設備無法被識別等狀況發生。 【發明内容】 鑒於上述内容，有必要提供一種供電控制電路，可 使得電腦從一狀態轉換到另一狀態後，電腦部件之供電 電壓均保持穩定，而不會發生跳變。 一種供電控制電路，包括第一至第六開關元件、第 一至第四電阻，該第一開關元件之第一端透過該第一電 阻連接一輔助電源，該第一開關元件之第二端與一電腦 5 201017391 主機板之南橋θ μ、Α. 一開關元件以接收—主機板狀態訊號，該第 • 開關元件之第-端，該第二開關元件之第 地，今笛 源狀態訊號，該第二開關元件之第二端接 Μ:開關元件之第三端連接該第一開關元件之第 誃第四;;3四開關元件之第一端連接-第-系統電源， ‘過該I:件之第二端接地，第四開關元件之第三端 ❹件之W第一：：連接該輔助電源’還連接該第五開關元 -. 五開關元件之第二端接地，該第五開關 、查垃㈣二端透過該第四電阻連接一第二系統電源，還 # ；5 ^二〇開關兀件之第一端，該第三開關元件之第二 一会Μ =開關元件之第二端分別連接該辅助電源及該第 筮1源、，該第二開關元件之第三端及該第六開關元 二端連接—電腦部件之供電端，該第—系統電源 ^第二系統電源之電壓，當電腦從軟體關機狀態切換 為=腦正常工作狀態後及當電腦從待機狀態被喚醒而進 ©=電腦正常工作狀態後，該主機板狀態訊號為高電平， 二電源狀態讯號經一段時間延遲後由低電平變為高電 :’該第四開關it件導通、第五開關㈣截止及第六開 ^件導通，該電腦部件之供電端均由第—系統電源穩 =供 >電，當電腦從正常工作狀態切換為電腦待機狀態 後，該主機板狀態訊號及電源狀態訊號為低電平，該第 二開關元件截止，第一開關元件及第三開關元件導通， 該電腦部件之供電端由該輔助電源穩定供電。 該供電控制電路透過控制該第四、第五及第六開關 6 201017391 兀件是否導通，當該第六開關元件導通時，該電腦部件 2供電端由第一系統電源穩定供電，還透過控制該第 、、第一及第三開關元件是否導通，當該第三開關元件 *導通時，該電腦部件之供電端由輔助電源穩定供電，從 而保也電腦從一狀態轉換到另一狀態後，電腦部件之供 電電壓均保持穩定，而不會發生跳變。 * 【實施方式】 清參閱圖1’本發明供電控制電路之較佳實施方式包 ©括場效應電晶體QLQ6、電阻R1_R6、電容C1及C2。該 供電控制電路連接在一 ATX電源（未示出）與一電腦部 件（未示出）之間，該ATX電源包括一辅助電源5V_SB、 兩系統電源5V—SYS及12V一SYS、一電源狀態訊號引腳。 該場效應電晶體Q1之源極透過該電阻R5連接該輔 助電源5V一 SB，還與一電腦主機板上之南橋晶片（未示 .出）連接以接收一主機板狀態訊號GPIO一S3_EN，該場效 應電晶體Q1之閘極連接該場效應電晶體Q2之沒極，還 ❹透過該電阻R1連接該輔助電源5V_SB，該場效應電晶體 Q1之汲極透過該電阻R2連接該辅助電源5V_SB，還連 接該場效應電晶體Q3之閘極。該場效應電晶體q2之閘 極連接該電源狀態訊號引腳以接收一電源狀態訊號 P\VR〇K_ATX ’源極接地。該場效應電晶體Q4之閘極透 過該電阻R6連接該系統電源5V_SYS，還透過該電容ci 接地，該場效應電晶體Q4之源極接地，沒極透過該電阻 R3連接該輔助電源5V_SB’還連接該場效應電晶體Q5 之閘極。該場效應電晶體Q5之源極接地，該場效應電晶 201017391 體Q5之沒極透過該電阻R4連接該系統電源12V_SYS， 還連接該場效應電晶體Q6之閘極。該場效應電晶體Q6 -及Q3之源極分別連接該系統電源5 v_SYS及該輔助電源 v 5V-SB °該兩場效應電晶體Q6及Q3之汲極連接電腦部 件之供電端Us，還透過該電容C2接地。 在本實施方式中，該等場效應電晶體Q1-Q6作為開 關元件’其中該等場效應電晶體Ql、Q2、Q4、Q5及Q6 均為NMOS場效應電晶體，該場效應電晶體q3為pM〇s ❹場效應電晶體，在其他實施方式中，也可採用其他類型 之開關元件，例如NPN型電晶體等，該電容C2為一電 解電容，在其他實施方式中，也可為其他類型之電容， 如固態電容等。該輔助電源5V_SB及系統電源5V__SYS 之電壓均為5伏特，該系統電源i2V_SYS之電壓為12 伏特。 電腦之不同狀態可分為電腦軟體關機狀態、電腦正 常工作狀態及電腦待機狀態，因此電腦之不同狀態之切 ❿換可分為：從電腦軟體關機狀態切換為電腦正常工作狀 態、從電腦正常工作狀態切換為電腦待機狀態及從電腦 待機狀態被喚醒而切換為電腦正常工作狀態。 主機板狀態訊號GPIO_S3一EN可在基本輸入輸出系 統中設定電腦在不同狀態時之高低電平，在本實施方式 中，主機板狀態訊號GPIO_S3一EN在電腦正常工作狀熊 及電腦軟體關機狀態為高電平，在電腦待機狀態為低^ 平。 " 電源狀態訊號PWROK一ATX在電腦軟體關機狀態時 201017391 為低電平’在電腦剛進入正常工作狀態之一段時間如 100-400ms内為低電平，在此段時間後為高電平，在電腦 -待機狀態時為低電平。 ‘ 當電腦在軟體關機狀態時，該電源狀態訊號 PWR〇K_ATX為低電平，該主機板狀態訊號gpi〇_S3 _ΕΝ 為兩電平’該系統電源5V—SYS及12V_SYS均不供電， 該輔助電源5V一SB供電，該場效應電晶體q2之閘極為 低電平而使場效應電晶體Q2截止，該場效應電晶體Q1 ❹之閘極與源極之間之電壓差小於該場效應電晶體Q1之導 通電壓而使場效應電晶體Q1截止，使得場效應電晶體 Q3之源極與閘極之間之電壓差小於該場效應電晶體Q3 之導通電壓而使場效應電晶體Q3截止’該場效應電晶體 Q4之閘極無電壓而使場效應電晶體Q4截止，使得該場 效應電晶體Q5之閘極為高電平而使場效應電晶體Q5導 通，場效應電晶體Q0之閘極為低電平而使場效應電晶體 截止，則電腦部件之供電端無電壓輸出。 〇 當電腦從電腦軟體關機狀態切換為電腦正常工作狀 態後’該電源狀態訊號PWROK一ATX經一段時間如 100-400毫秒延時後由低電平變為高電平，該主機板狀態 訊號GPIO一S3一EN為高電平，系統電源5V_SYS及 12V一SYS也供電，當電源狀態訊號pWR〇K_ATX為低電 平時，該場效應電晶體Q2之閘極為低電平而使場效應電 晶體Q2截止，該場效應電晶體Q1之閘極與源極之間之 電壓差小於該場效應電晶體Q1之導通電壓而使場效應電 晶體Q1截止，場效應電晶體q3之源極與閘極之間之電 201017391 壓差小於該場效應電晶體Q3之導通電壓而使場效應電晶 體Q3截止，經該電容C1延遲大約10毫秒以使系統電源 .5V_SYS穩定供電後，該場效應電晶體q4之閘極為高電 ‘平而使場效應電晶體Q4導通，使場效應電晶體Q5之閘 極為低電平而使場效應電晶體Q5截止，該場效應電晶體 Q6之閘極與源極之間之電壓差大於該場效應電晶體q6 之導通電壓而使場效應電晶體Q6導通，從而該系統電源 5V 一 SYS給該電腦部件之供電端us穩定供電。當電源狀 ❹態訊號PWROK_ATX轉換為高電平時，該場效應電晶體 Q2之閘極為高電平而使場效應電晶體q2導通，該場效 應電晶體Q1之閘極與源極之間之電壓差小於該場效應電 晶體Q1之導通電壓而使場效應電晶體Q1截止，使得場 效應電晶體Q3之源極與閘極之間之電壓差小於該場效應 電晶體Q3之導通電壓而使場效應電晶體q3截止，該場 效應電晶體Q4仍導通，使場效應電晶體Q5之閘極為低 電平而使場效應電晶體Q5截止，該場效應電晶體Q6仍 ❹導通’從而該系統電源5V一SYS仍給該電腦部件之供電端 Us穩定供電。因此當電腦從電腦待機狀態切換為電腦正 吊工作狀態後’該電源狀態訊號PWROK ATX由低電平 變為高電平時，該電腦部件之供電端Us均由系統電源 5V_SYS穩定供電。In a traditional power supply circuit of a USB device such as a mouse or a keyboard, when the computer is switched from one state to another, such as from a software shutdown state to a normal working state of the computer, the power state is connected to the power supply of the computer. The signal needs to go through a delay of 1〇〇_4〇〇 milliseconds to change from low level to high level, and the voltage supply to the USB device will be stable after the power status signal is high, so the power status signal is from When the low level is converted to a high level, the voltage supplied to the USB device may be unstable from the transition of the voltage to the voltage of another voltage, which may cause the USB device to be unrecognizable. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a power supply control circuit that allows the power supply voltage of a computer component to remain stable without a jump after the computer is switched from one state to another. A power supply control circuit includes first to sixth switching elements, first to fourth resistors, and a first end of the first switching element is connected to an auxiliary power source through the first resistor, and the second end of the first switching element is a computer 5 201017391 the south bridge of the motherboard θ μ, Α. A switching element to receive - the motherboard status signal, the first end of the second switching element, the second switching element of the ground, the current source signal, the The second end of the second switching element is connected: the third end of the switching element is connected to the fourth and fourth of the first switching element; the third end of the four switching element is connected to the -system power supply, 'over the I: The second end of the fourth grounding member is grounded, and the third end of the fourth switching element is first: the auxiliary power source is connected to the fifth switching element. The second end of the fifth switching element is grounded, the fifth switch The second end of the second circuit is connected to the second system through the fourth resistor, and the first end of the second switching element is the second end of the third switching element. The end is respectively connected to the auxiliary power source and the first source, the second The third end of the component and the second terminal of the sixth switch are connected to the power supply end of the computer component, the voltage of the first system power supply and the second system power supply, when the computer is switched from the software shutdown state to the brain normal working state and When the computer wakes up from the standby state and enters the normal working state of the computer, the status signal of the motherboard is high level, and the second power status signal changes from low level to high power after a period of delay: 'the fourth The switch is turned on, the fifth switch (four) is cut off, and the sixth open device is turned on. The power supply end of the computer component is stabilized by the first system power supply, and when the computer is switched from the normal working state to the computer standby state, The motherboard status signal and the power status signal are low, the second switching element is turned off, the first switching element and the third switching element are turned on, and the power supply end of the computer component is stably powered by the auxiliary power supply. The power supply control circuit controls whether the fourth, fifth and sixth switches 6 201017391 are turned on. When the sixth switching element is turned on, the power supply end of the computer component 2 is stably powered by the first system power supply, and Whether the first, first and third switching elements are turned on, and when the third switching element * is turned on, the power supply end of the computer component is stably powered by the auxiliary power source, thereby ensuring that the computer is switched from one state to another state, the computer The supply voltage of the components remains stable without hopping. * [Embodiment] Referring to Figure 1', a preferred embodiment of the power supply control circuit of the present invention includes a field effect transistor QLQ6, a resistor R1_R6, and capacitors C1 and C2. The power control circuit is connected between an ATX power supply (not shown) and a computer component (not shown). The ATX power supply includes an auxiliary power supply 5V_SB, two system power supplies 5V-SYS and 12V-SYS, and a power status signal. Pin. The source of the field effect transistor Q1 is connected to the auxiliary power source 5V-SB through the resistor R5, and is also connected to a south bridge chip (not shown) on a computer motherboard to receive a motherboard status signal GPIO_S3_EN. The gate of the field effect transistor Q1 is connected to the gate of the field effect transistor Q2, and the auxiliary power source 5V_SB is connected through the resistor R1. The drain of the field effect transistor Q1 is connected to the auxiliary power source 5V_SB through the resistor R2. The gate of the field effect transistor Q3 is also connected. The gate of the field effect transistor q2 is connected to the power state signal pin to receive a power state signal P\VR〇K_ATX ’ source ground. The gate of the field effect transistor Q4 is connected to the system power supply 5V_SYS through the resistor R6, and is also grounded through the capacitor ci. The source of the field effect transistor Q4 is grounded, and the auxiliary power supply 5V_SB' is connected through the resistor R3. Connect the gate of the field effect transistor Q5. The source of the field effect transistor Q5 is grounded, and the field effect transistor 201017391 body Q5 is connected to the system power supply 12V_SYS through the resistor R4, and is also connected to the gate of the field effect transistor Q6. The sources of the field effect transistors Q6- and Q3 are respectively connected to the system power supply 5v_SYS and the auxiliary power supply v5V-SB. The drains of the two field effect transistors Q6 and Q3 are connected to the power supply terminal Us of the computer component, and are also transmitted through The capacitor C2 is grounded. In the present embodiment, the field effect transistors Q1-Q6 are used as switching elements, wherein the field effect transistors Q1, Q2, Q4, Q5 and Q6 are NMOS field effect transistors, and the field effect transistor q3 is In other embodiments, other types of switching elements, such as an NPN type transistor, may be used. The capacitor C2 is an electrolytic capacitor. In other embodiments, other types may also be used. Capacitors, such as solid capacitors. The auxiliary power supply 5V_SB and the system power supply 5V__SYS have a voltage of 5 volts, and the system power supply i2V_SYS has a voltage of 12 volts. The different states of the computer can be divided into the computer software shutdown state, the computer normal working state and the computer standby state. Therefore, the different states of the computer can be divided into: switching from the computer software shutdown state to the normal working state of the computer, working normally from the computer. The state is switched to the computer standby state and is awakened from the computer standby state to switch to the normal working state of the computer. The motherboard status signal GPIO_S3-EN can set the high and low level of the computer in different states in the basic input/output system. In this embodiment, the motherboard status signal GPIO_S3-EN is in the normal working condition of the computer and the computer software is turned off. High level, low on the computer standby state. " Power status signal PWROK-ATX is low level when the computer software is turned off 201017391 is low level in the period when the computer just enters the normal working state, such as 100-400ms, after this period is high level, It is low during computer-standby state. When the computer is in the software shutdown state, the power status signal PWR〇K_ATX is low, the motherboard status signal gpi〇_S3 _ΕΝ is two levels', the system power supply 5V-SYS and 12V_SYS are not powered, the auxiliary The power supply is 5V-SB, the gate of the field effect transistor q2 is extremely low, and the field effect transistor Q2 is turned off. The voltage difference between the gate and the source of the field effect transistor Q1 is less than the field effect electricity. The on-state voltage of the crystal Q1 turns off the field effect transistor Q1, so that the voltage difference between the source and the gate of the field effect transistor Q3 is smaller than the on-voltage of the field effect transistor Q3, and the field effect transistor Q3 is turned off. The gate of the field effect transistor Q4 has no voltage and the field effect transistor Q4 is turned off, so that the gate of the field effect transistor Q5 is extremely high and the field effect transistor Q5 is turned on, and the gate of the field effect transistor Q0 is extremely When the FET is turned off, the power supply terminal of the computer component has no voltage output. 〇When the computer is switched from the computer software shutdown state to the normal working state of the computer, the power state signal PWROK-ATX changes from low level to high level after a period of time such as 100-400 millisecond delay, the motherboard status signal GPIO one S3-EN is high level, the system power supply 5V_SYS and 12V-SYS are also powered. When the power state signal pWR〇K_ATX is low level, the gate of the field effect transistor Q2 is extremely low and the field effect transistor Q2 is cut off. The voltage difference between the gate and the source of the field effect transistor Q1 is smaller than the on-voltage of the field effect transistor Q1 to turn off the field effect transistor Q1, and between the source and the gate of the field effect transistor q3. The voltage difference is less than the on-state voltage of the field effect transistor Q3 to turn off the field effect transistor Q3, and the capacitor C1 is delayed by about 10 milliseconds to stabilize the system power supply .5V_SYS after the power supply of the field effect transistor q4 Extremely high power 'Ping on the field effect transistor Q4 is turned on, so that the gate of the field effect transistor Q5 is extremely low and the field effect transistor Q5 is turned off. The gate of the field effect transistor Q6 is between the source and the source. Voltage difference A conducting voltage of the field effect transistor q6 of the field effect transistor Q6 is turned on, so that the system SYS to a 5V power supply terminal of the computer us stabilized power supply member. When the power state signal PWROK_ATX is converted to a high level, the gate of the field effect transistor Q2 is at a high level to turn on the field effect transistor q2, and the voltage between the gate and the source of the field effect transistor Q1. The difference is smaller than the on-voltage of the field effect transistor Q1 to turn off the field effect transistor Q1, so that the voltage difference between the source and the gate of the field effect transistor Q3 is smaller than the on-voltage of the field effect transistor Q3. The effect transistor q3 is turned off, the field effect transistor Q4 is still turned on, so that the gate of the field effect transistor Q5 is at a low level and the field effect transistor Q5 is turned off, and the field effect transistor Q6 is still turned on. 5V-SYS still supplies power to the power supply terminal Us of the computer component. Therefore, when the computer is switched from the standby state of the computer to the working state of the computer, when the power state signal PWROK ATX changes from a low level to a high level, the power supply terminal Us of the computer component is stably powered by the system power supply 5V_SYS.
當電腦從電腦正常工作狀態切換為電腦待機狀態 後，該電源狀態訊號PWROK一ATX及該主機板狀態訊號 GPIO—S3一EN均為低電平，系統電源5V—SYS及12v SYS 不供電，該辅助電源5V_SB供電，該場效應電晶^ Q2 201017391 之閘極為低電平而使場效應電晶體Q2截止，場效應電晶 體Q1之閘極為高電平而使場效應電晶體Q1導通，該場 '效應電晶體Q3之源極與閘極之間之電壓差大於該場效應 k電晶體Q3之導通電壓而使場效應電晶體Q3導通，該場 效應電晶體Q4之閘極為低電平而使場效應電晶體q4截 止使场效應電晶體Q5之閘極為尚電平而使場效應電晶 體Q5導通，該場效應電晶體Q6之閘極為低電平而使場 效應電晶體Q6截止，從而該輔助電源5 V一SB給該供電 ©端Us穩定供電。因此電腦從電腦正常工作狀態切換為電 腦待機狀態後，該電腦部件之供電端Us由輔助電源 5V_SB穩定供電。 當電腦從電腦待機狀態被喚醒而進入電腦正常工作 狀態後，其工作過程與當電腦從電腦軟體關機狀態切換 為電腦正常工作狀態後之工作過程相同，即當該電源狀 態訊號PWROK一ATX由低電平變為高電平時，該電腦部 件之供電端Us均由系統電源5V一SYS穩定供電。 Q 在其他實施方式中可以刪除產生分壓作用之電阻 R5 ’即該場效應電晶體Q1只接收該主機板狀態訊號 GPIO_S3一EN，也可以刪除產生濾波作用之電容C2，即該 兩场效應電bb體Q6及Q3之沒極僅與該供電端u g相連， 產生分壓作用之電阻R6及產生延遲作用之電容C1也可 同時刪除’即將該場效應電晶體Q4之閘極與該系統電源 5V_SYS直接相連。 該供電控制電路透過系統電源5V—SYS控制該等場 效應電晶體Q3、Q5及Q6是否導通，當該場效應電晶體 11 201017391 Q6導通時，該電腦部件之供電端Us由系統電源5V_SYS 穩定供電’還透過該電源狀態訊號PWR〇K—Ατχ及主機 *板狀態訊號GPI〇_S3_EN控制該場效應電晶體Qi、Q2 •及Q3是否導通，當該場效應電晶體Q3導通時，該電腦 部件之供電端Us由輔助電源5 V_SB穩定供電，從而保證 電腦從一狀態轉換到另一狀態後，電腦部件之供電電壓 均保持穩定，而不會發生跳變。 綜上所述，本發明符合發明專利要件，爰依法提出專 ©利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾 或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係本發明供電控制電路之較佳實施方式之電路 圖0 【主要元件符號說明】 R1-R6 %效應電晶體 Q1-Q6 電阻 電容 Cl、 12When the computer is switched from the normal working state of the computer to the standby state of the computer, the power status signal PWROK-ATX and the motherboard status signal GPIO-S3-EN are both low, and the system power supply 5V-SYS and 12v SYS are not powered. Auxiliary power supply 5V_SB power supply, the field effect transistor Q2 201017391 gate is extremely low and the field effect transistor Q2 is cut off, the field effect transistor Q1 gate is extremely high and the field effect transistor Q1 is turned on, the field The voltage difference between the source and the gate of the effect transistor Q3 is greater than the on-state voltage of the field effect k transistor Q3 to turn on the field effect transistor Q3, and the gate of the field effect transistor Q4 is at a low level. The field effect transistor q4 is turned off to make the gate of the field effect transistor Q5 extremely level and the field effect transistor Q5 is turned on. The gate of the field effect transistor Q6 is extremely low, and the field effect transistor Q6 is turned off, thereby The auxiliary power supply 5 V SB supplies the power supply terminal Us with stable power supply. Therefore, after the computer is switched from the normal working state of the computer to the standby state of the computer, the power supply terminal Us of the computer component is stably powered by the auxiliary power source 5V_SB. When the computer wakes up from the standby state of the computer and enters the normal working state of the computer, the working process is the same as when the computer is switched from the computer software shutdown state to the normal working state of the computer, that is, when the power state signal PWROK-ATX is low When the level changes to a high level, the power supply terminal Us of the computer component is stably powered by the system power supply 5V-SYS. In other embodiments, the resistor R5 that generates the voltage dividing action can be deleted. That is, the field effect transistor Q1 can only receive the motherboard state signal GPIO_S3-EN, and can also delete the capacitor C2 that generates the filtering effect, that is, the two field effect electricity. The BB body Q6 and Q3 have only the IGBT connected to the power supply terminal ug. The resistor R6 that generates the voltage divider and the capacitor C1 that generates the delay function can also simultaneously delete 'the gate of the field effect transistor Q4 and the system power supply 5V_SYS. Directly connected. The power supply control circuit controls whether the field effect transistors Q3, Q5 and Q6 are turned on through the system power supply 5V-SYS. When the field effect transistor 11 201017391 Q6 is turned on, the power supply terminal Us of the computer component is stably powered by the system power supply 5V_SYS. 'Controlling whether the field effect transistors Qi, Q2, and Q3 are turned on by the power state signal PWR〇K-Ατχ and the host* board status signal GPI〇_S3_EN, when the field effect transistor Q3 is turned on, the computer component The power supply terminal Us is stably powered by the auxiliary power supply 5 V_SB, so that after the computer is switched from one state to another, the power supply voltage of the computer components is stable without jumping. In summary, the present invention complies with the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a preferred embodiment of a power supply control circuit of the present invention. FIG. 0 [Description of main component symbols] R1-R6 % effect transistor Q1-Q6 resistance capacitance Cl, 12