TW201015870A - Successive approximation ADC with binary error tolerance mechanism - Google Patents

Abstract

A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. A non-binary successive approximation register (SAR) control logic that controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error.

Description

201015870 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to analog to digital converters (ADCs), particularly

I is a progressive approximation register (SAR) analog to digital converter with a binary error tolerance mechanism. [Prior Art] ❹ Analog-to-digital converters (ADCs) have a variety of architectures, such as flash, pipelined, and gradual approximation, which are frequently used architectures. Each of these architectures has its own advantages and is often chosen for different application needs. Among them, the progressive approximation ADC consumes lower power, smaller area and lower cost than other architectures. However, this architecture requires more clock cycles to produce output and is therefore less advantageous for high speed operation. Gradual approximation ADCs are mainly divided into two ways: binary approximation and non-binary approximation. Binary approximation ADC technology, such as H^O-CHiao Hong' Guo-Ming Lee WA 65-fJ/Conversion-step 0.9-V 200-KS/s Rail-to-Rail 8-bit Successive Approximation ADC", IEEE J. Solid -State Circuits, vol. 42, Oct. 2007, pp. 2161-2168. The 201015870 uses a digital-to-analog converter (DAC) to gradually approximate the sampled signal and determine the next state based on the comparison of the comparators. A voltage is applied upwards or downwards, and the amount of voltage changed each time is gradually decreased by a power of two. In this binary search mode, the operation is repeated several times to obtain a corresponding digital code output. Binary approximation ADC Technology is also exposed

Craninckx, G. van der Plas “A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-sharing SAR φ ADC in 90nm Digital CMOS”, ISSCC Dig. Tech. Papers ' February 2007, Pp. 246-247, which applies the same principle, but determines the increase or decrease of the amount of charge according to the amount of charge difference between the two ends of the comparator, and the amount of charge changed each time gradually decreases by a power of two. The operation is repeated several times in this binary search mode until the corresponding digital code output is obtained. The above two methods of binary approximation will be limited in speed. The main reason is that the voltage across the comparator or the parametric charge must be stable to less than 1/2 LSB (ie, 1/2 centimeter 1 where N is the resolution of the ADC). ) 'Comparator can perform comparison action, otherwise it will cause sampling error 0 non-binary approximation ADC technology, such as F. Kuttner "A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-m CMOS", IEEE Int. 201015870

Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 176-177. Unlike the binary approximation method, the non-binary approximation method does not approximate the power of two, but gradually decreases with a power of 185. This method has an error tolerance of approximately 12.7%, so samples can be sampled without a stable signal, which can shorten each clock cycle time; however, additional and complex digital correction mechanisms need to be added. Whether it is implemented as a logic circuit or a read-only memory, it takes power and circuit area. ❹ Given the shortcomings of traditional approaches to ADC architecture, a new ADC architecture is needed to maintain the advantages of traditional ADC architectures and avoid their shortcomings. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a new gradual approximation ® ADC that uses an error tolerance mechanism and a non-binary approximation method with high speed and binary error correction mechanism. A progressive approximation analog to digital converter (ADC) according to an embodiment of the invention 'an internal digital to analog converter (DAC) comprising a capacitor array having a capacitance value having a binary weight and at least one compensation capacitor configuration Among the capacitances of binary weights. The comparator receives and compares the sample input signal and the DAC round trip. Non-8 201015870 binary gradual approximation control circuit (4) sampling of the input signal, and according to the comparator's results (10) - (four) comparison of the signal or charge is not yet fully stable (such as stable ^ less two ... _, near-control The circuit is better than the second one. The second error is the tolerance of the error, and the corrector compensates the sampling error caused by the comparator. [Embodiment] The first figure shows that the octade is gradually approximating analog to digital converter (SARADC). First, an input (eg, non-inverting input) of the comparator 1〇 receives the sampled input signal I and is connected to the internal digit of the other input (eg, the reverse wheel) to the analog converter (Dac). Reset to the common mode voltage Vcj^ As shown, the dac is composed of electrical arrays (C7 i CG), which have a binary specific gravity m. Then, the comparator 1 compares the input signals. Vin and common mode power vcm to decide to add or subtract the v/4 voltage in the DAC (where V is the amplitude of the round signal). When the DAC reaches stability, the next comparison and decision are made. Until the round Can be approximated as: VCm ± V / 4 ± V / 8 ± V / 16 ± V / 32 ± V / 64 ± V / 128 ± V / 256 (where V is the amplitude of the input signal) 201015870 The second figure shows the implementation of the present invention For example, a single-ended progressive approximation ADC with a binary error tolerance mechanism. Although the embodiment uses an octet ADC as an example, the present invention is generally applicable to an n-bit ADC. In this embodiment, a progressive approximation ADC is used. Contains an internal DAC' consisting of a capacitor array (C7 to Clc) with non-binary specific gravity: C7=2C6=4C5=4C5c=8C4=16C3=16C3c=32C2=64C 1 =64Clc The approximating ADC further includes a comparator 20 that receives and compares the sampled input signal Vin and the DAC output. The gradual approximation control logic (SAR) 22 controls the sampling of the input signal Vin and controls according to the comparison result of the comparator 20. A series of comparisons, finally outputting the corresponding digital output for approximating the input signal Vin. In operation, first, an input of the comparator 20 (eg, a non-inverting input) receives the sample input signal Vin; and is connected to another The inside of an input (such as the inverting input) The digital to analog converter (DAC) is reset to the common mode voltage Vcm. As shown, the DAC is reset to the common mode voltage Vcm by connecting a switch in the DAC. Then the comparator 20 Comparing the input signal Vin with the common mode voltage Vcm to determine whether to add or subtract the V/4 voltage (where V is the amplitude of the input signal) in the DAC. In one embodiment, when the DAC circuit is stable to one bit accuracy ( However, when it is not fully stabilized, the control logic circuit (SAR) 22 is gradually approaching the comparison and decision of the next bit. Since the DAC signal is not completely stable, it will cause an error of V/4 (V/4*l/2+V/8). Since the remaining voltage change is approximately V/8 (V/16 V/32 V/64 V/128 V/256), ±V/8 must be added to compensate for this error. Repeat this operation until the lowest effective bit (LSB). The input signal can be approximated as:

Vcm±v/ 4 soil V/ 8 soil V/ 8 soil V/16 soil V/16 soil V/ 3 2 士V/ 3 2 士V/64士❹ V/64 soil V/128 soil V/128 soil V /256 soil V/256 In another embodiment (second diagram), when the DAC circuit is stable to two-bit accuracy (rather than the one-bit element described above), the control logic circuit (SAR) 22 is gradually approached. The comparison and decision of the next dollar. Since the DAC signal is not completely stable, it will cause an error of 3V/16 (V/4*l/22+V/8). Since the remaining voltage change is approximately V/8 (V/16 ± V / 32 φ soil V / 64 ± V / 128 ± V / 256), it is necessary to fill the soil V / 16 to compensate for the error. Repeat this operation until the least significant bit (LSB). The input signal can be approximated as:

Vcm Shi V / 4 soil V / 8 soil V / 16 Shi V / 16 soil V / 32 Shi V / 64 soil V / 64 soil V / 128 Shi V / 256 soil V / 256 will analyze the DAC voltage stability to a few Comparator resampling after bit accuracy will optimize the gradual approximation DAC. For an 11 201015870 N-bit ADC, the DAC is stable to x-bit precision resampling, and the interval between the comparators starting from the start of the comparison and the start of the DAC is yAt (where ΔtsRCWi^), the Bay ij solution The time required for a piece of data Ttotal can be approximated as:

Ttotal (X, y,N)^ T le +(x + y)At »(N +

X « Tsample + N(x + y) At+ -2)· At + (—) . yAt

X is partial to x:

^〇ία/ίώyj^l ΧΝ· At-·(yAt) = 0

OX X N-2 ^ N · At yAt = 0 x N — 2 x2 => N = y( =>xm y- ΑΓ-2 ~N~ Take the octet ADC as an example, assuming y and 5, then The optimized values X and 2 are obtained. Comparing the various X values shows that the time required is the shortest when x = 2. ® ^ = Ttotal = Tsampk + (1 + 5) Δ / * (8 + 6) = Tsample + 84Δί λ: = 2 Ttotal = Tsample + (2 + 5) At * (8 + 3) = Tsample +11 hd ^ = Tlotal = Tsample + (3 + 5)At * (8 + 2) = Tsample + 80Δί x = 8 — 7;to,=7;_e + (8 + 5)~*8 = ;rs_ + 104A, (corresponding to the ADC of the first figure) According to the above, when X=2, the ADC is optimized, Therefore, three compensation capacitors (ie, C5c, C3c, Clc) are used to correct the gradual approximation of the 12 201015870 ADC, as shown in the second figure. In general, for an η-bit ADC, the amount of compensation capacitor required can be expressed. It is [(n-2)/x], where [] is a Gaussian operation symbol, which takes an integer part of a value. In this embodiment, these compensation capacitors are configured in non-compensating capacitors in the following manner (C7, C6) Between C5, C4, C3, C2, C1 and C1): the first compensation capacitor (C5c). Configured in the third After (C5); the second compensation capacitor (C3c) is placed after the next second capacitor (C3); the third compensation capacitor parameter (Clc) is placed after the second capacitor (C1). The above optimization method can be applied to ADCs with different resolutions. Furthermore, for the larger resolution ADC 'the above optimization performance is better. The third figure illustrates the sampling waveform 31 corresponding to the first picture and Corresponding to the sampling waveform 32 of the second figure (x=2), eleven sampling binary values (ie, 1〇〇〇〇11111〇) indicated by brackets in the figure represent the output of the comparator 20 。. Then, this The bit output is processed by a binary error valley forensor after gradually approximating the control logic (SAR) 22 to produce an 8-bit digital output of the ADC to compensate for the sampling error. Although binary error tolerance in this embodiment The positivity device is located inside the gradual approximation control logic (SAR) 22, however, in other embodiments, it may also be located outside the gradual approximation control logic (SAR) 22. 13 201015870 For the ADC shown in the first figure ,its The output can be expressed as:

Out=128 · B1+64 · B2+32 · B3+16 · B4+8 · B5+4 · B6+2 · B7+1 · B8 or

Out=(0+255) / 2±64±32± 16±8±4±2± 1 ±〇. 5 where the symbol “+” is determined by the value of Bn being “1” or, 〇,, , n=l, 2,..., 8. For the ADC shown in Figure 2, the output can be expressed as:

Out=(0+255) /2±64±32± 16± 16±8±4±4±2± 1± 1±〇. 5 or

Out=-21 + 128· B1+64· B2+32· B3+32· B4+16· B5+8 · ΒΘ+8 · B7+4 · B8+2 · ΒΘ+2 · B10+1 · B11 Expressed as the formula shown in the fourth figure. For the example of the third figure, the processing of the Φ output (10000111110) can be as shown in the fifth figure. The sixth figure shows a binary error tolerance corrector of an embodiment of the present invention for converting the 11-bit output (B1 B2B3...B11) of comparator 20 to the 8-bit output of the ADC. In this embodiment, two inputs (eg, '1' and B11) are added using some half adders (HA), and three inputs (eg, 1, B9 and B10) are used using some full adders (FA). Each half adder or full adder produces a carry bit C that is fed to the adjacent front 201015870 stage half/full adder and produces a sum bit s fed to the parallel half/full adder. 'According to the above In the embodiment of the present invention, the operation speed of the non-binary gradual approximation adc will be larger than that of the conventional gradual approximation ADC, because the sampling is performed before the signal is completely stabilized, and a simple binary error tolerance correction mechanism is used to obtain the ADC. The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the claims of the present invention; any equivalent changes or modifications made without departing from the spirit of the invention should be included. The application for the application [simplified description of the schema]

The first-graph shows a schematic diagram of the octupary approximation analogy to the number of conversion ADCs. ,

The third figure of the single embodiment of the SAR has a binary error tolerance mechanism corresponding to the first waveform. The sampling waveform of one picture and the fourth picture corresponding to the first '^ show the two-dimensional error correction tolerance correction 15 201015870 The fifth figure illustrates the binary error tolerance correction operation of the output of the third figure. The sixth figure shows the binary error tolerance corrector of the embodiment of the present invention. 10 [Description of main component symbols] Comparator 20 Comparator 22 gradually approximating control Logic circuit 31 ❹32 Sample waveform of the first figure Example of sample waveform of the second figure Example 16

Claims (1)

201015870 X. Patent application scope: 1. A gradual approximation analog to digital converter (ADC) 'contains · a digital to analog converter (DAC); a comparator whose input receives a sample input signal, The other input receives the rounding of the DAC; a non-binary gradual approximation control circuit controls the sampling of the round-in signal, and controls a series of ratios according to the comparison result of the comparator, wherein the gradual approximation control The circuit controls the comparison before the signal or charge of the DAC = not fully stabilized; and a corrector to compensate for the error caused by the comparator. ❹ 2. As in the gradual approximation analog to digital converter described in claim 1, when the signal or charge of the DAC is stabilized to at least one bit accuracy, the above-mentioned gradual approximation control circuit controls comparison Go on. The converter, when the signal of the DAC is stabilized to x bit 3. As described in the scope of the approximation analog to digital conversion described in the second paragraph of the patent application, the above-mentioned gradual approximation control circuit controls the comparison. 4. The method of claim 3, wherein the DAC comprises a capacitor array having a capacitance value of a binary 17 201015870 weight and at least one compensation capacitor, as in the third application of the patent application scope. Configured in the capacitance of the binary weight. 5. For a gradual approximation analog to digital converter as described in claim 4, for an n-bit ADC, the number of compensation capacitors used by the DAC is [(η-2)/χ], where 丨】 is a Gaussian operation symbol, which takes an integer part of a value. 6. The gradual approximation analog to digital converter of claim 5, wherein the calibrator comprises a plurality of adders for respectively adding the output bits of the comparator. I I 7. The gradual approximation analog to digital converter of claim 1, wherein the ADC has an η bit resolution. ❹ 8. As in the gradual approximation analog-to-digital converter described in claim 7, when the signal or charge of the DAC is stabilized to the accuracy of the X-bit, the above-mentioned gradual approximation control circuit controls the comparison. For the η-bit ADC, the number of compensation capacitors used by the above DAC is [(η-2)/χ], where [I is a Gaussian operation symbol, which takes an integer part of a value. 18 201015870 9. The gradual approximation analog to digital converter of claim 8 wherein the ADC has an 8-bit resolution and the DAC package I comprises a capacitor array having a capacitance value of the following Binary weight: C7=2C6=4C5=4C5c=8C4=16C3=16C3c=32C2=64C1=64Clc. 10. The gradual approximation analog to digital ❿ converter as described in claim 9 wherein the output of the gradual approximation control circuit is corrected according to the following correction operation: Out=-21 + 128. Bl+64. B2+32. B3+32. B4+16. B5+8 · B6+8 · B7+4 . B8+2 · B9+2 · B10+1 · B11. 11. The gradual approximation analog to digital converter of claim 1 wherein the calibrator comprises a plurality of adders for respectively adding values of the same weight in the correction operation. 12. The gradual approximation analog to digital converter described in the scope of claim 5, wherein the above correction operation converts (Bi B2 B3 ... B11) into (A1 A2 A3 ... A8) according to the following formula: 201015870 B1 B2 B3 B5 B6 B8 B9 Bll + B4 B7 BIO A1 A2 A3 A4 A5 A6 A7 A8. 20