201015561 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種記憶體裝置及其方法，特破有關於一種具有錯誤 修正碼容量設定單元之㈣記憶贿㈣及其方法，雜雜閃記憶體的 使用狀態來設定。 【先前技術】 ⑩ 快閃記憶體(flash memory)係為一種非揮發性記憶體，即使移除供應電 源之後仍能保存資料。非及閘_ AND，删^型式的記憶體是一種快問 記憶體’具有肖密度躲’並且.其他種_記，隨。特獻ΝΑΝ]_ 間記憶體具有較大的儲存容量、較佳的記憶體存取速度以及低成本之特點。 > ^^#iE.^(error correction code, ECC)# 為nand快閃記憶體控制器的常用功能。具有多層式晶片(muitiievei ceu) 的NAND ‘决閃記憶體之成本較低，廣泛應用於固態碟機㈣id state drive, φ SSD)。然而多層式晶片的NAND快閃記憶趙亦有缺點，例如讀取对久性 endurance)*佳，而較差的讀取对久性的多層式晶片nand快閃記憶趙導致 固態碟機(SSD)的可靠度下降。有赛於此，讀有必要發展一種新式的快閃記 憶體’以解決上述問題。 【發明内容】 本發明之一目的在於提供一種具有錯誤修正碼(ECC)容量設定單元之 侧心It·制器及其方法，以依據快閃記憶體的使躲絲提升該快閃 記憶體控制器的錯誤修正瑪容量。 201015561 本侧另—目的在於提供-種具有錯縣正魏量設定單元之快閃記 憶體控制器及其方法，以改善該快閃記憶體的讀取/寫人耐久性㈣d endurance)以及可靠度。 為達成上述目的，本義提供-種具有修正碼容量設定單元之快 閃記憶趙控制器及其方法。該快閃記憶趙控制器包括控制單元、緩衝器、 錯誤修正碼(ECC)模組以及設定單元。控制單元用以產生一讀取命令，以讀 取該快閃纖_資_容’該,_記憶體具有雜區域·存該資料 β N容’並且具有第-備龍域，以儲存相對應於該資料内容的第—錯誤修 正碼(ECC)i。緩衝器用以儲存來自於該快閃記憶趙的資料區域之資料内 容。錯誤修正碼(ECC)模組利用該資料内容產生第二錯誤修正郷cc)值， 並且比較該第二錯誤修正碼(ECC)值與該第一錯誤修正碼保^^值然後依 據該比較躲來蚊該倾魄是林在複_碼(e_)。當該資料 内容存在該些個錯誤碼時，該設定單元計算該錯誤碼的數量，以決定該錯 誤碼的數量是否超出一預定臨界值。 ® 具體纽’當制誤碼的數量超㈣預辦界斜，槪定單元透過 該控制單元設定該快閃記憶體的資料區域，以分配一部分的資料區域作為 第二備用區域，其中該第一備用區域以及該第二備用區域的儲存容量相關 於該錯誤修正碼(ECC)容量，以使該錯誤修正碼(ECC)模組修正該資料内容 的錯誤碼。另一方面’當該些錯誤碼的數量小於該預定臨界值，該錯誤修 正碼(ECC)模組依據該第二錯誤修正碼(eCC)值與該第一錯誤修正碼戌cc) 值的比較結果來修JL該些錯誤碼。根據上述，當錯誤碼的數量超過一預定 201015561 • 臨界值時’該設定單元有效提高該快閃記憶體控制器的錯誤修正碼(eCC) 容量。 本發明之執行快閃記憶體控制器的控制方法包括下列步驟：產生一 讀取命令，以讀取該快閃記憶體的資料内容；（2)利用該資料内容產生一第 一錯誤修正碼(ECC)值；（3)比較該第二錯誤修正碼(ECC)值與該第一錯誤修 正碼(ECC)值，以依據該比較結果來決定該資料内容是否存在複數個錯誤 碼；（4)當該資料内容存在該些個錯誤碼時，利用設定單元計算該些錯誤碼 翁 一 的數量，以決定該錯誤碼的數量是否超出一預定臨界值；以及(5)該設定單 元6又疋該快閃s己憶體的資料區域，以分配一部分的資料區域作為一第二備 用區域’其中該第-備用區域以及該第二備用區域的儲存容量相關於該錯 誤修正碼(ECC)容量，以使該錯誤修正碼(ECC)模組修正該資料内容的錯誤 碼0 本發明使用一部分的儲存容量來執行高階的錯誤修正碼田cc)機制，以 改善非AM(NAND>刚記憶體的可靠度。該錯剩狂碼(Ε(χ)機制依據快 閃記憶體的使職態具有多段調整式修正#料之能力。可以利用額外 的錯誤修正碼(ECC)容量來提級航體驗用壽命。 為讓本發明之上勒容能更_錢，下文特舉較佳實施例，並配合 所附圖式’作詳細說明如下： 【實施方式】 參考第1 ® ’其♦示依據本發明實施例中快閃記憶體控㈣100之方 塊圖，係以設定單it 1〇〇來適應性設定錯誤修正郷cc)容量。該快間記憶 201015561 體控制器100包括控制單元102、緩衝器i〇4、錯誤修正碼(error correction code，ECC)模組106以及設定單元i〇8 該快閃記憶體控制器loo控制設定 單元108 ’以適應性調整快閃記憶體11〇的錯誤修正碼(ECC)容量。錯誤修 正碼(ECC)主要是用於提高快閃記憶體的資料整合性(dataintegrity)，並且確 保資料存取的可靠性(reliability)。該快閃記憶體no例如是非及閘(hand) 型式的快閃記憶體。 該快閃記憶體控制器100耦接於該快閃記憶體110，該控制單元1〇2耦 義 接於該設定單元108，並且透過複數個控訊號耦接至該快閃記憶體11〇。該 控制單元102產生一寫入命令，用以寫入該資料内容至該快閃記憶體u〇， 並且寫入該第一錯誤修正碼(ECC)值至該第一備用區域(如第2圖所示）>該 錯誤修正碼(ECC)模組106以及設定單元108分別耦接至該控制單元1〇2， 該緩衝器104分別耦接至該錯誤修正碼(ECC)模組1〇6以及快閃記憶體11〇。 參考第1圖以及第2圖，第2圖係緣示依據本發明實施例中非及閘 (NAND)型式的快閃記憶體之結構示意圖，其中該快閃記憶體具有第一備用 區域以及第二備用區域。控制單元102用以產生一讀取命令，以讀取該快 閃記憶體110的資料内容，該快閃記憶體110具有資料區域，以儲存該資 料内容，並且具有第一備用區域，以儲存相對應於該資料内容的第一錯誤 修正碼(ECC)值。在一實施例中，該快閃記憶體ι10係以複數個頁面①呢從） 來儲存該資料内容。緩衝器104用以儲存來自於該快閃記憶體11〇的資料 區域之資料内容。錯誤修正碼(ECC)模組106利用該資料内容產生第二錯誤 修正碼(ECC)值’並且比較該第二錯誤修正碼(ECC)值與該第一錯誤修正竭 8 201015561 (ECC)值然後依據該比較結果來決定該資料内容是否存在複數個錯誤碼 (errors) $該資料内容存在該些個錯誤碼時該設定料⑽計算該錯誤 碼的數量以决疋該錯誤碼的數量是否超出一預定臨界值。 具體來說’當觸誤碼的數量超_預定臨界值時，職定單元⑽ 透過該控制單元1〇2設定該快閃記，隨11()的資料區域，以分配—部分的 資料區域作為第二備用區域，其中該第一備用區域以及該第二備用區域的 儲存合量相關於該錯誤修正，ECC)容量，以使該錯誤修正碼(Ε(χ)模組修 ® 正該貝獅容的錯誤碼。另―方面，當該些錯誤碼的數量小於該預定臨界 值’該錯誤修正碼(ECC)模、组1〇6依據該第二錯誤修正碼(ECC)值與該第一 錯誤修正瑪(ECC)值力比較結果來修正該些錯誤碼。根據上述，當錯誤瑪的 數量超過-敎臨界辦’該蚊料1G8有餓高(b_)該賴記憶體控 制器100的錯誤修正碼(ECC)容量。 該第-備㈣域更包括-計數區域，以齡一計數值，並且依據該計 數值來決定該設定單元1〇8是否設定該資料區域，鄉成該第二備用區域。 ⑩ tmt數值大於-預定計數值時，該設定單元1G8設定該綱記憶體ιι〇， 以分配-部分的資料賊作為麟二翻區域。觸定計練例如是該快 閃記憶體的抹存計數值(wear leveling counter)，亦即抹存計數值係為該快閃 記憶體的使用狀態。 在一實施例中，該錯誤修正碼(ECC)容量係表示該快閃記憶體11〇的複 數個預定位元組(bytes)之可修正複數位元(bits)數量·»該第一備用區域與該第 二備用區域的儲存容量正比於該錯誤修正碼(ECC)容量。 201015561 • 繼續參考第1圖，該快閃記憶體110的控制訊號包括命令栓鎖致能訊 號(command latch enable signal，SCLE)、晶片致能訊號(chip enable signal， /SCE)、寫入致能訊號(write enable signal, /SWE)、位址致能訊號(address latch enable signal, SALE)、讀取致能訊號(read enable signal, /SRE)、輸入/輸出 (input/output signal，I/O)訊號以及預備/忙碌訊號(ready/busy signal，R/B) 〇 晶 片致能訊號(/SCE)表示當快閃記憶體110受到快閃記憶體控制器loo激發 時，該快閃記憶體110處於致能(active)狀態。例如當快閃記憶體11〇處於 ❹ 低準位時，該快閃記憶體110處於有效狀態。寫入致能訊號(/SWE)表示當 寫入致能訊號(/SWE)被激發時，例如是低準位時，將資料寫入至該快閃記 憶體110。 讀取致能訊號(/SRE)表示當讀取致能訊號(/SRE)被激發時，例如是低準 位時，讀取該快閃記憶體110内的資料。當該命令栓鎖致能訊號(SCle)被 激發時’該命令在寫入致能訊號(/SWE)的上升緣栓鎖。當該位址致能訊號 (SALE)被激發時，該位址在寫入致能訊號(/SWE)的上升緣栓鎖。輸入/輸出 ® (I/O)訊號表示傳輸於該快閃記憶體110與該資料暫存器之間的訊號。該預 備/忙碌訊號(R/B)表示該狀態模組報告給該快閃記憶體控制裝置100的狀態 訊號。 在一實施例中，快閃記憶體控器100提供給快閃記憶體11〇的寫入致 能訊號(/SWE) ’將選定的頁面(page)之位元組資料寫入至快閃記憶艘ι1〇， 且錯誤修正碼(ECC)模組106亦接收該位元組資料並產生相對應於該頁面的 錯誤修正碼(ECC)值。當該頁面中全部的位元組資料寫入至快閃記憶體no 201015561 ’ 之後’快閃記憶體控器100將該頁面的錯誤修正碼(ECC)值寫入至該頁面的 備用區域。接著當錯誤修正碼(ECC)值寫入完畢之後，傳送一寫入確定命令 至該快閃記憶體110 ’並且藉由將晶片致能訊號(/SCE)設為高準位，以使該 快閃記憶體110禁能(disable)。 參考第1-3圖’第3圖係依據本發明實施例中執行快閃記憶鱧控制器 1〇〇的控制方法之流程圖，以適應性(adaptively)設定錯誤修正碼(ECC)容 量。該快閃記憶體控制器100包括控制單元102、緩衝器104、錯誤修正碼 ® (enw ewrection code, ECC)模組106以及設定單元108，該方法包括下列步 驟： 在步驟S300中，控制單元102產生寫入命令，用以寫入該資料内容至 該快閃記憶體110。 在步驟S302中，該控制單元1〇2寫入該第一錯誤修正碼(ECC)值至該 第一備用區域。 在步驟S304中，該控制單元1〇2產生讀取命令，以讀取該快閃記憶體 ® 110的資料内容。 在步驟S306中’錯誤修正碼模組1〇6利用該資料内容產生第二 錯誤修正碼(ECC)值。 在步驟S308中，該錯誤修正瑪识叫模組1〇6峨該帛二錯誤修正碼 (ECC)值胃修正郷⑹值’赚據賊機絲蚊該資料内 谷是否存在複雜錯辦。當未包括錯誤碼，返回步驟S3Q4，侧執行步 驟 S310。 201015561 . 在步驟S310中，當該資料内容存在該些個錯誤碼時，利用設定單元ι〇8 計算該些錯誤碼的數量，以決定該錯誤碼的數量是否超出一預定臨界值。 當超出該預定臨界值，執行步驟S312a，而當未超出該預定臨界值，執行步 驟 S314。 在步驟S312a中’該設定單元1〇8設定該快閃記憶體的資料區域， 以分配一部分的資料區域作為一第二備用區域，其中該第一備用區域以及 該第二備用區域的儲存容量相關於該錯誤修正碼(ECC)容量，以使該錯誤修 ® 正碼(ECC)模組106修正該資料内容的錯誤碼。接著執行步驟S318。 在步驟S312b中，儲存一計數值於該第一備用區域，以依據該計數值 來決定該設定單元108是否設定該資料區域，以形成該第二備用區域。接 著在步驟S316中，當該計數值大於一預定計數值時，該設定單元1〇8設定 該快閃記憶體110，以分配一部分的資料區域作為該第二備用區域。 在步驟S314中，該錯誤修正碼(ECC)模組106依據該第一備用區域的 第一錯誤修正碼(ECC)值以及該第二錯誤修正碼(ecc)值，以修正該錯誤碼。 鲁 在步驟S318中，該錯誤修正碼(ECC)模組106依據該第一備用區域以 及該第二備用區域的第一錯誤修正碼(ECC)值以及該第二錯誤修正碼择cc) 值，以修正該錯誤碼。 綜上所述，本發明使用一部分的儲存容量來執行高階的錯誤修正碼 (ECC)機制，以改善非及閘(Nam))快閃記憶體的可靠度。該錯誤修正碼 (ECC)機制依據快閃記憶體的使用狀態具有多段調整式修正資料之能力。因 此可以利用額外的錯誤修正碼(ECC)容量來提高快閃記體的使用壽命。 12 201015561 ' 雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，本 發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍内， 當可作各種之更動與潤飾’因此本發明之保護範圍當視後附之申請專利範 圍所界定者為準。 【圖式簡單說明】 第1圖係依據本發明實施例中快閃記憶體控制器之方塊圖，係以設定 單元來適應性設定錯誤修正碼(ECC)容量。 第2圖係依據本發明實施例中非及閘型式的快閃記憶體之結構 示意圖，其中該快閃記憶體具有第一備用區域以及第二備用區域。 第3圖係依據本發明實施例中執行快閃記憶體控制器之流程圖，以適 應性(adaptively)設定錯誤修正碼(ECC)容量。 【主要元件符號說明】 1〇〇快閃記憶體控制器 102控制單元 104緩衝器 106 ECC模組 108設定單元 11〇快閃記憶體 13201015561 IX. Description of the Invention: [Technical Field] The present invention relates to a memory device and a method thereof, and particularly relates to a memory bribe (four) having a fault correction code capacity setting unit and a method thereof, and a method Set the usage status of the memory. [Prior Art] 10 Flash memory is a non-volatile memory that retains data even after the power supply is removed. Non-gate _ AND, delete type memory is a quick question memory 'has a density of hiding' and other kinds of _ note, with. Special offer] _ memory has the characteristics of large storage capacity, better memory access speed and low cost. >^^#iE.^(error correction code, ECC)# is a common function of the nand flash memory controller. NAND ‘flash memory with multi-layer wafers (muitiievei ceu) is less expensive and is widely used in solid state drives (IV) id state drives (φ SSD). However, multi-layer wafer NAND flash memory Zhao also has shortcomings, such as reading for long-term endurance*, while poorer read-to-length multi-layer wafer nand flash memory Zhao leads to solid state disk drive (SSD) Reliability is declining. In this case, it is necessary to develop a new type of flash memory to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a center-of-the-body controller with an error correction code (ECC) capacity setting unit and a method thereof for improving the flash memory control according to the flash memory The error correction of the device is the capacity of the device. 201015561 This side is another - the purpose is to provide a flash memory controller with a wrong count positive unit and its method to improve the read/write durability (d) of the flash memory and reliability . In order to achieve the above object, the present invention provides a flash memory controller having a correction code capacity setting unit and a method thereof. The flash memory controller includes a control unit, a buffer, an error correction code (ECC) module, and a setting unit. The control unit is configured to generate a read command to read the flash fiber, and the memory has a heterogeneous region, stores the data, and has a first-prepared domain to store the corresponding data. The first error correction code (ECC) i of the data content. The buffer is used to store the data content from the data area of the flash memory. The error correction code (ECC) module generates a second error correction 郷cc) value by using the data content, and compares the second error correction code (ECC) value with the first error correction code and then hides according to the comparison The mosquito is the forest in the complex _ code (e_). When the data content has the error codes, the setting unit calculates the number of the error codes to determine whether the number of the error codes exceeds a predetermined threshold. ® specific button 'the number of error codes exceeds (4) pre-emption skew, the setting unit sets the data area of the flash memory through the control unit to allocate a part of the data area as the second spare area, wherein the first The spare area and the storage capacity of the second spare area are related to the error correction code (ECC) capacity such that the error correction code (ECC) module corrects the error code of the data content. On the other hand, when the number of the error codes is less than the predetermined threshold, the error correction code (ECC) module compares the second error correction code (eCC) value with the first error correction code 戌cc) value. The result is to fix the error codes of JL. According to the above, when the number of error codes exceeds a predetermined 201015561 • threshold value, the setting unit effectively increases the error correction code (eCC) capacity of the flash memory controller. The control method for executing the flash memory controller of the present invention comprises the steps of: generating a read command to read the data content of the flash memory; and (2) generating a first error correction code by using the data content ( (3) comparing the second error correction code (ECC) value with the first error correction code (ECC) value to determine whether the data content has a plurality of error codes according to the comparison result; (4) When the data content has the error codes, the setting unit calculates the number of the error codes to determine whether the number of the error codes exceeds a predetermined threshold; and (5) the setting unit 6 Flashing the data area of the memory to allocate a part of the data area as a second spare area, wherein the storage capacity of the first spare area and the second spare area is related to the error correction code (ECC) capacity, The error correction code (ECC) module corrects the error code of the data content. The present invention uses a portion of the storage capacity to perform a high-order error correction code field cc) mechanism to improve non-AM (NAND> just memory The erroneous mad code (Ε(χ) mechanism has the ability to adjust multiple corrections according to the flash memory's status. The additional error correction code (ECC) capacity can be used to upgrade the life experience. In order to make the present invention more versatile, the preferred embodiments are described below, and are described in detail with reference to the following drawings: [Embodiment] Referring to the first 1 '' In the example, the block diagram of the flash memory controller (four) 100 is adapted to set the error correction 郷 cc) capacity. The fast memory 201015561 body controller 100 includes the control unit 102 and the buffer i〇4. The error correction code (ECC) module 106 and the setting unit i 〇 8 the flash memory controller loo control setting unit 108 ′ to adaptively adjust the error correction code (ECC) of the flash memory 11 〇 Capacity. The error correction code (ECC) is mainly used to improve the data integrity of the flash memory and ensure the reliability of the data access. The flash memory no is, for example, a hand. Type of flash memory. The flash memory controller 100 is coupled to the flash memory 110. The control unit 1 is coupled to the setting unit 108 and coupled to the flash memory 11 through a plurality of control signals. The control unit 102 generates a write command for writing the data content to the flash memory, and writing the first error correction code (ECC) value to the first spare area (as shown in FIG. 2) The error correction code (ECC) module 106 and the setting unit 108 are respectively coupled to the control unit 1〇2, and the buffer 104 is coupled to the error correction code (ECC) module 1〇6, respectively. Flash memory 11〇. Referring to FIG. 1 and FIG. 2, FIG. 2 is a schematic structural view of a non-NAND (NAND) type flash memory according to an embodiment of the present invention, wherein the flash memory has a first spare area and a first Two spare areas. The control unit 102 is configured to generate a read command to read the data content of the flash memory 110. The flash memory 110 has a data area to store the data content, and has a first spare area to store the phase. A first error correction code (ECC) value corresponding to the content of the material. In one embodiment, the flash memory ι 10 stores the data content from a plurality of pages 1 . The buffer 104 is used to store the data content from the data area of the flash memory 11A. An error correction code (ECC) module 106 generates a second error correction code (ECC) value using the data content and compares the second error correction code (ECC) value with the first error correction 8 201015561 (ECC) value and then Determining whether there is a plurality of error codes (errors) according to the comparison result. When the data content has the error codes, the setting material (10) calculates the number of the error codes to determine whether the number of the error codes exceeds one. The threshold is predetermined. Specifically, when the number of tactile errors exceeds a predetermined threshold, the job unit (10) sets the flash record through the control unit 1〇2, and the data area of the 11() is used as the data area of the distribution-part. a second spare area, wherein the storage amount of the first spare area and the second spare area is related to the error correction, ECC) capacity, so that the error correction code (Ε(χ)Module® is the The error code. In another aspect, when the number of the error codes is less than the predetermined threshold value, the error correction code (ECC) mode, the group 1〇6 is based on the second error correction code (ECC) value and the first error. Correct the horse (ECC) value comparison result to correct the error codes. According to the above, when the number of error horses exceeds -敎 threshold, the mosquito material 1G8 has a high hung (b_) error correction of the memory controller 100 The code (ECC) capacity further includes a -counting area, a count value of the age, and determining, according to the count value, whether the setting unit 1〇8 sets the data area, and the second spare area When the tmt value is greater than - the predetermined count value, the setting unit 1G8 The memory of the program is ιι〇, and the data thief of the distribution-part is used as the lining area. For example, the wear leveling counter of the flash memory, that is, the erase count value is The use state of the flash memory. In an embodiment, the error correction code (ECC) capacity is an executable multi-bit of a plurality of predetermined bytes of the flash memory 11 ( ( The number of bits » the storage capacity of the first spare area and the second spare area is proportional to the error correction code (ECC) capacity. 201015561 • Continuing to refer to FIG. 1 , the control signal of the flash memory 110 includes a command pin Command latch enable signal (SCLE), chip enable signal (SCE), write enable signal (SWE), address enable signal (address latch enable signal) , SALE), read enable signal (SRE), input/output (I/O) signal, and ready/busy signal (R/B) The power signal (/SCE) indicates that the flash memory 110 is flashed When the memory controller loo is excited, the flash memory 110 is in an active state. For example, when the flash memory 11 is at a low level, the flash memory 110 is in an active state. The energy signal (/SWE) indicates that data is written to the flash memory 110 when the write enable signal (/SWE) is activated, for example, at a low level. The read enable signal (/SRE) indicates that the data in the flash memory 110 is read when the read enable signal (/SRE) is activated, for example, at a low level. When the command latch enable signal (SCle) is activated, the command is latched at the rising edge of the write enable signal (/SWE). When the address enable signal (SALE) is activated, the address is latched at the rising edge of the write enable signal (/SWE). The Input/Output ® (I/O) signal indicates the signal transmitted between the flash memory 110 and the data buffer. The ready/busy signal (R/B) indicates the status signal that the status module reports to the flash memory control device 100. In one embodiment, the flash memory controller 100 provides a write enable signal (/SWE) to the flash memory 11' to write the byte data of the selected page to the flash memory. The ship ι1〇, and the error correction code (ECC) module 106 also receives the byte data and generates an error correction code (ECC) value corresponding to the page. When all the byte data in the page is written to the flash memory no 201015561', the flash memory controller 100 writes the error correction code (ECC) value of the page to the spare area of the page. Then, after the error correction code (ECC) value is written, a write determination command is sent to the flash memory 110' and the wafer enable signal (/SCE) is set to a high level to make the fast The flash memory 110 is disabled. Referring to Figures 1-3, FIG. 3 is a flow chart showing a method of controlling a flash memory controller 1 in accordance with an embodiment of the present invention to adaptively set an error correction code (ECC) capacity. The flash memory controller 100 includes a control unit 102, a buffer 104, an error correction code (ECC) module 106, and a setting unit 108. The method includes the following steps: In step S300, the control unit 102 A write command is generated for writing the data content to the flash memory 110. In step S302, the control unit 102 writes the first error correction code (ECC) value to the first spare area. In step S304, the control unit 102 generates a read command to read the data content of the flash memory ® 110. In step S306, the error correction code module 1〇6 uses the material content to generate a second error correction code (ECC) value. In step S308, the error correction module 〇 峨 峨 峨 错误 错误 错误 错误 错误 错误 EC 胃 胃 胃 胃 胃 胃 胃 胃 胃 胃 胃 胃 胃 胃 胃 胃 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 When the error code is not included, the process returns to step S3Q4, and the side proceeds to step S310. In step S310, when the error codes exist in the data content, the number of the error codes is calculated by the setting unit ι 8 to determine whether the number of the error codes exceeds a predetermined threshold. When the predetermined threshold is exceeded, step S312a is performed, and when the predetermined threshold is not exceeded, step S314 is performed. In step S312a, the setting unit 1〇8 sets the data area of the flash memory to allocate a part of the data area as a second spare area, wherein the storage capacity of the first spare area and the second spare area are related. The error correction code (ECC) capacity is such that the error correction code (ECC) module 106 corrects the error code of the data content. Then step S318 is performed. In step S312b, a count value is stored in the first spare area to determine whether the setting unit 108 sets the data area according to the count value to form the second spare area. Next, in step S316, when the count value is greater than a predetermined count value, the setting unit 〇8 sets the flash memory 110 to allocate a portion of the data area as the second spare area. In step S314, the error correction code (ECC) module 106 corrects the error code according to the first error correction code (ECC) value of the first spare area and the second error correction code (ecc) value. In step S318, the error correction code (ECC) module 106 selects the cc) value according to the first error correction code (ECC) value of the first spare area and the second spare area, and the second error correction code. To correct the error code. In summary, the present invention uses a portion of the storage capacity to perform a high order error correction code (ECC) mechanism to improve the reliability of the non-lamatom (Nam) flash memory. The error correction code (ECC) mechanism has the ability to modify data in multiple stages depending on the state of use of the flash memory. Therefore, additional error correction code (ECC) capacity can be utilized to increase the life of the flash recorder. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a flash memory controller in accordance with an embodiment of the present invention, which is adapted to set an error correction code (ECC) capacity by a setting unit. Fig. 2 is a schematic view showing the structure of a flash memory of a non-gate type according to an embodiment of the present invention, wherein the flash memory has a first spare area and a second spare area. Figure 3 is a flowchart of the execution of a flash memory controller in accordance with an embodiment of the present invention to adaptively set the error correction code (ECC) capacity. [Main component symbol description] 1〇〇 Flash memory controller 102 Control unit 104 buffer 106 ECC module 108 setting unit 11〇 Flash memory 13