TW201011862A - Intralevel conductive light shield - Google Patents

Abstract

A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

Description

201011862 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure including a conductive light shield, and a method for fabricating the structure. And the design structure of this structure. • [Prior Art] A para-pixel sensor includes a pixel sensing cell array that detects a two-dimensional signal. The pixel sensor includes an image sensor that converts a visual image into digital data and can be represented by an image, that is, an image frame. These pixel sensing cell lines are unitary elements for converting the above two-dimensional signals (which may include a visual image) into digital data. Commonly used pixel sensor types include image sensors used in digital cameras and light developing devices. These image sensors include charge-gathering devices (CCDs) or complementary metal-oxygen semiconductor (CM〇s) image sensors. • Although CMOS image sensors have been developed late compared to CCDs, CMOS image sensors offer lower power consumption, smaller size, and faster data processing than CCDs. It also provides a direct digital output that is not available in ccD. At the same time, 'CMC' S image sensors have lower manufacturing costs compared to CCDs' because many standard semiconductor processes can be used to make CMOS scenes like image sensors. For the above reasons, in recent years, cM〇s image sensors have been used commercially for a steady growth trend. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> shows an exemplary conventional semiconductor circuit including an image sensor pixel. The exemplary semiconductor circuit includes a photodiode 201011862 PD, a gi〇bal shutter transistor GS, a transfer gate transist TG, and a reset gate transistor ( Reset gate tTansist〇T) R_G, a source 随 ce ce ce 电 、 、 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 This call is called the transfer gate electro-crystal ship pole) constitutes a floating clock

One end of the photosensitive diode PD is grounded, and the other end of the photosensitive diode pD is directly connected to the source of the global shutter transistor GS (referred to as a full-domain shutter transistor source in this specification) And the source of the transfer gate transistor TG (referred to as the transfer gate transistor source in this specification). The pole of this transfer gate transistor is the source of the source-coupling transistor SJF _; 蛊; 5;, 丨 {2, ee 1 | θ.

This exemplary semiconductor circuit can be used as an alternative to form an image. The array of image sensors can form an array of image sensors that can be used for any optical, infrared, and selective power output node. Reset the IGS's drain and source to capture an image. This 201011862 helmet or rabbit external imaging device, including digital cameras. Every τ De 忒 J is - pixel. The operation of this array image sensor::-: sensor unit read program. The grading includes - the exposure of the silk sequence and - the reading program is line by line ^ 5 shouting using the global shutter method. This change. _ I仃卩 The time for reading the program is two lines per line: No: Exposure program and reading one ❷ The number of 汲 汲 节 ϋ ϋ ϋ 二 二 二 在 在 在 = = = = = = = The shutter-time object-time is shown as the time indicated by hv. In the figure, the photon system has a wavy arrow, and its weight control signal gSC turns on the global shutter transistor GS, ^ltr(PmningV〇ltaSC) ° ^苴 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This global shutter control signal gse is then changed to the t1 domain shutter transistor GS. At this stage, the same-global shutter control two gsc is applied to all the other shutters of an image sensor, including all the photodiodes of the detector, including the light in Figure 1:: Under the light, and generate a charge. The photodiode i r point continues to accumulate at one node of the photodiode 1^, which is connected to the global shutter transistor gs and the transfer gate transistor TG. The reset gate RG is turned on by the reset gate control signal rgc, and thus the voltage level of the active drain node FD. The same reset request control signal 丨.gc is applied:: 201011862 All the other resets in the image sensor will turn the voltage of the FD node into 9 bodies. In the case of a crane, the net is the same. The reset RG is then supplied with the voltage vdd substantially _. Same-reset between =3=^ body' to turn off all the other reset gates in the image sensor; (4), at the reset gate === = the voltage of the node FD remains the same Level. Transfer Ο Two-pole (four) charge accumulation two == == Turn-on transistor TG is transferred to floating 汲: two sets Γ ^ is applied to all other transfer-closed transistors and the voltage collected 'via - Shifting the closed crystal in the ! The transfer gate transistor G and other transitions (4) are moved in a row-by-row manner by shifting (4) (4) (4), and the line to be read is selected sequentially from the first line until the last-behavior. The row-selective cell system for each row is controlled by a total of two select signals rsc. Therefore, there can be a common = selection signal that is the same as the number of rows. Once a row is selected, the selection of the electrical RS in all rows of the selected row is turned on. The voltage generated by the voltage of the FD of an oceanic bungee node from the system power supply voltage Vdd changes proportionally with the number of photons generated by the photodiode pD, and the number of photons described above is affected by the impact. The amount of incident light of the photodiode PD changes in an equal proportion. The data at each pixel is fined out and the voltage is read in each column. The voltage level provides a first amount associated with the amount of charge generated by the photodiode PD. 201011862 For the selected row, the reset gate transistor is then turned on. This action allows a second number of reads, which are the background level signals for each pixel in the row. Subtracting the second quantity from the first quantity compensates for any circuit-related errors that occur when generating the first number of current measurements. In other words, any circuit-specific image data generated from the image sensor can be eliminated. error. However, there is a small amount of charge leakage from the floating dipole node FD to the substrate via the transfer gate transistor TG and the reset gate transistor RG because almost every device has a leakage current path. In practice, the most severe leakage is typically the leakage current generated by resetting the gate transistor. This leak changes the voltage of the floating gate node fd at the stop time (between the exposure program and the reader). Leakage current The noise in the noise in the signal in the image sensor pixel stops - approximation. Therefore, the noise caused by the global shutter method is a repentant image. The global shutter method uses the shadow of the whole two objects. The shadow of the shadow is the same as that of the whole image. In the first 7G of the pixel, the money is converted to a single 7G towel for all the lines. Go to the corresponding floating voltage and then continue from the image array. The / in the expansion method allows fine (four) (four) ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The time between the two columns in the queue is the time required for the r signal to be left in the floating time of the indefinite single line. ^ can have the least #待_, corresponding to the reading, corresponding to the integer image The reading number may have the longest waiting time because of the leakage charge or charge generation. The charge generation at the diffusion of the floating diffusion charge between the eight and the charge will have a significant effect on the quality of the floating number. For the letter shutter image read by the rhyme sensor, the standard for storing the initial charge efficiency is called "the signal of the global r" and "when the signal is read, the signal should be captured and captured; In the CMOS image sensor, the global shutter efficiency should be 1 (). However, this does not affect the effect of the leakage charge and/or charge on the actual teeth, and the image quality is relatively reduced. The floating diffusion of a shift gate transistor typically includes a pn junction at which any incident photon can generate additional charge by photocharge generation (ph〇t〇generati〇n), which changes at this node. The charge signal retained. These incident photons are therefore the noise of the signal retained by the floating diffusion. In order to prevent the incident light from reaching the floating diffusion, the current image sensor pixel design uses the inner connecting layer metal wire (interconnect Level metal wiring) 'It is formed on a via layer to block incident photons as a light screen. The wiring of the metal interconnect layer is thus limited to match the arrangement of the light screen. The closer to the floating in 201011862, the better the dynamic diffusion is to minimize the incident photon angle f that may reach the floating diffusion from the scattering angle. In some cases, adding a light screen while changing the internal connection wiring structure may require additional wiring. Channel, which may have a negative impact on the effective fill factor of the image sensor pixels used to collect the light, or may add unnecessary capacitance to the floating spread. According to the above, it is effective to provide floating diffusion. Shielding 2 The metal wiring of the metal wiring in the cm〇s image sensor pixel... has its market demand, and its design structure is also the same. ^ Bu' can provide a more angle protection for the floating pole The pixel structure of the CM0S image controller that does not adversely affect the metal wiring has its market %%, and its design structure is also the same. The light screen Smo does not have the S-line channel, however, it is effective for the floating pole. 〃 ? Its market demand, its design structure [invention content] In the layer, a screen is formed in the metal connection structure by a screen system of (4)^-layer window第二. The second dielectric layer is formed on the fine layer of the image sensor. The conductive screen covers a window of 201011862, which is formed from a top surface of the second dielectric layer. 2 into at least one via layer - in the lower order layer between the metal line layers, or in the top-side and - between any of the inter-metal interconnecting via layers, the germanium-metal layer cells are less susceptible to noise. For the light above the pixel pole of the image sensor. The stray light screen blocks the floating in the present invention, the CMOS image is located in a first dielectric layer and the second; j-light screen structure Forming at least a via window, the system is electrically connected, and the inner connection is formed between two gold (four): ===, and the sensory can be singularly erected, and the invention is also proposed. The design, manufacture, or testing of the design for the (10) image element, including: the light screen is located in the image sensing transducer, the data of the conductive screen, the conductive screen is The design lies between one and tenth: two-layer and - second dielectric layer. At least a germanium layer is formed in the metal interconnect structure from the one surface extending from the first dielectric layer to the first dielectric layer. This transmission county screen can be formed into a contact layer towel, its system boundary - semiconductor i two: face! Between a metal wire layer, or formed in any metal interconnected layer, between two metal wires. (3) 〇s shadow 12 201011862 signal noise detector pixel can be subsequent One of the semiconductor structures in the drain is provided to form - at least half of the top surface of a semiconductor substrate is formed on at least one of the semiconductor elements to form a conductive light panel, At least a node of a semiconductor component is detached; and a top surface, wherein the junction via is a body-opening. 2 a conductor-forming interface, wherein the junction layer is a substrate ▲ The board of the material of the material screen is more away from the semiconductor screen application, the method further includes forming at least a metal line in the conductive layer window - top ^, wherein the metal line - the bottom surface In another embodiment, the method further comprises: forming a dielectric substrate cover layer on the top surface of the semiconductor substrate, and forming a dielectric layer on the electrical substrate Above; and forming-middle process a middle-of-line 'MOL) dielectric layer overlying the substrate substrate, wherein the at least the gold riding system is formed directly on the intermediate process dielectric layer. According to another aspect of the present invention Providing a method for forming a semiconductor structure, comprising: 201011862 forming at least one semiconductor component over a top surface of a semiconductor substrate; forming a layer on the top surface of the semiconductor substrate to form at least a first layer metal line Forming a top surface of the at least-first-layer metal line - a first dielectric forms a conductive optical screen over the at least - semiconductor element, and the optical screen is directly located on the first dielectric layer a top surface; and a second dielectric layer formed over the conductive screen, wherein the first layer and the first dielectric layer completely encapsulate the conductive screen. In an example, the method further includes: forming a contact via directly on the at least-second layer metal line, wherein the contact layer is formed into a body-formed structure without any physically formed interface. And forming at least a second metal line therein In the second dielectric layer, wherein the metal line is directly formed on a top surface of the contact via window, and in another embodiment, the method further includes: in the first dielectric layer Forming a metal disk on the top surface, the metal disk is separated from the conductive light screen by the same material composition and thickness ; of the conductive light screen; and the metal disk is directly formed on the surface of the metal disk - Contact via window. Metal::; = shot 'This method further includes forming another contact via vial. In yet another embodiment, the method further includes: 14 201011862 directly in the dielectric layer Forming a first metal disk on the top surface, the first metal disk having the same material composition and the same thickness as the s-thin conductive screen; forming a first dielectric portion directly on one of the top surfaces of the conductive screen The first dielectric portion has a plurality of sidewalls that substantially perpendicularly conform to the sidewalls of the conductive screen; a second dielectric portion is formed directly over a top surface of the first metal disk , having the same material composition and the same thickness as the first dielectric portion ; And Lu directly forming a second metal plate over the second portion of the top surface of one of the dielectric. According to still another aspect of the present invention, there is provided another method of forming a semiconductor structure, comprising: forming at least one semiconductor component over a top surface of a semiconductor substrate; forming a conductivity over the at least one semiconductor component a light screen, wherein the at least one semiconductor component is separated from at least one node of the at least one semiconductor component (nod; • forming at least one metal line on a top surface of the conductive optical screen; and directly on the at least one metal line A contact pad is formed on one of the bottom surface and a top surface of the at least one semiconductor component. In one embodiment, the contact via is an integrally formed structure without any physically formed interface therein. In another embodiment, the conductive screen includes at least one downwardly projecting window portion adjacent one of the at least one semiconductor component, wherein the entirety of == includes the at least one downwardly projecting via window portion The same component 15 201011862 = is 'and is formed into a body without any physical interface formed in 1 , and the portion of the via that protrudes downward from the cap layer is laterally The electric substrate is covered in still another embodiment, the method further comprising: forming a dielectric substrate cover layer directly on the top surface of the semiconductor substrate, which is located under a portion of the conductive optical screen; and Forming a middle-process dielectric layer over the substrate cover layer under the at least one metal line. 7. In accordance with the present invention, a semiconductor structure is provided, including: at least a semiconductor component a top surface of the substrate; a conductive optical screen located on the charm-casting core and separated from at least one node of the at least one semiconductor component; at least one metal line on a top surface of the conductive optical screen And the contact layer is adjacent to the bottom surface of the at least the domain line and the top surface of the at least one semiconductor element. In the embodiment, the contact via window is an integrally formed structure. In another embodiment, the semiconductor structure further comprises: - a dielectric substrate covering (4) to a top surface of the material guide plate, and located under one of the conductive light screens And a middle-process dielectric layer M4 is over the dielectric substrate cover layer and under the at least one metal line. 16 201011862 The other-facing device provides another semiconductor structure, including: J - ί conductor 70 pieces are located - a top surface of the semiconductor substrate; a surface layer 1 - a metal line 'separated from a top surface of the semiconductor substrate; 1 electrical layer 'which is adjacent to the top of the at least one of the first layer of metal lines - a conductive screen disposed over the at least one semiconductor component and proximate to a top surface of the first dielectric layer;

The first dielectric layer is disposed on the conductive optical screen, wherein the first dielectric layer and the second dielectric layer encapsulate the entirety of the transducing optical screen. In an embodiment, the semiconductor structure further includes: a second metal line buried in the second dielectric layer; and a contact via window adjacent to a bottom surface of the at least one second metal line and a top surface of one of the at least one first layer of metal lines. In another embodiment, the semiconductor structure further comprises: a metal disk having the same material composition and the same thickness as the conductive optical screen, the metal disk being in close proximity to the top surface of the first dielectric layer, and Separating from the conductive screen; and another contact via, which is adjacent to one of the bottom surfaces of the other second metal line and one of the top surfaces of the far metal. According to still another aspect of the present invention, there is provided a design structure implemented in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising: Λ 17 201011862 -, - Data 'representative The semiconductor component is located on the semiconductor substrate; a first data-representative-conductive optical screen is located at the local interconnect layer and located above the semiconductor component; the first data 'represents the metal line - among the metal interconnect layers, the metal interconnect layer is over the local interconnect layer; and - the fourth data 'represents" the contact via window is adjacent to the metal line and the semiconductor component. In another embodiment, the design structure further includes: - a fifth data representation - a dielectric substrate cover layer adjacent to the top surface of the semiconductor substrate and located under one portion of the conductive light screen; and - The six data represents that the middle layer process dielectric layer is located above the dielectric substrate cover layer and is located under the at least one metal line. In yet another embodiment, the design structure further includes another data representative of a mid-range process (MOL) dielectric substrate layer adjacent to the dielectric substrate cover layer and a non-planar bottom surface of the passivation screen. In still another embodiment, the sixth data includes: a seventh data representing a lower middle 制f line (M〇L) dielectric layer directly bonded to the bottom surface of the conductive optical screen, One of the top surfaces of the process layer of the low towel stage process is coplanar with a top surface of the conductive screen; and an eighth data representing a higher middle layer process dielectric layer adjacent to the A bottom surface of one of the at least one metal lines and adjacent to a top surface of the lower middle dielectric layer. 18 201011862 In yet another embodiment, the design structure of the contact via is adjacent to another data of the conductive light warfare, representing the other of the other bottom surfaces. In a further embodiment, the second data comprises a downwardly projecting via window portion immediately adjacent to the at least = according to at least one of the conductive light screens, including the at least 2 One of the readings is that the reference system is composed of the same component and is formed by the body and the window portion is surrounded by the substrate cover layer. The 丨 layer _ part is laterally divided by the dielectric in another implementation, this design structure includes _ line frequency plus chest). In another embodiment, the design structure is stored in a storage medium as a data format for exchanging layout data of the integrated circuit.鬌 * In another embodiment, the semiconductor device includes one of the floating gates of the shifting transistor of the image sensor pixel. According to still another aspect of the present invention, there is provided a design structure implemented in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising: a first data representing a semiconductor component Located on a semiconductor substrate; a second data 'represents a first layer of metal lines separated from a top surface of the semiconductor substrate: a third data representing a first dielectric layer adjacent to the at least one first layer of gold 201011862 a top surface of the line; a semiconductor element-fourth data 'representative-conductive optical screen located at least above and adjacent to the top surface of the first dielectric layer; and overlying therein; Table: The second dielectric layer is located on the conductive optical screen, and the itf-dielectric layer and the second dielectric layer comprise the conductive optical screen as a whole. The design structure further includes: Representing a second metal line buried in the second dielectric layer; and - a seventh data representing a contact via window adjacent to the at least second layer metal, -= face, and the at least - - One of the layers of metal lines is the page. In yet another embodiment, the "contact pad" window is an integrally formed structure without any physically formed interface therein. F--implementation, the design structure further includes: • unit eight data, representing a metal disk having the same as the conductive optical screen; the knife and the same thickness, the metal disk is adjacent to the first dielectric layer The top surface is separated from the conductive screen; and the ninth data represents another contact interlayer window adjacent to the bottom surface of the other second layer metal line and a top surface of the metal disk. In the second embodiment, the design structure further includes another data, representing another bottom surface of the other metal line and the metal disk 20 201011862. In still another embodiment, the design structure further includes: The data represents a first metal disk having the same thickness as the material component of the transfer, wherein the first metal disk is the same top surface and separated from the conductive light screen; and &quot;Electrical layer: tenth- The data 'represents a first-dielectric portion immediately adjacent to the face'. The first-dielectric portion has a plurality of =2 screens in conformity with the side of the conductive auxiliary; d real, vertically vertical _ - twelfth lin' represents _ The second dielectric portion is separated from the first dielectric portion; and the thickness, wherein the second one of the thirteenth data represents a τth surface. The metal disk is adjacent to the second dielectric portion of the cable list. In yet another embodiment, the design structure includes: In yet another embodiment, the semiconductor structure includes a floating sensor of the image sensor pixel-floating pole. In another embodiment, the fourth data includes another data, and the at least one of the via window portions is located in the conductive optical screen, wherein the at least one via 3 portion is vertically adjacent to the first Conductor The conductor is a source region, a region, or a gate of a field effect transistor. Following the example, this design structure includes another data, representing at least a face. The mesa window of the Ui screen is adjacent to the conductive screen - Top 2! 201011862 [Embodiment] The optical screen is invented by the semiconductor structure, which includes -conductivity /, ^ and its design Structure, and will be described below in conjunction with the schema. In the description of the components of the present invention, the articles "an article "_", "this", "this" are used to mean one or more elements = in the drawings, the same reference numerals are used in the description of the present invention. Or letters are used to refer to similar or equivalent elements. For the details of known Wei or structure, for the sake of clarity, it is not necessary to rely on the present invention to represent its proportion. Please refer to FIG. 2 , which is an exemplary layout of a semiconductor circuit of the present invention, including a unit image sensor pixel 200 ′ including a photodiode 21 〇 , a floating drain 220 , and an active area portion 23 . Hey. The active region portion 23 includes a source and a drain block for use as a global 4-channel transistor (not explicitly shown), a reset gate transistor (not shown in the figure), and a source with (four) power. Crystals (not clearly indicated in the figure), and a row of selector transistors (not clearly labeled). A shifting transistor gate line 215 is located between the photodiode 2丨〇 and the floating drain 2 2 。. A reset gate transistor gate line 225 is located between the floating drain 22 () and the active region portion 230. A global shutter gate line 2〇5 is located between the active area portion 230 and the photodiode 210. A source follower gate line 235 and a row of selector gate lines 245 are located within the active region portion 23A. A light screen 280, represented by a dashed square, covers the area of the floating drain 22A. Preferably, but not necessarily, the &apos;screen 280 also covers the active area portion wo. The light screen 280 can block light&apos; to cause 彳-τ first charge generation (ph〇t〇generati〇n) to be suppressed within the floating dipole 220 and the active area portion 230. In the floating immersion no, the electric charge carrier generated in 201011862 can be reduced in the floating dipole 220 to store the electric charge, and the signal represented by the formula is stored in the hopper μ storage system. 230 in the t ti 7 carrier, when using the transistor in the active region portion 230 to sense the stored charge, the electrical signal of A is enhanced by the positive signal. TU# is reduced by the background of the operation of the transistor杂 4 Π , , , , , 根据 根据 根据 根据 根据 根据 根据 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — U 3 structure 6 - the first-last stage process is an in-line layer connection structure 9, which is composed of 7 and 8 - the second gold pixel 200. As a unit of FIG. 2, the sensor semiconductor substrate 2 includes Half of the exhibition show n (doping). 2 〇,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The t-layer 12 under the 3G includes a part of the direct bit field 32. The first-conductor type semiconductor region is the first conductive semiconductor region. - Conductive type is the opposite of the first - conductive type. For example, the first pass or all may have a second conductivity type doping, and one part of the direct source or all of the 'source electrodeless region 42 (not shown) In the demonstration, the material is formed and formed in the second conductivity type well as is well known in the art. The '' source and the drain region 42, 23 201011862 include the 7 to construct the word county board 2 Semi-conducting material _sheng example=1, pin alloy part 1, wrong, supplementary alloy part = mouth P is, 矽锗 carbon alloy part, arsenic clock carbon ring gold sulfide, other m Wei indium, _ indium gallium Indium, indium, and, for example, 'Shi Xi can be used as the semiconductor core, the first half of the well half of the hand movement ^ (four), and / or the field effect transistor's source and bungee are also Also, the 'semiconductor layer 12 is a single crystal structure, column. More preferably, the HM 2 body is difficult to be squashed, and the squarish row of the slabs are all in addition to the shallow trench isolation structure 20. That is, the semiconductor material is crystallized in atomic thickness in the source well of the entire semiconducting crystal, ', floating drain 4, and or field effect, for example. By applying a photoresist layer (not shown) on a semi-conductive substrate 2 Φ pad (not shown) and then performing an anisotropic (10) engraving of the pattern of the photoresist - The dielectric material 彡' then the depth of the shallow trench can be planarized by about lit. The shallow trench isolation structure is added from LU ^ υ υ water (nm) to about 600 nm ' and typically Between =5°°N., however, the smaller or larger thickness 'typically is the one part of the semiconductor layer 12'. The first conduction penalty has the same doping* The thickness of the &lt;d〇Pant) thick and soiled A bean region 32. depends on the thickness of the semiconductor layer|2 between the 201011862 pole & the electric layer 50, and the thickness of the second conductivity type charge collecting well 30, and It can be between about 500 nanometers and about 5 nanometers, and is typically between 999 nm and 3000 nm.净 The net moving dipole 40 has a second conductivity type doping, and when the transfer transistor is turned off to allow charge storage, the floating dipole is electrically floating, wherein the transfer transistor includes a second conduction type charge collection Well 3 汲, floating bungee 4 〇, and - between the two ^ - and - channel. Preferably, a separate implant (4), such as a mask, is used to independently control the depth of the second conductivity type charge collection well 3''''''''''' Preferably, the depth of the floating drain* is less than the depth of the second conductivity type charge collecting well 30. The dopant concentration of the floating drain 4 可以 may be between about ^101^13 to about 1, Gx 1G21/em3, and typically between (10) 1018/cm ^ , 〇 x 1 〇 2 〇 / cm 3 , The consideration of the month. The depth of the floating bungee (measured by the top surface of the +conductor substrate 2 and the bottom of the floating secret _ flat portion between about 30, m to about 3 (8) nm' and typically between about the meter ==300 is not between 'however, a larger or smaller depth is also considered in the present invention to sigh the second type charge - to form a photodiode (32, 3G), It will generate electrons and holes: the first subordinate = guided charge sub-system is proportional to the county to light II (four) in the second conduction type charge collection well 3Q (32, 3_ the number of precursors. In the t When the oxygen type is used and the second type is η type, the 'electron system is collected in the second pass = for the P well 30. When the first type is the type and the second type is the waiting type, the hole is in the The second conduction type charge collection (4) is collected. - First ^ = 201011862 The semiconductor material in the photonic diode and the photodiode (32, 3 〇) is produced by the semiconductor material in the semiconductor substrate 2 with two photon wavelength ranges of two The generation of photocharges generated by electron and hole pairing ==: Naiyi 一1 = ❹ ❹ mm * ^ 奸 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The second conductivity type charge collection well. In the absence of the series, the money: the polar body (32, 3G) lacks the area junction and turns into a master carrier, that is, a first ^ is located in the first conduction type. In the semiconductor region 32, a closed circuit is generated in a well, and if the circuit is sealed as a second pass (four), the common charge is charged. Especially if the carrier is in the middle, the second conductive charge is collected. The well is equal to the number of incident photons (assuming that == Μ before the entry into the lack of the region] the second carrier is combined with the main carrier of the photodiode in the photodiode, then the subcarrier will be “remained” by the combination. The stomach produces electric current or accumulates electric charge. 201011862 The second conductivity type of the 30-conducting semi-conductive Zhao material is formed by the regenerative electro-crystal system and the photodiode (3G, 32)-body formation; =: polar body type electric time Is the shift _ crystal - receive 1 is the electron H-type electric hybrid (ride 帛 帛 - material type / Τ * 3 〇 accumulation. When the transfer gate is turned on to guide the 电 ❹ well 3 〇 charge carriers The electricity that will be transferred to the floating gate 4 传导 in the conduction type charge collection and transferred from the photodiode 2) is a charge collection well. Type Wei Weiji 3 is used to transfer the material to read the crystal. I========================================================================================= The dielectric source and the gate metal semiconductor alloy region may still include - a semiconductor oxide substrate or a ruthenium oxynitride, or may include, for example, a cerium oxide. The λ 5 叮 ^ f is well known as a high dielectric a coefficient gate dielectric or a doped semiconductor material, such as a doped polycrystalline stone material or may include a gold metal semiconductor alloy region 59 and a source electrode used in the intermetallic electrode The metal semiconducting 'and the formation of i 4η to 49' are obtained by reacting a metal with a semiconductor material having a source and a gate region 42, a floating gate, and/or a gate 52. The pole gate 2 wire (four) blue 6G system is directly formed on the top surface of the semi-conductor plate 2, the dielectric gate 58 , the inter-metal semiconductor alloy region 5 (), and the source and the bungee gold 201011862 semiconductor alloy region 49. Above. The dielectric substrate cover layer 6 includes an electrical material such as a dielectric emulsion or a dielectric compound. For example, the dielectric substrate cover layer 6 may include a silicon nitride layer. The dielectric substrate cover layer 60 has a semiconductor substrate 2 and a gate structure to which a tensile stress or a tensile stress is applied. The dielectric substrate overlay 60 can be formed by low pressure vapor deposition (LPCVD), high speed thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), ® high density plasma chemical vapor deposition (HDPCVD). And other methods are formed. The thickness of the dielectric substrate cover layer 60 can be between about 1 nanometer and about 15 nanometers, and typically between about 25 nanometers and about 75 nanometers, although larger or smaller. Thickness is also considered in the context of the present invention. A middle-of-line (MOL) dielectric substrate 62 is formed over the dielectric substrate overlay 60. The mid-stage process dielectric substrate 62 can include, for example, a CVD oxide. The CVD oxide may be an undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (psg, phosphosilicate), fluorine. Fluorite glass (FSG), borophosphosilicate glass (BPSG), or a mixture thereof. The thickness of the mid-process dielectric substrate 62 can range from about ι to about 200 nm. Alternatively, the mid-stage dielectric substrate 62 may comprise an organosilicate glass (〇SG) or another low-k dielectric material having a dielectric constant of 2.8 or less. The mid-stage process dielectric substrate 62 can be formed by a conformal deposition or a non-smooth deposition. The mid-stage process dielectric substrate layer 62 is in close proximity to one of the top surfaces of the dielectric substrate cover layer 60. 201011862 A photoresist (not shown) is coated on the middle-process dielectric substrate 62 and patterned by light micro-views, and a hole 'semiconductor is formed on at least one node of the underlying semiconductor device. Components include transfer transistors and other transistors. The pattern in the photoresist is transferred to the mid-process dielectric substrate 62 and the dielectric substrate cap layer 62 to form at least one via via which extends to a semiconductor component on the semiconductor substrate 2. The nodes of the semiconductor elements above the semiconductor substrate 2 are selectively exposed, that is, at least one node is exposed, and at least another node is not exposed, so that only nodes to be electrically connected are exposed to at least one interface. Layer = the bottom end of the hole. For example, a via hole may be formed directly on the floating drain, and a drain metal semiconductor alloy region 49 is exposed, and directly connected to the gate of the source follower transistor of the pixel of the image sensor Another via window is formed over the pole 5 2 to expose a gate metal semiconductor alloy region. An opaque conductor layer (not shown) is deposited by methods known in the art, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like. The opaque conductor layer may comprise a metal material and may comprise crane, chin, titanium nitride, nitride, nitride, or alloys as described above. Alternatively, the impermeable 2 conductor layer may comprise a -doped semiconductor material, such as doped polycrystalline stone, via a heterogeneous alloy, or the like. The opaque conductor layer fills all of the at least one via in the mid-process dielectric substrate and in the dielectric substrate cap layer. The conductive screen 78 is formed without patterning the bright conductor layer by photolithography, and the bovine case covers the floating dipole 40 and other transistors except for the portion of the photodiode 0'32). . The area covered by S to the conductive screen of 78 jin corresponds to the portion of the screen 280 of Fig. 2. The conductive screen 78 includes at least a downwardly projecting via portion that is tied 20 201011862 7 ΤΓ light t-conductor for the supply of conductor elements. (10) The entirety of the conductive screen 78 includes the at least - downwardly projecting via portion, the material composition. The entirety of the conductive screen 78, including the at least one of the vias, may be a body-formed structure without any physical form. The at least one downwardly projecting via portion is laterally encased by an intermediate dielectric substrate 62 and a dielectric substrate cover layer 6〇. The bottom surface of the 5 = 78 is adjacent to the middle section of the dielectric system. The top surface is non-planar. The contour of the bottom surface of the materialized screen 78 is similar to the rim of the plasma substrate 62 and is also non-planar. The illuminating screen 78 can include at least two bottom portions, which are separated by a substrate. The conductive screen; the rim is similar to the conductive screen %% of the bottom age conductive light | 78 with the flat portion of the conductive screen 78 is too large, although larger or smaller thickness is also in the present invention Consider it. 4 between the 'conductive light screen 78, because it is adjacent to the semiconductor to the floating pole 4 〇 and / or the top surface of the soil in the sensing circuit' and thus the incident light at the arc angle, thereby suppressing the floating: r〇eL and No. 1: The photodiode among the transistors in the large circular structure, and the transistor of the semiconductor sensor image sensor. This conductivity may be - it allows only in the conductive screen 2 = 苡 = cloth 78 system miscellaneous, such as the ship's surface shot, and does not allow the full ^ sensor in the unit image sense Outside the area of the pixel. - Field king phase internal phase, for example 30 201011862 A mid-stage process dielectric layer 80 is formed over the exposed portion of the conductive optical screen 78 and the mid-process dielectric substrate 62. The mid-process dielectric layer 8 can comprise a CVD oxide, an organic tellurite glass (〇SG), or another low-k material having a dielectric constant of less than 2.8 as described above. The mid-process dielectric layer .80 can be formed by a conformal or non-smooth deposition. Preferably, the mid-stage process dielectric layer 80 is planarized by chemical mechanical planarization (CMp). Alternatively, the mid-process dielectric layer 80 may comprise a self-planarizing material such as a spin-on-glass (SOG) or a spin-on low-k dielectric material having less than 2 8 Dielectric constant. The thickness of the intermediate dielectric layer 80, whether after planarization or after planarization of the material, is sufficient to cover the entire top surface of the conductive screen 78. Preferably, the top surface of the middle-process dielectric layer 80 is at a distance from the highest portion of the top surface of the conductive screen 78 to avoid dielectric breakdown caused by the dielectric layer 8 of the middle-stage process (dielectric) Breakdown). Preferably, the distance is greater than 2 nanometers and more than 100 nanometers. The middle layer process dielectric layer 8 is an integrally formed junction without any physically formed interface therein. The mid-process dielectric layer 80 is directly connected to the bottom surface of the conductive screen 78 at the bottom end of the sidewall of the conductive screen 78. A photoresist (not shown) is applied over the dielectric layer 8 of the mid-stage process and patterned by photolithography to form at least one hole. The pattern in the photoresist is transferred to the semiconductor device through the middle-process dielectric layer 8, the middle-process dielectric substrate 62, and the dielectric substrate cover 60, and exposed to the semiconductor device 2 One node. This photoresist is selectively removed for the dielectric process layer 8 of the mid-stage process. A metal is deposited on the exposed surface of the middle dielectric layer 8 L on the exposed surface of the at least one hole, including the exposed surface of the semiconductor component: 201011862 The deposited metal is on the top surface of the middle layer dielectric layer 8G The upper part is removed by a combination of plane=back_, or two methods, and the part of the deposited metal remaining in the hole constitutes at least a contact via 88, which is from the section process The top surface of the dielectric layer 80 extends through the dielectric process (4) 8 〇, the middle split dielectric substrate 62, and the dielectric base 6G, and reaches a top of the semiconductor component above the semiconductor base 2 On the surface. For example, the at least one of the % m dot vias 88 can contact the top surface of the source and the drain metal semiconductor alloy region. Each of the at least-contact layers may be shaped by a single-deposition step without exposure to air. Thus, each of the at least-contact vias is a body-formed structure without any physically formed interface therein. Each of the two-contact "layer windows 88 has a top surface" which is defrosted with the middle-stage process dielectric layer 8::: a dielectric layer window 88 and has a bottom surface 'the system and the dielectric layer The bottom surface of Liu is coplanar. At least the contact via window 88 comprises a metal material such as tungsten, twisted, titanium, nitrided, nitrided, and nitrided. The second dielectric layer 90 is borrowed. Above the layer 8G by a method known in the art, conventional methods include chemical vapor deposition deposited by 2. The first-metal layer dielectric layer 9 is typically referred to as a mi layer. (4) Μ is -4 (four) layer, secret allows cross

1 wiring of the ¥ Β θ θ piece. The first-gold metallization is in the first-metal layer dielectric system in a pre-recorded pattern of gold (10). The f μ layer is sub- and filled with metal to form a first and the i-A/^ ray may include, for example, copper or a scale material. The first metal line 98 is connected to a top surface of the d/丨 plane δ vertically adjacent to the 〆201011862 ΐϊ # 98 #一底底. The conductive screen 78 is located below the first metal line layer, -&gt; The middle layer dielectric layer 8 is adjacent to the first metal line 98, the back-end-of-line dielectric cap layer no, and the second layer-two=layer 120, as is known in the art. The method is formed on the first metal line layer connection == two, conventional methods include chemical vapor deposition and spin-on deposition. The second interface s window is formed in the lower portion of the back-end dielectric coating 110 and the second dielectric ❹I 12G. The second layer of trenches I located above the second via is formed within the "higher" portion of the second dielectric layer 12(). Using a combination of physical vapor deposition and electric boat, the metal fills the second via and the first trench. The deposited metal is planarized by chemical mechanical polishing (CMp), back-engraving, or a combination of the two methods to form a second via window 108 and a second metal line 118. The second via window 1 8 and the second metal line 118 may comprise a material such as copper or aluminum. The back-end process dielectric cap layer 110, the lower portion of the second dielectric layer 120, and the second via window 108 together form a first back-end process (BE〇L, b^ack-end-of-line The connection structure 8 in the interlayer window layer. The higher portion of the second dielectric layer 12A and the second metal line m together form a (four) two metal line layer connection structure 9. Additional via layer interconnect structures (not shown) and additional metal line layer interconnect structures may be formed as desired. Referring to FIG. 4, which is a variation of the first exemplary semiconductor structure of the present invention, a conductive optical screen 78 is directly formed on the dielectric substrate cover layer 60. In addition, the middle dielectric layer 8 is formed directly on the top surface of the conductive screen 78 on the top surface of the 201011862 and on the top surface of the dielectric substrate cover layer 6G. In other words, the variant of Figure 3 is not a + conductor structure - the middle section process dielectric _ 62 body structure variant is omitted. (4) In the middle section, the dielectric layer 80 is located under the metal line 98 above the dielectric substrate covering layer (10). Conductive light screen 78 includes, which is in close proximity to a semiconductor component. Conductive light = window: the portion is laterally covered by the dielectric substrate cover layer 60. Referring to FIG. 5', it is according to the present invention:: impurity-conducting junction = a semiconductor substrate 2, the first - 丄: upper: The connection structure 9' is the same as the first embodiment. The second example - dielectric frosting ^ &lt; substrate contact interlayer window layer connection structure 4, comprising a + segment process dielectric bottom 62, its composition and junction base = (two) two 2 orders f The dielectric substrate 62 is directly formed on the dielectric layer of the middle-stage dielectric lining process: the AS can be included by the -_ a process dielectric layer 80 Α. The CVD oxide may be an undoped silicate glass (USG), a borosilicate glass (BSG), or a phosphosilicate glass (PSG). , Fluorite glass (FSG), borophosphosilicate glass (BPSG), or a mixture thereof. Alternatively, the lower mid-stage process dielectric layer 80A may comprise an organosilicate glass (OSG) or another low dielectric constant dielectric material having a dielectric constant of 2.8 or less. The mid-process dielectric layer 80A is then planarized by methods such as chemical mechanical polishing (CMP). ❹ In another case, the lower middle process dielectric layer 80A is formed by a self-planarization process, such as spin coating. The lower mid-stage dielectric layer 8A may comprise spin-on-glass (SOG) or a porous or non-porous low-k material having a dielectric constant of less than 2.8. The photolithography process is then used to remove the portion of the lower mid-process dielectric layer 8A above the conductor element, which portion is subsequently covered by a conductive screen. For example, 'coatable-resistive agent in the lower middle stage process (four) such as eight +

The process dielectric substrate 62 or the dielectric substrate cover layer (9) is selective.

Structurally, and through the sub-transistor of the semiconductor component under the light and other low-medium dielectric dielectric layer 201011862 80A is removed, that is, the hole is formed in the area of the subsequent optical screen. The pattern of photoresist is then transferred to the substrate 62 and the dielectric substrate cover 6 to form at least a hole 'which extends to the semiconductor element above the semiconductor substrate 2. Each node of the semiconductor element above the semiconductor substrate 2 is selectively exposed, and at least one node is exposed, and at least one node is not exposed such that only the electrically connected node is exposed to at least one The bottom of the layer aperture i is exemplified and the s ' can be formed - the via hole is exposed - the fused metal semiconductor alloy region 49 (which is directly above the floating drain) and can form another dielectric; I is exposed - A metal semiconductor alloy region 59 (which is directly above one of the gates 52 of one of the source image sensor pixels). ~ - An opaque conductor layer (not shown) is deposited by methods well known in the art, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like. The opaque conductor layer may comprise a metallic material&apos; and may comprise a crane, titanium, group, titanium nitride, nitrided group, gasified crane, or an alloy as described above. Alternatively, the opaque conductor layer may comprise a doped semiconductor material such as a doped polysilicon, a doped bismuth alloy or the like. The opaque conductor layer fills the dielectric removed in the lower mid-stage process; the volume removed by the f 80A towel is below the top surface of the remainder of the lower mid-section dielectric layer 80A. The opaque conductor layer is also filled with all of the at least one via in the towel dielectric substrate 62 and the dielectric substrate overlay. The opaque conductor layer is planarized by methods such as chemical mechanical polishing (CMP) to form a conductive optical screen 78, for example, which is covered with a floating drain 40 and other transistors, except for the photosensitive diode. Outside the part of (3〇32). The area covered by the conductive screen 78 corresponds to the area of the screen 280 in FIG. 36 201011862 Conductive light screen 78' includes at least one downwardly projecting via portion that is in close proximity to a semiconductor component and provides contact to the semiconductor component. The entirety of the conductive screen 78' includes the at least one downwardly projecting via portion, which may have the same material composition. The entirety of the conductive screen 78, including the at least one downwardly projecting via portion, may be an integrally formed structure without any physically formed interface therein. The at least one downwardly projecting via portion is laterally surrounded by the mid-process dielectric substrate 62 and the dielectric substrate cap layer 60. The bottom surface of the conductive screen 78' is in close proximity to the top surface of the intermediate process dielectric substrate 62. This top surface is non-planar. The contour of the bottom surface of the conductive screen 78 is contoured to the middle of the dielectric process 62 and is also non-planar. The ground screen, conductive screen 78, can include at least two bottom surface portions that are separated from the + conductor substrate 2 by different distances. The conductive screen 78 may have a top surface which is coplanar with a top surface of the second middle section = Jing 80A. Conductive light screen; 8, thick Ϊ to the thinnest part of the screen π to make the measurement reference, can be about 1 〇 对 对 对 对; 之 各 ; 结构 ; ; ; ; ; 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构The electro-crystal of the pixel sensor image sensor. These transistors may be a line layer, which allows wiring to be performed only on the area of the splayed V-screen 78, which is a portion of the local conductive screen 78', and (4)*. . For example, it is limited to the area of the unit image sensor 201011862 pixels and does not allow for global connections across this area, such as outside the area of the unit image sensor pixels. A higher mid-stage process dielectric layer 80B is formed over the conductive optical screen 78 and over the top surface of the lower mid-process dielectric layer 80A. The higher mid-stage process dielectric layer 80B may comprise a CVD oxide, an organic tellurite glass (〇SG), a spin-on glass (s〇G), a porous or non-porous spin-on material, or Another low dielectric constant material has a dielectric constant of less than 28 as described above. This higher mid-stage process dielectric layer 80B can include any material that can be used in the lower mid-stage process dielectric layer 8A. The lower middle process dielectric layer 80A and the upper middle process dielectric layer 8B together form a middle process dielectric layer (80A, 80B). Preferably, the upper middle layer dielectric layer 80A has a bottom surface. A distance is maintained from the top surface of the conductive screen 78 to prevent any dielectric breakdown through the higher mid-section process dielectric layer 80B. Preferably, the distance is greater than 20 nanometers, and more preferably greater than 1 nanometer. There may be a physically formed interface between the lower mid-process dielectric layer 80A and the upper mid-process dielectric layer 8B. The lower middle process dielectric layer 8A is directly connected to the bottom surface of the conductive optical screen 78 at the bottom end of the conductive screen 78. In one embodiment, the lower mid-section process dielectric layer 8A and the upper mid-stage process dielectric layer 80B comprise the same dielectric material. In another embodiment, the lower mid-stage process dielectric layer 80A and the higher mid-stage process dielectric layer 80B comprise different dielectric materials. A photoresist (not shown) is applied over the upper mid-stage dielectric layer 8B, 201011862 and patterned by photolithography to form at least one hole. The pattern in the photoresist is transferred to the higher middle-stage process dielectric layer 80B, the lower-stage process dielectric layer 80A, the middle-stage process dielectric substrate 62, and the dielectric substrate cover layer 6〇, and exposed. A node of one of the semiconductor elements above the semiconductor substrate 2. This photoresist is selectively removed for the mid-process dielectric layer 80. A metal layer is deposited on the exposed surface of the intermediate portion process dielectric layer 80B, and on at least one of the holes, all surfaces including the exposed surface of the semiconductor component. The portion of the deposited metal on the top surface of the dielectric layer _ of the higher middle section is removed by planarization, reverberation, or a combination of the two methods. The portion of the deposited metal remaining in the at least one hole constitutes at least one contact layer g 88, and the money extends from the top surface of the upper middle layer dielectric layer 8GB through the middle portion process dielectric layer (nen_ The middle-process dielectric substrate 62 and the dielectric substrate cover layer 6〇 reach the top surface of the semiconductor element above the semiconductor substrate 2. For example, the to-contact via (10) can contact a top surface of one of the source and the gate metal semiconductor alloy domains 49. The at least-contact layer (4) can be formed by a deposition process without exposure to the air. Thus, each of the at least one joint is an integrally formed structure without any physically formed dielectric material. Each of the 2-contact vias 88 has a top surface that is coplanar with the mid-process dielectric layer / (A, _ - top surface, connected to the dielectric window (10) and has a bottom basin Dielectric substrate covering layer ^ and titanium nitride. $ L Titanium, Xianzhen, Ni Ni, with the first-metal layer internal connection structure 6, _ first-back stage system Na e〇l) 201011862 layer window layer connection structure 8. The connection structure % in a second metal wire layer is formed by the method of the first embodiment. Additional via layer connections are not included) and additional metal line layer connections can be formed as needed. Referring to FIG. 6, which is a second embodiment of the semiconductor structure of the present invention, the optical screen 78 is directly formed on a dielectric substrate cover layer 6〇. The lower middle-stage dielectric layer is formed directly on one of the top surfaces of the dielectric substrate overlay. In other words, the second-stage semiconductor dielectric substrate 62' in the second exemplary semiconductor structure shown in FIG. The two examples of the semiconductor structure change If are omitted. The dielectric layer 80 is formed directly on the surface of the conductive screen 78. The middle layer dielectric layer (80 Å, 80 Å) is located on the dielectric substrate cover layer 6 位于 and under the first metal line 98. Conductive screen 78 includes at least a downwardly projecting via portion that is in close proximity to a semiconductor component. At least one of the downwardly projecting via portions of the conductive screen 78' is laterally surrounded by the dielectric substrate covering the layer 6. The bottom surface of the conductive light screen 78' is non-planar and is in close proximity to the top surface of the dielectric substrate cover layer 60. Referring to FIG. 7 , a third exemplary semiconductor structure of a third embodiment of the present invention includes a semiconductor substrate 2 low first metal line layer connection structure 6 and a first back end process (BEOL). The layered inner layer connection structure 8 and the second metal line layer inner connecting structure 9' are the same as the first embodiment. The third exemplary semiconductor structure further includes a substrate contact via inner connection structure 4 including a dielectric substrate cover layer 60 and a middle process dielectric substrate 62 having the same composition and structure as the first embodiment. . 10 201011862 In the formation of the dielectric substrate cover layer 60 and a middle section = direct her age 62 transmission wall - ^ bottom layer. Before forming the opaque conductor layer, at least one of the hole conductors is formed on the dielectric substrate cover layer 60 and the middle layer process dielectric substrate. The opaque conductor layer is then patterned to form a -conducting = screen ^ screen identical to the embodiment. The conductivity φ of this third embodiment is in close proximity to the -half (four) butterfly portion, which is (d) to the +conductor 7 member and provides contact to the semiconductor element. The dielectric method is formed by the middle-stage process () == process dielectric layer, the middle-stage process dielectric lining == above - the range of the semiconductor component. At least the second type of via hole system is from the middle stage process ==, and the delay is over the middle layer process dielectric layer 8〇 to reach the transmission screen. The first type of via hole is formed in the conductive screen 78 to have a small range of -====1: the exposed surface of the dielectric layer 8〇 and the top surface of the process dielectric layer 80 The exposed surface of the H-type hole. In the middle section (4), the remaining deposited metal forms at least one contact via; = 1 41 201011862 - the present electrocardiographic substrate is covered by the disk layer 6G' and reaches the semiconductor substrate 2 shaped τ thin conductor - the top. For example, the at least—contact meso-m 汲 汲 金属 合金 合金 合金 合金 合金 合金 J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J 89' extends from the top surface of the middle layer dielectric layer 8A through the top surface of the conductive light shield 78 from the tantalum dielectric layer 80. The at least one contact via 88 and the at least one metal screen contact are formed using a single-deposition step without contact with the air =: the fi via 88 and the at least - the metal screen contact Layered window; ', the interface of the structure without any physical axis: the at least-contact via window 88 and the at least one metal light screen contact via: the surface layer and the segment process dielectric layer (nen, _ The top surface of the common flat cover layer is 88. The bottom surface has a bottom surface and the dielectric substrate is covered with a hemp and a white surface. The mother-metal optical screen contact via 89 has two materials such as crane, titanium, group, nitrided, nitrided, and nitrogen=conductive light screen 78' due to its proximity to the semiconductor substrate 2 For each transistor in the sensing circuit, it can block the large circle j Ρ 在 在 在 在 在 在 在 在 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 九 九 九 九 九 九 九 九 九Wiring is performed on the area covered by the metal wire 42 201011862. The conductive light screen 78 is locally limited, for example, limited to the area of the pixel of the unit image sensor, and does not allow &lt;cross-domain connection across the area', such as in a pixel of a unit image sensor. Outside the area, a first metal wire layer inner connecting structure 6, a first back end process (be〇l), a "layer® layer inner connecting structure 8, and a second metal wire layer inner connecting structure 9, can be utilized as It is formed by the method used in an embodiment. An additional via structure (not shown) and an additional metal line interconnect structure can be formed by 0. ^ Please refer to FIG. 8 'which is a third example A variation of the semiconductor structure, wherein a conductive optical screen 78 is directly formed on a dielectric substrate cover layer 60. The intermediate f-process dielectric layer 80 is directly formed on the top of the dielectric substrate cover layer 6 The surface = and the top surface of the conductive screen 78. In other words, the third example of the semiconductor process dielectric substrate 62' in Fig. 7 is a variation of the semiconductor structure in the third example: the dielectric layer (10) Located on the dielectric substrate cover layer 6G, and placed under the ground 2:: The conductive screen 78 includes at least one downwardly projecting downwardly from two to two semiconductor elements. The layered window portion (not shown) of the dog in the conductive screen 78 is laterally mediated. The surface of the silk cup of the beauty cup 筌 Μ , , , 姐 四 四 四 四 四 四 四 四 = = = = = = = = = ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The semiconductor substrate 2 and the first metal wire layer are connected to the junction 201011862 ^ HI - the second metal wire layer inner connecting structure 9 , which is the same as the first embodiment. In the four semiconductor structures, the conductive light is not formed. The screen is connected to the structure 4. Instead, a conductive optical screen Μ is connected to the fourth-stage (BE0L) via layer of the fourth embodiment to be used as a fourth exemplary semiconductor structure processing method. The manufacturing method for forming the J-type non-semiconductor structure is the same, except that the process steps for forming the conductive screen in the connection structure 4 in the dielectric layer are omitted: it is not necessary to reduce the dielectric in the middle-stage process. In other words, it can also be formed in the case where the semiconductor structure towel is omitted. On the entire dielectric substrate cover layer 6〇. After the “electric substrate” is known as the metal wire layer internal connection structure 6, the method is used in the field (I include chemical gas debulking and spin coating deposition) to find the first The gold inner connecting structure 6 forms a late-stage process dielectric cap layer UG and a lower two-layer dielectric layer 12GA. The lower second dielectric layer i can comprise any material that can be used in embodiments to form the second dielectric layer 12G... gold = two dielectric layers 12 from above and patterned by photolithography A conductive optical screen 124 and a metal resistor 122 are formed. The conductive screen m covers the extent in the fourth semiconductor structure. The conductive screen m can cover, for example, a floating drain 4 〇 2 = body ' except for the photosensitive diode (9) in the - unit image sensing transducer. The area covered by the conductive screen 24 corresponds to the area of 280 in Fig. 2. For each transistor that slams the poles and/or senses the circuit, 44 201011862, the conductive screen 124 can block the incident light at a large arc angle, thereby suppressing the movement of the poles 40 and Four examples show that the optoelectronics in each of the transistors of the semiconductor structure are generated and these transistors may be the transistors of the pixel of the unit image sensor. The inter-optical screen 124 and the metal resistor 122 have the same composition and phase &quot; Conductive screen 124 and metal resistor 122 may comprise a conductor of gold metal nitride &apos; which has a suitable electrical resistivity. For example, the phosphor screen 124 and the metal resistor 122 may comprise a nitride group, a titanium nitride, a nitrogen metal Thunder day, a bismuth, a tantalum, an alloy thereof, or a combination thereof. The conductive screen 124 and preferably the thickness of the crucible 122 may be between about 1 nm and about 100 nm, and between about nanometer and about 30 nm, although the present invention also considers the top surface. And the example of the half of the cup and the (1) of the first metal wire 98 is less than the distance between the wires, which is referred to herein as the top of the first distance surface, and the top of the lower first dielectric layer 120A. The top and the top of the semiconductor substrate 2 and the ray are referred to herein as the second distance d2. The bottom surface of the conductive screen 124 is the bottom surface of the resistor 122, which is adjacent to the lower second dielectric layer leg. The second layer is used for the lower second dielectric layer.

And a second dielectric layer -20A of the south is formed to form a dielectric layer 120. The second brother-layer&quot; layered L system is formed in the second dielectric layer|2〇. At least - the 201011862 - type second via hole _ the second dielectric layer 12GA, the red dielectric layer 120B, the lower metal (four) - top surface. Each of the process dielectric cap layers (10) reaches a first-type second-layer via hole of the conductive-type optical film 124 extending to the metal resistor 122. At least one second type of second interlayer window is formed in the range of the metal resistor 122: #. The less-m-layer mesoporous line trough is formed by the combination of the vapor deposition and the thief by using the method of the second-layer dielectric layer 120B. Two-layer mesopores and first-layer performance; type and first type of mechanical grinding _ upper layer or = combination: square ==: type first layer of mesopores form first type first type second The layer (4) is formed in the second portion by the second layer, and the second layer is formed by the second layer, the second layer of the interlayer layer 1G9, and the second metal. The wire U8 may comprise a conductive optical screen 124 of the fourth embodiment, such as a copper or material material. In particular, the entire surface of the conductive screen 124 is in close proximity to the lower second dielectric layer and the higher second dielectric layer 'and the conductive screen m is the first dielectric layer (120A) , 120B) coated. The back-end process dielectric cap layer 110, the lower second dielectric layer A, the lower portion of the higher second dielectric layer 120B, the conductive optical screen] 24, the metal resistance ° 22 - the first type The two-layer vias (10), 'and the second-type second-layer vias h) 9 a form the first back-end process (BE0L) via-layer interconnect structure 8. The upper portion of the higher layer 201011862 dielectric layer ugb and the second gold pad 118 together form a second metal line layer connection structure 9. Additional interconnect layer interconnect structures (not shown) and additional metal line interconnect reductions can be formed as needed. Although the present invention describes that the conductive optical screen 124 is formed between the plurality of first metal lines and formed in the first metal line layer connection structure 6, and the second gold f two metal line (four) connection structure 9 , familiar with the technology « , any first metal wire separated from the top surface of one of the conductor substrates 2, and any second layer located on the upper layer of the first metal wire: genus = linear ^ - have the same The structure of the conductive screen. The present invention is clarified as follows: Fig. 10 is a fifth internal connection structure 4, n is a board, a substrate, according to the fifth sound of the present invention. The contact layer layer layer inner layer connection structure 9 4: Γ: structure 6, and - the second metal sheet, is the same as in the fourth embodiment. The structure in the connection structure 8 in a first 徭 = = OL) interlayer window layer is: the first example of the general W cover layer 11 〇 and a connection, the formation of a back-end process on the structure ) and - node 4 layer dielectric layer. From: the metal layer (not the second dielectric layer) 20 Α above, the formed stack is formed in the lower light screen 丨 24 and the dielectric portion of the light lithography patterning, forming a conductive Ί * 55: ^ n , the first stack of ®, and the second stack of "Maoji and - node dielectric 132" - "Chef low 47 201011862 by the transmission of light screen 124 and The first portion of the fifth semiconductor structure covers the portion of the fifth semiconductor structure that is to be removed from the incident light. The first stack of the screen 124 and the dielectric portion 134 can cover, for example, floating 汲 = 4 〇 and other transistors, except Outside the range of the diodes (3〇, 32) of a unit image sensor pixel, the range covered by the first stack consisting of the conductive screens 124 and 134 corresponds to the one in FIG. ^ 280 range. Consisting of conductive light screen 124 and dielectric part 134 = stacking 'pair #纽极4G and / or sensing electricity%% block large arc (four) reading light, brain suppression county 4Gjf = Z The photo-charge generated in each transistor of the semiconductor structure, and this can be the power of a unit image sensor pixel The crystal has a conductive screen 124 and a lower capacitance electrode 122, and the same thickness. Conductive light I, with a fine composition to - conductor gold:: lower electrode 122, may include _ = two = wide screen and lower capacitance electrodes can be used to package 22 and 24 and lower capacitance electrodes 122, the thickness of which can be between 'and typically between about 5 nm to: =: 〇 large or small thickness In the present invention, although the top surface of the conductive screen 124 and the lower capacitance electrode is farther away from the top surface of the semiconductor board 2, the metal line 98 OQ_body substrate 2, for example. In the first and second 蠄=face and the surface of the semiconductor substrate 2, the distance between the top surface of the semiconductor substrate 2 is increased. The distance from the bottom surface of the conductive optical screen 124 and the lower surface of the lower capacitive electrode 122 is the thickness of the kidney layer 12 〇 A. The recording of the adjacent low-red dielectric layer i Μ 132 series has phase _ composition and The phase H/^ portion 123 - the dot dielectric 132 comprises a dielectric material, such as hydride 7. The dielectric age 123 and the thickness of the node dielectric f 132 may be between about 3 〇. Between the meters, although a larger or smaller thickness is also formed on the node dielectric 132 in the photomicrolayer (not shown) of the present invention, and is formed into a higher capacitance electrode 142. Higher capacitance (10) c虱·曰, nitrite, nitriding scale, New Zealand, Chin, crane, its alloy, the thickness of the potentiometer electrode can be between about 1 Nai to between about 1 nanometer, 'Hami to about 3G nanometer Between the larger or smaller thickness of the axis is also considered in the present invention. The Ray dielectric layer 12GB is formed on the dielectric portion 134, the node dielectric layer, and the higher capacitance electrode 142. . The higher second layer β includes any material Si, a dielectric layer 12A, and a higher second dielectric layer 120, which are available for the lower second dielectric layer 120A, and a common gamma-electric layer m. Three types of ar ancient two-hole solid holes are formed in the second dielectric layer 12G. At least - the first type of second interlayer window is extended

Sri electric layer Cong, lower second layer dielectric layer ship, and post-process dielectric cover layer 1U), and reaching the first metal line 98 of the at least one first penalty _ &quot;di-ji, 丨The layer window is formed outside the conductive screen 丨24 201011862. At least &quot;&quot; the second type of second interlayer via extends through the upper second layer, the dirty portion - to the lower capacitive electrode 122. Each of the at least first-eri-th window apertures is formed within the range of the lower capacitance electrode 122 and outside the range of the higher capacitance electrode 142. At least - the third type of via hole extends to the high capacitance electrode 142. Each of the at least - third type second layer via holes is formed within the range of the higher residual electrode 142. The wire channel is formed in a higher portion of the higher second dielectric layer β 12GB by methods known in the art. A deposition step, such as a physical vapor deposition and an electrical combination method, is performed to fill the metal in the second-type, second-, and third-type second-layer vias and the second-layer trench. The deposited metal is planarized by chemical mechanical polishing (CMP), etch back, or a combination of the two to form a first type of second via 1 in the first type of second via. 〇8, forming a second type second via window 1〇9 between the second type second interlayer vias, and forming a third type second among the third type second interlayer vias The via window 1〇9, and the first metal line Π8 is formed in the line trench. The first type second via window 1 〇 8, the second type second layer via layer 109, the third type second via 109, and the second metal line 118 may include, for example, copper or aluminum. material. The two dielectric layers are coated with the conductive optical screen 124 of the fifth embodiment. In particular, the stacked entirety of the conductive optical screen 124 and the dielectric portion 134 is adjacent to the lower second dielectric layer 120A and the higher second dielectric layer 120A, and is comprised of the conductive optical screen 124 and The stack of dielectric portions 134 is covered by a second dielectric layer (Ι20Α, 2〇Β). Therefore, the conductive optical screen 124 is covered by a second dielectric layer (丨20Α, 120Β). 201011862 The lower capacitor electrode 122', the node dielectric 132, and the higher capacitance electrode 142 together form a metal-insulator-metal capacitor (MIMCAp^ back-end process dielectric cap layer 110, lower second dielectric layer 120A) a lower portion of the upper second dielectric layer 120B, a conductive optical screen 124, a dielectric portion 134, a MIMCAP (122', 132, 142), a first type second via window 1〇8, The second type first layer via window 1G9 and the third type second layer via window 1 () 9 together form a connection structure of the BE-back layer process layer (BEOL) vial layer. The souther portion of the layer dielectric layer 12A and the second metal line 118 together form a second metal line beta layer interconnect structure 9. Additional via layer interconnect structures (not shown) and additional metal line layers The internal connection structure can be formed according to the requirements. Referring to FIG. 1 , a sixth structure of the present invention includes a semiconductor substrate 2 , a substrate contact via layer and a: The second metal wire layer inner connecting structure 9 is the same as the fourth metal ring. - "&"; The in-layer connection structure 6 is modified and the ❹ metal line % covers the structure of the connection structure of the substantial structure and the interlayer structure to block the human light-emitting area, covering the connection structure 6 in the genus layer, and the latter stage Process dielectric four and fifth implementation 4. On the layer connection structure 6, as the electrical layer 110, the metal layer (not all) is formed directly in the back-end process medium to cover the photo-lithography acidification - Conductive light screen 154, which is the area in the first-gold structure to exclude incident light. Conductive light screen 154 crystal, except for JitT, covering, such as floating detector 4G, and other analog-like sensing A photodiode d Μ) 201011862, outside. The conductive screen] 54 and the first metal line gas group region correspond to the area of the light shield eagle in Fig. 2, and the ▲ Δι/ and/or the respective Γ π^ blocks in the sensing circuit The person who circulates the arc angle emits light, and the boundary suppresses the generation of the floating charge. For example, the photoelectricity of each electric crystal of the semiconductor junction. The resulting I-electrode body can be a transistor of a unit image sensor pixel. Luzhen, 154 may include a combination of nitriding, nitriding, tungsten nitride, group, titanium, to about. The thickness of the conductive screen 154 may be between about 1 nanometer =; between 'and typically between about 5 nanometers and about 3G nanometers, 隹..., larger or smaller thicknesses. In the consideration of the present invention. Plate 2 2 = Light ^ 154 is farther away from the semiconductor base than the top surface of the &quot;&quot; wire 98. For example, 'the distance between the top surface of the first metal line 98 and the semiconductor base' is referred to herein as the first distance dl, which is less than the distance between the top surface of the back surface and the top surface of the semiconductor substrate 2, Cheng Balei is guilty of distance. The bottom surface of the conductive screen 154 is adjacent to the top surface of the back-end dielectric coating 110. Cheng Jie; is formed on the bottom surface of the conductive optical screen 154 and the back-end system. The second dielectric layer 120 can comprise the same material as the first via and have the same thickness. Two second types of _ are formed in the second dielectric layer 12G. At least the first variable dye layer extends through the second dielectric layer 〖2G, and the rear process dielectric layer U0, and a metal line%-top surface. Each of the at least one first earth layer &apos;I layer window aperture is formed outside the range of the conductive screen]%. At least, the 201011862 line trough utilizes the upper portion of the two-layer dielectric layer 120 in the field. Lifa and: in the first, combined with the electric key, the metal is filled in the first type; m mesh ο =) L, : rr. The deposited metal system utilizes two: CMP back side, or a combination of the two: forming a first-type second-layer via in the via: second:: forming a second type The second via window 1〇9 and the first metal line 118 are formed in the via. The first-type second interlayer window (10), the second-type first-layer window 109, and the second metal line 118 may include materials such as copper or metal. ▲ The first-metal line 9S-back-end process dielectric cap layer 11〇, and the south capacitor electrode 142 together form a metal·insulator·metal capacitor • (MIMCAP). The back-end process dielectric cap layer 110, the lower portion of the second dielectric layer 120, the materialized light screen 154, the first-type second-layer via window 1〇8, and the first-type second-layer via window 109, together constitute a first-back-end process (BE〇L) via layer connection structure 8. The upper portion of the second dielectric layer 12A and the second metal line 118 together form a second metal line layer inner connection structure 9c&gt; additional via layer inner connection structure (not shown) and an additional metal line layer The inner connection structure can be formed as needed. Figure 2 is a block diagram showing an exemplary design flow for use in semiconductor design and semiconductor circuit fabrication in accordance with the present invention. The design flow varies with the type of integrated circuit (ic) designed by 201011862. For example, the design flow used to build an application specific 1C (ASIC) may be different from the design flow used to design a standard integrated circuit component. The design structure 920 is preferably an input value input into a design step 91, and may be from an intellectual property (IP) provider, a core provider, or a design company, or may be designed by a design process. The operands are generated or may come from other sources. ❹ 没 结构 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 一 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 ^_()11 language 'eg Verilog, VHDL, c, etc.) ^ This design structure 92 can be packaged in more than one machine readable medium. For example, design structure 920 can be representative of the present invention Figure 2 A text file or a pattern of one embodiment. The design step 910 preferably synthesizes (or translates) an embodiment of the invention shown in FIG. 2_ into a netlist 98〇, wherein The cable list can be exemplified by a list including a material screen, a wiring, a transistor, a logic gate, a circuit, an I/O, a module, etc., which are described with other components and circuits in an integrated circuit design. The connection method 'is recorded in at least one machine readable medium. For example, 'this medium can be -CD, a CF card (嶋_ _), other fast = recall, transmitted via the Internet - data Packets, or other applies to the network = tools. The synthesis step can be - repeat the steps, where the line list is simplified again _ The above, depending on the design specification and the parameters of the circuit. The design step, step 910 may include the use of a variety of round-robin values, for example, from - must be ten technology (such as different technology generations such as 32 nm, 45 Nai M, and ^ 201011862 nano, etc.) library element 930 (library element) which can collect a set of commonly used components, circuits, and devices (including modules, layout, and symbol representation), design specification 940, feature data 950 , verification data 960, design rule 970, and test data file 985 (which may include, for example, a forward-circuit circuit design program, such as point-in-time analysis, verification, design rule validation, location and routing operations, etc.). Cooked circuit design The skilled artisan can understand the scope of the electronic design automation tool and application used in the design step 910 without departing from the spirit and spirit of the present invention. The design structure of the present invention is not limited to any particular design. Further, "Ten Step 910 is preferably an embodiment of the invention shown in Figures 2-11, in conjunction with any additional integrated circuit design or data (if Translated into a second design structure 990. The design structure 990 is in a format and/or symbol data format for exchanging integrated circuit layout data (eg, stored in GDSII, OASIS, image files, or any other storage design) In a suitable format of the structure, there is a storable medium. The design structure 99 can include, for example, symbol data, data files, test data files, design content files, manufacturing data, layout parameters, wiring, metal layers, The layered window, the exterior, the path data through the production line, and any other data that the semiconductor manufacturer needs to produce the implementation of the present invention as shown in Figures 2-11. The design structure 990 can then proceed to step - 95 'for example' design structure 990 to trial production (tape-0Ut), perform &amp; enter - seal the mask house, send it to another design company, Return to a customer, etc. Although the present invention has been described in detail with reference to the specific embodiments thereof, it will be apparent from the foregoing description that many alternatives, modifications, and variations are obvious to those skilled in the art. Therefore, the present invention is also intended to cover such alternatives, modifications, and variations, which are included in the scope and spirit of the invention. x [Simple Description of the Drawings] In order to immediately understand the advantages of the present invention, please refer to the specific embodiment shown in the 'detailed'. The above description of the present invention is briefly described. The present invention is not to be construed as limiting the scope of the invention, and the present invention is described with reference to the accompanying drawings in which: FIG. A mutual conductor (CMOS) image sensor pixel. 2 is an exemplary layout for use in a semiconductor circuit including a conductive optical screen of the 'lighting screen', the area of which is indicated by a dashed square. FIG. 3 is the first embodiment of the present invention. A vertical cross-sectional view of a semiconductor structure is illustrated. Figure 4 is a vertical cross-sectional view showing a first exemplary semiconductor device variant in accordance with a first embodiment of the present invention. Figure 5 is a vertical cross-sectional view of a second exemplary semiconductor device in accordance with a second embodiment of the present invention. Figure 6 is a vertical cross-section of a second exemplary variant in accordance with a second embodiment of the present invention. Figure 7 is a vertical sectional view of a third exemplary semiconductor device in accordance with a third embodiment of the present invention. Figure 8 is a vertical cross-sectional view of a 201011862 variant of a third exemplary semiconductor structure in accordance with a third embodiment of the present invention. Figure 9 is a vertical sectional view showing a fourth exemplary semiconductor structure in accordance with a fourth embodiment of the present invention. Figure 10 is a vertical sectional view showing a fifth exemplary semiconductor structure in accordance with a fifth embodiment of the present invention. - Figure 11 is a vertical cross section of a sixth exemplary semiconductor structure in accordance with a sixth embodiment of the present invention. Figure 12 is a flow diagram of a design flow for designing and fabricating a semiconductor circuit of the present invention. [Main component symbol description] 2 Semiconductor substrate 4 Substrate contact via layer internal connection structure 6 First metal line layer internal connection structure 8 First rear stage process via layer internal connection structure 9 Second metal line layer internal connection structure Φ 12 semiconductor layer 20 shallow trench isolation structure 30 second conductivity type charge collection well 32 first conduction type semiconductor region 40 floating drain 42 source and drain region 49 source and drain metal semiconductor alloy region 50 gate dielectric Electrical layer 52 gate dielectric gate spacer 58

201011862 59 Gate metal semiconductor alloy region 60 dielectric substrate overlay 62 middle segment dielectric substrate 78, 78' conductive optical screen 80 middle segment dielectric layer 80A lower middle segment dielectric layer 80B higher middle segment process dielectric Layer 88 contact via 89 metal light screen contact via 90 first metal line dielectric layer 98 first metal line 108 second via window 108' first type second via window 109 second Type second via window 109' third type second layer via window 110 back end process dielectric cap layer 118 second metal line 120 second layer dielectric layer 120A lower second layer dielectric layer 120B higher Two-layer dielectric layer 122 metal resistor 122' lower capacitance electrode 123 dielectric portion 124 conductive optical screen 132 node dielectric 142 higher capacitance electrode 201011862

154 Conductive light screen 200 Image sensor pixel 205 Global shutter gate line 210 Photodiode 215 Transfer transistor gate line 220 Floating pole 230 Active area section 225 Reset gate transistor gate line 235 Source Follower Gate Line 245 Row Selector Gate Line 280 Light Screen 900 Design Flow 910 Design Step 920 Design Structure 930 Library Element 940 Design Specification 950 Feature Data 960 Validation Data 970 Design Rule 980 Cable List 985 Test Data File 990 The second design structure 995 step FD floating diffusion GS global shutter transistor PD photodiode 201011862 RG reset gate transistor RS row select transistor SF source with benefit transistor TG transfer gate transistor Vdd power supply voltage gsc Global shutter control signal rgc reset gate control signal rsc row select signal tgc shift gate control signal hv photon dl first distance d2 second distance d2. second distance

60

Claims (1)

201011862 VII application patent range 1 · To form a semiconductor structure, comprising: forming at least a semiconductor component on a top surface of a conductor substrate; and forming a conductive optical screen on the semiconductor component, wherein the conductivity is first Turning at least - the at least one of the side elements - the node is detached; and the layer window is the body - two constructs =; pass ==::== The method described in the article, including the conductivity, is included in the conductivity The method of claim 2, wherein the method of claim 2 includes: f is formed on a top surface of the semiconductor substrate to form a dielectric substrate cover layer, The conductive screen is formed on the electrical base cap layer; and a mid-stage process dielectric layer is disposed on the dielectric substrate cover layer, wherein the at least-metal line is directly formed on the 4. A method for forming a semiconductor structure, comprising: forming at least one semiconductor component over a top surface of a semiconductor substrate; forming at least one of a top surface of one of the germanium semiconductor substrates a layer of metal wire; At least one of a top surface of a first metal line formed on a first dielectric layer 61 and 201011862 an electrical layer; forming a conductive optical screen on the at least-semiconductor component and the first surface of the Weidi-dielectric layer; and forming a second on the conductive optical screen The dielectric layer, wherein the first electrical layer and the second dielectric layer completely encapsulate the conductive optical screen. The method of claim 4, further comprising: forming a contact via directly over at least the second layer of metal lines to form at least a second metal line to the second dielectric layer Wherein the second layer of metal wire is formed directly on the top surface of the contact via. 6. The method of claim 5, further comprising: forming a metal disk on the top surface of the second electrical layer, the metal disk having a conductive optical screen having the same composition and thickness The metal disk is separated from the conductive screen; and a further contact via is formed directly on the top surface of the metal disk. The method of claim 6, further comprising forming another contact layer window adjacent to the surface of the __τ of the other second metal line and the top surface of the metal disk. 8. The method of claim 6, further comprising: forming a first-metal disk directly on the top surface of the dielectric layer, the first-to-one disk having the same conductivity as the two conductive optical screens a material composition and a same thickness, wherein the first metal disk is separated from the conductive optical screen; and r&gt; 2 201011862, the gantry is connected to a top surface of the conductive optical screen to form a first dielectric portion The first dielectric portion has a plurality of sidewalls that conform substantially perpendicularly to the sidewalls of the conductive screen. 9. The method of claim 8, further comprising: forming directly on the top surface of the first metal disk - the second dielectric portion having the same material as the first dielectric portion a composition and the same thickness, wherein the first dielectric portion is separated from the first dielectric portion, and a second metal is formed directly on the top surface of the second dielectric portion. The method of claim 4, further comprising forming another contact via directly over the top surface of the metal disk. The method of claim 5, wherein the junction via is a body-formed structure with any physical interface formed therein. 12. A method for forming a semiconductor structure, comprising: forming at least one semiconductor component over a top surface of a semiconductor substrate; forming a conductive optical screen over the at least one semiconductor component, wherein the at least The semi-navigation member is separated from the at least one node of the at least one semiconductor element, forming at least a metal line on a top surface of the conductive optical screen; and directly on at least one of the bottom surface of the metal line and the at least one semiconductor element A top layer is formed on the top surface. 63 201011862 f as claimed in the patent scope 帛 12 tearing method, which makes: ·,, an integrally formed structure without any physical interface formed in its towel \ &quot; 曰^^^^^^^^^^^^^^^^^^^ Where ^ at least - the downwardly protruding via window portion == tr, wherein the entirety of the materialized light screen, including the to/to ΐ ί = Two = shape ==: is composed, and is, the structure of the shape and the interface of the physical axis is at its t, and the at least-downward protruding layer of the Hungarian 4 points is heterogeneously surrounded by the layer of Qianki Newcap . K. The method of claim 12, further comprising: forming a dielectric substrate cover layer directly on a top surface of the semiconductor substrate, the system being located under a portion of the conductive light screen; A middle-process dielectric layer is formed over the electrical substrate overlay, and is disposed under the at least one metal line. 16. The method of claim 15, wherein the underside of the conductive screen is non-planar and immediately adjacent to a top surface of the dielectric substrate cover. 17. The method of claim 15 wherein the mid-stage dielectric substrate layer is directly on the top surface of the dielectric substrate overlay and on one of the non-planar bottom surfaces of the conductive screen. 8. The method of claim 15, wherein the contact via has a top surface that is coplanar with a top surface of the middle dielectric layer, and the connection is 64 201011862: The window has a bottom surface and a method of aligning with a bottom surface of the dielectric substrate cover layer, wherein the conductive optical screen is spaced apart from the semiconductor substrate. The method of claim 15, wherein the tightly formed structure has no physically formed interface therein, and a bottom surface &quot;at least a metal line-bottom surface&quot; and is directly connected to the conduction The method of claim 15 wherein the conductive screen has a thickness & </ RTI> wherein the entirety of the conductive screen is separated from the semiconductor substrate by a fixed distance. 22. The method of claim 15, further comprising: forming a lower-middle-stage dielectric layer directly bonding the top surface of the lower-middle-process dielectric layer to the conductive optical screen Conducting a sense of a common plane; and forming a higher-middle-stage dielectric layer adjacent to the at least one of the metal lines: and immediately adjacent to the lower-stage dielectric layer of the dielectric layer The method of recording the high level of anger is the same as the method described in Item 15 of the 201011862 patent range, and further includes directly connecting at least the other on the top surface of the pass, and the other bottom surface of the at least one metal wire. A via structure 24. A semiconductor structure comprising: at least one semiconductor component, a top surface of a recording semiconductor substrate; a ❿ ❹ -, a car 2 illuminating screen located on the at least the semiconductor component and associated with Separating at least one node of the first one + conductor 70; at least one metal line on a top surface of the conductive optical screen; and at least; the at least - gold - semiconductor structure according to item 24 , wherein the contact layer is _ The structure of the shape ' does not have any physical interface formed therein. Shen Ru applied for the semiconductor structure described in item 24 of the patent scope, and included the above-mentioned access to the british sub-network, and the position = as claimed in the patent, the second semiconductor structure, _ | The lower protruding via window portion is immediately adjacent to the at least "semiconducting" physically formed interface, and the intervening window portion 201011862 without any main confinement is laterally surrounded by the ageing substrate. On the second eve, please refer to the semiconductor structure described in item 26 of the patent, in which. The bottom surface is non-planar and is adjacent to one of the dielectric substrate overlays. The semiconductor structure is as described in claim 26 of the patent scope, and includes the application of the 26th item of the casting structure.忖 ΓΓ ΓΓ ΓΓ ΓΓ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , For example, the semiconductor structure described in claim 26, wherein the = includes at least two bottom portions having different separation distances between the two bottom portions g, and wherein the conductive surface is located at the at least one Jinlin - under the bottom. u non + top 32 · As described in the scope of claim 26, the layer is an integrally formed structure and has no physical shape: the interface is two screens ^^ to ^ Jin Zai - the bottom surface, and is directly connected to the The conductive structure is as described in claim 26, wherein the conductive 201011862 optical screen comprises at least two portions having a thickness of a ke, and the conductive optical screen has a flat 舳Separated from the substrate by "fixed distance". 34. The semiconductor structure of claim 1, wherein the middle-stage dielectric layer comprises: a lower-medium process dielectric layer directly bonded to a bottom surface of the conductive optical screen, wherein the lower middle-process dielectric layer The top surface is coplanar with a top surface of the conductive screen; and a higher middle layer process dielectric layer is adjacent to a bottom surface of the at least one metal line and adjacent to the lower middle processing dielectric layer A top surface. _ 35_ The semiconductor structure of claim 26, further comprising at least a contact via window adjacent to the top surface of the materialized screen and another bottom surface of the at least one metal line. 36. A semiconductor structure comprising: off; a semiconductor component on a top surface of the semiconductor substrate; at least one first-layer metal line and a top surface of one of the semiconductor substrates; a layer immediately adjacent to the at least one first layer of metal lines; the first; the semi-hybrid element, and immediately adjacent to the electrical layer above the conductive optical screen, wherein the first dielectric barrier - 1 1 The layer system _ material screen (4) is covered inside. 201011862 37. The semiconductor structure of claim 36, further comprising: - the first layer of metal line buried in the material-contact via window adjacent to the at least one second and the at least - first-layer metal line - Top surface. One of the bottom surfaces of the riding line 38. The structure of the half (10) according to the scope of claim 37 and without any physical 39. The semiconductor structure described in the application of the 37th item, including the conductive screen Separating; and the top surface of the electrical layer 'and no other-contact via, its mesa and one of the top surfaces of the metal disk. One of the metal wires of a layer; | 40. As described in claim 39, the J-point mesoscopic window is adjacent to the top surface of the second-layer metal. The bottom of the moxibustion and the gold enamel. If the fifth half of the lit and the same thickness, the butterfly disc is separated from the transmission county screen; the miscellaneous face, and the iti part ‘the system (four) to the pass I, there are plural (4) The system is substantially perpendicular to the side wall 69 201011862 of the conductive screen; the material having the same composition of two parts is separated by the first dielectric part; = one side of the first metal disk, and a second metal disk Adjacent to the top surface of the second dielectric portion. 'Saki Lin—_ ah, manufacturing, butterfly η - designed machine readable medium, the design structure includes: ^ n = 1 2 3 semiconductors on the semiconductor substrate; on the semiconductor components; The light screen is located in a partially interconnected layer and the metal is in the inner layer of the genus, and the fourth data of the conductor cake represents the contact structure to the metal line and the half window 42. The contact layer of the towel is a body-formed structure without any physically formed interface therein. 44. The design structure of claim 42 further comprising: cup eve = five data representing a dielectric substrate overlay immediately adjacent to the semiconductor substrate 1 = and located under one portion of the conductive optical screen '· And a representative of the above-mentioned towel-strip dielectric layer is located above the dielectric substrate-clad layer and under the at least-metal line. 'Du Rujia asks for the design structure described in item 44 of the patent scope, and includes one of the other numbers 70 201011862. 46. The design data described in item 42 of the claimed patent scope includes additional data, which represents at least - two ^The fourth number of conductive optical screens, wherein the at least _ _ ^ ^ ^ points in the adjacent to a conductor structure 'the conductor series is located on the semiconductor substrate directly tight or tested 47. - squama structure 'the system Implemented in a rib design-design machine H readable medium 'The design structure includes: Si:: the semiconductor component is located on a semiconductor substrate; surface separation; the first layer metal line and the semiconductor layer one of the semiconductor layers The wire is represented by a 'representative-first dielectric layer' on the at least one first member overlying the at least one semiconductor element and immediately adjacent to a top surface of the first dielectric layer, and The second dielectric layer is located on the conductive screen, and the second dielectric layer is disposed on the conductive screen. The conductive screen is 48. t, · and, for example, please The design structure described in item 47 further includes: Eighth data, representing a first The second layer of metal wire is buried with a younger brother and seven data 'representative-contact layer window is adjacent to the - the gold layer line - the bottom surface and the at least the first layer of the metal line - the layer 201011862 49. The design structure of item 48, wherein the contact via window is an integrally formed structure without any physically formed interface therein. 72