201006007 九、發明說明 【發明所屬之技術領域】 本專利案關係於發光裝置。 【先前技術】 例如發光二極體（LED )及雷射二極體的固態光源可 以提供顯著超過例如白熾燈或螢光燈的其他發光形式的各 φ 項優點。例如，當LED或雷射二極體被排列成紅、綠及 藍原色的陣列時，它們可以作爲白光源或作爲多色顯示器 。在此等架構中，固態光源大致更有效並產生較傳統白熾 燈或螢光燈爲少之熱量。雖然固態發光提供某些優點，但 固態發光所用之傳統半導體結構與裝置係相對地昂貴。有 關於傳統固態發光裝置的成本之一爲傳統固態發光裝置的 相對的低製造產量。 參考圖1，傳統LED結構100包括一基材105，其例 Ο 如由藍寶石、碳化砂或尖晶石所形成。一緩衝層110被形 成在基材105上。緩衝層110主要作爲一濕潤層，以提升 藍寶石基材的平順、均勻覆蓋。緩衝層110典型由GaN、 InGaN、A1N或AlGaN所形成並具有約100至500埃的厚 度。緩衝層130典型使用金屬有機化學氣相沈積（ MOCVD)沈積薄非晶層。 一 P摻雜III-V族化合物層120係被形成緩衝層110 上。該P摻雜III-V族化合物層120典型係由GaN所形成 。一InGaN量子井層130被形成在該p摻雜ni-V族化合 201006007 物層120上。一主動III-V族化合物層140然後形成在該 InGaN量子井層130上。一η摻雜III-V族化合物層150 被形成層140上。該ρ摻雜III-V族化合物120爲η摻雜 。一 Ρ-電極160被形成在該η摻雜III-V族化合物層150 上。一 η電極170係被形成在第一 III-V族化合物層120 上。 傳統LED結構100的缺點爲有關於小基材尺寸的低 φ 製造產量。例如，藍寶石或碳化矽基材典型被供給有直徑 2至4吋。傳統LED結構100的另一缺點爲其分層結構容 易受到破損。例如藍寶石或碳化矽的適當基才典型不能以 單晶方式加以取得。ρ摻雜III-V族化合物層120可能由 於不同熱膨脹及於ρ摻雜III-V族化合物層與基材間之晶 格失配，甚至在緩衝層110出現時，而造成破損或剝離。 不同熱膨脹及晶格失配也可能在LED結構中，產生彎曲 變形（即捲起）。結果，使LED結構1〇〇的發光效能受 ❹ 到損害。 因此，有需要一種發光裝置，其可以克服傳統發光系 統中之部份或所有缺點。 【發明內容】 在一態樣中，本發明關係於發光裝置，其包含：一基 材，其具有第一面與不與第一面平行的第二面；一發光層 ，安置該第二面上，以發光，該發光層具有一不與該第一 面平行的發光面。 -5- 201006007 在另一態樣中’本發明關係於發光裝置，其包括：一 基材；及一發光層’安置在該基材上，以發光，該發光層 具有一佔用面積並具有發光面區域，其係大於佔用面積。 在另一態樣中，本發明有關於發光裝置，其包含：具 有第一面的一基材；一發光層，安置在該基材的至少一部 份上，該發光層具有發光面，其係不平行於該第一面；及 一反射緩衝層’安置在該發光層的至少一部份上，以反射 φ 自該發光層發射的光，及其中該反射緩衝層在爲發光層所 發射光的頻譜範圍中，具有高於3 0 %的反射係數。 在另一態樣中’本發明關係於發光裝置，其包含：具 有第一面及一溝渠形成在該第一面的一基材；及一發光層 ’安置在該溝渠內，用以發光，該具有發光面不平行於第 一面的發光層，其中該溝渠外的第一面可以包括至少一寬 度大小窄於1 000微米。 在另一態樣中，本發明關係於一發光裝置，其包具有 Φ 第一面及一凸部形成在該第一面上基材；及一發光層，安 置在該凸部上，用以發光，該發光層具有不與該第一面平 行的發光面。 在另一態樣中，本發明關係於一發光裝置，其包含： 具有第一面的基材；形成在該基材中之溝渠，其中該溝渠 部份被多數不平行於第一面的第一溝渠面所界定；一反射 緩衝層，在該第一面及該多數第一溝渠面的至少一部份上 :及一發光層，在該反射緩衝層上，其中該發光層可以發 射離開該反射緩衝層的光，其中該被發射的光係被侷限於 -6 - 201006007 窄於150度的角範圍內。 在另一態樣中，本發明關係於一種製造發光裝置的方 法。該方法包含：在一基材上形成發光層，該基材具有第 一面與不平行於該第一面的第二面，其中該發光層具有不 平行於該第一面的發光面，其中該發光層可以發光。 系統的實施包含以下之一或多者。發光層可以包括： 量子井層，當電流被產生於量子井層時，其可以發光。量 φ 子井層可以包含由InN、InGaN、GaN、AlGaN及InGaAIN 所選出之材料所形成之一層。該發光裝置可以更包含在基 材與發光層間之一緩衝層。該緩衝層在爲發光層所發射的 光之頻譜範圍內，有高於3 0%的反射係數。該緩衝層在爲 發光層所發射的光之頻譜範圍內，有高於50 %的反射係數 。緩衝層可以具有範圍200至200,000埃的厚度。緩衝層 可以包含銘、氮化銘、銘合金、或Ag及其合金，作爲反 射緩衝層。緩衝層可以包含由 GaN、ZnO、AIN、HfN、 φ AlAs、SiCN、TaN及SiC所選出之材料。發光裝置可以更 包含在基材與發光層間之一下ΠΙ-V族化合物，以及，在 發光層上的上ιπ-ν族化合物層。基材可以具有一溝渠形 成在第一面中，及其中該發光層係安置於該溝渠內。該溝 渠外的第一面可以包含窄於1〇〇〇微米的至少一寬度大小 。基材可以具有一凸部形成在該第一面上’及其中該發光 層係安置於該凸部上。該凸部外的第一面可以包含窄於 1000微米的至少一寬度大小。該基材可以包含砂、氧化砂 、氮化鎵、碳化矽、或藍寶石。該基材可以包含絕緣層上 201006007 覆矽（SOI)基材，或簡單地爲矽黏結至玻璃上，以形成 用於內連線電極的停止層。 上述發光裝置有關的優點爲相較於傳統LED發光裝 置，其顯著地增加發光強度。所揭示之發光裝置及方法提 供較傳統具有相同基材佔用面積的LED發光裝置爲大之 發光面。在所揭示發光裝置下之反射層可以降低吸收有關 的光損失並進一步增加發光效率。形成在所揭示發光裝置 φ 的上III-V族化合物上的透明導電層可以增加於上電極與 上III-V層間之電接觸，並同時，最大化來自所揭示發光 裝置的發光強度。 有關於所揭示之發光裝置的另一優點爲其發光係對焦 於較傳統LED發光裝置爲窄的角度範圍。在所揭示發光 裝置中之更集中角度發光降低了在不想要方向的光損失， 因而，增加了在想要照射方向的亮度增加並降低了功率消 耗。 φ 有關於所揭示之發光裝置的另一優點爲其較傳統發光 系統更容易製造、堅固及更可靠。所揭示之發光裝置及製 程可以克服不同熱膨脹及在下III-V族化合物層與基材間 之晶格失配並防止相關層破裂及剝離、及在傳統LED發 光系統中已知的問題。 所揭示之發光裝置及製程允許發光裝置的更高產量及 大量製造發光裝置。大量的固態LED可以被製造在大基 材，例如矽晶圓或玻璃基材上。相較於傳統發光裝置所用 之小基材，因爲矽晶圓可以設在更大的尺寸（例如6至12 201006007 吋矽晶圓）中，所以，可以大量改良製造生產量。所揭示 發光裝置可以使用商用可得半導體處理設備，例如ALD 及MOCVD系統加以製造，而不必使用客製化製造設備， 這使得所揭示製程容易實施。所揭示之發光裝置可以較傳 統發光裝置在時間及成本上更能有效製造。 再者，所揭示發光裝置可以相較於部份傳統LED裝 置作得更密集、更小型化並更符成本效益。所揭示之發光 裝置可以在矽爲主之基材加以製造，以允許在基材之電子 控制電路的積集。 【實施方式】 以下之圖式係倂入作爲本說明書的一部份，並與說明 一起顯示本發明之實施例，作用以解釋本發明之原理。 參考圖2A至3C，發光裝置2 0 0係被形成在具有上面 207的基材205上（圖3B)。發光裝置200包括在下表面 φ 207下的基材205中的溝渠210。溝渠210具有相對於上 面207傾斜的一或多數溝渠面213 (圖3B )。溝渠210也 可以具有一底面219，其係平行於上面207。底面219的 面積可以保持爲小於溝渠面213的面積的20%。205可以 是矽爲主，上面207可以平行於（100)結晶面。溝渠面 213可以平行於（111)結晶面。（或者，上面207可以平 行於（1 1 1 )結晶面。溝渠面2 1 3可以平行於（1 00 )結晶 面。）溝渠210因此可以具有倒置錐形的形狀，或者，在 205中之截頭倒置錐形狀，這在上面207中形成一正方形 -9- 201006007 開口。一內緣217被形成在兩鄰近溝渠面213的交界處。 205可以是具有外緣2〇8的矩形或正方形。發光裝置200 可以在一半導體晶圓上與一批次的其他發光裝置一起製造 ’並被切片爲分開的晶粒。發光裝置200可以具有爲平行 於上面2 0 7的面之平坦區所界定的矩形或正方形晶粒。 發光裝置200包含：一反射緩衝層215，在上面207 與溝渠面213上；一下πΐ-ν族化合物層220，在反射緩 φ 衝層215上；一或更多量子井層230，在下III-V族化合 物層220上；及一上m-γ族化合物層240。下III-V族化 合物層220及上ΙΠ-ν族化合物層240各包含一 III族元 素及一 V族元素。III族元素典型爲鎵。V族元素典型爲 氮化物。適用於下III-V族化合物層220及上III-V族化 合物層240的III-V族化合物分別可以是η-型摻雜及p-型 摻雜。在溝渠面213上的上III-V族化合物層240部份係 被稱爲斜上III-V族化合物層240Α並朝向相對於205的 Φ 上面207的一角度。發光裝置200也包含：一下電極270 ，在下III-V族化合物層220上，以及，一上電極260在 上III-V族化合物層240上。 在部份實施例中，如圖4Α所示，一半導體晶圓400 包括2x2陣列的發光結構400A-400D形成在基材405上。 各個發光結構400A-400D可以具有類似於上述發光裝置 200的結構。發光結構400A-400D可以在半導體晶圓上， 形成爲2x2矩陣。發光結構400A-400D可以被使用作爲單 一發光裝置，或者’它但可以藉由切割分開，以形成類似 -10- 201006007 於發光裝置200的個別發光裝置。在另一例子中’包含4x 4陣列的發光結構510的半導體晶圓500係如圖4C所示 〇 參考圖3D及4B， 發光結構400A、400B可以形成 在基材405中之溝渠410上。基材405可以由矽、氧化矽 、氮化鎵、藍寶石或玻璃所形成。基材205也琶以例如矽 層在玻璃上的雙層結構所形成，或絕緣層上覆矽（SOI) φ 晶圓所形成。矽層可以具有（1〇〇)上表面。矽層的厚度 可以用以界定溝渠的深度。對於矽爲主之基材，基材405 可以具有在（100)結晶面向中有上面405A。溝渠410的 面410A、410B可以沿著（111)結晶面方向。基材405也 可以包含互補金屬氧化物半導體（CMOS )材料，及一 CMOS電路用以驅動及控制發光裝置400。 反射緩衝層415被形成在基材405的面405A上及在 溝渠410中之斜面410A、410B上。反射緩衝層415的作 • 用爲反射自發光裝置400所發射的光離開基材405，以防 止所發射的光爲基材405所吸收。例如，基材405可以爲 砂爲主’其吸收在可見光範圍的光。反射緩衝層415可以 在由發光裝置400所發射光的頻譜中具有高於3〇%、5〇% 、或70%爲反射係數。 反射緩衝層415可以在真空室內，維持於550。(：至 8 50 °C的範圍內之一溫度，例如約70(rC，使用原子層沈積 (ALD)沈積在基材405上。反射緩衝層415可以具有約 200至200, 〇〇〇埃的厚度’例如1〇〇〇至〇〇〇埃。反射 -11 - 201006007 緩衝層415也可以濕潤並在基材405上形成一均勻層。反 射緩衝層4 1 5也可以具有結晶結構，以晶格磊晶匹配至基 材405及下III-V族化合物層420 (如下述）。 反射緩衝層415的ALD形成可以涉及使用TaN或 TiN及10至100埃的層厚度。原子層沈積（ALD)係爲“ 奈米”技術，允許幾奈米的超薄膜被以準確控制的方式加 以沈積。ALD具有自限原子逐層成長的特性，並對基材相 φ 當高地保角。對於在發光裝置中，形成緩衝層，ALD可以 使用例如液體鹵化物或氣相形式之有機金屬的兩或更多前 驅物。ALD可以涉及加熱以將前驅物分解爲反應物種。前 驅物之一也可以是電漿氣體。藉由每一循環沈積一層， ALD經常提供極端準確的超薄膜成長，因爲循環數決定原 子層數，及所沈積膜的準確厚度。因爲在每一循環中， ALD製程準確地沈積一原子層，所以，可以取得奈米規格 的沈積製程上之完整控制。再者，ALD具有能實質等向沈 # 積的優點》因此，ALD有利於沈積緩衝層於V型溝渠中之 斜面410A及410B，及在U型溝渠中之垂直面上。 下III-V族化合物層420係被形成在反射緩衝層415 上。下III-V族化合物層420可以由摻矽的n-GaN形成。 下ΠΙ-V族化合物層420可以具有範圍1至50微米的厚度 ，例如1 〇微米。 用於反射緩衝層415的材料係被選擇，以滿足與基材 405及下III-V族化合物層420的高反射度及晶格匹配的 要求。例如，反射緩衝層415可以由Α1、氮化鋁、Α1氧 -12- 201006007 化物、Ag、Ag氧化物、及A1、Au及Ag的合金加以形成 。反射緩衝層415也可以由例如TaN、TiN、GaN、ZnO、 AIN、HfN、AlAs、或SiC的一或更多材料所形成。反射 緩衝層415可以具有範圍200至200,000埃，例如1，000 至10,000埃的厚度。 量子井層430被形成在下III-V族化合物層420上。 量子井層43 0係由具有厚度範圍由5至200埃，例如50 φ 埃的InN或InGaN所作成。上III-V族化合物層440係被 形成在量子井層430上。上III-V族化合物層440可以藉 由例如AU.iGao.9N的p型摻雜GaN所形成。上III-V族 化合物層可以具有範圍由0.1至10微米，例如1微米的 厚度的鋁摻P-GaN層440。量子井層430在下III-V族化 合物層420與上III-V族化合物層440間形成一量子井。 —導電層450被選擇地形成在上III-V族化合物層440上 。導電層450至少部份透明。適用於導電層450的材料可 φ 以包含ITO或薄層p-型歐姆金屬，例如Ni/Au。上電極 460可以形成在導電層450上（或當沒有導電層450時， 形成在上ΠΙ-V族化合物層440上）。導電層450的包含 可以根據基材405是否被切薄，以允許更多發射光離開發 光裝置400加以決定。如果基材405並未被切薄，使得更 多光可以離開發光裝置400時，則較佳包含導電層450。 下電極470可以被形成在下III-V族化合物層420上。上 電極460及下電極470可以分稱爲ρ_電極及η_電極。在導 電層450中使用透明ΙΤΟ材料可以顯著地增加於上電極 -13- 201006007 460及上III-V族化合物層440間之導電率，同時，最大 化由量子井層430射出的光離開導電層450的上面》 量子井層430可以形成一量子井，用以在下III-V族 化合物層420及上III-V族化合物層440間之電載子。電 壓可以施加至下電極470及上電極460之間，以在量子井 層430中，產生電場以激勵爲量子井層43 0所形成之量子 井中之載子，在下III-V族化合物層420及上III-V族化 φ 合物層440間形成用於電載子的量子井。激勵載子的重組 合可以發出光。發射波長多數係由在量子井層43 0中之材 料的帶隙加以決定。 在本說明書中，名詞“量子井”表示侷限電荷載子或帶 電粒子，例如電子及電洞至大致二維平坦區的電位井。在 半導體發光裝置中，量子井可以捕捉激勵電子及電洞並界 定當電子及電洞重組於量子井時，光發射的波長並產生光 子。 # 在本說明書中，量子井可以包含一均勻層或多數的量 子井。例如，量子井層（例如圖5Ε至51中之量子井層 430 )可以包含由 InN、GaN、InGaN、AlGaN、InAIN 或 AlInGaN作成之大致均勻層。量子井也可以包含界定一或 多量子井的多層結構。一量子井也可以例如藉由包夾在兩 GaN 層間之 InGaN、AlGaN、InAIN、或 InGaAIN 所形成 。量子井可以藉由包夾在GaN或AlGaN層中之InGaN層 所形成。量子井可以包含一或一堆疊此分層結構加以形成 ，各層界定上述量子井。 -14- 201006007201006007 IX. Description of the Invention [Technical Field of the Invention] This patent is related to a light-emitting device. [Prior Art] Solid state light sources such as light emitting diodes (LEDs) and laser diodes can provide significant advantages over the various φ terms of other forms of illumination such as incandescent or fluorescent lamps. For example, when an LED or a laser diode is arranged in an array of red, green, and blue primary colors, they can be used as a white light source or as a multi-color display. In these architectures, solid state light sources are generally more efficient and produce less heat than conventional incandescent or fluorescent lamps. While solid state lighting provides certain advantages, conventional semiconductor structures and devices used in solid state lighting are relatively expensive. One of the costs associated with conventional solid state lighting devices is the relatively low manufacturing throughput of conventional solid state lighting devices. Referring to Figure 1, a conventional LED structure 100 includes a substrate 105, such as sapphire, carbonized sand or spinel. A buffer layer 110 is formed on the substrate 105. The buffer layer 110 acts primarily as a wetting layer to enhance the smooth, uniform coverage of the sapphire substrate. The buffer layer 110 is typically formed of GaN, InGaN, AlN or AlGaN and has a thickness of about 100 to 500 angstroms. The buffer layer 130 typically deposits a thin amorphous layer using metal organic chemical vapor deposition (MOCVD). A P-doped III-V compound layer 120 is formed on the buffer layer 110. The P-doped III-V compound layer 120 is typically formed of GaN. An InGaN quantum well layer 130 is formed on the p-doped ni-V compound 201006007 layer 120. An active III-V compound layer 140 is then formed on the InGaN quantum well layer 130. An n-doped III-V compound layer 150 is formed on layer 140. The p-doped III-V compound 120 is n-doped. A Ρ-electrode 160 is formed on the n-doped III-V compound layer 150. An η electrode 170 is formed on the first III-V compound layer 120. A disadvantage of the conventional LED structure 100 is the low φ manufacturing yield for small substrate sizes. For example, sapphire or tantalum carbide substrates are typically supplied with a diameter of 2 to 4 angstroms. Another disadvantage of the conventional LED structure 100 is that its layered structure is susceptible to breakage. Suitable groups such as sapphire or tantalum carbide are typically not available in a single crystal. The p-doped III-V compound layer 120 may be damaged or peeled due to different thermal expansion and lattice mismatch between the p-doped III-V compound layer and the substrate, even when the buffer layer 110 is present. Different thermal expansions and lattice mismatches can also cause bending deformation (i.e., rolling up) in the LED structure. As a result, the luminous efficacy of the LED structure 1 受 is impaired. Accordingly, there is a need for a lighting device that overcomes some or all of the shortcomings of conventional lighting systems. SUMMARY OF THE INVENTION In one aspect, the present invention is directed to a light emitting device comprising: a substrate having a first surface and a second surface not parallel to the first surface; a light emitting layer disposed to the second surface The light-emitting layer has a light-emitting surface that is not parallel to the first surface. -5- 201006007 In another aspect, the present invention relates to a light-emitting device comprising: a substrate; and a light-emitting layer disposed on the substrate to emit light, the light-emitting layer having a footprint and having a light-emitting layer The area of the face is larger than the occupied area. In another aspect, the invention relates to a light emitting device comprising: a substrate having a first side; a light emitting layer disposed on at least a portion of the substrate, the light emitting layer having a light emitting surface, Is not parallel to the first surface; and a reflective buffer layer is disposed on at least a portion of the light-emitting layer to reflect φ light emitted from the light-emitting layer, and wherein the reflective buffer layer is emitted by the light-emitting layer In the spectral range of light, there is a reflection coefficient higher than 30%. In another aspect, the present invention relates to a light-emitting device, comprising: a substrate having a first surface and a trench formed on the first surface; and a light-emitting layer disposed in the trench for emitting light, The light emitting layer having a light emitting surface that is not parallel to the first surface, wherein the first surface outside the trench may include at least one width dimension narrower than 1000 micrometers. In another aspect, the present invention relates to a light-emitting device having a first surface and a convex portion formed on the first surface substrate, and a light-emitting layer disposed on the convex portion for The light-emitting layer has a light-emitting surface that is not parallel to the first surface. In another aspect, the present invention is directed to a light emitting device comprising: a substrate having a first side; a trench formed in the substrate, wherein the trench portion is partially non-parallel to the first side a reflective buffer layer; a reflective buffer layer on the first surface and at least a portion of the plurality of first trench surfaces: and a light-emitting layer on the reflective buffer layer, wherein the light-emitting layer can be emitted away from the The light of the reflective buffer layer, wherein the emitted light system is limited to an angular range of -6 - 201006007 narrower than 150 degrees. In another aspect, the invention relates to a method of fabricating a light emitting device. The method includes: forming a light-emitting layer on a substrate, the substrate having a first face and a second face not parallel to the first face, wherein the light-emitting layer has a light-emitting surface that is not parallel to the first face, wherein The luminescent layer can emit light. The implementation of the system includes one or more of the following. The luminescent layer can include: a quantum well layer that can illuminate when current is generated in the quantum well layer. The φ subwell layer may comprise a layer formed of materials selected from InN, InGaN, GaN, AlGaN, and InGaAIN. The illuminating device may further comprise a buffer layer between the substrate and the luminescent layer. The buffer layer has a reflection coefficient higher than 30% in the spectral range of the light emitted by the light-emitting layer. The buffer layer has a reflectance of more than 50% over the spectral range of the light emitted by the luminescent layer. The buffer layer may have a thickness ranging from 200 to 200,000 angstroms. The buffer layer can contain inscriptions, nitrides, alloys, or Ag and its alloys as a reflective buffer. The buffer layer may comprise a material selected from GaN, ZnO, AIN, HfN, φ AlAs, SiCN, TaN, and SiC. The light-emitting device may further comprise a bismuth-V compound between the substrate and the luminescent layer, and an upper ιπ-ν compound layer on the luminescent layer. The substrate may have a trench formed in the first side, and wherein the luminescent layer is disposed within the trench. The first side of the trench may comprise at least one width that is narrower than 1 micron. The substrate may have a convex portion formed on the first surface ′ and the luminescent layer is disposed on the convex portion. The first face outside the protrusion may comprise at least one width that is narrower than 1000 microns. The substrate may comprise sand, oxidized sand, gallium nitride, tantalum carbide, or sapphire. The substrate may comprise a 201006007 overlay (SOI) substrate on the insulating layer or simply be bonded to the glass to form a stop layer for the interconnect electrodes. An advantage associated with the above described illumination device is that it significantly increases the illumination intensity compared to conventional LED illumination devices. The disclosed illuminating device and method provide a larger illuminating surface than conventional LED illuminators having the same substrate footprint. The reflective layer under the disclosed illumination device can reduce absorption-related light loss and further increase luminous efficiency. The transparent conductive layer formed on the upper III-V compound of the disclosed light-emitting device φ can be increased in electrical contact between the upper electrode and the upper III-V layer, and at the same time, maximizes the intensity of illumination from the disclosed light-emitting device. Another advantage associated with the disclosed illumination device is that its illumination system focuses on a narrower range of angles than conventional LED illumination devices. The more concentrated angular illumination in the disclosed illumination device reduces the loss of light in the unwanted direction, thus increasing the increase in brightness in the desired illumination direction and reducing power consumption. Another advantage of φ with respect to the disclosed illumination device is that it is easier to manufacture, robust and more reliable than conventional illumination systems. The disclosed illuminating devices and processes overcome various thermal expansions and lattice mismatches between the lower III-V compound layer and the substrate and prevent cracking and peeling of the associated layers, as well as problems known in conventional LED lighting systems. The disclosed illumination device and process allow for higher throughput of the illumination device and mass production of the illumination device. A large number of solid state LEDs can be fabricated on large substrates such as germanium wafers or glass substrates. Compared to the small substrate used in the conventional light-emitting device, since the germanium wafer can be set in a larger size (for example, 6 to 12 201006007 吋矽 wafer), the manufacturing throughput can be greatly improved. The disclosed illuminating devices can be fabricated using commercially available semiconductor processing equipment, such as ALD and MOCVD systems, without the use of custom manufacturing equipment, which makes the disclosed process easy to implement. The disclosed illuminating device can be more efficiently manufactured in time and cost than conventional illuminating devices. Moreover, the disclosed illumination device can be made denser, more compact, and more cost effective than some conventional LED devices. The disclosed illuminating device can be fabricated on a ruthenium-based substrate to allow for the accumulation of electronic control circuitry on the substrate. The following drawings are included to be a part of the specification, and are intended to illustrate the embodiments of the invention. Referring to Figures 2A through 3C, a light-emitting device 200 is formed on a substrate 205 having an upper surface 207 (Fig. 3B). Light emitting device 200 includes a trench 210 in substrate 205 under lower surface φ 207. The trench 210 has one or more trench faces 213 (Fig. 3B) that are inclined relative to the upper face 207. The trench 210 can also have a bottom surface 219 that is parallel to the upper surface 207. The area of the bottom surface 219 can be kept to be less than 20% of the area of the trench surface 213. 205 may be predominantly ruthenium and upper 207 may be parallel to the (100) crystal plane. The trench surface 213 may be parallel to the (111) crystal plane. (Alternatively, the upper surface 207 may be parallel to the (1 1 1 ) crystal plane. The trench surface 2 1 3 may be parallel to the (100) crystal plane.) The trench 210 may thus have an inverted cone shape, or a cut in 205 The head is inverted in the shape of a cone, which forms a square -9-201006007 opening in the upper 207. An inner edge 217 is formed at the junction of two adjacent trench faces 213. 205 may be a rectangle or square having an outer edge 2〇8. Light emitting device 200 can be fabricated on a semiconductor wafer with a batch of other illumination devices and sliced into separate dies. The illumination device 200 can have rectangular or square grains defined by flat regions parallel to the face of the upper surface. The illuminating device 200 comprises: a reflective buffer layer 215 on the upper surface 207 and the trench surface 213; a lower π ΐ-ν compound layer 220 on the reflective buffer layer 215; one or more quantum well layers 230, in the lower III- On the group V compound layer 220; and an upper m-γ compound layer 240. The lower III-V compound layer 220 and the upper germanium-ν compound layer 240 each comprise a group III element and a group V element. Group III elements are typically gallium. The group V element is typically a nitride. The III-V compound suitable for the lower III-V compound layer 220 and the upper III-V compound layer 240 may be η-type doping and p-type doping, respectively. The portion of the upper III-V compound layer 240 on the trench surface 213 is referred to as the oblique upper III-V compound layer 240 and is oriented at an angle relative to the Φ upper surface 207 of 205. The light emitting device 200 also includes a lower electrode 270 on the lower III-V compound layer 220, and an upper electrode 260 on the upper III-V compound layer 240. In some embodiments, as shown in FIG. 4A, a semiconductor wafer 400 comprising a 2x2 array of light emitting structures 400A-400D is formed on a substrate 405. Each of the light emitting structures 400A-400D may have a structure similar to that of the above-described light emitting device 200. The light emitting structures 400A-400D can be formed as a 2x2 matrix on a semiconductor wafer. The light emitting structures 400A-400D can be used as a single light emitting device, or 'it can be separated by cutting to form an individual light emitting device similar to -10-201006007 to the light emitting device 200. In another example, a semiconductor wafer 500 comprising a 4x4 array of light emitting structures 510 is shown in Figure 4C. Referring to Figures 3D and 4B, light emitting structures 400A, 400B may be formed on trenches 410 in substrate 405. Substrate 405 can be formed of tantalum, yttria, gallium nitride, sapphire or glass. The substrate 205 is also formed by, for example, a two-layer structure in which a bismuth layer is formed on the glass, or a silicon oxide (SOI) φ wafer on the insulating layer. The ruthenium layer may have a (1 〇〇) upper surface. The thickness of the layer can be used to define the depth of the trench. For a crucible-based substrate, the substrate 405 can have an upper surface 405A in the (100) crystal orientation. The faces 410A, 410B of the trench 410 may follow the (111) crystal plane direction. Substrate 405 may also comprise a complementary metal oxide semiconductor (CMOS) material, and a CMOS circuit for driving and controlling illumination device 400. The reflective buffer layer 415 is formed on the face 405A of the substrate 405 and on the slopes 410A, 410B in the trench 410. The reflective buffer layer 415 is used to reflect light emitted from the light emitting device 400 away from the substrate 405 to prevent the emitted light from being absorbed by the substrate 405. For example, substrate 405 can be sand dominated by light that absorbs in the visible range. The reflection buffer layer 415 may have a reflection coefficient higher than 3〇%, 〇%, or 70% in the spectrum of light emitted by the light-emitting device 400. The reflective buffer layer 415 can be maintained at 550 in a vacuum chamber. (: a temperature in the range of up to 8 50 ° C, for example about 70 (rC, deposited on the substrate 405 using atomic layer deposition (ALD). The reflective buffer layer 415 may have a thickness of about 200 to 200, 〇〇〇 The thickness 'e.g., 1 〇〇〇 to 〇〇〇. Reflection -11 - 201006007 The buffer layer 415 can also wet and form a uniform layer on the substrate 405. The reflective buffer layer 415 can also have a crystalline structure to the lattice Epitaxial matching to substrate 405 and lower III-V compound layer 420 (as described below). ALD formation of reflective buffer layer 415 may involve the use of TaN or TiN and a layer thickness of 10 to 100 angstroms. Atomic Layer Deposition (ALD) System For the "nano" technology, a few nanometers of ultra-thin film are allowed to be deposited in an accurately controlled manner. ALD has the characteristics of self-limiting atom-by-layer growth and high-preservation of the substrate phase φ. Forming a buffer layer, ALD may use two or more precursors of an organometallic such as a liquid halide or a gas phase. ALD may involve heating to decompose the precursor into a reactive species. One of the precursors may also be a plasma gas. By depositing one layer per cycle, ALD often provides extremely accurate ultra-thin film growth because the number of cycles determines the number of atomic layers and the exact thickness of the deposited film. Because the ALD process accurately deposits an atomic layer in each cycle, nanometer specifications can be achieved. Complete control over the deposition process. Furthermore, ALD has the advantage of being able to substantially sink the product. Therefore, ALD facilitates the deposition of the buffer layer in the V-type trenches 410A and 410B, and the vertical plane in the U-shaped trench. The lower III-V compound layer 420 is formed on the reflective buffer layer 415. The lower III-V compound layer 420 may be formed of germanium-doped n-GaN. The lower germanium-V compound layer 420 may have a range of 1. A thickness of up to 50 microns, such as 1 Å. The material used to reflect the buffer layer 415 is selected to meet the high reflectivity and lattice matching requirements of the substrate 405 and the lower III-V compound layer 420. The reflective buffer layer 415 may be formed of Α1, aluminum nitride, Α1 oxy-12-201006007, Ag, Ag oxide, and an alloy of A1, Au, and Ag. The reflective buffer layer 415 may also be made of, for example, TaN, TiN, GaN, ZnO, AIN, HfN, A One or more materials of lAs, or SiC are formed. The reflective buffer layer 415 may have a thickness ranging from 200 to 200,000 angstroms, for example, 1,000 to 10,000 angstroms. The quantum well layer 430 is formed on the lower III-V compound layer 420. The quantum well layer 43 0 is made of InN or InGaN having a thickness ranging from 5 to 200 angstroms, for example, 50 φ angstroms. The upper III-V compound layer 440 is formed on the quantum well layer 430. The upper III-V compound layer 440 can be formed by p-type doping GaN such as AU.iGao.9N. The upper III-V compound layer may have an aluminum-doped P-GaN layer 440 having a thickness ranging from 0.1 to 10 μm, for example, 1 μm. The quantum well layer 430 forms a quantum well between the lower III-V compound layer 420 and the upper III-V compound layer 440. - A conductive layer 450 is selectively formed on the upper III-V compound layer 440. Conductive layer 450 is at least partially transparent. The material suitable for the conductive layer 450 may be φ to comprise ITO or a thin layer of p-type ohmic metal, such as Ni/Au. The upper electrode 460 may be formed on the conductive layer 450 (or on the upper germanium-V compound layer 440 when the conductive layer 450 is absent). The inclusion of the conductive layer 450 can be determined depending on whether the substrate 405 is thinned to allow more of the emitted light to exit the development optical device 400. If the substrate 405 is not thinned so that more light can exit the light emitting device 400, the conductive layer 450 is preferably included. The lower electrode 470 may be formed on the lower III-V compound layer 420. The upper electrode 460 and the lower electrode 470 may be referred to as a ρ_electrode and an η_electrode, respectively. The use of a transparent germanium material in the conductive layer 450 can significantly increase the conductivity between the upper electrode-13-201006007 460 and the upper III-V compound layer 440, while maximizing the light emitted by the quantum well layer 430 from the conductive layer. The upper surface of 450" quantum well layer 430 can form a quantum well for the electrical carriers between the lower III-V compound layer 420 and the upper III-V compound layer 440. A voltage may be applied between the lower electrode 470 and the upper electrode 460 to generate an electric field in the quantum well layer 430 to excite a carrier in the quantum well formed by the quantum well layer 430, in the lower III-V compound layer 420 and A quantum well for the electro-carrier is formed between the upper III-V group φ layer 440. The recombination of the excitation carrier can emit light. The emission wavelength is mostly determined by the band gap of the material in the quantum well layer 43 0 . In the present specification, the term "quantum well" means a potential well that confines charge carriers or charged particles, such as electrons and holes to a substantially two-dimensional flat region. In semiconductor light-emitting devices, quantum wells capture excitation electrons and holes and define the wavelength at which light is emitted and generate photons when electrons and holes are recombined in a quantum well. # In this specification, a quantum well can contain a uniform layer or a majority of quantum wells. For example, a quantum well layer (e.g., quantum well layer 430 in Figures 5A through 51) may comprise a substantially uniform layer made of InN, GaN, InGaN, AlGaN, InAIN, or AlInGaN. Quantum wells may also contain multiple layers of structure defining one or more quantum wells. A quantum well can also be formed, for example, by sandwiching InGaN, AlGaN, InAIN, or InGaAIN between two GaN layers. Quantum wells can be formed by sandwiching an InGaN layer in a GaN or AlGaN layer. The quantum wells may comprise one or a stack of layers formed to form the layers, the layers defining the quantum wells described above. -14- 201006007
InN的帶隙約1.9eV，低於約3.4eV的GaN的帶隙。 較低帶隙的InN或InGaN層可以界定一電位井，用以捕捉 例如電子及電洞的電荷載子。被捕獲的電子及電洞可以重 組，以產生光子（發光）。在InN或InGaN中之帶隙因此 可以決定發光的顏色。換句話說，發光的顏色可以藉由調 整在InGaN中之In及Ga的組成物加以調整。例如，一量 子井可以由InN層發出紅光、由In(〇.5)Ga(0.5)N層發出 φ 綠光、及在量子井中，由In(0.3)Ga(0.7)N中發出藍光。 在一態樣中，所掲示之發光裝置可以包含一具有第一 面及不平行第一面的第二面之基材；及一發光層，安置在 該第二面上，以發光，該發光層具有一不平行於該第一面 的發光面。藉由描述一層安置在另一層“之上方”或“上”， 這不必然表示兩層必須彼此直接接觸；事實上，其間可能 有一或更多其他層，這將如同此說明之其他部份所述。在 一態樣中，所揭示的發光裝置可以包含一基材；及一發光 φ 層，安置在該基材之上方以發出，該發光層具有一佔用面 積並具有較佔用面積爲大之發光面區域。在另一態樣中， 所揭示之發光裝置可以包含：具有一第一面及有一凸部形 成在該第一面上的基材；及一發光層，安置在該凸部上， 用以發光，該發光層具有不平行於該第一面的發光面。 圖3E及3F分別顯示用於發光結構的其他層結構及材 料組成物例子，其可以包含溝渠、例如錐體的凸部 '及其 他包含不平行於基材頂面之斜面的結構。只爲了顯示目的 ，該等層係被顯示於水平方向。描述了在溝渠之斜面上或 -15- 201006007 在凸部及基材上面的層之順序、厚度及組成物。在緩衝 下的Ah 03層可以提供反射由基材發出的光所需之反射 。量子井層可以藉由二至十週期的GaN : Mg及InxGai. 層所形成。GaN : Mg層可以例如約5nm厚。InxGa^N 可以例如約2nm厚。下III-V族化合物層可以由被摻雜 Mg或Si的GaN作成，其厚度大約2微米。上III-V族 合物層可以由被摻以Mg或Si的GaN、被摻以Mg或 φ 的AlGaN所作成，其厚度大約lOOnm。上電極可以由大 厚2〇Onm的ITO層所形成，或分別由Ni及Au作成之 層所作成。 在部份實施例中，一反射緩衝層可以被形成在基 405上。第一緩衝層及第二緩衝層可以被依序形成在基 405上。至少第二緩衝層爲反射性的。所組合用於第一 衝層及第二緩衝層的反射係數係高於由發光裝置發射的 之頻譜範圍中的30%、50%或70%。下III-V族化合物 然後被形成在第二反射緩衝層上。量子井層、上III-V 化合物層、導電層、上電極、及下電極可以然後被連續 成，以形成該發光裝置。 應注意的是，在晶圓400、500中之發光結構可以 由切片及切除加以分離，以形成個別發光裝置，各個發 裝置被供電以在個別應用中發光。在晶圓400、500中 發光結構各可以被使用作爲積體發光裝置。在晶圓400 500中之發光結構的下電極可以被電連接，以允許它們 接至一共同外部電極。在晶圓400或500中的發光結構 層 度 χΝ 層 以 化 Si 約 雙 材 材 緩 光 層 族 形 藉 光 之 或 連 的 -16- 201006007 上電極可以連接至不同外部電極，這允許在晶圓400或 500中之發光結構被個別定址以導通及關閉。在晶圓400 或500中之發光結構的上電極可以被連接至一共同外部電 極，以允許在晶圓400或500中之發光結構被成群地導通 或關閉，以提供大面積之發光裝置。 上述發光裝置的另一優點爲所揭示發光裝置及製程可 以克服不同熱膨脹及於下III-V族化合物層與基材間之晶 φ 格失配，並防止相關層破裂及剝離。已知晶格失配及不同 熱膨脹的嚴重性隨著於下III-V族化合物與基材（或緩衝 層）間之橫向接觸尺寸的函數。傳統LED發光裝置經常 製造於2吋及4吋基材上，並可能在該下III-V族化合物 層與基材（或緩衝層）的接觸區域受到大應力。在矽爲基 的基材中，對於（1〇〇)面的晶格失配及不同熱膨脹係遠 大於對於（111)面者。 所揭示之發光裝置藉由分割（111)溝渠面及在溝渠 〇 間之（100)上面，而分解大（100)表面積。溝渠的開口 (在圖3A-3C中之210)可以在100微米至10 0mm的範圍 間，例如1至20mm。（ 1 00 )上面207的寬度“D”（圖4B )可以被保持例如窄於1 〇〇〇微米，這是遠小於用以製造 傳統LED發光裝置的晶圓基材的寬度。同樣地，底面215 的寬度“W”（圖3C)也可以保持例如窄於200微米。藉由 保持這些尺寸很小’有關於不同熱膨脹及晶格失配的應力 可以被顯著地降低。 上述發光裝置可以產生遠較傳統LED裝置爲高之發 -17- 201006007 光強度。參考圖6A及6B，傳統LED發光裝置600包含 一在基材600上之平坦發光面610。依據本發明之發光裝 置650包含具有上面660及具有斜發光面670的溝渠的基 材65 5。對於矽爲主之基材，上面可以沿著（1〇〇 )結晶面 及平行於（1 1 1 )結晶面的斜發光面670A、670B。斜發光 面670A、670B相對於上面660具有54.7度角。對於在上 面6 6 0上相同的佔用面積，沿著各個這些面量測的斜發光 φ 面670A、670B的面積總和爲在傳統LED裝置600中之平 坦發光面610的面積的l/(cos(54.7°))(即約1.73倍）。 所揭示之發光裝置係相容於其他物質材料及斜面溝渠面的 相對取向。應了解的是，所揭示之發光裝置係相容於其他 基材材料及斜溝渠面的相對取向。斜溝渠面可以在20度 及8 0度間之一角度，或者更特定的例子，即於相對於基 材的上面，於約50度至60度間。 在所揭示發光裝置中溝渠的發光面可以大於溝渠開口 暴 面積的1倍、或1.2倍、或1.4倍、或1.6倍。在上述發 光裝置的大發光表面積允許產生較傳統LED裝置所能產 生之更高光發射強度。對於形成在個別晶粒上之發光裝置 (例如圖2A中之200 )，爲總和斜溝渠面所提供的發光 面可以具有較發光裝置的平坦區（例如圖2A中之發光裝 置2 00的佔用面積）爲大的面積。 所述發光裝置的另一優點爲它們可以發出較傳統LED 裝置更集中角度範圍的光。參考圖6A及6B，平坦發光面 610發出180度角範圍的光。相對於基材法線方向，角度 -18- 201006007 發射分佈620具有3 60度旋轉對稱。發光裝置65〇包含分 別依據角度分佈680A及680B發光的斜發光面670A及 6 7 0B，這些係組合以完成一發光角分佈68 0。發光角分佈 680具有相對於基材法線方向的90度旋轉對稱及70.6°的 角寬，這係少於爲在傳統LED發光裝置600中之角發光 分佈620的角度範圍的一半。因此，發光裝置65 0的發光 較集中及較傳統LED發光裝置有效。所揭示之發光裝置 0 係相容於其他基材材料及斜溝渠面的相對取向。由斜溝渠 面發出之光可以侷限於小於150度、120度、100度或80 度的角度範圍內，以提供不同度數的角度集中光發射。 參考圖 5A-5I及圖 8，發光裝置400 (200、300或 600 )的製程可以包含以下步驟。應注意的是，所述使用 溝渠的製程係爲用於發光結構的例子。該製程也可以應用 至例如凸部（例如錐體）的其他發光結構及其他包含不平 行於基材的相對上面的斜面的不同結構。一遮罩層401係 Φ 被形成在基材405(圖5A)上。基材405具有一上面 405A。在遮罩層401的開口 402係被界定予以形成之溝渠 的位置與開口。一或更多溝渠410係形成在基材405中（ 圖5B1及5B2的步驟810)。溝渠410可以藉由化學蝕刻 基材4 0 5加以形成。濕式蝕刻係被沿著所有方向作等向蝕 刻。例如’一蝕刻劑可以對於（1 1 1 )矽結晶面比較其他 結晶面方向有較慢的鈾刻率。因此，蝕刻劑（例如Κ Ο Η ) 可以在基材405中建立溝渠410，其中，溝渠面41〇α、 410Β係沿著（111)矽結晶面。蝕刻可以底切在硬遮罩層 -19- 201006007 401下之矽，以在Si ( 100 )晶圓的頂部形成（硬）遮罩 層401懸突（圖5B1)。硬遮罩層401被隨後移除（如圖 5B2所示）。 一或多數緩衝層可以使用原子層沈積（ALD)或 MOCVD，下一個被形成在基材405上（步驟820 )。例如 ，使用原子層沈積（ALD )，一緩衝層213(或210)係 被下一個形成在基材205上（步驟820)。基材205可以 Φ 具有上面朝向（100)結晶面。緩衝層213或210可以由 GaN、ZnO、AIN、HfN、AlAs或SiC所形成。緩衝材料的 原子層沈積可以使用例如由應用材料公司所購得之 IPRINT Centura之商用設備加以執行。原子層沈積可以涉 及真空室的去氣、施加前驅材料、及單層單層地沈積緩衝 材料。基材（或室）溫度可以控制於約600°C。在ALD製 程中，形成成核層的層厚可以薄至12埃，這遠較用於在 傳統LED結構（例如圖1所繪之LED結構1 00 )中形成 Φ 緩衝層的MOCVD所需之300埃的厚度爲薄。步驟820也 可以稱爲低溫緩衝層的ALD。 反射緩衝層係在真空室中使用原子層沈積（ALD )加 以沈積在基材205上，真空室被維持在範圍由550。(：至 8 5 0°C，例如670°C的相對低溫。第二緩衝層可以在真空室 中使用原子層沈積（ALD )沈積在第一緩衝層上，該真空 室被維持在範圍由8 5 0°C至1 250°C間之例如100CTC的相對 闻溫。反射緩衝層可以由Al、A1氧化物、Ag、Ag氧化物 、Au、Au氧化物、及包含Al、Ag或Au的合金所形成。 -20- 201006007 反射緩衝層也可以包含GaN、ZnO、AIN、HfN、AlAs或 SiC。反射緩衝層可以具有約20至300埃的厚度。反射緩 衝層的結晶結構可以具有磊晶匹配至基材及下III-V族化 合物層的晶格，以降低由基材至下III-V族化合物層的晶 格結構轉移，這可以降低在多層結構中之破裂及剝離的機 會。 對於發光裝置發光裝置400，反射緩衝層415可以藉 _ 由MOCVD、PVD、ALD或分子束幕晶（MBE )，而形成 在基材405的表面405A及溝渠410中之斜面410A、410B 上。反射緩衝層415可以由ALD TaN或TiN材料加以形 成。在其他例子中，反射緩衝層415的形成琶以包含以下 之一程序：使用MOCVD，以1000°C沈積A1N及以l〇〇〇°C 沈積GaN ;使用MOCVD，以700°C沈積GaN，其後，以 MOCVD 以 l〇〇〇°C 沈積 GaN ;使用 PVD 以 5 0(TC 沈積 HfN ，其後’使用MBE，以700°C沈積GaN ;及使用MOCVD φ ’以1000 °c沈積Si CN，其後使用MOCVD，以1000 r沈 積 GaN。 在V型溝渠410中的面410A及410B中形成反射緩 衝層415的優點爲面410A及410B的（111)結晶方向可 以允許在矽基材、反射緩衝層415、及下III-V族化合物 層420間之較佳晶格匹配。較佳晶格匹配可以顯著地降低 由部份傳統發光裝置之晶格失配所造成之破裂問題。 下III-V族化合物層420被下一個形成在反射緩衝層 415上（圖5D的步驟83 0 )。下III-V族化合物層420可 -21 - 201006007 以由η-型摻雜GdN材料所形成。GaN可以在矽被摻雜的 同時，使用MOCVD被成長在反射緩衝層415上。矽摻雜 可以加強拉伸應力，以使壓縮及拉伸強度可以平衡。結果 ，可以顯著地防止在形成下III-V族化合物層420時的破 裂。 一量子井層43 0被下一個形成在下Πΐ-ν族化合物層 420上（圖5E的步驟840)。量子井層430可以包含由 0 InN、GaN、InGaN、AlGaN、InAIN、或 AlInGaN 所作成 之實質均勻層。量子井層430也可以包含界定一或更多量 子井的多層結構。量子井可以例如藉由包夾在兩GaN或 AlGaN 層間之 InGaN、AlGaN、InAIN、或 InGaAIN 層所 形成。量子井層43 0可以包含一堆疊此等分層結構，各個 界定一量子井。 上III-V族化合物層440係被形成在量子井層430上 (圖5F之步驟850)。不同於下III-V族化合物層42 0爲 φ η-型摻雜及上III-V族化合物層440爲p-型摻雜，下III-V 族化合物層420可以爲ρ-型摻雜及上III-V族化合物層 440可以爲η-型摻雜（如圖9之流程圖所示）。 透明導電層450可以隨後被選用地形成在上III-V族 化合物層440上（圖5G的步驟860)。量子井層的形成 可以包含多MOCVD步驟。該多步驟的各步驟可以包含沈 積一層厚5 0埃。 量子井層430、上III-V族化合物層44 0及導電層450 也可以由MOCVD形成。下III-V族化合物層420、量子井 -22- 201006007 層430、上III-V族化合物層440的MOCVD形成及反射緩 衝層415的ALD形成也可以在同一 ALD/CVD室系統中形 成，以最小化基材移動進出真空室的次數。該製程產量可 以進一步改良。在處理時的雜訊也可以降低。 量子井層430、上III-V族化合物層440、及導電層 450可以藉由以光阻塗覆並以光微影加以作出圖案。量子 井層43 0、上III-V族化合物層440、及導電層450的部份 0 可以藉由濕式蝕刻移除’以曝露出下III-V族化合物層 420的上面的一部份（圖5H的步驟870)。 上電極4 60被隨後形成在導電層450上（圖5H的步 驟8 80 )。上電極460可以包含Ni/Au雙層，其分別具有 12nm及lOOnm的厚度。導電層450的製造可以涉及塗覆 光阻層在4501上及下III-V族化合物層420的曝露的上表 面上。光阻層然後使用光微影加以圖案化並選擇地移除以 形成一遮罩。電極材料係被隨後沈積在遮罩的開口中。不 φ 想要之電極材料及光阻層被隨後移除。 下電極470被隨後形成在下III-V族化合物層420上 (圖5H)。下電極470可以包含AuSb/Au雙層。AuSu層 的厚度爲18nm，而Au層的厚度爲lOOnm。下電極470的 形成也可以藉由形成在下ΠΙ-V族化合物層420上具有開 口的光阻遮罩、沈積電極材料並隨後移除不想要的電極材 料及光阻層，而完成下電極470。最後，形成發光裝置 400 〇 或者，參考圖51，一保護層48 0可以被引在發光裝置 -23- 201006007 400上，用以保護使之免於濕氣、氧及在環境中之其他有 害物質。保護層480可以由例如氧化矽、氮化矽或環氧等 之介電材料作成。保護層可以被作出圖案，以曝露出上電 極460及下電極470，以允許它們可以接收外部電壓。在 部份實施例中，保護層可以包含導熱材料，例如A1及Cu ，以提供適當對發光裝置400的冷卻。 應注意的是，下III-V族化合物層及上III-V族化合 φ 物層可以具有不同摻雜配置，只要它們摻雜含量係彼此相 對即可。下III-V族化合物層可以爲P-型摻雜及上III-V 族化合物層可以爲η-型摻雜。或者，下III-V族化合物層 可以爲η-型摻雜及上III-V族化合物層可以爲ρ-型摻雜。 圖7爲依據本發明的另一發光裝置700的透視圖。不 同於在遮罩層中之正方開口（圖5Α及以下之步驟800 ) ，一矩形開口被形成在遮罩層410中，以產生蝕刻後的長 溝渠。矩形開口有時較佳爲溝渠開口的長縱深比。例如， ❹ 部份發光裝置需要長形發光面。對於矽爲主之基材，上面 可以平行於（1 〇〇 )結晶面。類似於前述說明，斜溝渠面 係平行於（111)結晶面。長斜溝渠面可以至少50%大於 斜第一溝渠面的面積，在長溝渠的末端。 所揭示之發光裝置及製程可以包含一或更多之以下優 點。所揭示之發光裝置及製程可以克服有關於下III-V族 化合物層與基材間之晶格失配並防止在傳統發光裝置中之 相關層的破裂。所揭示之發光裝置及製程可以防止由於ρ-摻雜III-V族化合物層與基材間之不同熱膨脹造成之ρ-摻 -24- 201006007 雜或η-摻雜III-V族化合物層的破裂或剝離。有關於所揭 示之發光裝置的優點爲發光裝置可以藉由增加發光裝置的 密度及藉由來自溝渠中之斜面或垂直面的額外發光而顯著 地增加發光效率。 在所揭示之發光裝置中的發光層可以被形成在上述溝 渠以外之其他結構類型中。參考圖9A至10C，例如，一 發光裝置900係被形成在具有上面907的基材905上。發 ❹ 光裝置900包含一凸部910在上面907之上。凸部910具 有一或更多凸出面 913(圖10A-10C)，並相對於上面 907有一斜率。凸部910也可以具有一頂面919，其係實 質平行於上面907。頂面919的面積可以保持小於凸出面 913之一的20%。凸部910也可以具有錐體或截頭錐體的 形狀，在上面907之上。 基材905可以爲矽爲主：上面907可以平行於（100 )結晶面。凸出面913可以平行於（1 1 1 )結晶面。（或 Φ 者’上面907可以平行於（111)結晶面。凸出面913可 以平行於（1〇〇)結晶面。）基材905也可以包含多層之 絕緣層上覆政（SOI)結構。 一緣917被形成在兩鄰接凸出面913的交界。基材 905可以具有外緣908的矩形或正方形。發光裝置900可 以與其他發光裝置一起製造在一半導體晶圓上，並切片以 形成分開之晶粒。發光裝置900可以具有爲平行於上面 907的面中之平坦區所界定之矩形或正方形晶粒形狀。 發光裝置900包含：一反射緩衝層915在上面9〇7上 -25- 201006007 及凸出面913上；下III-V族化合物層920在一反射緩衝 層915上；一或更多量子井層93 0在下ΙΙΙ·ν族化合物層 920上；及一上III-V族化合物層940。在凸出面913上的 上III-V族化合物層940之部份係被朝向相對於基材905 的上面907的一角度。發光裝置900也包含一下電極970 在下III-V族化合物層920上及一上電極960在上III-V 族化合物層940上。 φ 在部份實施例中，如圖11Α、11Β所示，一半導體晶 圓1000包含2x2陣列的發光結構1000A-1000D形成在基 材905上。各個發光結構1000A-1000D可以具有類似於上 述發光裝置900的結構。發光結構1000A-1000D可以形成 在半導體晶圓上呈2x2陣列。發光結構1 000A-100D可以 使用爲單一發光裝置，或者它們可以藉由切割與切片加以 分離，以形成類似於發光裝置200的個別發光裝置。在另 一實施例中，如圖11C所示，半導體晶圓1 1〇〇可以包含 〇 4χ4陣列的發光結構1 1 10。 如上所述，基材905可以爲矽爲主。上面907可以平 行於（1〇〇)結晶面。凸出面913可以平行於（111)結晶 面。（100 )上面207的寬度“D1”（圖1 1Β )可以例如保 持爲低於1〇〇〇微米，這係遠低於製造傳統LED發光裝置 的晶圓基材的寬度。藉由使此尺寸保持小，有關於不同熱 膨脹的應力及晶格失配可以被顯著降低。 圖9A-1 1C所示之發光裝置可以產生與傳統LED裝置 不同的角度分佈。參考圖12，發光裝置900包含形成在基 -26- 201006007 材905上之凸部910。具有發光面1270A及1270B的發光 層係被形成在凸部9 1 0的斜面上。對於矽爲主之基材，上 面907可以沿著（1〇〇 )結晶面及斜面發光面1270A、 1270B平行於（1 1 1 )結晶面。相對於上面907，發光面 1 270八、1 2708係有54.7°角。對於在上面的相同佔用面積 ，在發光面1 270A、1270B的發光面積總和大約爲在傳統 LED裝置600(圖6A)的面積的1.73倍。所揭示之發光 〇 裝置係相容於其他基材材料及斜凸出面的相對取向。斜凸 出面可以在20度至80度間之一角度，或者，更特定例爲 相對於基材的上面爲50度至60度間。 在所揭示之發光裝置的凸部上的發光面可以多於凸部 的基礎面積的一倍、或1.2、或1.4或1.6倍。在所述發光 裝置中之大發光面積允許所揭示之發光裝置產生較傳統 LED裝置爲高的發光強度。來自發光面1270A、1270B的 光可以假設如圖12所示之寬分佈1 280。 實施例可以包含一或更多之以下優點。所揭示之發光 裝置及相關製程可以提供較高產量的發光裝置，因此，較 傳統發光裝置有較低之製造成本。所揭示之發光裝置及相 關製程他可以提供更密集之發光裝置，並例如可以包含一 發光元件、一驅動器、電源及光調變單元，整合在單一半 導體基材上。 前述說明及附圖應被認爲本發明之原理的說明。本發 明可以以各種形狀及大小加以架構，並且，並不限於所述 較佳實施例的尺寸。本發明之各種應用將爲熟習於本技藝 -27- 201006007 者所了解。因此，本發明並不被限於所述之例子及特定結 構與操作。相反地，所有適當修改及等效可以落在本發明 之範圍內。例如，η-摻雜及p-摻雜III-V族化合物層可以 在位置上交換，即，Ρ-摻雜ΠΙ-V族化合物層可以位在量 子井層下，及η-摻雜III-V族化合物層可以位在量子井層 上。所示發光裝置可以適用以發出綠、藍，及其他顏色的 光。 ❹ 應了解的是，所揭示之系統與方法係適用於大範圍的 應用中，例如雷射二極體、藍/uv LED、霍爾效應感應器 、開關、UV檢測器、微電機系統（MEMS )、及RF功率 電晶體中。所揭示之裝置可以包含其他各種應用的元件。 例如，根據本案裝置的雷射二極體可以包含用以產生雷射 光的反射面或鏡面。對於發光應用，本案之系統可以包含 其他反射器及擴散器。 應了解的是，本案所揭示之發光裝置並不限於所述之 〇 溝渠及凸部。基材可以包含具有第一取向的第一面及第二 取向的第二面。該第一及第二面可以可不形成一溝渠或凸 部。多數III-V族化合物層可以被形成在該基材上。當電 流產生於該III-V族化合物層時，III-V族化合物層可以發 光。 【圖式簡單說明】 圖1爲傳統LED結構的剖面圖； 圖2A爲依據本發明實施例之發光裝置的透視圖； -28- 201006007 圖2B爲在圖2A中之發光裝置的前角落部的詳細透視 rm · 圖， 圖3A爲沿著在圖2A中之線A-A的發光裝置的剖面 圖； 圖3B爲在圖3 A的發光裝置的一側部的詳細剖面圖； 圖3C爲在圖3A的發光裝置的底部的詳細剖面圖； 圖3D爲在圖2A中之線B_B的發光結構剖面圖； φ 圖3E及3F圖爲用於發光結構的層結構及材料組成物 的例子； 圖4A爲依據本發明之在基材上製造的發光結構的2x 2陣列的透視圖； 圖4B爲沿圖4A之線B-B的發光結構的一部份剖面 圖； 圖4C爲依據本發明之基材上製造的4x4陣列的發光 結構的透視圖； # 圖5A爲具有用以形成圖4B的發光裝置的圖案遮罩的 基材的剖面圖； 圖5B1爲在蝕刻經圖5A所示之遮罩後，在圖5A中 之發光裝置的透視圖； 圖5B2及5C-5I爲形成圖4B的發光裝置的不同步驟 的剖面圖； 圖6A爲傳統LED發光裝置的發光角度分佈例的示意 Ιαΐ · 圖， 圖6Β爲由圖2Α所示之發光裝置所發射的光的角度分 -29- 201006007 佈的示意圖； 圖7爲依據本發明的另一發光裝置的透視圖； 圖8爲用於圖2至圖7的矽爲主的發光裝置的製程的 流程圖； 圖9A爲依據本發明另一實施例之發光裝置的透視圖 » 圖9B爲圖9A之發光裝置的前角落部份的詳細透視圖 ❹ 圖10A爲沿著圖9A線A-A所取之發光裝置的剖面圖The band gap of InN is about 1.9 eV, which is lower than the band gap of GaN of about 3.4 eV. A lower bandgap InN or InGaN layer can define a potential well to capture charge carriers such as electrons and holes. The captured electrons and holes can be reassembled to produce photons (luminescence). The band gap in InN or InGaN can thus determine the color of the luminescence. In other words, the color of the luminescence can be adjusted by adjusting the composition of In and Ga in InGaN. For example, a quantum well can emit red light from the InN layer, φ green light from the In(〇.5)Ga(0.5)N layer, and blue light from In(0.3)Ga(0.7)N in the quantum well. In one aspect, the illustrated light emitting device can include a substrate having a first side and a second side that is not parallel to the first side; and a light emitting layer disposed on the second side to emit light, the light emitting The layer has a light emitting surface that is not parallel to the first side. By describing one layer "above" or "on" another layer, this does not necessarily mean that the two layers must be in direct contact with each other; in fact, there may be one or more other layers in between, as will be described elsewhere herein. Said. In one aspect, the disclosed light-emitting device may comprise a substrate; and a light-emitting φ layer disposed above the substrate for emitting, the light-emitting layer having a footprint and having a larger footprint region. In another aspect, the disclosed light emitting device may include: a substrate having a first surface and a convex portion formed on the first surface; and a light emitting layer disposed on the convex portion for emitting The light emitting layer has a light emitting surface that is not parallel to the first surface. Figures 3E and 3F show examples of other layer structures and material compositions for the light-emitting structure, respectively, which may include trenches, e.g., protrusions of the pyramids, and other structures that include slopes that are not parallel to the top surface of the substrate. These layers are displayed in the horizontal direction for display purposes only. Describes the sequence, thickness, and composition of the layers on the slope of the trench or -15-201006007 above the protrusions and substrate. The Ah 03 layer under buffer can provide the reflection needed to reflect the light emitted by the substrate. The quantum well layer can be formed by two to ten cycles of GaN:Mg and InxGai. layers. The GaN : Mg layer may be, for example, about 5 nm thick. InxGa^N may be, for example, about 2 nm thick. The lower III-V compound layer may be formed of GaN doped with Mg or Si and has a thickness of about 2 μm. The upper III-V compound layer may be made of GaN doped with Mg or Si, AlGaN doped with Mg or φ, and has a thickness of about 100 nm. The upper electrode may be formed of an ITO layer having a thickness of 2 Å Onm or a layer made of Ni and Au, respectively. In some embodiments, a reflective buffer layer can be formed on the base 405. The first buffer layer and the second buffer layer may be sequentially formed on the base 405. At least the second buffer layer is reflective. The reflection coefficients combined for the first and second buffer layers are higher than 30%, 50% or 70% of the spectral range emitted by the illumination device. The lower III-V compound is then formed on the second reflective buffer layer. The quantum well layer, the upper III-V compound layer, the conductive layer, the upper electrode, and the lower electrode may then be continuously formed to form the light-emitting device. It should be noted that the light emitting structures in the wafers 400, 500 can be separated by slicing and cutting to form individual lighting devices, each of which is powered to emit light in an individual application. The light-emitting structures in the wafers 400, 500 can each be used as an integrated light-emitting device. The lower electrodes of the light emitting structures in wafer 400 500 can be electrically connected to allow them to be connected to a common external electrode. The layer of the light-emitting structure in the wafer 400 or 500 is layered to form Si. The double-layer light-diffusing layer family is connected by light or the 16-201006007 upper electrode can be connected to different external electrodes, which allows the wafer to be The light-emitting structures in 400 or 500 are individually addressed to be turned on and off. The upper electrode of the light emitting structure in wafer 400 or 500 can be connected to a common external electrode to allow the light emitting structures in wafer 400 or 500 to be turned on or off in groups to provide a large area of light emitting device. Another advantage of the above-described light-emitting device is that the disclosed light-emitting device and process can overcome different thermal expansion and crystal lattice mismatch between the lower III-V compound layer and the substrate, and prevent cracking and peeling of the relevant layer. The lattice mismatch and the severity of the different thermal expansions are known to function as a function of the lateral contact size between the lower III-V compound and the substrate (or buffer layer). Conventional LED lighting devices are often fabricated on 2" and 4" substrates and may be subjected to large stresses in the contact area of the lower III-V compound layer with the substrate (or buffer layer). In the ruthenium-based substrate, the lattice mismatch and the different thermal expansion systems for the (1 〇〇) plane are much larger than those for the (111) plane. The disclosed illuminating device decomposes a large (100) surface area by dividing the (111) trench surface and above (100) between the trenches. The opening of the trench (210 in Figures 3A-3C) may be in the range of 100 microns to 100 mm, such as 1 to 20 mm. (100) The width "D" of the upper 207 (Fig. 4B) can be kept, for example, narrower than 1 〇〇〇 micron, which is much smaller than the width of the wafer substrate used to fabricate conventional LED illuminators. Likewise, the width "W" of the bottom surface 215 (Fig. 3C) can also be maintained, for example, narrower than 200 microns. By keeping these dimensions small, the stresses associated with different thermal expansions and lattice mismatches can be significantly reduced. The above-mentioned illuminating device can produce a light intensity of -17-201006007 which is much higher than that of the conventional LED device. Referring to Figures 6A and 6B, conventional LED lighting device 600 includes a planar light emitting surface 610 on substrate 600. Light-emitting device 650 in accordance with the present invention includes a substrate 65 5 having a top surface 660 and a trench having a sloped light-emitting surface 670. For the base material based on ruthenium, the upper surface may be along the (1 〇〇) crystal plane and the oblique light-emitting surfaces 670A, 670B parallel to the (1 1 1) crystal plane. The oblique illumination surfaces 670A, 670B have an angle of 54.7 degrees with respect to the upper surface 660. For the same footprint on the upper 660, the sum of the areas of the oblique illuminating φ faces 670A, 670B measured along each of these faces is l/(cos() of the area of the flat illuminating face 610 in the conventional LED device 600. 54.7°)) (ie about 1.73 times). The disclosed illumination device is compatible with the relative orientation of other material materials and beveled trench surfaces. It will be appreciated that the disclosed illumination device is compatible with the relative orientation of other substrate materials and oblique trench surfaces. The inclined trench can be at an angle between 20 and 80 degrees, or a more specific example, between about 50 and 60 degrees relative to the top of the substrate. In the disclosed illumination device, the illumination surface of the trench may be greater than one, or 1.2, or 1.4, or 1.6 times the area of the trench opening. The large illuminating surface area of the above-described illuminating device allows for a higher light emission intensity than conventional LED devices can produce. For a light-emitting device (eg, 200 in FIG. 2A) formed on an individual die, the light-emitting surface provided for the sum of the inclined trenches may have a flatter region than the light-emitting device (eg, the footprint of the light-emitting device 200 in FIG. 2A) ) for a large area. Another advantage of the illumination devices is that they can emit light in a more concentrated range of angles than conventional LED devices. Referring to Figures 6A and 6B, the flat illumination surface 610 emits light in the range of 180 degrees. The angle -18-201006007 emission profile 620 has a 3 60 degree rotational symmetry with respect to the normal direction of the substrate. The illumination device 65A includes oblique illumination surfaces 670A and 607B that emit light in accordance with the angular distributions 680A and 680B, respectively, which are combined to complete an illumination angle distribution 68 0 . The illuminating angle distribution 680 has a 90 degree rotational symmetry with respect to the normal direction of the substrate and an angular width of 70.6, which is less than half the angular range of the angular illuminating distribution 620 in the conventional LED lighting device 600. Therefore, the illumination of the illumination device 65 0 is more concentrated and more effective than the conventional LED illumination device. The disclosed illuminating device 0 is compatible with the relative orientation of other substrate materials and oblique trench surfaces. The light emitted by the oblique trench can be limited to an angular range of less than 150, 120, 100 or 80 degrees to provide angularly concentrated light emission of different degrees. Referring to Figures 5A-5I and Figure 8, the process of illumination device 400 (200, 300 or 600) may comprise the following steps. It should be noted that the process of using the trench is an example for a light-emitting structure. The process can also be applied to other illuminating structures such as protrusions (e.g., cones) and other different structures including opposing upper faces that are not parallel to the substrate. A mask layer 401 is formed on the substrate 405 (Fig. 5A). Substrate 405 has an upper surface 405A. The opening 402 in the mask layer 401 is defined by the location and opening of the trench to be formed. One or more trenches 410 are formed in the substrate 405 (step 810 of Figures 5B1 and 5B2). The trench 410 can be formed by chemically etching the substrate 405. The wet etch is anisotropically etched in all directions. For example, an etchant can have a slower uranium engraving rate for the (1 1 1 ) 矽 crystal plane compared to other crystal plane directions. Thus, an etchant (e.g., Κ Η 可以 ) can establish a trench 410 in the substrate 405 wherein the trench faces 41 〇 α, 410 沿着 are along the (111) 矽 crystal face. The etch can be undercut under the hard mask layer -19-201006007 401 to form a (hard) mask layer 401 overhang on top of the Si (100) wafer (Fig. 5B1). The hard mask layer 401 is subsequently removed (as shown in Figure 5B2). One or more buffer layers may be deposited using atomic layer deposition (ALD) or MOCVD, the next being formed on substrate 405 (step 820). For example, using atomic layer deposition (ALD), a buffer layer 213 (or 210) is formed next on the substrate 205 (step 820). The substrate 205 may have a top surface oriented toward (100) crystal faces. The buffer layer 213 or 210 may be formed of GaN, ZnO, AIN, HfN, AlAs or SiC. Atomic layer deposition of the buffer material can be performed using, for example, a commercial device of IPRINT Centura available from Applied Materials. Atomic layer deposition can involve degassing of the vacuum chamber, application of precursor materials, and deposition of buffer materials in a single layer of monolayer. The substrate (or chamber) temperature can be controlled to about 600 °C. In the ALD process, the layer thickness of the nucleation layer can be as thin as 12 angstroms, which is much higher than the 300 required for MOCVD to form a Φ buffer layer in a conventional LED structure (such as the LED structure 100 depicted in FIG. 1). The thickness of angstrom is thin. Step 820 may also be referred to as ALD of the low temperature buffer layer. The reflective buffer layer was deposited on the substrate 205 using atomic layer deposition (ALD) in a vacuum chamber maintained at a range of 550. (: to a temperature of 850 ° C, such as a relatively low temperature of 670 ° C. The second buffer layer can be deposited on the first buffer layer in a vacuum chamber using atomic layer deposition (ALD), which is maintained in the range of 8 A relative temperature of, for example, 100 CTC between 50 ° C and 1 250 ° C. The reflective buffer layer may be composed of Al, Al oxide, Ag, Ag oxide, Au, Au oxide, and an alloy containing Al, Ag or Au. -20- 201006007 The reflective buffer layer may also comprise GaN, ZnO, AIN, HfN, AlAs or SiC. The reflective buffer layer may have a thickness of about 20 to 300 angstroms. The crystalline structure of the reflective buffer layer may have epitaxial matching to a lattice of the substrate and the lower III-V compound layer to reduce the lattice structure transfer from the substrate to the lower III-V compound layer, which can reduce the chance of cracking and peeling in the multilayer structure. The light-emitting device 400, the reflective buffer layer 415 can be formed on the surface 405A of the substrate 405 and the slopes 410A, 410B in the trench 410 by MOCVD, PVD, ALD or molecular beam curtain crystal (MBE). The reflective buffer layer 415 It can be formed from ALD TaN or TiN materials. In other cases The formation of the reflective buffer layer 415 includes one of the following procedures: depositing A1N at 1000 ° C and depositing GaN at 10 ° C using MOCVD; depositing GaN at 700 ° C using MOCVD, thereafter, MOCVD deposits GaN at 10 ° C; uses PVD to deposit HfN at 50 °, then 'Uses MBE to deposit GaN at 700 ° C; and uses MOCVD φ ' to deposit Si CN at 1000 ° C, after which it is used MOCVD, depositing GaN at 1000 r. The advantage of forming the reflective buffer layer 415 in the faces 410A and 410B in the V-type trench 410 is that the (111) crystallographic direction of the faces 410A and 410B may allow for the germanium substrate, the reflective buffer layer 415, And the preferred lattice matching between the lower III-V compound layer 420. The preferred lattice matching can significantly reduce the cracking problem caused by the lattice mismatch of some conventional light-emitting devices. The lower III-V compound layer 420 is formed on the reflection buffer layer 415 next (step 83 0 of FIG. 5D). The lower III-V compound layer 420 may be -21 to 201006007 to be formed of an n-type doped GdN material. GaN may be formed in the crucible While doping, it is grown on the reflective buffer layer 415 using MOCVD. The stress is stretched so that the compression and tensile strength can be balanced. As a result, cracking at the time of forming the lower III-V compound layer 420 can be remarkably prevented. A quantum well layer 43 0 is formed next in the lower Πΐ-ν compound layer 420 (step 840 of Figure 5E). Quantum well layer 430 can comprise a substantially uniform layer of 0 InN, GaN, InGaN, AlGaN, InAIN, or AlInGaN. Quantum well layer 430 may also include a multilayer structure defining one or more quantum wells. The quantum well can be formed, for example, by sandwiching an InGaN, AlGaN, InAIN, or InGaAIN layer between two GaN or AlGaN layers. The quantum well layer 43 0 can comprise a stack of such hierarchical structures, each defining a quantum well. Upper III-V compound layer 440 is formed on quantum well layer 430 (step 850 of Figure 5F). The lower III-V compound layer 42 0 is φ η-type doped and the upper III-V compound layer 440 is p-type doped, and the lower III-V compound layer 420 may be ρ-type doped and The upper III-V compound layer 440 may be η-type doped (as shown in the flow chart of FIG. 9). A transparent conductive layer 450 can then be selectively formed on the upper III-V compound layer 440 (step 860 of Figure 5G). The formation of the quantum well layer can include multiple MOCVD steps. Each of the steps of the multi-step may comprise depositing a layer of 50 angstroms thick. The quantum well layer 430, the upper III-V compound layer 44 0, and the conductive layer 450 may also be formed by MOCVD. The lower III-V compound layer 420, the quantum well-22-201006007 layer 430, the upper III-V compound layer 440, the MOCVD formation and the ALD formation of the reflective buffer layer 415 can also be formed in the same ALD/CVD chamber system, Minimize the number of times the substrate moves into and out of the vacuum chamber. The process yield can be further improved. The noise during processing can also be reduced. The quantum well layer 430, the upper III-V compound layer 440, and the conductive layer 450 may be patterned by photoresist coating and photolithography. The quantum well layer 43 0, the upper III-V compound layer 440, and a portion 0 of the conductive layer 450 may be removed by wet etching to expose a portion of the upper portion of the lower III-V compound layer 420 ( Step 870) of Figure 5H. Upper electrode 4 60 is then formed on conductive layer 450 (step 880 of Figure 5H). The upper electrode 460 may comprise a Ni/Au bilayer having a thickness of 12 nm and 100 nm, respectively. Fabrication of conductive layer 450 may involve coating the photoresist layer on the exposed upper surface of 4501 and lower III-V compound layer 420. The photoresist layer is then patterned using photolithography and selectively removed to form a mask. The electrode material is subsequently deposited in the opening of the mask. The electrode material and photoresist layer that are not desired are subsequently removed. The lower electrode 470 is subsequently formed on the lower III-V compound layer 420 (Fig. 5H). The lower electrode 470 may contain an AuSb/Au bilayer. The AuSu layer has a thickness of 18 nm, and the Au layer has a thickness of 100 nm. The formation of the lower electrode 470 can also be accomplished by forming a photoresist mask having an opening on the lower ΠΙ-V compound layer 420, depositing an electrode material, and then removing the unwanted electrode material and photoresist layer. Finally, a light-emitting device 400 is formed or, with reference to FIG. 51, a protective layer 48 0 can be introduced on the light-emitting device -23-201006007 400 to protect it from moisture, oxygen, and other harmful substances in the environment. . The protective layer 480 may be formed of a dielectric material such as hafnium oxide, tantalum nitride or epoxy. The protective layer can be patterned to expose the upper electrode 460 and the lower electrode 470 to allow them to receive an external voltage. In some embodiments, the protective layer can comprise a thermally conductive material, such as A1 and Cu, to provide adequate cooling of the illumination device 400. It should be noted that the lower III-V compound layer and the upper III-V compound φ layer may have different doping configurations as long as their doping contents are opposite to each other. The lower III-V compound layer may be P-type doped and the upper III-V compound layer may be η-type doped. Alternatively, the lower III-V compound layer may be η-type doped and the upper III-V compound layer may be ρ-type doped. Figure 7 is a perspective view of another illumination device 700 in accordance with the present invention. Unlike a square opening in the mask layer (Fig. 5A and below step 800), a rectangular opening is formed in the mask layer 410 to create a long trench after etching. The rectangular opening is sometimes preferably a long aspect ratio of the trench opening. For example, 部份 some illuminators require a long illuminating surface. For ruthenium-based substrates, the top surface can be parallel to (1 〇〇) crystal faces. Similar to the foregoing description, the inclined trench surface is parallel to the (111) crystal plane. The long inclined trench can be at least 50% larger than the area of the inclined first ditch, at the end of the long ditch. The disclosed illumination device and process can include one or more of the following advantages. The disclosed illuminating device and process can overcome the lattice mismatch between the lower III-V compound layer and the substrate and prevent cracking of the associated layer in conventional illuminators. The disclosed light-emitting device and process can prevent cracking of the p-doped-24-201006007 impurity or η-doped III-V compound layer due to different thermal expansion between the p-doped III-V compound layer and the substrate. Or peel off. An advantage associated with the disclosed illumination device is that the illumination device can significantly increase luminous efficiency by increasing the density of the illumination device and by additional illumination from the bevel or vertical plane in the trench. The luminescent layer in the disclosed illuminating device can be formed in other types of structures than the above-described trenches. Referring to Figures 9A through 10C, for example, a light-emitting device 900 is formed on a substrate 905 having an upper surface 907. The light emitting device 900 includes a protrusion 910 above the upper surface 907. The projection 910 has one or more projections 913 (Figs. 10A-10C) and has a slope relative to the upper surface 907. The projection 910 can also have a top surface 919 that is substantially parallel to the upper surface 907. The area of the top surface 919 can be kept less than 20% of one of the convex surfaces 913. The projection 910 may also have the shape of a cone or frustum above the upper surface 907. The substrate 905 can be predominantly ruthenium: the upper surface 907 can be parallel to the (100) crystal plane. The convex surface 913 may be parallel to the (1 1 1 ) crystal plane. The upper surface 907 may be parallel to the (111) crystal plane. The convex surface 913 may be parallel to the (1 〇〇) crystal plane. The substrate 905 may also include a plurality of layers of insulating layer overlying (SOI) structures. A rim 917 is formed at the boundary of the two adjacent convex surfaces 913. Substrate 905 can have a rectangular or square shape with outer edge 908. The light emitting device 900 can be fabricated on a semiconductor wafer together with other light emitting devices and sliced to form separate crystal grains. Light emitting device 900 can have a rectangular or square grain shape defined by a flat region parallel to the face of upper surface 907. The illuminating device 900 includes: a reflective buffer layer 915 on the upper surface 9〇7-25-201006007 and the convex surface 913; a lower III-V compound layer 920 on a reflective buffer layer 915; one or more quantum well layers 93 0 is on the lower ΙΙΙ ν compound layer 920; and an upper III-V compound layer 940. A portion of the upper III-V compound layer 940 on the convex surface 913 is oriented at an angle with respect to the upper surface 907 of the substrate 905. The light emitting device 900 also includes a lower electrode 970 on the lower III-V compound layer 920 and an upper electrode 960 on the upper III-V compound layer 940. φ In some embodiments, as shown in Figures 11A and 11B, a semiconductor wafer 1000 comprising a 2x2 array of light emitting structures 1000A-1000D is formed on a substrate 905. Each of the light emitting structures 1000A-1000D may have a structure similar to the above-described light emitting device 900. The light emitting structures 1000A-1000D can be formed in a 2x2 array on a semiconductor wafer. The light emitting structures 1000A-100D can be used as a single light emitting device, or they can be separated by cutting and slicing to form an individual light emitting device similar to the light emitting device 200. In another embodiment, as shown in Fig. 11C, the semiconductor wafer 1 1 〇〇 may comprise a light-emitting structure 110 of an array of χ 4χ4. As described above, the substrate 905 can be predominantly ruthenium. The upper surface 907 can be parallel to the (1 inch) crystal plane. The convex surface 913 may be parallel to the (111) crystal plane. (100) The width "D1" of the upper surface 207 (Fig. 1 Β ) can be maintained, for example, below 1 〇〇〇 micrometer, which is much lower than the width of the wafer substrate from which the conventional LED light-emitting device is fabricated. By keeping this size small, stresses and lattice mismatches with respect to different thermal expansions can be significantly reduced. The illuminating device shown in Figures 9A-1 1C can produce a different angular distribution than conventional LED devices. Referring to Fig. 12, a light-emitting device 900 includes a convex portion 910 formed on a base -26-201006007 material 905. The light-emitting layer having the light-emitting surfaces 1270A and 1270B is formed on the slope of the convex portion 910. For the substrate mainly composed of ruthenium, the upper surface 907 may be parallel to the (1 1 1 ) crystal plane along the (1 〇〇) crystal plane and the slope-emitting surface 1270A, 1270B. With respect to the upper surface 907, the light-emitting surfaces 1 270 and 1 2708 have an angle of 54.7. For the same footprint on top, the sum of the illumination areas on the illuminated faces 1 270A, 1270B is approximately 1.73 times the area of the conventional LED device 600 (Fig. 6A). The disclosed luminescent device is compatible with the relative orientation of other substrate materials and obliquely convex faces. The oblique projections may be at an angle between 20 and 80 degrees, or, more specifically, between 50 and 60 degrees with respect to the upper surface of the substrate. The illuminating surface on the convex portion of the disclosed illuminating device may be more than one time, or 1.2, or 1.4 or 1.6 times the base area of the convex portion. The large illuminating area in the illuminating device allows the disclosed illuminating device to produce a higher luminous intensity than conventional LED devices. The light from the light-emitting surfaces 1270A, 1270B can be assumed to have a broad distribution 1 280 as shown in FIG. Embodiments may include one or more of the following advantages. The disclosed illuminating devices and associated processes can provide higher throughput illuminators and, therefore, have lower manufacturing costs than conventional illuminators. The disclosed illumination device and associated process can provide a more dense illumination device and can, for example, comprise a light-emitting element, a driver, a power supply, and a light modulation unit integrated on a single-half conductor substrate. The foregoing description and drawings are to be regarded as illustrative The invention can be constructed in a variety of shapes and sizes and is not limited to the dimensions of the preferred embodiment. Various applications of the present invention will be apparent to those skilled in the art -27-201006007. Therefore, the present invention is not limited to the examples and specific structures and operations described. On the contrary, all appropriate modifications and equivalents may fall within the scope of the invention. For example, the η-doped and p-doped III-V compound layers may be exchanged in position, ie, the yttrium-doped yttrium-V compound layer may be under the quantum well layer, and the η-doped III- The group V compound layer can be on the quantum well layer. The illustrated illumination device can be adapted to emit light in green, blue, and other colors. ❹ It should be understood that the disclosed systems and methods are suitable for a wide range of applications, such as laser diodes, blue/uv LEDs, Hall effect sensors, switches, UV detectors, microelectromechanical systems (MEMS). ), and in RF power transistors. The disclosed device can include elements of various other applications. For example, a laser diode according to the apparatus of the present invention may comprise a reflective surface or a mirror surface for generating laser light. For illuminating applications, the system of the present invention can include other reflectors and diffusers. It should be understood that the illumination device disclosed in the present disclosure is not limited to the above-described ditches and protrusions. The substrate can include a first side having a first orientation and a second side having a second orientation. The first and second faces may or may not form a ditch or a projection. A majority of the III-V compound layer can be formed on the substrate. When a current is generated from the III-V compound layer, the III-V compound layer can emit light. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a conventional LED structure; FIG. 2A is a perspective view of a light-emitting device according to an embodiment of the present invention; -28- 201006007 FIG. 2B is a front corner portion of the light-emitting device of FIG. 2A Figure 3A is a cross-sectional view of the light-emitting device along line AA of Figure 2A; Figure 3B is a detailed cross-sectional view of one side of the light-emitting device of Figure 3A; Figure 3C is Figure 3A A detailed sectional view of the bottom of the light-emitting device; FIG. 3D is a cross-sectional view of the light-emitting structure of the line B_B in FIG. 2A; φ FIGS. 3E and 3F are examples of the layer structure and material composition for the light-emitting structure; FIG. A perspective view of a 2x2 array of light-emitting structures fabricated on a substrate in accordance with the present invention; FIG. 4B is a partial cross-sectional view of the light emitting structure along line BB of FIG. 4A; FIG. 4C is a fabrication of a substrate in accordance with the present invention. A perspective view of a 4x4 array of light emitting structures; #FIG. 5A is a cross-sectional view of a substrate having a pattern mask for forming the light emitting device of FIG. 4B; FIG. 5B1 is after etching the mask shown in FIG. 5A, Figure 5A is a perspective view of the light-emitting device; Figures 5B2 and 5C-5I are for forming Figure 4B FIG. 6A is a schematic diagram showing an example of a light-emitting angle distribution of a conventional LED light-emitting device, and FIG. 6A is an angle of light emitted by the light-emitting device shown in FIG. 2A. -29-201006007 Figure 7 is a perspective view of another light-emitting device according to the present invention; Figure 8 is a flow chart of a process for the light-emitting device of Figure 2 to Figure 7; Figure 9A is another embodiment of the present invention; Fig. 9B is a detailed perspective view of the front corner portion of the light emitting device of Fig. 9A. Fig. 10A is a cross-sectional view of the light emitting device taken along line AA of Fig. 9A.
I 圖10B爲在圖10A之發光裝置的側部份的詳細剖面圖 圖10C爲在圖10A之發光裝置的上部份的詳細剖面圖 » 圖11A爲依據本發明之製造於基材上之2x2陣列發光 Ο 結構的透視圖； 圖1 1 B爲沿著圖1 1 A的線B - B的發光結構的部份剖 面圖； 圖11C爲依據本發明之製造在基材上的4x4陣列的發 光結構的透視圖；及 圖12爲示於圖9A之發光裝置所發射的光的角度分佈 示意圖。 【主要元件符號說明】 -30- 201006007 100 ： LED 結構 1 05 :基材~ 1 1 〇 :緩衝層 120: p-摻雜III-V族化合物層 130 · InGaN量子井層 140 :主動III-V族化合物層 150: η-摻雜III-V族化合物層 1 6 0 : Ρ 電極 1 7 0 : Ν電極 200 :發光裝置 20 5 :基材 2 0 8 :外緣 217 :內緣 240 :上III-V族化合物層 240Α:斜上III-V族化合物層 φ 260 :上電極 2 7 0 :下電極 220 :下III-V族化合物層 2 1 0 :溝渠 2 1 3 :溝渠面 2 3 0 :量子井層 2 1 5 :反射緩衝層 207 :上面 2 1 9 :底面 -31 - 201006007 400 :半導體晶圓 400A-D : #光結構 405 :基材 405A :上面 4 1 0 :溝渠 410A, B :面 4 1 5 :反射緩衝層 _ 4 3 0 :量子井層 700 :發光裝置 440:鋁摻雜p-GaN層 4 6 0:上電極 470 :下電極 420:下III-V族化合物層 5 00 :半導體晶圓 5 1 0 :發光結構 . 40 1 :遮罩層 402 :開口 405A :上面 450 :導電層 480 :保護層 600 :發光裝置 605 :基材 6 1 0 :平坦發光面 650 :發光裝置 -32- 201006007 65 5 :基材 670A，B :斜發光面 900 :發光裝置 905 :基材 9 0 8 :外緣 910 :凸部 9 1 5 :反射緩衝層 參 917 :緣 920 :下III-V族化合物層 913 :凸部面 907 :上面 940 :上III-V族化合物層 9 6 0:上電極 970 :下電極 9 3 0 :量子井層 Φ 9 1 9 :頂面 1000·半導體晶圓 100A-D :發光結構 1 1 10 :發光結構 1270A, B :斜發光面 1 2 8 0 :寬分佈 6 2 0 :角發射分佈 670A，B :斜發光面 680:發光角分佈 -33-Figure 10B is a detailed cross-sectional view of the side portion of the light-emitting device of Figure 10A. Figure 10C is a detailed cross-sectional view of the upper portion of the light-emitting device of Figure 10A. Figure 11A is a 2x2 fabricated on a substrate in accordance with the present invention. Figure 1 1B is a partial cross-sectional view of the light-emitting structure along line B-B of Figure 11A; Figure 11C is a 4x4 array of light-emitting fabricated on a substrate in accordance with the present invention; A perspective view of the structure; and Figure 12 is a schematic illustration of the angular distribution of light emitted by the illumination device of Figure 9A. [Main component symbol description] -30- 201006007 100 : LED structure 1 05 : Substrate ~ 1 1 〇: Buffer layer 120: p-doped III-V compound layer 130 · InGaN quantum well layer 140: Active III-V Group compound layer 150: η-doped III-V compound layer 1 60 0 : Ρ electrode 1 7 0 : Ν electrode 200 : illuminating device 20 5 : substrate 2 0 8 : outer edge 217 : inner edge 240 : upper III -V group compound layer 240Α: obliquely III-V compound layer φ 260 : upper electrode 2 7 0 : lower electrode 220 : lower III-V compound layer 2 1 0 : trench 2 1 3 : trench surface 2 3 0 : Quantum well layer 2 15 5: reflection buffer layer 207: upper surface 2 1 9 : bottom surface - 31 - 201006007 400 : semiconductor wafer 400A-D : #光结构405 : substrate 405A : upper 4 1 0 : trench 410A, B : Face 4 1 5 : Reflection buffer layer _ 4 3 0 : Quantum well layer 700: Light-emitting device 440: Aluminum-doped p-GaN layer 4 6 0: Upper electrode 470: Lower electrode 420: Lower III-V compound layer 5 00 : semiconductor wafer 5 10 : light-emitting structure. 40 1 : mask layer 402 : opening 405A : upper surface 450 : conductive layer 480 : protective layer 600 : light-emitting device 605 : substrate 6 1 0 : flat light-emitting surface 650 : light-emitting device -32- 201006007 65 5 : Substrate 670A, B: oblique light-emitting surface 900: light-emitting device 905: substrate 9 0 8 : outer edge 910: convex portion 9 1 5 : reflective buffer layer 917: edge 920: lower III-V compound layer 913: Convex surface 907: Upper surface 940: Upper III-V compound layer 9 6 0: Upper electrode 970: Lower electrode 9 3 0 : Quantum well layer Φ 9 1 9 : Top surface 1000· Semiconductor wafer 100A-D: Light-emitting structure 1 1 10 : Light-emitting structure 1270A, B: oblique light-emitting surface 1 2 8 0 : wide distribution 6 2 0 : angular emission distribution 670A, B: oblique light-emitting surface 680: light-emitting angle distribution -33-