TW201005633A - Recovery apparatus for solving branch mis-prediction and method and central processing unit thereof - Google Patents

Abstract

According to the exemplary examples of the present invention, a recovery apparatus for solving branch mis-prediction and method and central processing unit thereof are provided. The recovery apparatus includes an instruction buffer, at least one circulation instruction buffer, and a decoding and pairing circuit, wherein the decoding and pairing circuit is coupled to the instruction buffer and the circulation instruction buffer. The instruction buffer stores a plurality of instructions, and the circulation instruction stores a recovery instruction queue corresponding to the instructions, wherein the recovery instruction queue includes a plurality of recovery instructions. The decoding and pairing circuit both decodes and pairs the instructions and the recovery instructions. The decoding and pairing circuit outputs the recovery instructions to an instruction execution processing circuit which is externally connected to the decoding and pairing circuit when the branch mis-prediction occurs.

Description

201005633 A wv 〇1-TW 28199twf. doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a branch prediction of a central processing unit (CPU) Apparatus, and particularly related to a reply apparatus for solving Branch Mis-Prediction and its method and its central processing unit. ^ [Prior Art] With the advancement of semiconductor technology, computers have become a necessity for everyday life, and people can use computer design programs to handle many transactions. The most important core in the computer is the central processing unit. Currently, the central processor on the market will have branch prediction devices to process branch instructions. In general, about four to five instructions in a program will have a branch instruction, so using a central processor with a branch prediction device will perform better. However, when the central processor processes the branch instruction, the branch prediction device cannot accurately predict the next instruction that should be executed at a time. Therefore, the branch prediction device may generate a branch prediction error and cause a loss of performance of the central processing unit, which is commonly known as Branch Penalty. In order to solve this problem, many research institutes and CPU manufacturers will try to reduce the probability of branch prediction errors in order to improve the performance of the central processor. Therefore, many prediction algorithms (Predicti〇n • Algorithm) and branch prediction architectures are widely proposed. • However, the algorithms or hardware architecture of these softwares are only reduced by 201005633.

.Ol-TW 28199twf.doc/n The probability of predicting errors. For the conditional branch in the program or the final loop of the loop operation (Finai Loop), there is a case of branch prediction error. Therefore, in order to solve the problem of branch prediction error, the researchers proposed a multi-path execution. The Multi-Path Execution CPU Architecture overcomes the above problems. However, the multi-path execution CPU can only handle one branch prediction error, so the multi-path execution CPU needs a Confidence Estimator to help the central processor fetch multiple simultaneously. The instruction of the path. In addition, the multi-path execution of the central processor will execute the instructions of the two paths at the same time, so the CPU of the multi-way execution needs a register renaming mechanism to handle the data correlation ( Data Dependency) Issue with Register Commitment. At present, the multi-path execution of the central processor is too high in complexity, most of which is only in the theoretical stage and research, and rarely implemented on hardware. In addition, in the related papers and research, the central processor of multi-path execution only increases the performance by about 10%. In addition to the way the multiprocessor execution of the multiprocessor executes multipath execution, another way is to use the multi-threading CPU to let the compiler (c〇mplier) utilize two lines ^ (Threads) To handle multipath execution. However, in a super-scalar CPU (Superscalar CPU) with a deep pipeline, the method or architecture of multi-path execution cannot be implemented as a circuit because of the high complexity of the 2010-0633_28199twf.doc/n. In addition, because of the instructions to execute multiple paths, the above architecture and methods require reliable estimators, or require the efforts of the compiler to achieve performance improvements. SUMMARY OF THE INVENTION The present invention provides a recovery apparatus and method thereof for solving a final branch (Final L〇op) branch prediction error 条件 of a conditional branch or a loop operation, and a central processing unit thereof, This reply device can effectively reduce the performance loss caused by branch prediction errors. In addition, due to the low complexity of the inventive recovery device and method, it can be applied to a deep-Pipeline ultra-pure central processor. An example of the present invention provides a reply device for resolving a branch prediction error, the reply device comprising an instruction buffer, at least one loop buffer and a decoding pairing circuit. The decoding pairing circuit is coupled to the instruction buffer and the ring instruction buffer. The instruction buffer is used to store a plurality of instructions, and the circular instruction buffer is used to store a recovery complex command column corresponding to the plurality of instructions. The reply instruction column includes a plurality of reply instructions. The decoding pairing circuit decodes and pairs with the plurality of instructions and the reply command. When the branch prediction error occurs, the decoding pairing circuit outputs the reply commands to the instruction execution processing circuit connected thereto. According to an embodiment of the present invention, the recovery device further includes a branch indicator buffer, a cache controller, and an instruction cache memory circuit. Wherein the branch indicator buffer is coupled to the cache controller, the cache controller is coupled to the finger cache memory circuit, and the instruction cache memory is coupled to the ring type command buffer 201005633 ------ --i) l-TW 28199twf.doc/n Punch and instruction buffer. The branch indicator buffer is used to detect whether a branch prediction occurs, and when the branch prediction occurs, the indicator program count is sent to the cache controller. The cache controller captures a plurality of instructions and reply commands stored by the cache controller according to the index program control instruction cache. The instruction cache memory circuit is used to store multiple instructions and reply instructions.

An example of the present invention provides a reply method for solving a branch prediction error, the method comprising the steps of: (a) receiving a plurality of instructions to an instruction buffer memory, and receiving a plurality of reply instructions corresponding to the plurality of instructions to At least one circle of instruction buffer memory; (b) encoding and pairing the plurality of instructions and the reply instruction; (C) outputting the plurality of reply instructions to the instruction execution processing circuit when a branch prediction error occurs. According to an embodiment of the present invention, the above reply method further includes the following steps: (d) setting the branch prediction error bit of the plurality of reply instructions to 丨, = recording the branch program count of the plurality of reply instructions. According to an example of the present invention, the above reply method further includes the following

(e) If no branch prediction error occurs, the plurality of instructions are output and the processing circuit is executed. 9 V According to an embodiment of the present invention, the number of reply commands that can be stored by the above-described ring-shaped command is equal to the number of instructions of the instruction execution device. An example of the present invention provides a central device having a reply device including an instruction buffer, at least one loop-type protector, a decode pairing circuit, and an instruction execution processing circuit. The processing circuit is coupled to the decoding pairing circuit, and the processing circuit is coupled to the decoding pairing circuit. The instruction buffer is used to store a plurality of instructions 'a circular instruction buffer for storing a reply instruction column corresponding to the plurality of instructions'. The reply instruction column includes a plurality of reply instructions. Decoding the pairing circuit for decoding and pairing the plurality of instructions and the reply instruction. When the branch prediction error occurs, the decoding pairing circuit outputs the plurality of reply fingers; and the instruction execution processing circuit, the instruction execution processing circuit is configured to perform the Reply instructions and instructions. According to an embodiment of the present invention, the central processing unit further includes a branch indicator buffer, a cache controller, and an instruction cache memory circuit. The indicator buffer is connected to the cache controller, and the cache controller is used to make the memory circuit. The instruction cache is coupled to the ring instruction buffer and the instruction buffer. The branch indicator buffer is used to detect whether a branch prediction occurs, and when the branch prediction occurs, the indicator program count is sent to the cache controller. The cache controller retrieves a plurality of instructions and reply commands stored by the cache according to the index program control instruction cache. Instruction cache The S-memory circuit is used to store multiple instructions and reply instructions. In summary, the reply device and method thereof provided by the example of the present invention and its central processor are to reduce the loss caused by branch prediction errors. The recovery device provided by the example of the present invention only needs to add at least one ring-shaped instruction buffer and several logic gates in the original decoding pairing circuit to the original central processor architecture, so the complexity is low and easy to implement. On the circuit. In addition, it is assumed that in the pipeline architecture in which the cache hit ratio and the branch index buffer hit rate are 95% #12., the central portion of the reply device is compared with the central processor without the instruction buffer. The performance of the treatment can be increased by about 9 to 10% by 9 OI-TW 28199twf.doc/n 201005633. The above described features and advantages of the present invention will be more apparent from the following description. [Embodiment]

An example of the present invention provides a replying apparatus, method and central processing unit for solving branch prediction errors, which are used to reduce the performance loss caused by branching prediction errors. As mentioned above, there are about one branch instruction in about 4 to 5 instructions in a program, and it is inevitable that there will be a branch prediction error in the conditional branch or the final loop. Therefore, the reply device provided by the example of the present invention can make the instruction execution processing circuit of the back end continue to execute the corresponding recovery age when the branch prediction error occurs, thereby reducing the loss of the overall performance. Referring to Figure 1, Figure 1 provides a central processor 1 in accordance with an example of the present invention. The central processing unit 100 includes a reply device 10 for branch prediction error, an instruction execution processing circuit 20, an instruction cache circuit 3, a f control 11 4G, and a branch indicator buffer It (Brand! Target Buffer·, simply, BTB) 50. The branch indicator buffer is connected to the cache controller 40, the cache controller 4〇 is connected to the instruction cache memory circuit %, and the reply device 10 is coupled to the instruction execution processing circuit 2 and the instruction cache. Between the memory 30. It should be noted that the instruction execution processing circuit 20 may be an ultra-pure amount of execution processing circuit with a deep pipeline, however, the instruction 201005633

01-TW 28199 twf.doc/n The type of processing circuitry 20 is not intended to limit the invention. Additionally, the instruction cache memory circuit 30, the cache controller 40, and the branch indicator buffer 5 are separated from the reply device 1 in this example, however, this example is not intended to limit the invention. In other words, another embodiment is to design the instruction cache memory circuit 30, the cache controller 40 or the branch indicator buffer 50 in the reply device 10. When the branch indicator buffer 50 detects that a branch instruction occurs, and

When the branch instruction hits the branch indicator buffer 50, the branch indicator buffer 50 sends the target program count (Target Pr〇gram c〇unter, referred to as Target PC) to the cache controller 4〇. The cache controller fetches the instruction fetch memory 30 based on the index program count command to fetch the plurality of instructions stored in the cache memory 30 and sends the instructions to the reply device 1 .

The reply device 10 temporarily stores the instructions fetched from the instruction cache 3 to its buffer, wherein the instructions may include multiple branch predictions = knife instructions, multiple general instructions, and multiple prediction errors. Reply instructions. + Next, the reply device 10 performs the action of composing the mother and the paking at the same time as the branch instruction and the reply command predicted by the branch, or the operation of encoding and pairing only the general command. When the branch error has not occurred, the replying device 10 sends a plurality of general instructions or branch pre-branch instructions to the instruction execution circuit 2G of the back end. However, if the branch prediction error occurs, the acknowledgment device sends a plurality of reply commands to the instruction execution circuit 20 of the back end to continue execution. When the branching error occurs, the instruction execution processing circuit 2 clears all instructions in the /, s line. However, the scale, shouting device (7) will send 11 waw -^yj.TW 28199twf.doc/n multiple reply commands to the instruction execution processing circuit 20 to continue execution, so the reply device 10 can use this period of time to retrieve and temporarily Multiple instructions to be executed after saving. Thus, it is possible to effectively reduce the performance loss caused by the pipeline of the instruction execution processing circuit 20 and the suspension of the recovery device 10 when the branch prediction error is effectively reduced. < Next, the structure and implementation of the recovery device 1A will be further described. As shown in Fig. 1, the reply device 10 includes at least one or more Circulation Instruction Queues 60-62, an instruction buffer 63, and a decode pairing circuit 64. The ring-shaped instruction buffers 60-62 are coupled between the decoding pairing circuit 64 and the instruction cache circuit 3A, and the decoding pairing circuit 64 is coupled to the instruction execution processing circuit 2, the instruction buffer 63. Then, it is coupled between the decoding pairing circuit 64 and the instruction cache circuit. In the pipelined central processing unit, the decoding pairing circuit 64 can be integrated in the decoding stage of the pipeline front stage (Dec〇de Stage), and the instruction execution processing circuit 20 can include the stage of the back stage of the pipeline, such as the execution of the Lu 9 command. Stage (Execution Stage). It should be noted that although the number of the ring-shaped command buffers 60 62 of the present example is three, it is not intended to limit the present invention. In other words, the design of the number of the instruction buffers 6〇~62 can be designed according to the user. In this example, it is assumed that the instruction buffer 63 can store one instruction and the average of every four instructions has one branch instruction. Therefore, the number of the circular instruction buffers 6〇~62 is set to (12/ 4=3). • In other words, the general design principle of the number of circular instruction buffers 60 to 62, where X represents the instruction that the instruction buffer 63 can store 12 201005633 -------- Jl-TW 28199twf .doc/n means that there is one branch instruction per n instructions, "calling - taking the smallest integer greater than x/w. · In addition, in this model, the ring type instruction buffers 60~62 ^ The number of reply commands that can be stored is 6. However, this number is not intended to limit the present invention. In other words, the number of reply commands that can be stored by the number of the instruction buffers 6 "62 can be based on the user's Need to design. In this example, it is assumed that the instruction execution processing circuit 2 〇t can handle six instructions at the same time. Therefore, the number of the ring-shaped instruction buffers 6 〇 to 62 is set = the number of responsive commands that can be stored is six. Briefly, the number of reply instructions that can be stored by the number of ring buffers 60 to 62 is generally set to the maximum number of instructions that the back end instruction execution processing circuit can process. Take control 11 according to the indicator program count (four) command cache memory 〇 娜 ( (Feteh) 取 取 取 3 3 (), a number of instructions, a number of general instructions and branch instructions will be sent to the instruction buffer The magic storage 鬌 雏 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 62 The slave memory circuit 3G is sent to the ring type instruction buffers 6() to 62, respectively, wherein the reply command line includes a plurality of reply instructions. In addition, the instruction fetching circuit 64 of the $ terminal is a super-scaling instruction of the _line '$row circuit'. This example uses three ring-shaped instruction buffers 60-62 to temporarily store the reply command. Therefore, the central processing unit 100 using the return device 10 can effectively reduce the branch loss when a branch prediction error occurs. 201005633^28199twf.doc/n Then when the branch instruction enters the decoding pairing circuit 64, its corresponding reply command also enters the decoding pairing circuit 64 at the same time. At this time, the decoding matching circuit 64 simultaneously decodes and pairs the branch instruction and the reply instruction. Next, the decoding pairing circuit 64 sets the Mis-Prediction Valid Bit of the branch instruction to 1, and simultaneously records the Branch pr〇gram Counter inherited by the branch. In the case where there is a branch prediction error again, the decoding pairing circuit 64 outputs the branch instruction to the back end instruction execution processing circuit 2A. In addition, if the general instruction is not the branch instruction entering the decoding pairing circuit 64, then the decoding pairing circuit 64 only receives the general instruction, and after decoding and pairing the general instruction, the general instruction is sent to the back instruction execution. Processing circuit 2〇. When a branch prediction error occurs, the instruction of the entire instruction execution processing circuit 2 and the instruction buffer 63 are cleared. At this time, the decoding pairing circuit 64 sends a plurality of reply instructions corresponding to the branch instruction of the branch prediction error to the instruction execution processing circuit 20, thereby causing the instruction execution processing circuit 2 to execute these reply instructions. At this time, since there is a reply instruction existing pipeline of the instruction execution processing circuit 20, and is subsequently executed, the instruction buffer 63 can use this period of time to retrieve a new instruction, thereby reducing the branch prediction error and requiring a pause ( The Stall) instruction performs a performance penalty caused by the pipeline of the processing circuit 2 and the drag-and-drop pairing circuit 64. In addition, since the above-mentioned instruction cache memory circuit 3 needs to intercept a plurality of instructions to the instruction buffer 63 and the ring type instruction buffers 60 to 62 at the same time, the instruction cache memory circuit 3 can be executed. Designed with the architecture of the Skew Cache. At this time, in each time interval 201005633 Λ . «01-TW 28199 twf.doc/n, the instruction cache memory circuit 30 can be read out 8 characters at the same time. For the conditional branch or the final loop, the branch prediction mechanism predicts that branching will occur but there is actually no such situation. Therefore, under the architecture of the instruction cache memory circuit 30 with side-to-side cache, the instruction is not fast. There is additional consumption of the bandwidth of the memory circuit 30. Of course, the above-described instruction cache memory circuit 30 with side-to-side cache architecture is not intended to limit the present invention.

Ming's use of this design is only to avoid additional consumption of the bandwidth of the instruction cache memory circuit. Continuing to refer to Fig. 1' here, the instruction stored in the instruction buffer 63 in Fig. 配合 is matched with the above-mentioned instructions. It is assumed that a branch prediction error occurs in the final loop or conditional branch. As shown in FIG. ,, the instruction buffer 63 胄 12 instructions, which are η_8, η_4, η (branch instruction), m_e, ιη·8, m_4, m (branch instruction), te, t 8, respectively. t 4, t (branch instruction), s, s+4. The ring type instruction buffer 62 stores six reply command columns corresponding to the first branch instruction η, and the first reply command is the verb 4 ', which is the command η. On the other hand, the instruction ^ may be the branch target predictor 5G for the branch target _-Target predicted by the branch instruction n; that is, the branch indicator prediction mechanism predicts the instruction η after t jumps to the instruction (4) due to the branch. Similarly, the prototype instruction buffer 6i stores six reply instruction columns corresponding to the second branch instruction m, and the first reply instruction is (4). The circular command buffer H 60 stores six response commands corresponding to the third branch instruction t for the third finger, and the first reply command is the trait 4, that is, the command (10) times the command. . The instruction s is the branch prediction mechanism for the branch instruction t prediction branch 15 201005633 χ , VJ1-T"W 28199twf.doc/n target here assumes that the branch prediction error is the occurrence of the order t, then when the instructions n-8, n_4 Insufficient s in the brother of a knives pre-remaining means that the circuit 64 is only for the command n_8, the element 4 pairing circuit 64, decommissioning 芸 ti, mu change knee ifc person n_ to do decoding and pairing action, then Straight ^n_8, n(10) = 2〇. Then, the first, the instruction η enters the human lion H = ❹

At the same time, the loop-like instruction is received as a complex solution because there is no branch prediction error. The circuit 64 then aligns the instruction n, m r with the fresh horse pairing circuit 20. _C, m_8, m-4 are sent to the instruction execution process. Then, when the first branch instruction n enters the decode pairing circuit 64, the response of the received ring type instruction buffer 61 is decoded when the pairing circuit 64 (4) is decoded, so that m+4' There are no branch prediction errors, so the decode pairing circuit 64 then sends the instructions m, t_e, t_8, Μ to the instruction execution circuit 20. When the second branch instruction t enters the decoding pairing circuit 64, the decoding pairing circuit 64 also receives the ring type instruction buffer. 61 _ complex instruction t+4 'Assume that the instruction t will branch to the next instruction meter 4 instead of the branch prediction. The instruction s, at this time, because the branch prediction error occurs, the decoding pairing circuit 64 decodes and pairs the plurality of reply instructions of the instruction buffer 61 and sends the reply instructions to the instruction execution processing circuit 20 In order to reduce the branch prediction error, it is necessary to stall the instruction to execute the pipeline of the processing circuit 20 and to drag the performance loss caused by the decoding pairing circuit 64. This kind of situation often occurs in the rewinding program loop. For example, a certain 201005633 a...VJ1-TW 28199twf.doc/n loop needs to be returned from the instruction t to the instruction S several times before the loop can be ended to the next one. Command t+4. When the loop returns repeatedly, the branch prediction mechanism learns that "finger ♦ will t jump to instruction S" as the benchmark for branch prediction; however, when the callback ends, the instruction ί continues to the next instruction. At +4, an error occurs in the I prediction, causing a hindrance (Hazard) when the processor executes. The invention can efficiently respond to such branch prediction errors. Finally, please refer to FIG. 2. FIG. 2 is a flow chart of a method for recovering a branch prediction error according to an example of the present invention. This method ^ is applied to a central processing unit, and in particular to a super-quantity central processing unit with deep pipelines. First, a plurality of instructions are received to the instruction buffer memory in step S80', and a plurality of responses corresponding to the plurality of instructions are received to at least one of the instruction buffer memories. Next, in step sgi, the plurality of instructions and the reply command are encoded and paired, the knife prediction error bits of the reply fingers are set to 1, and the back fingers are recorded in the eight-dip program count. Finally, in step S82, when the branch prediction error H, the plurality of reply instructions are output to the instruction execution processing circuit; if no branch prediction ® error occurs, the plurality of instructions are output to the instruction execution processing circuit. In summary, the reply device and method thereof provided by the examples of the present invention and its central processor are to reduce the loss caused by branch prediction errors. And the above reply device only needs to add at least the original central processor architecture. A looped instruction buffer is paired with several logic gates in the original decoding pair, so its complexity is low and easy to implement on the circuit. Also, assume the same hit rate in the cache hit rate and branch indicator buffer In a 95% 12-stage pipeline architecture, compared to a central processor without an instruction buffer, 17 201005633 ...-J1-TW 28199twf.doc/n has the central processing performance of this reply device The effect of the iU/e can be increased. The present invention has been implemented as described above, but it is not intended to be used in the spirit and scope of the present invention. A few changes and refinements ^The protection system of the invention is defined as the ribs of the invention. The definition of the patent system is ❹ [Simplified illustration of the drawing] FIG. 1 is a schematic diagram of a central processing unit 10 according to an example of the present invention. A flowchart of a reply method for solving a branch prediction error provided by the example. [Main component symbol description] 100: CPU 10: Responsive device ❹ 20: Instruction execution processing circuit 30: Instruction cache memory circuit 40: Fast Take controller 50: branch indicator buffers 60 to 62: circle type instruction buffer 63: instruction buffer '64: decoding pairing circuit • S80 to S82: step flow

Claims (1)

201005633 01- 28199twf.doc/n X. Application for Patent Park: 1. A replies for solving branch prediction errors, including: an instruction buffer for storing a plurality of instructions; at least one lap instruction buffer For storing a reply command column corresponding to the instructions, the reply command column includes a plurality of reply fingers eight and " a decoding pairing circuit 'followed by the instruction buffer and the circular instruction buffer' for decoding and pairing the instructions and the reply instruction, and when the branch prediction error occurs, the decoding pairing circuit outputs the reply instructions A processing circuit is executed for an instruction connected thereto. 2. The reply device of claim 1, wherein if no branch prediction error occurs, the decoding pairing circuit outputs the ^ command to the instruction execution processing circuit. — 3· As claimed in claim 1, the reply device further includes: a buffer buffer for detecting whether there is a branch prediction Raw, when the branch prediction occurs, send an indicator program count to a cache controller; the cache controller is lightly connected to the branch indicator buffer, and according to the indicator program count control - command cache _ taking the instruction of the age and the reply instruction; and the instruction cache memory circuit is coupled to the instruction path, the circular instruction buffer and the instruction buffer for storing the instruction With these reply instructions. 4. The reply device of claim 1, wherein the number of reply commands that the ring type instruction buffer can store is equal to ^ instruction ^ 19 201005633 * -^01-TW 28199twf.doc/n The number of instructions that the row processing circuit can execute. 5. The reply device of claim 1, wherein the decoding pairing circuit further sets the branch prediction error bit of the reply command to 1 ' and records the branch program count of the reply commands. 6. A method for recovering a branch prediction error, comprising: receiving a plurality of instructions to an instruction buffer memory, and receiving and multiplexing a plurality of instructions corresponding to the plurality of instructions to at least one of the instruction buffer memories; encoding and pairing the instructions with the reply instructions; and outputting the reply instructions to an instruction when the branch prediction error occurs Processing circuit. 7. The method for replying according to item 6 of the patent application scope, further comprising: setting the branch prediction error bit of the reply instructions to 1, and recording the branch program counts of the reply instructions. 8. The method for replying according to claim 6 of the patent application, further comprising: if the right no branch prediction error occurs, outputting the instructions to the instruction execution processing circuit. The reply method of claim 6, wherein the number of reply commands that the bar sound instruction buffer can store is equal to the number of instructions that the command processing circuit can execute. A central processing unit having a replying device, comprising: a buffer for storing a plurality of instructions; a type instruction buffer 11 for storing 7 columns corresponding to the instructions, the reply command column comprising a plurality of reply commands The exhausting pairing circuit 'lights up' to the command buffer and the ring-shaped finger 20 -01-TW 28199twf.doc/n 201005633 i slow 3 branches with the reply commands to solve the problem and match the i finger; == the decoding Pairing the _ to the instruction execution processing circuit, the light is connected to the decoding pairing circuit to execute the replies and the instructions. 11. In the case of the central processing unit described in claim 10, if there is no branch deletion error, the decoding circuit outputs the instructions to the instruction execution processing circuit. — 12. The central processor described in item 1G of the patent scope further includes: a branch indicator buffer, and if there is a branch with a branch prediction, when the branch is generated, the indicator program is sent. To - the cache controller is programmed to be connected to the branch indicator buffer, according to the indicator program, the command system - the command thread __ takes its storage order and the reply commands; and A ❿ the command cache The memory circuit is transferred to the instruction cache memory circuit, the ring type instruction buffer and the instruction buffer, and the instruction and the reply instruction are used. The central processing unit of claim 10, wherein the number of replies that can be stored by the lap command buffer is the number of instructions that the instruction execution processing circuit can execute. 14. The central processing unit of claim 10, wherein the decoding pairing circuit further sets the branching error bit of the recovery age to 1, and records the branch program count of the reply instructions. twenty one