TW201003651A - Method of making record on magnetic memory device - Google Patents

Method of making record on magnetic memory device Download PDF

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Publication number
TW201003651A
TW201003651A TW098112213A TW98112213A TW201003651A TW 201003651 A TW201003651 A TW 201003651A TW 098112213 A TW098112213 A TW 098112213A TW 98112213 A TW98112213 A TW 98112213A TW 201003651 A TW201003651 A TW 201003651A
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Taiwan
Prior art keywords
pulse
pulse wave
layer
magnetization
main
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TW098112213A
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Chinese (zh)
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TWI451410B (en
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Hiroyuki Ohmori
Masanori Hosomi
Minoru Ikarashi
Tetsuya Yamamoto
Kazutaka Yamane
Yuki Oishi
Hiroshi Kano
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Sony Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B61/00Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1675Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1693Timing circuits or methods
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/10Magnetoresistive devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/902Specified use of nanostructure
    • Y10S977/932Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/933Spintronics or quantum computing
    • Y10S977/935Spin dependent tunnel, SDT, junction, e.g. tunneling magnetoresistance, TMR

Abstract

A method of making a record in a magnetic memory device which has a memory layer which holds information as magnetization directions of a magnetic material and a magnetization reference layer which is provided over the memory layer with an insulating layer interposed therebetween. Recording is made by using current flowing between the memory layer and the magnetization reference layer through the insulating layer. An error rate as high as that of when a write pulse a little higher than the inversion threshold value is applied can be maintained even when a write pulse considerably higher than the inversion threshold value is applied. To record one piece of information, at least one main pulse and at least one subpulse are applied in the same direction. The main pulse is a pulse having a pulse height and a pulse width both of which are great enough to record the information. The subpulse is a pulse satisfying at least one of two conditions: one that the pulse width thereof is shorter than that of the main pulse and the other that the pulse height thereof is lower than that of the main pulse. At least one subpulse is applied after the main pulse is applied.

Description

201003651 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種磁性記憶體元件 ^ t β錄方法,該磁性 。己fe、體元件包含·記憶層,並传成彳μ 士 八係磁化方向可變化,將資訊 作為磁體之磁化方向保持;及磁 IU丞+層,其 介隔絕緣層而設置,為磁化方向之基 ' 〜曰 „ ’且藉由通過絕緣 層而流於記憶層與磁化基準層之間 免々丨L,進行資訊的記 錄。201003651 VI. Description of the Invention: [Technical Field] The present invention relates to a magnetic memory element ^ t β recording method, the magnetic property. The body element contains a memory layer, and the magnetization direction of the 彳μ 士八系 can be changed, and the information is held as the magnetization direction of the magnet; and the magnetic IU丞+ layer is provided with the isolation edge layer, which is the magnetization direction. The basis ' 曰 „ ' and the information is recorded by flowing through the insulating layer between the memory layer and the magnetization reference layer.

【先前技術】 於電腦等資訊機器,作為隨機存取記憶體⑽nd⑽[Prior Art] In a computer such as a random access memory (10) nd (10)

Access Memory :隨機存取記憶體)係廣泛使用動作高速、 可進行高密度記錄之DRAM(Dynamie RAM :動態續)。 然而,由於D副為電源切斷後,資訊即消失的揮發性記 隐μ 因此強烈期待即使電源切斷仍可保持資訊、對機器 之低消耗電力化不可或缺的非揮發性記憶體之高速化及高 密度大容量化。 ^作為非揮發性記憶體,快閃記憶體等已實用化,但近年 來,作為高速、大容量、低消耗電力之非揮發性記憶體, 利用磁性電阻效果之磁性記憶體受到矚目而開發正在進 展。例如利用通道磁性電阻(Tunnel Magnet〇resistance ; TMR)效果之磁性記憶體元件,亦即由MTJ元件所組成,藉 由利用电流所激發之磁場來使記憶層之磁化方向反轉,以 己錄資之磁性隨機存取記憶體(Magnetic ram : MRAM) 只用化(例如 Freescale Semiconductoi•公司製之 MR2A1 6( 137416.doc 201003651 商品名)等)。 圖9(a)係表示MTJ元件之基本構造及其記憶資訊之讀出 動作之說明圖。如圖9(a)所示,MTJ元件1〇〇具有所謂磁性 通道接合(Magnetic Tunnel Junction : MTJ),其係於記情 層1〇5與磁化基準層1〇3之2種強磁層之間,夾持有非磁之 薄絕緣層即通道絕緣層1〇4之構造。記憶層1〇5係由具有單 軸磁性各向異性之強磁導體所組成,能以來自外部的作用 使磁化方向變化,且將磁化方向作為資訊保持。例如該磁 化方向對於磁化基準層1〇3之磁化方向「平行」亦或「反 平行」,係分別作為「0」及r丨」之資訊記憶。 饮MTJtl件1〇〇之資訊讀出係利用T]y[R效果,其係由於 上述2種磁層之相對磁化方向之差異,對於通過通道絕緣 層1〇4而流於記憶層105與磁化基準層1〇3之間之通道電流 之電阻值會變化。該電阻值係於記憶層1〇5之磁化方向與 磁化基準層103之磁化方向平行時,取定最小值,於反平 行時取定最大值。 圖9(b)係表示由MTJ元件!00所組成iMRAM之記憶體胞 (memory cell)的構造之—例之部分立體圖。於該Mram, 作為列布線之字元線及作為行布線之位元線配置成矩陣 狀,於其等之各交點之位置配置有MTJ元件1〇〇,形成相 當於1位元之記憶體胞。 於s己憶體胞之上部,寫入用位元線i22及讀出用位元線 123係將層間絕緣膜夾於其間而設置,MTJ元件1〇〇相接於 碩出用位元線123而配置於其下,進—步於MTJ元件1〇〇之引 137416.doc 201003651 出電極層106之下’夾著絕緣層而配置有寫入用字元線12ι。 另一方面,於記憶體胞之下部,在例如矽基板等之半導 月立基板 111 设置 MOS(Metal Oxide Semiconductor:金屬 /氧 化物/半^體)型场效電晶體,作為用以於讀出動作時選擇 . 該記憶體胞之選擇用電晶體110。電晶體110之閘極電極Access Memory (Random Access Memory) is a DRAM (Dynamie RAM: Dynamic Continuation) that uses high-speed operation and high-density recording. However, since the D pair is a volatile memory that disappears after the power is turned off, it is strongly expected that the information can be kept and the non-volatile memory that is indispensable for the low power consumption of the device can be speeded up even if the power is turned off. And high density and large capacity. ^ As a non-volatile memory, flash memory, etc. have been put into practical use. In recent years, as a non-volatile memory with high speed, large capacity, and low power consumption, magnetic memory using magnetic resistance effects has been developed. progress. For example, a magnetic memory element using a tunnel magnetoresistance (TMR) effect, that is, an MTJ element, is used to invert the magnetization direction of the memory layer by using a magnetic field excited by a current. The magnetic random access memory (Magnetic ram: MRAM) is used only (for example, MR2A1 6 (137416.doc 201003651 trade name) manufactured by Freescale Semiconductoi Co., Ltd.). Fig. 9(a) is an explanatory view showing the basic structure of the MTJ element and the read operation of the memory information. As shown in FIG. 9(a), the MTJ element 1 has a so-called magnetic tunnel junction (MTJ), which is applied to two kinds of ferromagnetic layers of the sensible layer 1〇5 and the magnetization reference layer 1〇3. Between, the structure of the non-magnetic thin insulating layer, that is, the channel insulating layer 1〇4 is sandwiched. The memory layer 1〇5 is composed of a strong magnetic conductor having uniaxial magnetic anisotropy, which can change the magnetization direction by external action and maintain the magnetization direction as information. For example, the magnetization direction is "parallel" or "anti-parallel" to the magnetization direction of the magnetization reference layer 1 〇 3, and is used as the information memory of "0" and r 丨 respectively. The information reading system of the MTJtl device uses the T]y[R effect, which is due to the difference in the relative magnetization directions of the above two magnetic layers, and flows to the memory layer 105 and the magnetization through the channel insulating layer 1〇4. The resistance value of the channel current between the reference layers 1〇3 changes. This resistance value is obtained by taking the minimum value when the magnetization direction of the memory layer 1〇5 is parallel to the magnetization direction of the magnetization reference layer 103, and the maximum value when the anti-parallel is performed. Figure 9(b) shows the MTJ component! 00 is a partial perspective view of the structure of the memory cell of the iMRAM. In the Mram, the word line as the column wiring and the bit line as the row wiring are arranged in a matrix, and the MTJ element 1 is placed at the position of each of the intersections to form a memory equivalent to 1 bit. Body cell. In the upper part of the cell, the write bit line i22 and the read bit line 123 are provided with the interlayer insulating film interposed therebetween, and the MTJ element 1 is connected to the master bit line 123. And placed underneath, the input word line 12ι is placed next to the electrode layer 106 under the electrode layer 106 of the MTJ element 1 '. On the other hand, in the lower portion of the memory cell, a MOS (Metal Oxide Semiconductor) field effect transistor is provided on the semiconductor substrate 111 such as a germanium substrate, for reading. Select during the action. The memory cell is selected by the transistor 110. Gate electrode of transistor 110

n5係將胞間相連而形成帶狀,其兼作讀出用字元線。而 且,源極區域114係經由讀出用連接插塞1〇7而連接於MTJ ^ ; 70件1〇〇之引出電極層;汲極區域116係連接於作為讀 出用之列布線之感測線124。 於如此所構成之MR AM,對期望之記憶體胞之MTj元件 100之貝讯寫入(記錄),係藉由分別於該記憶體胞所含之列 之寫入用字元線12ι及行之寫入用位元線122流入寫入電 流’於2條寫入用布線之交點的位置,產生由該等電流所 造成之磁界的合成磁界而進行。藉由該合成磁界,期望之 記憶體胞之而元件⑽之記憶層105係往特定之磁化方 U 7 ’亦即往對於磁化基準層⑻之磁化方向「平行」亦或 反平仃」之方向磁化,進行資訊之寫入(記錄)。 - 立而^'’從MTJ元件100之資訊讀出係於包含有期望之記 ,I之歹丨之5貝出用子元線,即於閘極電極π 5施加選擇 L唬使°亥列之選擇用電晶體1 1〇全部為開啟(導通)狀態。 配合此’於包含有期望之記憶體胞之行之讀出用位元線 123與感測線124之間’施加讀出電壓。其結果,僅選擇期 望之記憶體胞,該MTJ元件1〇〇之記憶層1〇5之磁化方向之 差異係作為利用麗效果而流於MTJ元件1〇〇之通道電流 137416.doc 201003651 往(省略 的大小差異而檢測。通道带 迎逼电々丨L係從感測線124取出 圖示)周邊電路而測定。 ™R型之職趙係利用根據奈㈣體特有之自旋依存傳 導現象之磁性電阻效果’進行資訊讀出之非揮發性記憶 體,由於藉由磁化方向之反轉進行重寫,因此實質上可進 行無限次重寫’關於存取時間亦有報告為高速(參考例如 R. Scheuerlein et al τςςί-r η· 5 iSSCC DlSest Technical Papers, pp.128-129, Feb_2000)。 ,然而:在以電流磁界進行寫人之殿鳩,為了重寫而須 流有大量電流(例如數爪八程度),消耗電力變大。而且,若 MTJ元件微細化,則重寫所必要之電流顯示出增大的趨 2 ’另-方面’由於寫入用布線變細,因此難以流入對重 寫充分之電流。而且高積體化進展,於鄰接之其他記 憶體胞誤寫入之確率變高。進一步由於分別需要寫入用布 線及讀出用布、線,因此構造上複雜。由於該等原因,㈣ 以電流磁界進行寫入之MRAM之高密度大容量化。 因此,作為根據不同原理而對磁性記憶體元件之記憶層 寫入(記錄)資訊之元件,於寫入時利用藉由自旋注入所進 行之磁化反轉之磁性記憶體元件係受到矚目。自旋注入係 藉由於磁化方向固定之強磁導電層(磁化基準層)流入電 流,創造出由自旋的方向偏向一方之電子集團所組成之電 流(自旋偏極電流:Spin_p〇larized current),並將該電流、、主 入於磁化方向可變化之磁導電層(記憶層)之操作。如此一 來,於自旋偏極電流流於記憶層時,藉由經自旋偏極之電 137416.doc 201003651 子與構成記憶層之磁體之電子的相 仆古“ 作用,使記憶層之磁 化方向與磁化基準層之磁化方向— 夂之力(力矩)會發揮作 用。因此,藉由流入某臨限值以上 + ^ 值以上之電流密度之自旋偏極 电机’可使記憶層之磁化方向反韓 u汉轉(參考例如後述之專利 文獻1及非專利文獻1)。The n5 system is connected to each other to form a strip shape, which also serves as a reading word line. Further, the source region 114 is connected to the MTJ^; 70-piece lead-out electrode layer via the read-out connection plug 1〇7; the drain region 116 is connected to the sense of the wiring for reading. Line 124. In the MR AM thus constructed, the write (record) of the MTj element 100 of the desired memory cell is written by the write word line 12 and the row respectively included in the memory cell. The write bit line 122 flows into the position where the write current 'at the intersection of the two write wirings, and the combined magnetic boundary of the magnetic boundary caused by the currents is generated. By means of the synthetic magnetic field, the memory layer 105 of the component (10) is desirably stored in the direction of the specific magnetization U 7 ', that is, in the direction of "parallel" or anti-flat" to the magnetization direction of the magnetization reference layer (8). Magnetization, writing (recording) information. - The information from the MTJ element 100 is read from the information element containing the desired one, and the 5th output sub-line of the I, that is, the gate electrode π 5 is applied to select L唬. The selected transistors 1 1 〇 are all turned on (on). The read voltage is applied between the read bit line 123 and the sense line 124 in the row including the desired memory cell. As a result, only the desired memory cell is selected, and the difference in the magnetization direction of the memory layer 1〇5 of the MTJ element is used as the channel current 137416.doc 201003651 to the MTJ element 1 using the 丽 effect. It is detected by omitting the difference in size. The channel band is measured by the peripheral circuit in the case where the circuit L is taken out from the sensing line 124. The non-volatile memory of the TMR type, which uses the magnetic resistance effect according to the spin-dependent conduction phenomenon unique to the Nai (four) body, is rewritten by the reversal of the magnetization direction, so Unlimited rewriting can be performed 'About access time is also reported as high speed (see for example R. Scheuerlein et al τςςί-r η 5 iSSCC DlSest Technical Papers, pp. 128-129, Feb_2000). However, in the case of writing a person's temple with a current magnetic field, a large amount of current (for example, a few claws) has to be flown for rewriting, and power consumption is increased. Further, when the MTJ element is miniaturized, the current necessary for rewriting exhibits an increased tendency. In addition, since the write wiring is thinned, it is difficult to flow a current sufficient for rewriting. Moreover, the high integration progresses, and the accuracy of mis-writing of other memory cells adjacent to each other becomes high. Further, since the writing wiring and the reading cloth and the line are separately required, the structure is complicated. For these reasons, (4) the high density and large capacity of the MRAM to be written by the current magnetic boundary. Therefore, as an element for writing (recording) information to a memory layer of a magnetic memory element according to a different principle, a magnetic memory element which utilizes magnetization reversal by spin injection at the time of writing is attracting attention. The spin injection generates a current composed of an electron group that is biased toward one side by a direction of spin (spin_p〇larized current) by a current flowing in a strong magnetic conductive layer (magnetization reference layer) in which the magnetization direction is fixed. And the current, the operation of the magnetic conductive layer (memory layer) which is mainly changed in the magnetization direction. In this way, when the spin-polar current flows in the memory layer, the magnetization of the memory layer is caused by the action of the spin-polarized electric 137416.doc 201003651 and the electrons of the magnets constituting the memory layer. The direction and the magnetization direction of the magnetization reference layer - the force (torque) of the 会 will work. Therefore, the magnetization direction of the memory layer can be made by the spin-polar motor that flows into the current density above +^ of a certain threshold. The anti-Korean-Chinese transfer (see, for example, Patent Document 1 and Non-Patent Document 1 to be described later).

圖1〇係表示後料利讀2所示之磁化方肖Μ自B 入而反轉之MTJ元件(以下稱為自方走注入而元件)所組 成、利用藉由自旋注入所造成之磁化反轉之難鳩(以下 稱為自旋力矩MRAM)之構造之—例之部分立體圖。於該 自旋力矩MRAM,作為列布線之字元線215及作為行布線 之位元線218配置成矩陣狀,於其等之各交點之位置配置 有1個自旋注入MTJ元件220,形成有相當於丨位元之記憶 體胞。圖1 0係表示記憶體胞4個份。 於下部之半導體基板211,後述之選擇用電晶體21〇形成 於各記憶體胞,字元線215兼作選擇用電晶體21〇之閘極電 極。而且,汲極區域216係於圖中左右之選擇用電晶體共 通地形成,於該汲極區域216連接有列布線219。 圖11係表示自旋力矩MRAM之記憶體胞之構造之部分剖 面圖。於記憶體胞之中央部,從下層依序疊層有基底層 20 1、反強磁層202、磁化固定層203a、中間層203b、磁化 基準層203c、通道絕緣層204、記憶層205及保護層206之 各層’形成有自旋注入MTJ元件220。自旋注入MTJ元件 220之層構成基本上係與通常之MTJ元件1〇〇相同。 磁化固定層203a、中間層203b及磁化基準層203c係疊層 137416.doc 201003651 於反強磁層202之上,作為全體構成固定磁化層。由強磁 導體所組成之磁化固定層203a之磁化方向係藉由反強磁層 202而固定。同樣由強磁導體所組成之磁化基準層2〇3()係 介隔非磁層之中間層203b而與磁化固定層203a形成反強磁 結合。其結果’磁化基準層203c之磁化方向係固定於磁化 固疋層203a之磁化方向的相反方向。於圖11所示之例中, 磁化固定層203a之磁化方向固定於朝左,磁化基準層2〇3c 之磁化方向固定於朝右。 若將固疋磁化層製成上述疊層鐵構造’則可使固定磁化 層對於外部磁界之感度降低’因此可抑制由於外部磁界所 造成之固定磁化層的磁化變動,使MTJ元件之安定性提 升。而且,由於從磁化固定層2〇3a及磁化基準層2〇3c所漏 出之磁通相互抵銷,因此藉由調整該等之膜厚,可將從固 定磁化層漏洩之磁通抑制在最少。 Z fe、層5係由具有單軸磁性各向異性之強磁導體所組 成,以來自外部的作用可使磁化方向變化,且可將磁化方 向作為貧訊保持。例如該磁化方向對於磁化基準層2〇3c之 磁化方向「平行」'亦或「反平行」,係分別作為「〇」及 「1」之資訊記憶。於磁化基準層20氕與記憶層2〇5之間, »又置有非磁之薄絕緣層之通道絕緣層2〇4,藉由磁化基準 層203c、通道絕緣層2〇4及記憶層2〇5形成磁性通道接合 (MTJ)。 〇 另一方面,於記憶體胞之下部, 板2 1 1中經元件分離之井區域2 i 1 & 在矽基板等之半導體基 ’作為用以選擇該記憶 137416.doc 201003651 月豆胞之選擇用電晶體210而設置有由閘極絕緣膜2 12、源極 私極2 13、源極區域2丨4、閘極電極2丨$、汲極區域2丨6及汲 極電極21 7所組成之m〇s型場效電晶體。 士上it遥擇用電晶體210之閘極電極21 5係將胞(cell) 間相連而形成為帶狀,並兼作作為第丨列布線之字元線。 而且,沒極電極217係連接於作為第2列布線之列布線 219,源極電極213係經由連接插塞2〇7而連接於自旋注入 MTJ兀件220之基底層2〇1。另一方面,自旋注入MTJ元件 220之保護層2〇6係連接於設置在記憶體胞之上部、作為行 布線之位元線2 1 8。 對期望之記憶體胞之自旋注入MTJ元件22〇記錄資訊 時,於包含有期望之記憶體胞之列的字元線2丨5施加選擇 信號,使該列之選擇用電晶體21〇全部為開啟(導通)狀態。 配s此於包含有期望之記憶體胞之行的位元線2 1 8與列 布線219之間,施加寫入電壓。其結果,選擇期望之記憶 體胞,自旋偏極電流貫流於該自旋注入MTJ元件22〇之記 憶層205,將記憶層2〇5往特定之磁化方向磁化,進行資訊 記錄。 此時,首先,自旋注入MTJ元件22〇之磁化基準層2〇3c 之磁化方向對於兄憶層2 〇 5之磁化方向處於「反平行」之 狀怨,藉由寫入使其反轉為記憶層2〇5之磁化方向對於磁 化基準層2〇3c之磁化方向「平行」之狀態之情況時,如圖 11所不,將臨限值以上之電流密度之寫入電流從記憶層 205流往磁化基準層2〇3c。藉此,作為實體而言,臨限值 137416.doc 201003651 以上之電子密度之自旋偏極電子流會從磁化基準層203 c流 往記憶層205,引發磁化反轉。 相反地,使對於記憶層205之磁化方向處於「平行」狀 態之磁化基準層203c之磁化方向反轉為「反平行」狀態之 情況時,將臨限值以上之電流密度之寫入電流往上述之相 反方向,亦即從磁化基準層203c流往記憶層205,作為實 體而言,臨限值以上之電子密度之電子流會從記憶層205 流往磁化基準層203c。 而且,來自自旋注入MTJ元件220之資訊讀出係與MTJ元 件100同樣利用TMR效果來進行。自旋注入MTJ元件220之 寫入及讀出兩者均利用記憶層205中之電子、與貫流該層 之自旋偏極電流之相互作用,讀出係於自旋偏極電流之電 流密度小的區域進行,寫入係於自旋偏極電流之電流密度 大、超過臨限值之區域進行。 由於藉由自旋注入所進行之磁化反轉之可否係取決於自 旋偏極電流之電流密度,因此於自旋注入MTJ元件220, 記憶層之體積越小,與體積成比例,以更少的電流即可進 行磁化反轉(參考非專利文獻1)。而且,於選擇用電晶體 210所選擇之記憶體胞寫入資訊,因此與藉由電流磁場所 進行之寫入不同,不會有於鄰接之其他胞誤寫入之虞。而 且,於寫入及讀出可共用大部分之布線,因此構造簡化。 進一步而言,由於比起磁場寫入,磁體形狀的影響更小, 因此容易提高製造時之良率。從該等觀點來看,自旋力矩 MRAM比起以電流磁場進行寫入之MRAM,更適於微細 137416.doc -10- 201003651 化、高密度大容量化。 然而,由於使用選擇用電晶體210進行寫入(記錄),因 此產生其他問題點。亦即,於寫入時可流於自旋注入MTJ 元件220之電流係受到可流於選擇用電晶體210之電流(電 _ 晶體之飽和電流)限制。一般而言,隨著電晶體之閘極寬 或閘極長變小,電晶體之飽和電流亦變小,因此為了確保 對自旋注入MTJ元件220之寫入電流,選擇用電晶體210之 小型化受到限制。因此,為了儘可能將選擇用電晶體210 r、 ' 小型化,將自旋力矩MRAM最大限度地高密度大容量化, 儘可能使寫入電流之臨限值減少係不可或缺。 而且,為了防止通道絕緣層204絕緣損壞,亦必須使寫 入電流之臨限值減少。而且,為了減少MRAM之消耗電 力,亦必須儘可能使寫入電流臨限值減少。 而藉由自旋注入所進行之磁化反轉所需要之電流之臨限 值,就現象論而言顯示出與記憶層2 0 5之自旋制動常數α、 、 飽和磁化量Ms之二次方及體積V成比例,與自旋注入效率Fig. 1 shows the magnetization of the MTJ element (hereinafter referred to as the self-injection and the element) which is formed by the inversion of the magnetization square shown in the second reading, and the magnetization caused by the spin injection. A partial perspective view of the construction of the difficulty of reversing (hereinafter referred to as spin torque MRAM). In the spin torque MRAM, a word line 215 as a column wiring and a bit line 218 as a row wiring are arranged in a matrix, and one spin injection MTJ element 220 is disposed at a position of each of the intersections. A memory cell corresponding to the 丨 bit is formed. Figure 10 shows 4 parts of memory cells. On the lower semiconductor substrate 211, a selection transistor 21, which will be described later, is formed in each memory cell, and the word line 215 also serves as a gate electrode of the selection transistor 21A. Further, the drain region 216 is formed in common in the left and right selection transistors in the figure, and the column wiring 219 is connected to the drain region 216. Figure 11 is a partial cross-sectional view showing the structure of a memory cell of a spin torque MRAM. In the central portion of the memory cell, a base layer 20 1 , an antiferromagnetic layer 202 , a magnetization fixed layer 203 a , an intermediate layer 203 b , a magnetization reference layer 203 c , a channel insulating layer 204 , a memory layer 205 , and protection are sequentially laminated from the lower layer. Each layer of layer 206 is formed with a spin implant MTJ element 220. The layer composition of the spin-injected MTJ element 220 is substantially the same as that of the conventional MTJ element. The magnetization fixed layer 203a, the intermediate layer 203b, and the magnetization reference layer 203c are laminated 137416.doc 201003651 on the antiferromagnetic layer 202 to constitute a fixed magnetization layer as a whole. The magnetization direction of the magnetization fixed layer 203a composed of a strong magnetic conductor is fixed by the antiferromagnetic layer 202. Similarly, the magnetization reference layer 2〇3() composed of a strong magnetic conductor forms an antiferromagnetic bond with the magnetization fixed layer 203a via the intermediate layer 203b of the nonmagnetic layer. As a result, the magnetization direction of the magnetization reference layer 203c is fixed in the opposite direction to the magnetization direction of the magnetization solid layer 203a. In the example shown in Fig. 11, the magnetization direction of the magnetization fixed layer 203a is fixed to the left, and the magnetization direction of the magnetization reference layer 2?3c is fixed to the right. If the solid-state magnetization layer is formed into the laminated iron structure described above, the sensitivity of the fixed magnetization layer to the external magnetic boundary can be reduced. Therefore, the magnetization variation of the fixed magnetization layer due to the external magnetic boundary can be suppressed, and the stability of the MTJ element can be improved. . Further, since the magnetic fluxes leaked from the magnetization fixed layer 2〇3a and the magnetization reference layer 2〇3c cancel each other, the magnetic flux leaking from the fixed magnetization layer can be suppressed to the minimum by adjusting the film thicknesses. Z fe and layer 5 are composed of a strong magnetic conductor having uniaxial magnetic anisotropy, and the magnetization direction can be changed by external action, and the magnetization direction can be maintained as a poor signal. For example, the magnetization direction is "parallel" or "anti-parallel" to the magnetization direction of the magnetization reference layer 2〇3c, and is used as the information memory of "〇" and "1", respectively. Between the magnetization reference layer 20 氕 and the memory layer 2 〇 5, a channel insulating layer 2 〇 4 having a non-magnetic thin insulating layer is further disposed by the magnetization reference layer 203 c, the channel insulating layer 2 〇 4 and the memory layer 2 〇5 forms a magnetic channel junction (MTJ). On the other hand, in the lower part of the memory cell, the well region 2 i 1 & in the plate 2 1 1 is separated from the semiconductor substrate of the ruthenium substrate or the like as the memory for selecting the memory 137416.doc 201003651 The selection transistor 210 is provided with a gate insulating film 2 12 , a source private electrode 2 13 , a source region 2 丨 4 , a gate electrode 2 丨 $ , a drain region 2 丨 6 , and a drain electrode 21 7 . The m〇s type field effect transistor is composed. The gate electrode 21 of the transistor 210 is connected to each other to form a strip shape, and also serves as a word line for the second column wiring. Further, the electrodeless electrode 217 is connected to the column wiring 219 which is the second column wiring, and the source electrode 213 is connected to the base layer 2〇1 of the spin injection MTJ element 220 via the connection plug 2〇7. On the other hand, the protective layer 2〇6 of the spin-implanted MTJ element 220 is connected to the bit line 2 18 which is provided as a row wiring on the upper portion of the memory cell. When the spin of the desired memory cell is injected into the MTJ element 22, the selection signal is applied to the word line 2丨5 including the column of the desired memory cell, so that the selection transistor 21 of the column is all To be on (on) state. The write voltage is applied between the bit line 2 18 and the column wiring 219 including the row of the desired memory cell. As a result, the desired memory cell is selected, and the spin-polar current flows through the memory layer 205 of the spin-implanted MTJ element 22, and the memory layer 2〇5 is magnetized in a specific magnetization direction to perform information recording. At this time, first, the magnetization direction of the magnetization reference layer 2〇3c of the spin injection MTJ element 22 is "anti-parallel" to the magnetization direction of the brother layer 2 〇5, and is reversed by writing to When the magnetization direction of the memory layer 2〇5 is in a state of “parallel” to the magnetization direction of the magnetization reference layer 2〇3c, as shown in FIG. 11, the write current of the current density above the threshold value flows from the memory layer 205. To the magnetization reference layer 2〇3c. Thereby, as an entity, the spin-polar electron flow of the electron density above the threshold 137416.doc 201003651 flows from the magnetization reference layer 203c to the memory layer 205, causing magnetization reversal. On the other hand, when the magnetization direction of the magnetization reference layer 203c in which the magnetization direction of the memory layer 205 is in the "parallel" state is reversed to the "anti-parallel" state, the current density of the current density above the threshold value is applied to the above. In the opposite direction, that is, from the magnetization reference layer 203c to the memory layer 205, as an entity, an electron flow of electron density above the threshold flows from the memory layer 205 to the magnetization reference layer 203c. Further, the information reading from the spin injection MTJ element 220 is performed in the same manner as the MTJ element 100 by the TMR effect. Both the writing and the reading of the spin-injected MTJ element 220 utilize the interaction of the electrons in the memory layer 205 with the spin-polar current flowing through the layer, and the current density of the spin-bias current is small. The area is written in a region where the current density of the spin-bias current is large and exceeds the threshold. Since the magnetization reversal by spin injection depends on the current density of the spin bias current, the spin of the MTJ element 220, the smaller the volume of the memory layer, proportional to the volume, and less The current can be reversed by magnetization (refer to Non-Patent Document 1). Further, since the memory cell selected by the transistor 210 is selected to write information, unlike the writing by the current magnetic field, there is no possibility that another adjacent cell is mistakenly written. Moreover, most of the wiring can be shared by writing and reading, so that the structure is simplified. Further, since the influence of the shape of the magnet is smaller than that of the magnetic field writing, it is easy to improve the yield at the time of manufacture. From these viewpoints, the spin torque MRAM is more suitable for the fine-grained MRAM than the MRAM that is written by the current magnetic field. However, since writing (recording) is performed using the selection transistor 210, other problems are caused. That is, the current which can flow through the spin injection MTJ element 220 at the time of writing is limited by the current (saturation current of the electric crystal) which can flow through the selection transistor 210. In general, as the gate width of the transistor or the gate length becomes smaller, the saturation current of the transistor also becomes smaller. Therefore, in order to ensure the write current for the spin injection of the MTJ element 220, the small size of the transistor 210 is selected. Limited access. Therefore, in order to miniaturize the selection transistor 210 r and ' miniaturization, the spin torque MRAM is maximized and increased in capacity, and it is indispensable to reduce the threshold of the write current as much as possible. Moreover, in order to prevent insulation damage of the channel insulating layer 204, it is necessary to reduce the threshold of the write current. Moreover, in order to reduce the power consumption of the MRAM, it is also necessary to reduce the write current threshold as much as possible. The threshold value of the current required for the magnetization reversal by the spin injection shows a quadratic square of the spin-braking constant α and the saturation magnetization Ms of the memory layer 205. And volume V proportional, and spin injection efficiency

K.J η成反比。因此,藉由適當選擇該等,可降低磁化反轉所 需要之電流之臨限值。 然而,另一方面,自旋注入MTJ元件220為了成為可靠 之記憶體元件,必須確保記憶層205之記憶體保持特性(磁 化之熱安定性),磁化方向不因熱運動而變化。熱安定性 係與記憶層205之飽和磁化量Ms及體積V成比例。 記憶層205之飽和磁化量Ms及體積V係與磁化反轉所需 要之電流之臨限值及熱安定性雙方相關,處於當縮小該等 137416.doc -11 - 201003651 因子,使磁化反轉所+ ^ 性亦降低之取捨關係。 了…女疋 :面障:::磁化反轉所需要之電流的臨限值降低,必 與熱安定性之確保之同時成立,-面主 要改善自旋注入之对漆; ,. >率η。本木發明者係為了使自旋力 MRAM可成為比其他 疋力矩 立 已匕版更有脱肀力之記憶體,持續銳 思開發可使磁化反轉所需要之電流密度之臨限值減低、與 &己憶體保持特性(熱安定性)確保㈣成立之MTW料(參考 日本特開2GG6-165265號公報、日本特開·7]㈣…虎公 報、日本特開·7_48·號公報、專利文獻2及日本特願 2006-35G113等)。其結果,不斷接近其實現。 [先行技術文獻] [專利文獻1]日本特開2〇〇3_m82號公報(第s及7頁、圖幻 [專利文獻2]日本特開扇7_287923號公報(第7_15頁、圖2) [非專利文獻 1]F.J.Albert et al·,Appl. Phys. Lett·,v〇1 77,(2002),p.3809 【發明内容】 [發明所欲解決之問題] 然而,本案發明者使用上述MTj材料,製作並調查寫入 電流密度之臨限值小的自旋注入MTJ元件之處,辨明以往 在論文或學會發表中亦未報告之特殊現象出現。亦即,於 該自旋注入MTJ元件,確認到即使若考慮到寫入錯誤率, 將所施加之寫入脈波設定稍微大於反轉臨限值(作為進行 外插所得之推測值),可確保10-25以下之寫入錯誤率,但 137416.doc •12- 201003651 若將所把加之舄入脈波設定甚大於反轉臨限值,則會有寫 脈波父得越大,反而寫入錯誤率越增加之趨勢(參考圖 )於此,於大於反轉臨限值之記錄電壓所引發之錯誤 稱為「高記錄電壓錯誤」。K.J η is inversely proportional. Therefore, by appropriately selecting these, the threshold of the current required for magnetization reversal can be reduced. On the other hand, however, in order to become a reliable memory element, the spin injection MTJ element 220 must ensure the memory retention characteristics (thermal stability of magnetization) of the memory layer 205, and the magnetization direction does not change due to thermal motion. The thermal stability is proportional to the saturation magnetization Ms and the volume V of the memory layer 205. The saturation magnetization Ms and volume V of the memory layer 205 are related to both the threshold and the thermal stability of the current required for magnetization reversal, and are in the process of reducing the 137416.doc -11 - 201003651 factor, so that the magnetization reversal + ^ The trade-off relationship is also reduced.疋Nursing: Face Barrier::: The threshold of the current required for magnetization reversal is reduced, which must be established at the same time as the thermal stability is ensured. η. In order to make the spin force MRAM become a more distracting memory than other 疋 立 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , (4) Established MTW material (see Japanese Patent Laid-Open No. 2GG6-165265, JP-A-7) (4)... Tiger Gazette, Japanese Special Report No. 7_48. Patent Document 2 and Japanese Patent Application No. 2006-35G113, etc.). As a result, it is constantly approaching its implementation. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei 2〇〇3_m82 (Sections s and 7 and Fig. 2 [Patent Document 2] Japanese Laid-Open Patent Publication No. 7-287923 (page 7-15, Fig. 2) Patent Document 1] FJAlbert et al., Appl. Phys. Lett., v. 1 77, (2002), p. 3809 [Disclosure] [The problem to be solved by the invention] However, the inventor of the present invention uses the MTj material described above. Produce and investigate the spin injection MTJ component with a small threshold value of the current density, and identify the special phenomenon that has not been reported in the paper or the publication of the society. That is, the MTJ component is injected into the spin to confirm Even if the write error rate is taken into consideration, the applied write pulse wave setting is slightly larger than the inversion threshold value (as an estimated value obtained by extrapolation), and the write error rate of 10-25 or less can be secured, but 137416.doc •12- 201003651 If the added pulse is set to be greater than the inversion threshold, the write pulse will be larger, but the write error will increase (refer to the figure). Therefore, the error caused by the recording voltage greater than the inversion threshold is called "high." Recording voltage error. "

γ —有數百Mbit之谷量之自旋力矩mram記憶體晶片之 貫際寫人,係考慮到自旋注入MTJ元件之反轉臨限值之偏 差或起因於電晶體及布線之反轉臨限值之偏差等,設定為 靶加甚大於反轉臨限值之平均值之寫入脈波。因此,若上 述現象出現’於對自旋力矩MRAM記憶體晶片之實際寫 入,無法確保1〇-25以下之寫入錯誤率。 而且,由於MRAM或自旋力矩RAM係作為構成記憶層之 磁體之磁化方向而保持有資訊,目此若暴露於強烈的外部 磁场’則記憶層之磁化方向會變化,資訊消失。特別於寫 入(記錄)過程之中途’對於外部磁場之耐受性顯著降低: 因此需要用以使作用於磁性記憶體元件之外部磁場減少之 磁性屏蔽,於前述市售2MRAM(MR2A16)亦有配備。然 而,為了以磁性屏蔽獲得磁場遮蔽效果,需要某程度之厚 度及體積,無法避免記憶體IC之體積或重f增加、=者= 格上升。γ - the spin torque mram memory chip with hundreds of Mbits, which is based on the deviation of the inversion threshold of the spin injection MTJ component or the reversal of the transistor and wiring The deviation of the threshold value, etc., is set as the write pulse wave whose target is added to be larger than the average value of the inversion threshold. Therefore, if the above phenomenon occurs in the actual writing of the spin torque MRAM memory chip, the write error rate of 1 〇 25 or less cannot be ensured. Further, since the MRAM or the spin torque RAM maintains information as the magnetization direction of the magnet constituting the memory layer, if it is exposed to a strong external magnetic field, the magnetization direction of the memory layer changes, and the information disappears. Especially in the middle of the writing (recording) process, the tolerance to the external magnetic field is significantly reduced: therefore, a magnetic shield for reducing the external magnetic field acting on the magnetic memory element is required, which is also available in the aforementioned commercially available 2MRAM (MR2A16). Equipped. However, in order to obtain a magnetic field shielding effect by magnetic shielding, a certain degree of thickness and volume is required, and it is impossible to avoid the increase in the volume or weight f of the memory IC, and the increase in the = cell.

.別於自旋力矩RAM,例如於文獻(Kjt〇 et a丨.,了 D V〇l. 40, 2007年,p.1261)表示有外部磁場影響記錄電流或 反轉時間,進一步於文獻(G.D.Fu咖et al·,AplphysUt 麗年,P.1525G9)表示有由於通電所造成之自旋 注入MTT元件之發熱,對於外部磁場之耐受性進—步降低 137416.doc 201003651 之可能性,必須預先更提高對於外部磁場之耐受性。 本發明係有鑑於此類狀況而完成,其目的在於提供一種 磁性記憶體元件之記錄方法,該磁性記憶體元件包含:記 憶層,其係磁化方向可變化,將資訊作為磁體之磁化方向 保持;及磁化基準層,其對於記憶層介隔絕緣層而設置, :、、、方向之基準,且藉由通過絕緣層而流於記億層與磁 化基準層之間之電流,進行資訊的記錄;即使於施加有甚 大於反轉臨限值之寫入脈波之情況下,仍可保持於施加有 =微大於反轉臨限值之寫入脈波之情況下所獲得之寫入錯 。吳率而且對於外部磁場之耐受性提升。 [解決問題之技術手段] ^發明者經重複進行銳意研究,結果發現藉由設計寫 :波之施加方法’可解決上述問題,終至完成本發明。 亦即,本發明係關於一 旺°己體兀件之記錄方法, 磁性記憶體元件之記錄方法,該磁性記憶體元件 化:二:記憶層’其係包含有強磁導體,磁化方向可變 字貝δ孔作為磁體之磁化 伤射& & . 乃π保待,及基準磁化層,其 ’、子;月IJ述記憶層介隔絕缘> % # 磁芥士人 έ、、象層而s又置,包含有強磁導體, 声而、.ώ Μ、,+ 之基旱,且精由通過前述絕緣 增而流於w述記憶層鱼前 資訊的準磁化層之間之電流,進行 貝。礼的兄錄,其特徵為: m ^ 於5己錄1個貧訊時,朝同向施加1 個以上之主脈波及丨個以 m ^ 上之刹脈波;於前述1個以上之主 脈波後,施加1個以上 爻王 之副m之4脈波,將於前述主脈波後施加 之田】脈波設為符合脈波t I比則述主脈波短之脈波,亦或脈 137416.doc 14 201003651 波咼比前述主脈波低之脈波之至少一方條件之脈波。 此外’前述脈波為電壓控制、電流控制、亦或電力控制 均可。 【實施方式】 [發明之效果] 若依據本發明之磁性記憶體元件之記錄方法,藉由如後 述實施型態及實施例所示,於記錄丨個資訊時’於前述^固Different from the spin torque RAM, for example, in the literature (Kjt〇et a丨., DV〇l. 40, 2007, p. 1261) indicates that there is an external magnetic field affecting the recording current or the inversion time, further in the literature (GD Fu café et al., Aplphys Ut, P.1525G9) indicates that there is a possibility of spin-injection of the MTT component due to energization, and the tolerance to the external magnetic field is further reduced by 137416.doc 201003651. Improve the tolerance to external magnetic fields. The present invention has been made in view of such circumstances, and an object thereof is to provide a recording method of a magnetic memory element, the magnetic memory element comprising: a memory layer which is changeable in magnetization direction and holds information as a magnetization direction of the magnet; And a magnetization reference layer, which is provided with respect to the memory layer through the isolation edge layer, and the reference of the direction, and the current flowing between the cell layer and the magnetization reference layer through the insulating layer, and recording information; Even in the case where a write pulse having a value greater than the inversion threshold is applied, the write error obtained in the case where the write pulse of = slightly larger than the inversion threshold is applied can be maintained. Wu rate and improved tolerance to external magnetic fields. [Technical means for solving the problem] The inventors have repeatedly conducted intensive studies, and as a result, found that the above problem can be solved by designing the writing method of wave application, and the present invention is completed. That is, the present invention relates to a recording method of a magnetic component, a magnetic memory component recording method, and a magnetic memory component: a memory layer comprising a strong magnetic conductor and a variable magnetization direction The word δ hole acts as a magnetization shot of the magnet && . is π guaranteed, and the reference magnetization layer, its ', child; month IJ memory layer dielectric isolation edge> The layer is s, and contains a strong magnetic conductor, the sound of the sound, the ώ Μ, the base of the +, and the current flowing through the aforementioned insulation increases the current between the quasi-magnetized layers of the fish front information , carry the shell. The rites of the rites are characterized by: m ^ when 1 has recorded 1 poor news, applying more than one main pulse wave and one brake pulse on m ^ in the same direction; more than one main pulse wave in the above After that, applying 4 or more pulses of the sub-m of the king of the king, the pulse wave applied after the main pulse wave is set to match the pulse wave t I ratio, and the pulse wave of the main pulse wave is short, or the pulse 137416. Doc 14 201003651 A pulse wave of at least one condition of a pulse wave lower than the aforementioned main pulse wave. Further, the aforementioned pulse wave may be voltage control, current control, or power control. [Embodiment] [Effect of the Invention] According to the recording method of the magnetic memory device according to the present invention, when the information is recorded as described in the following embodiments and examples,

以上之主脈波後,施加前述丨個以上之副脈波,將於前述 主脈波後施加之副脈波設為符合脈波寬比前述主脈波短之 脈波,亦或脈波高比前述主脈波低之脈波之至少—方條件 之脈波’即使於施加有甚大於反轉臨限值之寫入脈波之情 :下’仍可保持與以稍微大於反轉臨限值之寫入脈波所獲 得同樣之寫入錯誤率。 又 一顯現先前所述之高記錄電壓錯誤之機構或藉由本發明將 馬入錯誤率抑制在較小之機制,並非可謂已完全_。缺 而,從於施加有猶微大於反轉臨限 …、 未構成_,於施加有甚大於反…=波之情況下 β B日 孓夂铃限值之寫入脈波之情 下產生問題,而且寫入脈波越大,寫入錯誤率越,加來 思慮,可推測相較於反轉臨 : 引起問題。 舄入電力的注入會 於以往藉由單—脈波所進行 力注入所產生之寫入錯等未…由於過剩之寫入電 寫入錯誤率高。而且 原、樣成為結果’因此 相對於此,於本發 寫Μ對於外部磁場之耐受性低。 ’於前述1個以上之主脈波後,施加! 137416.doc -15 - 201003651 個以上之副脈波,因此以藉由該副脈波所進行之寫入,可 修正於前述主脈波所產生之寫入錯誤之可能性高。而且, 由於將於前述主脈波後施加之副脈波設為符合脈波寬比前 述主脈波短之脈波,亦或脈波高比前述主脈波低之脈波之 至少一方條件之脈波,因此於藉由前述副脈波所進行之寫 入’難以積存過剩的能量,不易出現上述高記錄電壓錯 誤。藉由以上效果,利用本發明之磁性記憶體元件之記錄 方法’寫入錯誤率減少’而且寫入時對於外部磁場之而才受 性提升。 於本發明之磁性記憶體元件之記錄方法,於包含有前述 1個以上之主脈波、及其後施加之前述1個以上之前述副脈 波之脈波列中,宜至少設置一組連續3個脈波之組合、且 脈波見及脈波面之至少一方漸次減少之組合。 而且,於前述1個以上之主脈波之末端與其後施加之前 述1個以上之前述副脈波之前端之間,設置3 ns以上之時間 間隔。(此外’脈波之末端及前端分別係脈波之下降及上 升中,高度成為脈波高之最大值之一半的位置.。以下同。) 而且’包含有前述丨個以上之主脈波、及其後施加之前 述1個以上之前述副脈波之脈波列中,於任意選擇之連續2 個脈波之組合,宜將後脈波設為符合脈波寬2 ns以上、1〇 ns以下’亦或脈波高為前脈波之〇 7倍以上、〇 95倍以下之 至少一方條件之脈波,且於前脈波之末端與後脈波之前瑞 之間設置5 ns以上之時間間隔。 而且’包含有前述1個以上之主脈波、及其後施加之前 137416.doc • 16· 201003651 述1個以上之前述副脈波之脈波列中,於任意選擇之連續2 個脈波之組合’宜使後脈波符合脈波寬3 ns以下,亦或脈 波高為前脈波之0.95倍以下之至少一方條件,且前脈波之 末端與後脈波之前端之時間間隔設為小於5 ns。 . 接著,於圖式參考下,更具體說明本發明較佳之實施型 態。 實施型態1After the main pulse wave, the plurality of sub-pulse waves are applied, and the sub-pulse wave applied after the main pulse wave is set to be a pulse wave having a pulse width wider than the main pulse wave, or the pulse wave height is higher than the main pulse wave. At least the pulse of the low pulse - even if the applied pulse wave is greater than the inversion threshold: the lower 'can still remain with the write pulse slightly larger than the reverse threshold The wave gets the same write error rate. Another mechanism for exhibiting a high recording voltage error as described above or a mechanism for suppressing the error rate of the horse by the present invention is not completely _. Lacking, from the application of the imitation is greater than the reversal threshold ..., does not constitute _, in the case of applying more than the inverse ... = wave in the case of the β B 孓夂 ring limit of the write pulse wave And the larger the write pulse, the more the write error rate, plus the thoughts, it can be speculated that compared to the reverse: cause problems. The injection of the incoming power is caused by a write error or the like caused by the force injection by the single pulse wave in the past. The write error rate is high due to the excess write power. Moreover, the original sample becomes the result. Therefore, in contrast to this, the tolerance to the external magnetic field is low. After the above one or more main pulse waves, apply! 137416.doc -15 - 201003651 More than the secondary pulse wave, so the writing by the secondary pulse wave can correct the possibility of writing errors caused by the main pulse wave. Further, since the sub-pulse wave applied after the main pulse wave is set to be a pulse wave having a pulse width wider than the main pulse wave, or a pulse wave having a pulse wave height lower than a pulse wave having a lower pulse wave than the main pulse wave, In the writing by the aforementioned secondary pulse wave, it is difficult to accumulate excess energy, and the above-mentioned high recording voltage error is unlikely to occur. With the above effects, the recording method of the magnetic memory element of the present invention has a 'write error rate reduction' and the writing is improved for the external magnetic field. In the method of recording a magnetic memory device according to the present invention, at least one set of consecutive 3s is included in the pulse train including the one or more main pulse waves and the one or more of the sub-pulse waves applied thereafter. A combination of pulse waves and a combination of at least one of the pulse waves and the pulse wave surface is gradually reduced. Further, a time interval of 3 ns or more is provided between the end of the one or more main pulse waves and the front end of the one or more of the sub-pulses described above. (In addition, the end of the pulse wave and the front end are respectively a position where the height of the pulse wave is one-half of the maximum value of the pulse wave during the fall and the rise of the pulse wave. The same applies to the above-mentioned "the main pulse wave of the above-mentioned one or more." In the pulse train of the above-mentioned one or more of the sub-pulse waves applied, the combination of the arbitrarily selected two consecutive pulse waves is preferably such that the pulse wave width is equal to or greater than 2 ns and less than 1 ns. Or a pulse wave having a pulse wave height of at least one of 7 times or more and 95 times or less of the front pulse wave, and a time interval of 5 ns or more between the end of the front pulse wave and the front pulse wave. Further, in the pulse wave train including the one or more main pulse waves described above and the subsequent application of 137416.doc • 16· 201003651, the pulse wave train of the plurality of pulse waves is arbitrarily selected. 'The posterior pulse wave should be at least one of the pulse width less than 3 ns, or the pulse wave height is less than 0.95 times the front pulse wave, and the time interval between the end of the front pulse wave and the front end of the back pulse wave is set to be less than 5 Ns. Next, a preferred embodiment of the present invention will be described in more detail with reference to the drawings. Implementation type 1

p 於實施型態1,主要針對關於請求項1〜3之自旋注入MTJ 元件之記錄方法之例說明。 於圖15及圖16,表示本實施型態所用之自旋力矩mram 之記憶體胞之構造及自旋注入MTJ元件之構成。 圖15係表示由磁化方向藉由自旋注入而反轉2Mtj元件( 以下稱為自旋注入MTJ元件)所組成,並利用藉由自旋注入 所造成之磁化反轉之MRAM(以下稱為自旋力矩mram)2 構造之一例之部分立體圖。於該自旋力矩mram,作為列 Q 布線之字元線15及作為行布線之位元線18配置成矩陣狀, 方、其%之各父點之位置配置有1個自旋注入元件, • 形成有相當於1位元之記憶體胞。圖15係表示記憶體胞4個 份。 於下部之半導體基板丨1,後述之選擇用電晶體1〇形成於 各記憶體胞,字元線15兼作選擇用電晶體1〇之閘極電極。 而且,沒極區域16係於圖中左右之選擇用f晶體共通地形 成’於s亥沒極區域1 6連接有列布線19。 圖16係表示自旋力矩MRAM之記憶體胞之構造之部分剖 137416.doc 201003651 面圖。於記憶體胞之中央部,從下層依序疊層有基底層 1 '反強磁層2、磁化固定層3a、中間層3b、磁化基準層 3c、通道絕緣層4、記憶層5及保護層6之各層,形成有自 旋注入MTJ元件20。 磁化固定層3a、中間層3b及磁化基準層3c係疊層於反強 磁層2之上,作為全體構成固定磁化層。由強磁導體所組 成之磁化固定層3a之磁化方向係藉由反強磁層2而固定。 同樣由強磁導體所組成之磁化基準層3c係介隔非磁層之中 間層3b而與磁化固定層33形成反強磁結合。其結果,磁化 基準層3c之磁化方向係固定於磁化固定層3a之磁化方向的 相反方向。於圖16所示之例中,磁化固定層3a之磁化方向 固定於朝左’磁化基準層3c之磁化方向固定於朝右。 若將固定磁化層製成上述疊層鐵構造,則可使固定磁化 層對於外部磁界之感度降低,因此可抑制由於外部磁界所 造成之固定磁化層的磁化變動,使MTJ元件之安定性提 升。而且,由於從磁化固定層3a及磁化基準層“所漏出之 磁通相互抵銷,因此藉由調整該等之膜厚,可將從固定磁 化層漏洩之磁通抑制在最小。 、。己丨.¾層5係由具有單軸磁性各向異性之強磁導體所組 成,以來自外部的作用可使磁化方向變化,且可將磁化方 向作為貝汛保持。例如該磁化方向對於磁化基準層3c之磁 化方向「平行」亦或「反平行」,分別作為「〇」及「1」 之貝讯§己憶。於磁化基準層3c與記憶層5之間,設置有非 磁之薄絕緣層之通道絕緣層4,藉由磁化基準層3c '通道 137416.doc •18· 201003651 絕緣層4及記憶層5形成磁性通道接合(而)。 另一方面’於記Μ胞之下部,切基板等之半導體基 板1中,.、工兀件刀離之井區域丄la,作為用以選擇該記憶體 胞之選擇用電晶體1〇而設置有由閉極絕緣膜口、源極電極 1 3、源極區域14、間梅兩代】 、 电極1 5、汲極區域1 6及汲極電極1 7 所組成之MOS型場效電晶體。 如上述’選擇用電晶體1G之閘極電極15係將胞間相連而 形成為帶狀,並兼作為第1列布線之字元線。而且,及極 電極17係連接於作為第2列布線之列布線19,源極電極13 係介隔連接插塞7而連接於自旋注入贿元件2〇之基底層 1另方面,自旋注AMTJ元件2〇之保護層6係連接於設 置在記憶體胞之上部、作為行布線之位元線18。 ° 對期望之記憶體胞之自旋注人贿元件2Q記錄資訊時, 於包含有期望之記憶體胞之列的字元線15施加選擇信號, 使該列之選擇用電晶體1〇全部為開啟(導通)狀態。:合 ;匕3有期望之§己憶體胞之行的位元線1 8與列布線19 — 乜加寫入书壓。其結果,選擇期望之記憶體胞,自 广:極甩流貫流於該自旋注入MTj元件加之記憶層5,將 記憶層5往特定之磁化方向磁化,進行資訊記錄。 此時,首先,自旋注入MTJ元件2〇之磁化 ,方向對於記憶層5之磁化方向處於「反平行」之狀^ 猎由寫入使其反轉為記憶層5之磁化方向對於磁化基準層 ^之磁化方向「平行」之狀態之情況時,如圖9所示^ ""限值以上之電流密度之寫入電流從記憶層5流往磁化基 137416.doc 19 201003651 準層3c。藉此’作為實體而言,臨限值以上之電子密度之 自旋偏極電子流會從磁化基準層3c流往記憶層5,引發磁 化反轉。 相反地’使對於記憶層5之磁化方向處於「平行」狀態 之磁化基準層3c之磁化方向反轉為「反平行」狀態之情況 時,將臨限值以上之電流密度之寫入電流往上述之相反方 向,亦即從磁化基準層3c流往記憶層5 ,作為實體而言, 臨限值以上之電子密度之電子流會從記憶層5流往磁化基 準層3c。 來自自方疋/主入MTJ元件20之資訊讀出係利用tmr 效果來進行。自旋注入MTJ元件2〇之寫入及讀出兩者均利 用。己隐層5中之電子、與貫流該層之自旋偏極電流之相互 作用’頃出係於自旋偏極電流之電流密度小的區域進行, 寫入係於自旋偏極電流之電流密度大、超過臨限值之區域 進行。 此外,磁化基準層3c係為了於記錄動作中,使磁化不會 反轉或不安定化,與PtMn、IrMn等反強磁體組合而固定磁 化方向、使用CoPt等頑磁性大的材料、加工為大於記憶層 5之面積而使用或藉由外部磁場往特定方向磁化均可。 磁化基準層3c作為單獨的強磁體層,或如圖b所示, 隔崎之非磁金屬所組成之中間層3b而與磁化固定層33 平打地磁性結合均可。磁化基準層3e之磁化為面内磁化 垂直磁化均可。而B ^ ^ 而且,磁化基準層3c配置於記憶層5之 側、配置於上側或者配置於上下均可。 137416.doc •20· 201003651 通道絕緣層4宜由氧化物或氮化物等之陶瓷材料組成。 特別若作為通道絕緣層4設置氧化鎂Mg〇層,於磁化基準 層3c及s己憶層5之至少通道絕緣層4側設置層,則可 取得較大之磁性電阻變化率’因此較適宜。 圖1係表不根據實施型態丨之磁性記憶體元件之記錄方法 之寫入脈波列之例之曲線圖。於實施型態i,於記錄丨個資 Λ時,於主脈波後,施加脈波高與主脈波相同、脈波寬比 主脈波短之副脈波。主脈波及副脈波為電壓控制、電流控 制、亦或電力控制均可。 圖1 (1)係表示於1個主脈波後施加丨個副脈波之情況。主 脈波係與以往以單一脈波進行寫入之情況相同,其為具有 足以記錄資訊之脈波高及脈波寬之脈波。該情況下,如前 述,對具有數百Mbit之容量之自旋力矩MRAM記憶體晶片 之實際寫A ’係考慮到自旋注人MTj元件之反轉臨限值之 偏差或起因於電晶體及布線之反轉臨限值之偏差等,施加 甚大於反轉臨限值之平均值之寫入脈波。其結果,出現寫 入脈波越大,反而寫入錯誤率越增加之高記錄電屋錯誤。 於以往藉由單一脈波所進行之寫入,由於藉由上述主脈 波進行寫入而產生之寫入錯誤未修正而原樣成為結果,因 此寫入錯誤率高。而且,寫入時對於外部磁場之耐受性 低。相對於此,於本實施型態,於主脈波後,施加具有超 過反轉臨限值之脈波高之副脈波,因此以藉由副脈波所進 仃之寫入,可修正於主脈波所產生之寫入錯誤的可挹性 高。而且’由於副脈波之脈波寬比主脈波之脈波寬短,因 137416.doc -21 - 201003651 此於錯由副脈波所進行 丁 禺入,難以積存過剝鲊旦 出現上述高記錄電壓# 里,不易 包&錯决。错由以上效 型態之磁性記憶體元件 、根據本實施 _ + 口己錄方法中,寫入錯莩圭、士 , 寫入蚪對於外部磁場之耐受性提升。 、減^、, 此時,於主脈波之太硿, 、;u 末编與副脈波之前端之間,宜钟 π s i-Λ上’更官部·罢< °又置3 更且叹置5如以上之時間間隔。此係 保用以使於藉由主脈波進 一充刀確 時間。 1入所積存之過剩能量散逸之 圖1⑺係表示於"固主脈波後施加2個副脈 求項2’將主脈波、副脈波1及副脈波2作為脈波寬;次: 少之連續3個脈波之組合㈣叙例。該情況下,利用^ 由田j脈波1所進行之寫入及藉由副脈波2所進行之寫入,重 複2次修正,而且越後來施加之脈波,其脈波寬越短,不 易出現由於過剩能量之積存所造成的高記錄電壓錯誤,因 此寫入錯誤率改善之可能性變得更高。 圖2係表示根據實施型態丨之寫入脈波列之例之曲線圖, 其表不有各種主脈波之例。圖2(a)及圖2(b)係於主脈波中 設置停止寫入電力注入之丨ns程度之短停止期間之例。如 圖2(a)所示,即使於主脈波之中間部設置停止期間,仍無 效果’但若如圖2(b)所示,於主脈波之末端附近設置停止 期間’會具有使一定期間内注入之寫入電力有效地逐漸減 少’使上述高記錄電壓錯誤不易出現之效果(參考日本特 願 2008-107768)。 圖2(c)及圖2(d)係施加2個主脈波之例。圖2(c)係表示施 137416.doc -22· 201003651 加脈波高及脈波寬均相等之主脈波丨及主脈波2之情況,圖 2(d)係表示施加脈波高及脈波寬互異之主脈波丨及主脈波2 之情況。無論如何,藉由先行之主脈波丨所進行之寫入均 因藉由後續之主脈波2所進行之寫入而無效,因此未特別 有施加複數主脈波之效果。 圖3係表示根據實施型態丨之寫入脈波列之例之曲線圖, 其表示有各種副脈波之例。圖3(a)係於主脈波後施加2悃, 一般為施加複數副脈波之例,利用藉由副脈波所進行之寫 入,重複2次修正,一般重複複數次,因此寫入錯誤率改 善之可能性變得更高。該情況下,如既已利用圖i(b)所敘 述,期待構成為副脈波之脈波寬漸次減少。另一方面,圖 3(b)及圖3(c)係設置有先行於最後之主脈波之副脈波之 例’未特別有施加此類副脈波之效果。 實施型態2 於實施型態2,主要針對關於請求項丨及2之自旋生入 MTJtl件之記錄方法之其他例說明。 圖4及圖5係表示根據實施型態2之磁性記憶體元 丁 I吕己 〆、法之寫入脈波列之例之曲線圖。於實施型態2,於記 錄1個資訊時,於主脈波後’施加脈波寬與主脈波相同、 皮π比主脈波低之副脈波。主脈波及副脈波為電壓护 制 $流控制、亦或電力控制均可。 圖4係表示於丨個主脈波後施加丨個副脈波之情況,圖4(勾 及⑻係用以說明其效果之說明圖。主脈波係與以往以單一 ’波進行寫入之情況相$,其為具有足以記錄資訊之脈波 137416.doc -23- 201003651 南及脈波寬之脈波。該情況下,如前述,對具有數百Mbit 之容量之自旋力矩MRAM記憶體晶片之實際寫入,係考慮 到自旋注入MTJ元件之反轉臨限值之偏差或起因於電晶體 及布,.泉之反轉g品限值之偏差等,施加甚大於反轉臨限值之 平均值之寫入脈波。 其結果,如圖4⑷所示,於具有平均之反轉臨限值之磁 性記憶體元件,出規於V兹_ + + β i 見於错由主脈波所進行之寫入,比反轉 臨限值過剩之寫入電力注入,反而寫入錯誤率增加之高記 錄電壓錯誤。相對於此,% 於此剡脈波之脈波高雖高於平均之反 轉S品限值,但並非{;卜JJL b 4 -- 非比千均之反轉臨限值顯著高之程度。因 此,若施加副脈波會耷A冷y_ “進仃’修正於主脈波所產生之寫 决。而且,於藉由副脈波 剩能量,因此不易出現上、卜灯之寫入,甚少注入過 旲协目士 阿5己錄電壓錯誤。藉由以上效 果,於具有平均之反轉臨限值之磁性 誤率減少,寫入時對於外邻磁+ 兀件’寫入錯 丁卜口p磁場之耐受性提升。 另-方面,如圖4(b)所示,於反轉臨限值 體元件,會有副脈波之脈波$ ^ 4性記憶 ,,^ 反阿小於反轉臨限值之情洧. §亥磁性S己憶體元件,即使施加副脈波,仍不會進於 副脈波2無效,原樣維持藉由主脈波之寫入仃寫入, 於反轉臨限值高之磁性記悴 、°果。然而, 比反轉臨限值顯著高之”件,主脈波之脈波高並非 值』者问之私度,於藉由主脈波 出現由於過剩能量之注入而寫入錯誤率增加之甚少 錯誤。亦即,藉由主脈波進行寫入錯誤率小=記錄電慶 無修正的必要。 良好寫入, 137416.doc •24· 201003651 從以上結果來看,若利用圖4所示之寫入脈波列,無論 對於具有平均之反轉臨限值之磁性記憶體元件,亦或對於 反轉臨限值高之磁性記憶體元#,均彳進行寫入錯誤率小 之良好寫入。 • 圖5係表示於1個主脈波後施加2個副脈波,對應於請求 • 項2,將主脈波、副脈波丨及副脈波2作為脈波高漸次減少 之連續3個脈波之組合而構成之例。該情況下,如圖5(勾所 〇 示,對於具有平均之反轉臨限值之磁性記憶體元件,利用 藉由副脈波1所進行之寫入來進行修正’與圖4(a)所示之情 況具有同樣效果。副脈波2為無效。如圖5(b)所示,於反轉 臨限值高之磁性記憶體元件,與圖4(b)所示之情況相同, 主脈波之脈波高並非比反轉臨限值顯著高之程度,藉由主 脈波進行良好寫入,無修正的必要。而且,如圖5(c)所 示,對於反轉臨限值低之磁性記憶體元件,利用藉由副脈 波1所進行之寫入及藉由副脈波2所進行之寫入,重複2次 Cj 么 而且越後來她加之脈波,越不易出現由於過剩能量 注入所造成之高記錄電壓錯誤,因此寫入錯誤率改善之可 能性變得更高。 . 從以上結果來看’若利用圖5所示之寫入脈波列,相較 於利用圖4所示之寫入脈波列之情況,可進行進一步寫入 錯誤率更小之良好寫入。 [實施例] 於實施例中,於包含有自旋注入MTJ元件之自旋力矩 MRAM,適用根據本發明之實施型態丨及2之記錄方法,並 137416.doc -25- 201003651 驗證本發明之效果。實施例1及2係作為請求 w貝3〜5之根撼 的貫驗,貫施例4係作為請求項2之根據的實驗。每 一 男驗係一 面於元件之長轴方向施加磁場,一面重複進行抹& 錄、再生,並測定寫入錯誤率。施加磁場之方向係與所欲 記錄之磁化方向相反之方向。 人 實施例1 於實施例1 ’對應於根據實施型態丨之磁性記憶體元件之 記錄方法,施加圖1 (”所示之寫入脈波列。所用之自旋力 矩MRAM係包含有由下述層所構成之自旋注入mtj元件 20。 基底層1 :膜厚5 nm之Ta膜; 反強磁層2 :膜厚30 nm之PtMn膜; 磁化固定層3 a :膜厚2nm之CoFe膜; 中間層3b :膜厚0·7 nm之Ru膜; 磁化基準層3 c :膜厚2nm之CoFeB膜; 通道絕緣層4 :膜厚0.8nm之氧化鎂MgO膜; 記憶層5 :膜厚3 nm之CoFeB膜; 保護層6 :膜厚5 nm之Ta膜 旋注入MTJ元件20之俯視形狀係長軸長度為150〜250 短轴長度為70〜85 nm之橢圓形,記憶層5之頑磁性為 140 Oe。 —面於該自旋注入MTJ元件20施加50 〇e之外部磁 場’ 一面接續於脈波電壓0.8 V、脈波寬30 ns之主脈波, 施加脈波電壓〇.8 V、脈波寬W之副脈波。此時,將副脈波 之脈波見W、及主脈波之末端與副脈波之前端之間之脈波 137416.doc -26- 201003651 間隔D予以各種改變,調查該等與寫入錯誤率之關係。 圖6係表示施加有脈波寬%為丨〜3〇 ns之副脈波的情況下 之寫入錯誤率與脈波間隔0之關係之曲線圖。從圖6可得知 2種不同趨勢。亦即,於作為副脈波利用脈波寬撕為1 μ之 • 脈波之情況下,在脈波間隔D為1 ns之情況時,錯誤率改 . 善效果顯著,若脈波間隔D超過5 ns,幾乎無改善效果。 另一方面,於作為副脈波利用脈波寬%為2 或3 μ之 脈波之情況下,在脈波間隔D為3 ns以上,更期待為5 ns以 上之情況時,藉由本發明之錯誤率改善效果顯著。若作為 副脈波利用脈波寬W為5 ns以上之脈波之情況下,改善效 果邊小,右副脈波之脈波寬w與主脈波之脈波寬相同而為 30 ns,完全未見有改善。 實施例2 於貝把例2對應於根據實施型態2之磁性記憶體元件之 記錄方法,施加圖4所示之寫入脈波列。所用之自旋力矩 〇 MRAM係與實施例1所用之自旋注入MTJ元件20具有相同 之層構成,包含有記憶層5之頑磁性為125 〇e之自旋生入 • 簡元件2G。—面於該自mMTJ元件20施加5G 〇e之外 . 部磁場’ 一面接續於脈波電壓0.9 V、脈波寬30 ns之主脈 波’施加脈波電壓V、脈波寬30 ns之副脈波。此時,將副 脈波之脈波a £ V、及主脈波之末端與副脈波之前端之間 之脈波間隔D予以各種改變,調查該等與寫入錯誤率之關 係。 圖7係表不一面於1〜ns之範圍内改變脈波間隔D,一 137416.doc -27- 201003651 面=查寫人錯誤率及主脈波與副脈波之脈波電壓比之關係 °果的曲線圖。雖未如圖6程度明確,但於圖7認為亦右 2種不同趨勢。 $ 於脈波間隔D設為3 ns以卜夕g -w τ M a- r j, 门 ns M上之情況下,僅於主脈波與副p is an implementation example 1, and is mainly directed to an example of a recording method of the spin injection MTJ element of the claims 1 to 3. Figs. 15 and 16 show the structure of the memory cell of the spin torque mram used in the present embodiment and the configuration of the spin injection MTJ element. Fig. 15 is a view showing an MRAM in which a magnetization reversal is performed by spin injection of a 2Mtj element (hereinafter referred to as a spin injection MTJ element), and magnetization inversion by spin injection is used (hereinafter referred to as self). Partial perspective view of one example of the rotational moment mram)2 configuration. In the spin torque mram, the word line 15 as the column Q wiring and the bit line 18 as the row wiring are arranged in a matrix, and one spin injection element is disposed at the position of each of the % of the parent points. , • Forms a memory cell equivalent to 1 bit. Fig. 15 shows four parts of memory cells. In the lower semiconductor substrate 丨1, a selection transistor 1 to be described later is formed in each of the memory cells, and the word line 15 also serves as a gate electrode for the selection transistor 1A. Further, the non-polar region 16 is selected from the left and right in the figure, and is commonly formed by the f crystal. The column wiring 19 is connected to the sigma-polar region 16. Fig. 16 is a partial cross-sectional view showing the configuration of the memory cell of the spin torque MRAM 137416.doc 201003651. In the central portion of the memory cell, a base layer 1 'antiferromagnetic layer 2, a magnetization fixed layer 3a, an intermediate layer 3b, a magnetization reference layer 3c, a channel insulating layer 4, a memory layer 5, and a protective layer are sequentially laminated from the lower layer. Each of the layers 6 is formed with a spin injection MTJ element 20. The magnetization fixed layer 3a, the intermediate layer 3b, and the magnetization reference layer 3c are laminated on the antiferromagnetic layer 2 to constitute a fixed magnetization layer as a whole. The magnetization direction of the magnetization fixed layer 3a composed of a strong magnetic conductor is fixed by the antiferromagnetic layer 2. Similarly, the magnetization reference layer 3c composed of a strong magnetic conductor forms an antiferromagnetic bond with the magnetization fixed layer 33 via the intermediate layer 3b of the nonmagnetic layer. As a result, the magnetization direction of the magnetization reference layer 3c is fixed in the opposite direction to the magnetization direction of the magnetization fixed layer 3a. In the example shown in Fig. 16, the magnetization direction of the magnetization fixed layer 3a is fixed to the magnetization direction of the leftward magnetization reference layer 3c to the right. When the fixed magnetization layer is formed into the laminated iron structure, the sensitivity of the fixed magnetization layer to the external magnetic boundary can be lowered. Therefore, the magnetization fluctuation of the fixed magnetization layer due to the external magnetic boundary can be suppressed, and the stability of the MTJ element can be improved. Further, since the magnetic flux leaked from the magnetization fixed layer 3a and the magnetization reference layer cancel each other, the magnetic flux leaking from the fixed magnetization layer can be suppressed to the minimum by adjusting the film thicknesses. .3⁄4 layer 5 is composed of a strong magnetic conductor having uniaxial magnetic anisotropy, which can change the magnetization direction by external action, and can maintain the magnetization direction as a beryllium. For example, the magnetization direction is for the magnetization reference layer 3c. The magnetization direction is "parallel" or "anti-parallel", respectively, as "〇" and "1". Between the magnetization reference layer 3c and the memory layer 5, a channel insulating layer 4 of a non-magnetic thin insulating layer is provided, and the magnetic layer is formed by the magnetization reference layer 3c' channel 137416.doc •18·201003651 insulating layer 4 and memory layer 5. Channel engagement (and). On the other hand, in the semiconductor substrate 1 of the lower portion of the cell, the substrate is cut, and the well region is separated from the well region, and is set as the selection transistor 1 for selecting the memory cell. There is a MOS type field effect transistor composed of a closed-electrode insulating film port, a source electrode 13 , a source region 14 , a two-phase source, an electrode 15 , a drain region 16 and a drain electrode 17 . The gate electrode 15 of the above-mentioned 'selective transistor 1G' is formed by connecting cells to each other to form a strip shape, and also serves as a word line of the first column wiring. Further, the electrode electrode 17 is connected to the column wiring 19 as the second column wiring, and the source electrode 13 is connected to the base layer 1 of the spin injection bridging element 2 via the connection plug 7, and The protective layer 6 of the AMTJ element 2 is connected to the bit line 18 which is provided on the upper portion of the memory cell as a row wiring. ° When the information is recorded on the spin-filled component 2Q of the desired memory cell, a selection signal is applied to the word line 15 including the column of the desired memory cell, so that the selection transistor 1 of the column is all Turn on (on) state. : 匕 ; 匕 3 has the desired § 己 体 体 体 体 体 体 体 体 体 与 与 与 与 列 列 列 列 列 列 列 列 列 列 列 列 列As a result, the desired memory cell is selected, and the turbulent flow is applied to the spin-injecting MTj element plus the memory layer 5, and the memory layer 5 is magnetized in a specific magnetization direction for information recording. At this time, first, the magnetization of the MTJ element 2 is spin-injected, and the direction is "anti-parallel" to the magnetization direction of the memory layer 5. The hunting is reversed to the magnetization direction of the memory layer 5 for the magnetization reference layer. When the magnetization direction is "parallel", the write current of the current density above the limit value of the ^ "" limit value flows from the memory layer 5 to the magnetization base 137416.doc 19 201003651 quasi-layer 3c. By this, as a solid, the spin-polar electron flow of the electron density above the threshold will flow from the magnetization reference layer 3c to the memory layer 5, causing magnetization reversal. Conversely, when the magnetization direction of the magnetization reference layer 3c in which the magnetization direction of the memory layer 5 is in the "parallel" state is reversed to the "anti-parallel" state, the current density of the current density above the threshold value is applied to the above. In the opposite direction, that is, from the magnetization reference layer 3c to the memory layer 5, as an entity, an electron flow of electron density above the threshold flows from the memory layer 5 to the magnetization reference layer 3c. The information reading from the 疋/master MTJ element 20 is performed using the tmr effect. Both the writing and the reading of the spin injection MTJ element 2 are used. The interaction between the electrons in the hidden layer 5 and the spin-polar current of the cross-flow is performed in a region where the current density of the spin-bias current is small, and the current is applied to the spin-bias current. It is carried out in areas with high density and exceeding the threshold. Further, in order to prevent the magnetization from being reversed or unstable during the recording operation, the magnetization reference layer 3c is combined with an antiferromagnetic magnet such as PtMn or IrMn to fix the magnetization direction, and a material having a large coercive property such as CoPt is used to be processed to be larger than The area of the memory layer 5 may be used or may be magnetized in a specific direction by an external magnetic field. The magnetization reference layer 3c may be magnetically bonded to the magnetization fixed layer 33 as a separate ferromagnetic layer or as an intermediate layer 3b composed of a non-magnetic metal such as b. The magnetization of the magnetization reference layer 3e is in-plane magnetization and vertical magnetization. Further, B ^ ^, the magnetization reference layer 3c is disposed on the side of the memory layer 5, is disposed on the upper side, or is disposed on the upper side. 137416.doc •20· 201003651 The channel insulating layer 4 should be composed of a ceramic material such as oxide or nitride. In particular, if a magnesium oxide Mg layer is provided as the channel insulating layer 4, and a layer is provided on at least the channel insulating layer 4 side of the magnetization reference layer 3c and the sigma layer 5, a large magnetic resistance change rate can be obtained, which is preferable. Fig. 1 is a graph showing an example of a write pulse train which is not based on the recording method of the magnetic memory element of the embodiment. In the implementation type i, when a single resource is recorded, after the main pulse wave, a secondary pulse wave having the same pulse wave height as the main pulse wave and having a pulse width shorter than the main pulse wave is applied. The main pulse and the secondary pulse wave can be voltage control, current control, or power control. Fig. 1 (1) shows a case where a sub-pulse wave is applied after one main pulse wave. The main pulse wave system is the same as the conventional case of writing with a single pulse wave, and is a pulse wave having a pulse wave height and a pulse width sufficient for recording information. In this case, as described above, the actual write A ' of the spin torque MRAM memory chip having a capacity of several hundred Mbits takes into account the deviation of the inversion threshold of the spin injection MTj component or is caused by the transistor and The deviation of the inversion threshold of the wiring, etc., is applied to the write pulse which is much larger than the average value of the inversion threshold. As a result, the higher the write pulse wave is, the higher the write error rate is, the higher the record house error is. In the conventional writing by a single pulse wave, since the writing error caused by writing by the main pulse is not corrected, the result is as it is, and thus the writing error rate is high. Moreover, the tolerance to external magnetic fields during writing is low. On the other hand, in the present embodiment, after the main pulse wave, the sub-pulse wave having the pulse wave height exceeding the inversion threshold value is applied. Therefore, the main pulse wave can be corrected by the writing of the sub-pulse wave. The write errors generated are highly variable. Moreover, 'because the pulse width of the secondary pulse wave is shorter than the pulse width of the main pulse wave, the 137416.doc -21 - 201003651 is erroneously inserted by the secondary pulse wave, and it is difficult to accumulate the above-mentioned high record. In voltage #, it is not easy to pack & wrong. According to the magnetic memory component of the above-mentioned effect type, according to the method of the present invention, the tolerance of the external magnetic field is improved by writing the wrong 莩, 士, and writing 蚪. , minus ^,, at this time, in the main pulse wave too, ,; u between the end of the end and the side of the auxiliary pulse wave, should be π s i-Λ on the 'more official · stop · ° ° set 3 more And sigh 5 times the above interval. This is used to ensure that the time is corrected by the main pulse. 1 (7) is shown in Fig. 1 (7) after the "main pulse" is applied to the main pulse wave, the secondary pulse wave 1 and the secondary pulse wave 2 as the pulse width; A combination of three consecutive pulse waves (four) a legend. In this case, the writing by the field j pulse 1 and the writing by the sub-pulse 2 are repeated twice, and the pulse wave width is shorter as the pulse wave is applied later. A high recording voltage error due to accumulation of excess energy occurs, so the possibility of improvement in the write error rate becomes higher. Fig. 2 is a graph showing an example of a write pulse train according to an embodiment of the present invention, which shows an example of various main pulse waves. Fig. 2(a) and Fig. 2(b) show an example in which a short stop period in which the write pulse power injection is stopped is set in the main pulse wave. As shown in Fig. 2(a), even if a stop period is provided in the middle portion of the main pulse wave, there is no effect. However, if a stop period is provided near the end of the main pulse wave as shown in Fig. 2(b), there is a certain period of time. The write power to be injected is effectively reduced gradually, so that the above-mentioned high recording voltage error is unlikely to occur (refer to Japanese Patent Application No. 2008-107768). 2(c) and 2(d) show an example in which two main pulse waves are applied. Fig. 2(c) shows the application of 137416.doc -22· 201003651 with the main pulse wave and the main pulse wave 2 with equal pulse wave height and pulse width, and Fig. 2(d) shows the application of pulse wave height and pulse width mutual The case of the main pulse wave and the main pulse wave 2 are different. In any case, the writing by the preceding main pulse 无效 is invalidated by the writing by the subsequent main pulse 2, so that the effect of applying the complex main pulse is not particularly effective. Fig. 3 is a graph showing an example of a write pulse train according to an embodiment of the present invention, which shows an example of various auxiliary pulse waves. Fig. 3(a) is an example of applying 2 悃 after the main pulse wave, generally applying a plurality of sub-pulse waves, and repeating the correction twice by using the writing by the sub-pulse wave, generally repeating the plurality of times, so the writing error The possibility of rate improvement becomes higher. In this case, as described above with reference to Fig. i(b), it is expected that the pulse width of the sub-pulse wave is gradually decreased. On the other hand, Fig. 3(b) and Fig. 3(c) are provided with an example of a sub-pulse wave preceding the last main pulse wave, and the effect of applying such a sub-pulse wave is not particularly applied. The implementation type 2 is in the implementation type 2, and is mainly directed to other examples of the recording method for the requesting item 丨 and the spin-in which the MTJ tl piece is generated. Fig. 4 and Fig. 5 are graphs showing an example of a magnetic memory cell according to the second embodiment of the present invention. In the implementation mode 2, when one piece of information is recorded, after the main pulse wave, the auxiliary pulse wave having the same pulse width as the main pulse wave and the skin π being lower than the main pulse wave is applied. The main pulse and the secondary pulse are voltage protection. The flow control or power control can be used. Fig. 4 shows a case where a sub-pulse wave is applied after one main pulse wave, and Fig. 4 (hook (8) is an explanatory diagram for explaining the effect. The main pulse wave system is compared with the case of writing with a single 'wave. $, which is a pulse wave having a pulse wave width of 137416.doc -23- 201003651 sufficient to record information. In this case, as described above, for a spin torque MRAM memory chip having a capacity of several hundred Mbits The actual writing takes into account the deviation of the inversion threshold of the spin injection MTJ component or the deviation of the inversion product limit of the transistor and the cloth, and the application is much larger than the inversion threshold. The average value is written into the pulse wave. As a result, as shown in Fig. 4 (4), the magnetic memory element having the average inversion threshold value is expressed by V _ + + β i and is found by the main pulse wave. Write, the write power injection is excessive than the reverse margin, and the write error rate is increased by the write error rate. On the other hand, the pulse wave height of the pulse wave is higher than the average reverse S product. Limit, but not {; Bu JJL b 4 -- the degree of reversal of the non-existing reversal threshold is significantly higher Therefore, if the secondary pulse wave is applied, the cold y_ "into" is corrected by the write generated by the main pulse. Moreover, since the energy is left by the auxiliary pulse wave, it is difficult to write the upper and lower lamps. Less injected into the 旲 旲 阿 阿 阿 阿 阿 阿 阿 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The tolerance of the magnetic field of the mouth p is improved. On the other hand, as shown in Fig. 4(b), in the component element of the inversion threshold, there will be a pulse wave of the auxiliary pulse wave, and ^^ is less than Inversion of the threshold value. §Hei magnetic S recall element, even if the auxiliary pulse wave is applied, it will not be invalid in the auxiliary pulse wave 2, and it will remain written by the main pulse wave as it is. The magnetic record is higher than the limit value. However, the "higher than the reversal threshold", the pulse wave height of the main pulse wave is not the value of the private degree, due to the presence of excess energy due to the main pulse wave There is very little error in the write error rate due to the injection, that is, the write error rate by the main pulse wave is small = the record is not corrected. Good write, 137416.doc •24· 201003651 From the above results, if the write pulse train shown in Fig. 4 is used, whether for a magnetic memory element having an average reversal threshold, or Reversing the magnetic memory element # with a high threshold, and writing a good write error rate is small. • Figure 5 shows that two sub-pulses are applied after one main pulse, corresponding to the request • Item 2 The main pulse wave, the auxiliary pulse wave 丨 and the auxiliary pulse wave 2 are combined as a combination of three consecutive pulse waves whose pulse wave height is gradually reduced. In this case, as shown in FIG. 5, for the average inverse The correction of the magnetic memory element having the transition value by the writing by the sub-pulse 1 has the same effect as the case shown in FIG. 4(a). The secondary pulse wave 2 is invalid. As shown in Fig. 5(b), the magnetic memory element having a high inversion threshold is the same as the case shown in Fig. 4(b), and the pulse wave height of the main pulse wave is not significantly higher than the inversion threshold. With good writing by the main pulse, there is no need for correction. Further, as shown in FIG. 5(c), the magnetic memory element having a low inversion threshold is repeated by writing by the sub-pulse 1 and writing by the sub-pulse 2 Two times Cj and the later she added the pulse wave, the more difficult the recording voltage error caused by the excess energy injection, the higher the possibility of improving the write error rate. From the above results, "If the write pulse train shown in Fig. 5 is used, it is possible to perform a better write with a smaller write error rate than in the case of the write pulse train shown in Fig. 4. . [Embodiment] In the embodiment, the spin torque MRAM including the spin injection MTJ element is applied to the recording method according to the embodiment of the present invention, and the method of the present invention is verified by 137416.doc -25-201003651 effect. Examples 1 and 2 are tests for requesting the roots of ws 3 to 5, and Example 4 is an experiment for the basis of claim 2. Each male system applies a magnetic field to the long axis of the component, repeats the erasing & recording, and records the write error rate. The direction in which the magnetic field is applied is in the opposite direction to the direction of magnetization to be recorded. Human Embodiment 1 In Embodiment 1 'corresponding to the recording method of the magnetic memory element according to the implementation type, the write pulse train shown in Fig. 1 (" is applied. The spin torque MRAM used includes the lower The spin formed by the layer is implanted into the mtj element 20. The base layer 1 : a Ta film having a film thickness of 5 nm; the antiferromagnetic layer 2: a PtMn film having a film thickness of 30 nm; the magnetization fixed layer 3 a : a CoFe film having a film thickness of 2 nm Intermediate layer 3b: Ru film with film thickness of 0·7 nm; magnetization reference layer 3 c: CoFeB film with film thickness of 2 nm; channel insulating layer 4: magnesium oxide MgO film with film thickness of 0.8 nm; memory layer 5: film thickness 3 The CoFeB film of nm; the protective layer 6: the film of the Ta film with a thickness of 5 nm is injected into the MTJ element 20 in a plan view having a long axis length of 150 to 250 and a short axis length of 70 to 85 nm, and the magnetization of the memory layer 5 is 140 Oe—the external magnetic field applied to the spin injection MTJ element 20 by 50 〇e is connected to a main pulse wave with a pulse voltage of 0.8 V and a pulse width of 30 ns, and a pulse wave voltage of 88 V is applied. The pulse wave of the width W. At this time, see the pulse wave of the secondary pulse wave and the pulse wave between the end of the main pulse wave and the front end of the auxiliary pulse wave 137416.doc -26- 2 01003651 Various changes are made to the interval D, and the relationship between the write error rate and the write error rate is investigated. Fig. 6 shows the write error rate and the pulse wave interval in the case where the pulse wave width % is applied to the side pulse wave of 丨~3〇ns. A graph of the relationship of 0. Two different trends can be seen from Fig. 6. That is, in the case where the pulse wave is torn as a pulse wave of 1 μ as the auxiliary pulse wave, the pulse wave interval D is 1 ns. In the case of the case, the error rate is changed. The good effect is remarkable. If the pulse interval D exceeds 5 ns, there is almost no improvement. On the other hand, when the pulse wave width is 2 or 3 μ as the secondary pulse wave, the pulse wave is used as the secondary pulse wave. When the pulse wave interval D is 3 ns or more and more desirably 5 ns or more, the error rate improvement effect of the present invention is remarkable. When the pulse wave width W is 5 ns or more as the auxiliary pulse wave, the pulse wave width W is 5 ns or more. In the case where the improvement effect is small, the pulse width w of the right side pulse wave is the same as the pulse width of the main pulse wave and is 30 ns, and there is no improvement at all. Example 2 Example 2 corresponds to the embodiment according to the embodiment. The recording method of the magnetic memory element of 2 applies the write pulse train shown in Fig. 4. The spin force used. The matrix MRAM has the same layer constitution as the spin injection MTJ element 20 used in the first embodiment, and includes a spin-in/simplification element 2G in which the memory layer 5 has a retentive magnetization of 125 〇e. - The surface is from the mMTJ. The element 20 is applied with 5G 〇e. The magnetic field is connected to a pulse wave voltage of 0.9 V and a pulse wave width of 30 ns. The pulse wave voltage V is applied and the pulse wave width is 30 ns. At this time, the pulse wave a £ V of the sub-pulse wave and the pulse wave interval D between the end of the main pulse wave and the front end of the sub-pulse wave are variously changed, and the relationship with the write error rate is investigated. Fig. 7 shows that the pulse interval D is changed within a range of 1 ns, and a 137416.doc -27-201003651 surface = the error rate of the human error and the pulse wave voltage ratio of the main pulse and the secondary pulse wave. The graph. Although not as clear as shown in Fig. 6, in Fig. 7, it is considered that there are two different trends. $ is the pulse interval D is set to 3 ns in the case of 卜 ̄ g -w τ M a- r j, in the case of the gate ns M, only the main pulse and the vice

脈波之脈波電壓比為D 7 L 马0.7以上、1 .〇以下之情況時,出現改 善效果’特別於脈波電麼比為0 8以上、〇·95以下之情況 寺改善效果顯著。有效之副脈波的脈波電壓存在有下 限,係表示正進行藉由副脈波之寫入。 方面於脈波間隔D設為1 ns或2 ns之情況下,於主 脈波與副脈波之脈波電壓比為G_8以上、〇.95以下之情況咱 出現之改善效果,據判係與上述同樣為依據本發明之另 果’脈波電壓比為〇·3以上、Q 95以下,副脈波之脈波電遲 J於反轉L限值之情況時出現之改善效果,據判係依據萬 他發明之效果。 實施例3 於貫施例3,調查根據實施型態〗之磁性記憶體元件之記 錄方法之對於外部磁場之耐受性。所用之自旋力矩mram 係與實施例1所用之自旋注入MTJ元件2〇具有相同之層構 成,包含有δ己憶層5之頑磁性為2丨2 〇e之自旋注入MTJ元 件20。一面於該自旋注入以以元件2〇施加〇〜2〇〇 〇e之外部 磁場’ 一面調查使寫入脈波電壓在〇 5〜〇 7 V之範圍内變化 之情況下之寫入錯誤率。電壓之極性為正。 圖8係以等高線連結上述外部磁場、及寫入錯誤率相對 於寫入脈波電壓分別為〇丨、〇 〇1及〇 〇〇1之位置而表示之 137416.doc •28· 201003651 埘踩圖 石 於1❹宜 場變大’則必須對抗強大的外部磁場以 要更ΪΓ寫入資訊,因此為了維持相同之寫入錯誤率,需 成入脈波電壓。因此’預測上述等高線在圖8會 命壓越大之=線。而且,若外部磁場為一定,則預測脈波 电i越大,舄入錯誤率變得越小。 之==以脈波寬100 ns之單-脈波記錄之比較例 y之、、-口果。該情況下,於外部磁場 :繼如預測成為右升之曲線,但於外部磁二之Ϊ 二盖空’出現即使增大脈波電壓,寫入錯誤率仍未 ::象。於該區域,在外部磁場一定之情況下,脈波 大,寫人錯誤率反而變越大,即引起前述高記錄電 10另—方面’圖8⑷係於脈波寬100 ns之主脈波後,設置 -之脈波間隔後施加脈波寬3 ns之副脈波之情 曲π磁場大的區域為止,上述等高線成為右升之 若外部磁場為一定,則脈波電壓越大,寫入 二人:小。如此’於根據實施型態1之記錄方法,增 之情況時之寫人錯誤率受到改善,可捧大 作範圍,於強大的外部磁場作用之情況下,對於 磁%之耐受性提升。 、 =此於若依據根據實施型態】之磁性記憶體元件之精 錯誤少之記錄動作,於境下’可進行 遮蔽外部磁場之磁性屏蔽之Λ;! ,可減少 —小型化、輕量可將自旋力矩 J37416.doc -29- 201003651 實施例4 於實施例4,調查作為寫入脈波列,利用在脈波寬丨〇 ns 之主脈波組合有各種脈波寬及脈波間ρ南之副脈波之脈波列 之情況下之寫入錯誤率。此時,對應於實施型態丨,主膽 波及副脈波之脈波尚設為相同,後來施加之副脈波之脈波 寬係與先前施加之副脈波之脈波寬相同,亦或短於其。所 用之自旋力矩MRAM係具有與實施例丨所用之自旋注入 MTJ元件20相同之層構成,白冬古^ 曰傅取包3有5己憶層5之頑磁性為13〇When the pulse wave voltage ratio of the pulse wave is D 7 L or more and 0.7 or less, the improvement effect is observed. Especially when the pulse wave power ratio is 0 8 or more and 〇·95 or less, the temple improvement effect is remarkable. The pulse wave voltage of the effective side pulse wave has a lower limit, indicating that the writing by the side pulse wave is being performed. In the case where the pulse wave interval D is set to 1 ns or 2 ns, the improvement effect of the pulse wave voltage ratio of the main pulse wave and the auxiliary pulse wave is G_8 or more and 〇.95 or less, and it is judged that In the same way, according to the invention, the pulse wave voltage ratio is 〇·3 or more, Q 95 or less, and the pulse wave electric delay J of the auxiliary pulse wave is in the case of the inverted L limit. The effect of his invention. [Embodiment 3] In Example 3, the tolerance to external magnetic fields of the recording method of the magnetic memory element according to the embodiment was investigated. The spin torque mram used has the same layer structure as that of the spin injection MTJ element 2A used in the first embodiment, and includes the spin injection MTJ element 20 in which the repulsive layer 5 has a coercivity of 2 丨 2 〇e. Write error rate in the case where the spin pulse is injected to apply the external magnetic field of 〇~2〇〇〇e to the element 2〇 while the write pulse voltage is changed within the range of 〇5 to 〇7 V. . The polarity of the voltage is positive. 8 is a diagram showing the external magnetic field connected by a contour line, and the writing error rate is expressed as a position of 〇丨, 〇〇1, and 〇〇〇1 with respect to the write pulse voltage, respectively. 137416.doc •28· 201003651 埘If the stone becomes larger in the field, then it must fight against the powerful external magnetic field to write information more. Therefore, in order to maintain the same write error rate, the pulse voltage must be formed. Therefore, it is predicted that the above contour line will have a greater life pressure in Fig. 8 = line. Further, if the external magnetic field is constant, the larger the predicted pulse wave energy i, the smaller the intrusion error rate becomes. == Comparative example of single-pulse recording with a pulse width of 100 ns y, , - mouth fruit. In this case, the external magnetic field: as predicted, becomes the curve of the right rise, but after the external magnetic second, the second cover is empty, and even if the pulse voltage is increased, the write error rate is still not the same. In this area, when the external magnetic field is fixed, the pulse wave is large, and the error rate of the writing person becomes larger, that is, the high recording power is caused to be the other side. FIG. 8(4) is after the main pulse wave having a pulse width of 100 ns. After setting the pulse interval of 3 ns, the pulse wave width of 3 ns is applied to the area where the π magnetic field is large, and the contour line becomes right up. If the external magnetic field is constant, the pulse voltage is larger, and the two are written. :small. Thus, according to the recording method of the first embodiment, the error rate of the writer is improved, and the range of the error can be increased, and the tolerance to the magnetic % is enhanced by the action of a strong external magnetic field. = If this is based on the recording operation of the magnetic memory component according to the implementation type, the magnetic recording of the external magnetic field can be shielded in the environment;!, can be reduced - miniaturized, lightweight Spin torque J37416.doc -29- 201003651 Embodiment 4 In the fourth embodiment, the investigation is used as the write pulse train, and the main pulse wave combined with the pulse width 丨〇 ns has various pulse widths and pulse waves. The write error rate in the case of the pulse wave of the secondary pulse wave. At this time, corresponding to the implementation type 丨, the pulse waves of the main bifurcation wave and the auxiliary pulse wave are still set to be the same, and the pulse width of the secondary pulse wave applied later is the same as the pulse width of the previously applied auxiliary pulse wave, or Shorter than it. The spin torque MRAM used has the same layer composition as the spin injection MTJ element 20 used in the embodiment ,, and the white magnetic ^ 曰 取 包 3 有 有 有 有 有 己 己 己 己 己 己 己 己 己

Oe之自旋注入MTJ元件20。一面於兮白妒、+ ®4自旋 >主入MT J元件2 0 使50 〇e之外部磁場作用,—面施, 向把加脈波電壓為1.1 V之主 脈波及副脈波。 1叫λγ Μ順序,表示主脈波及 副脈波之脈波寬及脈波間隔,於最後表示利用該寫入脈波 列之情況下之寫入錯誤率。 [表1 ]The spin of Oe is injected into the MTJ element 20. On one side of the 兮 妒, + ® 4 spin > the main MT J element 2 0 to make the external magnetic field of 50 〇e, the surface application, the main pulse wave and the auxiliary pulse wave with a pulse voltage of 1.1 V. 1 is called λγ Μ sequence, indicating the pulse width and pulse interval of the main pulse and the secondary pulse, and finally indicates the write error rate in the case of using the write pulse train. [Table 1 ]

137416.doc 副 脈波2 (ns) 脈波 間隔3 (ns) 副 脈波3 (ns) 寫入 錯誤率 (%) 4.2xl〇'3 1.3xl0'3 2 2.8xl0'5 1 1 1 7.6xl〇·4 2 1 1 1.8xl〇·5 8.0χ1〇·2 8.1χ1〇-2 Ι.ΙχΙΟ-3 2.2χ1〇'3 1 1·7χ1〇-4 •30. 201003651 比較例1係施加有單一脈波之情況,該情況下之寫入錯 誤率為8.0χ 10·2。比較例2係先行於主脈波而施加有副脈波 之情況。該情況下之寫入錯誤率為81χ1〇-2,與比較例1在 誤差範圍内不變,表示先行於主脈波之副脈波無效。 脈波列1及脈波列2係於主脈波之10⑽後,施加丨個副脈 波之情況,作為該情況下之副脈波之脈波寬係3 ns比2 ns 良好。此係由於對充分進行藉由副脈波之寫入而言,若採 用2 ns,脈波寬可能稍微過短。脈波列3〜5係於主脈波後, 施加2個或3個副脈波之情況,寫入錯誤率較副脈波為^固 之脈波列2更改善。 脈波列6若先行之無效的副脈波除外,主脈波以後之脈 波構成與脈波列2相同,寫入錯誤率亦大致相同。脈波列7 及脈波列8係於主脈波之1 ns後,施加脈波寬為1 ns之短副 脈波之情況’比起比較例1,其寫入錯誤率改善。該情況 下’接連2個脈波寬為1 ns之短副脈波之脈波列8係較副脈 波為1個之脈波列7,其寫入錯誤率更改善。其中,如前 述,於脈波列7及脈波列8之結果’可能重疊有本發明之咬 果及其他發明之效果。 接著,說明以上實施型態之寫入脈波的發生電路。 圖13係表示從1個矩形脈波生成上述實施型態之包入有 主脈波及副脈波之寫入脈波之寫入脈波發生電路之構成 圖。 該寫入脈波發生電路3 0係使用複數緩衝器3 2、3 3、 」4及 複數邏輯電路35、36構成。於寫入脈波發生電路3〇之輪 137416.doc -31- 201003651 端3 1輸入有矩形之脈波信號。輸入於輸入端3 1之矩形之脈 波信號係輪入於或閘邏輯之邏輯電路36之一輸入端、及閘 邏輯之邏輯電路35之非反轉輸入端、及串聯地連接之緩衝 器32、33。於此,串聯地連接之緩衝器32、33係用以生成 副脈波之寬,藉由缓衝器32、33之延遲時間之選定,可選 定任意的副脈波之時間tdl。缓衝器32、33之輸出係輸入 於及閘邏輯之邏輯電路35之非反轉輸入端。及閘邏輯之邏 輯電路35之輸出係通過緩衝器34而輸入於或閘邏輯之邏輯 電路36之另一輸入端。於此,缓衝器34係生成主脈波及副 脈波之間之時間td2 ’藉由緩衝器34之延遲時間之選定, 可設定任意的時間td2。然後,藉由或閘邏輯之邏輯電路 36,獲得以主脈波及副脈波所構成之寫入脈波,並從寫入 脈波發生電路30之輸出端37輸出。 圖14係表示使用波形記憶體及D/A轉換電路所生成之 入脈波之寫入脈波發生電路4〇之構成之圖。於波形記億 41儲存有以主脈波及副脈波所構成之寫入脈波之波形 料。寫广脈波之波形資料係將可從2n階段中選擇輸出位 之N位兀作為旧% ’以複數字元之時間序列資料構成。 波形記憶體4】設置有讀出用u個琿,該等⑽埠係㈣ 轉換電㈣之Ν個輸人端分別連接。d/a轉換電路㈣ 由波形§己憶體41,將駕入晰、、由+ 舄入脈波之波形資料於每N位元之 料(1字元)輸入’轉換為類比 碰轉換電㈣以例如梯作為以脈波輸出 例如梯狀電阻電路等構成。藉由使 此類寫入脈波發生電路, 门目由度獲得寫入脈波之 137416.doc -32· 201003651 形,可容易且以高自由度獲得上述各實施型態之寫入脈 波。 此外,於圖8之例中,為了可從23階段中決定輸出位 準,將1字元之位元數N設為「3」,但本發明不限定於此。 以上,根據實施型態說明本發明,但本發明不受該等例 任何限制,於不脫離發明主旨之範圍内當然可適宜地變 更。 [產業上之可利用性] 若依據本發明,可實現一種改善寫入時之過渡特性,寫 入失敗少,寫入電流密度之臨限值小,可高積體化、高速 化及低消耗電力化之自旋注入磁化反轉型mtj元件,可對 小型、輕1且低價格之非揮發性記憶體之實用化做出貢 獻。 、 【圖式簡單說明】 圖1係表示根據本發明之實施型態丨之磁性記憶體元件之 §己錄方法之寫入脈波列之例之曲線圖; 圖2(a)〜(d)係表示同樣磁性記憶體元件之記錄方法之寫 入脈波列之例之曲線圖; 圖3(a)〜(c)係表示同樣磁性記憶體元件之記錄方法之寫 入脈波列之例之曲線圖; 圖4(a)、4(b)係表示根據本發明之實施型態2之磁性纪憶 體几件之記錄方法之寫入脈波列之例之曲線圖; 圖5(a)〜(c)係表示同樣磁性記憶體元件之記錄方法之寫 入脈波列之例之曲線圖; 137416.doc -33- 201003651 、、圖6係表示本發明之實施例1之磁性記憶體元件之記錄方 去之寫入錯誤率與脈波間隔之關係之曲線圖; 、圖7係表不本發明之實施例2之磁性記憶體元件之記錄方 法之寫入錯誤率與副脈波之高度之關係之曲線圖; —圖8(a) 8(b)係表不依據本發明之實施例3之磁性記憶體 一之°己錄方去之對於外部磁場之耐受性之曲線圖; 圖^係表*MT;元件之基本構造及其記憶資訊之讀出動 °兒月圖(a) ’及表不由MTJ元件所組成之mram之記憶 月丑胞之構造之一例之部分立體圖(b); 系表示專利文獻2所示之自旋力矩MRAM之構造之 部分立體圖; 圖11係表示同樣由自旋注〜ΜΊ^件所組成之自旋力矩 MRAM^ ^ ^ ^ ^ ^ ^ ^ ^ ^ . 圖12係表示寫入脈波電壓與寫入錯誤率之關係之曲線 圖; 圖13係表示從!個矩形脈波生成上述實施型態之包含有 皮及d脈波之寫入脈波之寫入脈波發生電路之構成之 圖; '圖14係表不使用波形記憶體及d/a轉換電路生成寫入脈 波之寫入脈波發生電路之構成之圖; 圖15係表不關於本發明之實施型態之自旋力矩mram之 記憶體胞之構造之部分立體圖;及 _係表示關於本發明之實施型態之自旋注入元件 之構成之剖面圖。 137416.doc -34- 201003651 【主要元件符號說明】 1 基底層 2 3 a 3b 3c 4 5 6 7 10 11 11a 12 13 14 15 16 17 18 19 20 21 30, 40137416.doc Secondary pulse 2 (ns) Pulse interval 3 (ns) Secondary pulse 3 (ns) Write error rate (%) 4.2xl〇'3 1.3xl0'3 2 2.8xl0'5 1 1 1 7.6xl 〇·4 2 1 1 1.8xl〇·5 8.0χ1〇·2 8.1χ1〇-2 Ι.ΙχΙΟ-3 2.2χ1〇'3 1 1·7χ1〇-4 •30. 201003651 Comparative Example 1 is applied with a single pulse In the case of waves, the write error rate in this case is 8.0 χ 10·2. Comparative Example 2 is a case where a secondary pulse wave is applied first to the main pulse wave. In this case, the write error rate is 81 χ 1 〇 -2, which is constant within the error range from Comparative Example 1, indicating that the secondary pulse wave preceding the main pulse wave is invalid. The pulse train 1 and the pulse train 2 are applied to the main pulse wave 10 (10), and the sub-pulse is applied. In this case, the pulse width of the sub-pulse is 3 ns better than 2 ns. This is because the pulse width may be slightly too short if 2 ns is used for sufficient writing by the secondary pulse. When the pulse trains 3 to 5 are connected to the main pulse wave and two or three sub-pulse waves are applied, the write error rate is improved as compared with the pulse wave train 2 in which the sub-pulse wave is fixed. Except for the secondary pulse wave which is invalid before the pulse wave train 6, the pulse wave after the main pulse wave is the same as the pulse wave train 2, and the write error rate is also substantially the same. The pulse train 7 and the pulse train 8 are applied to the short pulse wave having a pulse width of 1 ns after 1 ns of the main pulse wave. The write error rate is improved as compared with Comparative Example 1. In this case, the pulse wave train 8 of the short sub-pulse wave having two pulse widths of 1 ns is one pulse wave train 7 of the sub-pulse, and the write error rate is further improved. Here, as described above, the results of the pulse train 7 and the pulse train 8 may overlap the effect of the bite of the present invention and other inventions. Next, a circuit for generating a write pulse wave of the above embodiment will be described. Fig. 13 is a view showing a configuration of a write pulse wave generating circuit for generating an address pulse of a main pulse and a sub-pulse in the above-described embodiment from one rectangular pulse wave. The write pulse wave generating circuit 30 is composed of a plurality of buffers 3 2, 3 3, "4" and a plurality of logic circuits 35 and 36. The wheel pulse wave generating circuit 3 is turned on. 137416.doc -31- 201003651 The end 3 1 input has a rectangular pulse wave signal. The rectangular pulse signal input to the input terminal 31 is input to one of the input terminals of the logic circuit 36 of the OR gate logic, the non-inverting input terminal of the logic circuit 35 of the gate logic, and the buffer 32 connected in series. 33. Here, the buffers 32, 33 connected in series are used to generate the width of the sub-pulse, and the time tdl of the arbitrary sub-pulse can be selected by the selection of the delay times of the buffers 32, 33. The outputs of the buffers 32, 33 are input to the non-inverting input of the logic circuit 35 of the AND gate logic. The output of the logic circuit 35 of the AND gate logic is input through buffer 34 to the other input of the logic circuit 36 of the OR gate logic. Here, the buffer 34 generates the time td2' between the main pulse wave and the sub-pulse wave by the delay time of the buffer 34, and can set an arbitrary time td2. Then, the write pulse wave composed of the main pulse wave and the sub pulse wave is obtained by the logic circuit 36 of the OR gate logic, and is output from the output terminal 37 of the write pulse wave generating circuit 30. Fig. 14 is a view showing the configuration of the write pulse wave generating circuit 4A of the pulse wave generated by the waveform memory and the D/A conversion circuit. The waveform is stored in a waveform of a write pulse composed of a main pulse and a sub-pulse. The waveform data of the wide pulse wave can be selected from the 2n stage to select the N bit of the output bit as the old %' to form the time series data of the complex digital element. The waveform memory 4 is provided with u 珲 for reading, and the input terminals of the (10) ( (4) conversion electric power (4) are respectively connected. d/a conversion circuit (4) From the waveform § Remembrance 41, the waveform data that is driven into the clear, and + into the pulse wave is input into the material of each N-bit (1 character) and converted into analog-to-digital conversion (4) For example, a ladder is used as a pulse wave output such as a ladder resistor circuit. By writing such a pulse wave generating circuit, the gate pulse is obtained by the write pulse wave 137416.doc -32· 201003651, and the write pulse of each of the above embodiments can be obtained easily and with a high degree of freedom. Further, in the example of Fig. 8, in order to determine the output level from the 23rd stage, the number N of the 1-character bits is set to "3", but the present invention is not limited thereto. The present invention has been described above on the basis of the embodiments, but the present invention is not limited thereto, and may of course be appropriately changed without departing from the spirit of the invention. [Industrial Applicability] According to the present invention, it is possible to improve the transient characteristics at the time of writing, and the writing failure is small, the threshold of the writing current density is small, and the integration, the speed, and the low consumption can be achieved. The spin-injected magnetization inversion type mtj device for electric power can contribute to the practical use of small, light, and low-priced non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a graph showing an example of a write pulse train of a magnetic memory element according to an embodiment of the present invention; FIG. 2(a) to (d) A graph showing an example of a write pulse train of a recording method of the same magnetic memory element; and FIGS. 3(a) to 3(c) are diagrams showing an example of a write pulse train of the recording method of the same magnetic memory element. 4(a) and 4(b) are graphs showing an example of a write pulse train of a recording method of several magnetic memory elements according to an embodiment 2 of the present invention; Fig. 5(a) ~(c) is a graph showing an example of a write pulse train of the recording method of the same magnetic memory element; 137416.doc -33-201003651, and Fig. 6 shows a magnetic memory element of the embodiment 1 of the present invention. A graph of the relationship between the error rate and the pulse interval of the recording side; and FIG. 7 shows the writing error rate and the height of the auxiliary pulse wave of the recording method of the magnetic memory element of the second embodiment of the present invention. A graph of the relationship; - Fig. 8(a) 8(b) shows a magnetic memory according to the third embodiment of the present invention. The graph of the tolerance of the recording to the external magnetic field; Figure ^ is the table *MT; the basic structure of the component and the reading of the memory information. (a) 'and the mram composed of MTJ components A partial perspective view of a structure of a memory ugly cell (b); a partial perspective view showing a structure of a spin torque MRAM shown in Patent Document 2; and FIG. 11 is a view showing a same composition of a spin note. Spin torque MRAM^ ^ ^ ^ ^ ^ ^ ^ ^ ^ . Figure 12 is a graph showing the relationship between the write pulse voltage and the write error rate; Figure 13 shows the slave! The rectangular pulse wave generates a configuration of the write pulse wave generating circuit including the write pulse wave of the skin and the d pulse wave in the above embodiment; 'Fig. 14 shows that the waveform memory and the d/a conversion circuit are not used. FIG. 15 is a partial perspective view showing a structure of a memory cell of a spin torque mram according to an embodiment of the present invention; and FIG. 15 is a partial perspective view showing a structure of a memory cell of a spin torque mram according to an embodiment of the present invention; A cross-sectional view showing the configuration of a spin injection element of an embodiment of the invention. 137416.doc -34- 201003651 [Description of main component symbols] 1 Base layer 2 3 a 3b 3c 4 5 6 7 10 11 11a 12 13 14 15 16 17 18 19 20 21 30, 40

反強磁層 磁化固定層 中間層 磁化基準層 通道絕緣層 記憶層 保護層 連接插塞 選擇用電晶體 半導體基板 井區域 閘極絕緣膜 源極電極 源極區域 閘極電極 >及極區域 汲極電極 位元線 列布線 自旋注入磁化反轉MTJ元件 元件分離構造 寫入脈波發生電路 137416.doc -35-Antiferromagnetic layer magnetization fixed layer intermediate layer magnetization reference layer channel insulation layer memory layer protection layer connection plug selection transistor semiconductor substrate well region gate insulating film source electrode source region gate electrode > and polar region bungee Electrode bit line column wiring spin injection magnetization inversion MTJ element element separation structure write pulse wave generation circuit 137416.doc -35-

Claims (1)

201003651 七、申請專利範圍: 1. 一種磁性記憶體元件之記錄方法,該磁性記憶體元件至 少包含:記憶層’其係包含有強磁導體,磁化方向可變 化,將資訊作為磁髀夕路几士上, 之磁化方向保持;及基準磁化層, 其對於前述記憶層介隔絕緣層而設,包含有強磁導體, 磁化方向固定而為磁化方向之基準;且藉由通過前述絕 緣層而流於前述記憶層與前述基準磁化層之間之電流進 行資訊的記錄; 於記錄1個資訊時,朝同向施加m以上之主脈波幻 個以上之副脈波; 於前述1個以上之主脈波後,施加1個以上之前述則脈 波; 7把加於則述主脈波後之副脈波為符合脈波寬比前述 主脈波短之脈波、亦或脈波高比前述主脈波低之脈波之 至少一條件之脈波。 2·如請求項1之磁性記憶體元件之記錄方法,其中於包含 月J述1個以上之主脈波及其後施加之前述1個以上之前述 副脈波之脈波列中,至少設置一組連續3個脈波之纟且合 且為脈波寬及脈波高之至少一方漸次減少之組合。 3.如請求項1之磁性記憶體元件之記錄方法,其中於前述i 们以上之主脈波之末端與其後施加之前述1個以上之前 述副脈波之前端之間,設置3 ns以上之時間間隔; (其中,脈波之末端及前端分別係脈波之下降及上升中 阿度成為脈波高之最大值之一半的位置;以下亦同)。 137416.doc 201003651 4.如請求項1或2之磁性記憶體元件之記錄方法,其中包含 前述1個以上之主脈波及其後施加之前述i個以上之前述 副脈波之脈波列中,於任意選擇之連續2個脈波之組合 中,令後脈波為符合脈波寬為2 ns以上1〇⑽以下、亦或 脈波高為前脈波之0.7倍以上〇 95倍以下之至少一條件之 脈波,且於則脈波之末端與後脈波之前端之間設置5 w 以上之時間間隔。 5. 6. 如π求項1或2之磁性記憶體元件之記錄方法,其中包含 有钔述1個以上之主脈波及其後施加之前述1個以上之前 述釗脈波之脈波列中,⑤#意選擇之連續2個脈波之組 口中後脈波符合脈波寬為3 ns以下、亦或脈波高為 前脈波之0.8倍以下之s + I主v —條件’且令前脈波之末端與 後脈波之前端之時間間隔小於5 ns。 士月求員1或2之磁性記憶體元件之記錄方法,其中包含 有前述1個以上之主日ρΏ u _ 脈波及其後施加之前述1個以上之前 这田)脈波之脈波列中,於任意選擇之連續2個脈波之組 °中H皮付合脈波寬為3 ns以下、亦或脈波高為 前脈波之0.95倍以下 卜之至v —條件,且令前脈波之末端 與後脈波之前端之時間間隔為小於5ns。 137416.doc201003651 VII. Patent application scope: 1. A magnetic memory component recording method, the magnetic memory component at least comprising: a memory layer comprising a strong magnetic conductor, the magnetization direction can be changed, and the information is used as a magnetic circuit And a reference magnetization layer, wherein the reference magnetization layer is provided for the memory layer isolation layer, comprising a strong magnetic conductor, the magnetization direction being fixed and being the reference of the magnetization direction; and flowing through the insulating layer Recording the current between the memory layer and the reference magnetization layer; when recording one piece of information, applying more than m of the main pulse wave of more than m to the same direction; and one or more of the main pulse waves Thereafter, one or more of the aforementioned pulse waves are applied; 7 the auxiliary pulse wave applied to the main pulse wave is a pulse wave having a pulse width wider than the main pulse wave, or a pulse wave having a lower pulse wave than the main pulse wave The pulse of at least one condition of the wave. 2. The method of recording a magnetic memory device according to claim 1, wherein at least one of the pulse waveforms including the one or more main pulse waves of the month J and the one or more of the auxiliary pulse waves applied thereafter is set. A combination of three consecutive pulse waves and a combination of at least one of a pulse width and a pulse height is gradually reduced. 3. The method of recording a magnetic memory device according to claim 1, wherein a time of 3 ns or more is set between an end of the main pulse wave of the above i or more and a front end of the one or more of the sub-pulse waves applied later. Interval; (wherein, the end of the pulse wave and the front end are respectively the drop of the pulse wave and the position where the Ada is one of the maximum values of the pulse wave height; the same applies hereinafter). The method for recording a magnetic memory device according to claim 1 or 2, wherein the one or more main pulse waves and the pulse wave train of the one or more of the sub-pulse waves applied thereafter are included in In a combination of two consecutively selected pulse waves, the posterior pulse wave is at least one condition that the pulse width is 2 ns or more and 1 〇 (10) or less, or the pulse wave height is 0.7 times or more and 95 times or less of the front pulse wave. The pulse wave is set at a time interval of 5 w or more between the end of the pulse wave and the front end of the back pulse wave. 5. 6. The recording method of the magnetic memory element according to the π item 1 or 2, wherein the one or more main pulse waves and the pulse wave train of the one or more of the pulsation waves applied later are included 5# The selected posterior pulse wave of the continuous 2 pulse waves corresponds to a pulse width of 3 ns or less, or the pulse wave height is 0.8 times or less of the pre-pulse wave s + I main v - condition 'and the precursor The time interval between the end of the wave and the front end of the back pulse is less than 5 ns. The method for recording a magnetic memory element of the 1st or 2nd member, wherein the one or more main day ρΏ u _ pulse waves and the one or more of the previous ones before the pulse wave are applied In the group of two consecutive continuous pulse waves, the H-shaped pulse width is 3 ns or less, or the pulse wave height is 0.95 times of the front pulse wave to the v-condition, and the pre-pulse wave is obtained. The time interval between the end of the end and the front end of the back pulse is less than 5 ns. 137416.doc
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