TW201003613A - Output stage circuit and gate driving module using the same and method for controlling scanning line - Google Patents

Abstract

A gate driving module suitable for generating a scanning signal to a scanning line to enable a plurality of pixels coupled to the scanning line is provided. The gate driving module includes an output stage circuit and a compare and feedback unit. The output stage circuit generates the scanning signal to an input terminal of the scanning line according to a clock signal. The compare and feedback unit modulates the waveform of the scanning signal according to the scanning signal in the waveform of an output terminal of the scanning line, and makes the time through each pixel from enabling to disabling approximately to equal. Therefore, the flicker-noise of the display-panel can be reduced and consequently the display-quality of LCD can be promoted by the present invention.

Description

201003613 r 1 i W 23494twf.doc/n IX. Description of the invention: [Technical field to which the invention pertains] The invention relates to a method for controlling a wheel-out stage circuit, a gate drive module, and a field line, and in particular The output stage circuit of the ^^^^ waveform of the adjustable-scanning line and the gate driving module and the control method of the scanning line using the same. [Prior Art] n. With the improvement of semiconductor technology, liquid crystal display (Liquid Cry has low power consumption, light weight, high resolution, color miscellaneous: W and so on. Therefore, liquid crystal display in recent years It has been widely replaced by a hybrid (4) Na _RayTube, CRT) to become the mainstream of the next generation of displays. Figure 1 ###################### Please refer to the book, the book suppresses the display of the 11-dimensional structure of the six '..., 冓 10 〇 including the thin film transistor ίο 液晶 液晶 CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL The bungee is £, and the parasitic capacitance Cgd. i. The connection between the two-dimensional structure (10) can be clearly seen. The storage of the electricity valley Cs is the design of the shared rr?丨*', and the 'Figure' (Cs 〇n Com_). ,. The day is not for the S-thin film _ _ _ Figure. Please also refer to Figure i and Figure ^·, =, the other - the biggest difference in the structure of the halogen is painting; ^ pixel architecture just on (Cs on Gate The design: The storage valley Cs is in the gate regardless of which of the above-mentioned types of drivers, ^ ^ " (gate rapidly drops to the low level voltage (Lv G) by the standard level voltage (HVg) G ''and the thin film transistor 1〇1 is turned off 5 23494twf.doc/n 201003613 Ν' 'caused by the parasitic electric valley Cgd (c〇UpHng effect), so the thin film transistor 101 has the same extreme d voltage The time will also drop by a voltage level (AVd), the value of which can be expressed as:

C (1) gd c, cs + q where AVG of equation (1) is the high-level scan voltage HVg minus the low-level scan voltage lvg, that is, avg=hvg-LVg. This varying voltage level (ΔVD) is called the feed-through voltage and is not a constant. However, due to the physical properties of the liquid crystal molecules, the liquid crystal capacitance clc has different capacitance values with different gray level cross-voltages. It can be seen that the value of the feedthrough voltage (ΔνΕ>) is different for each pixel of different gray scales (Pixel). In addition, there are parasitic capacitances and parasitic resistances (there are the effects of parasitic electrical parasitic resistance on the scanning line). This delay is difficult to Cdelay), and the value of ΔVG is smaller as the display panel is farther away from the scanning voltage wheel. In addition, the RC delay of each scan line in the display panel is again 1: 1: no plate is the same as the same - line one) the pixel pass voltage of the pixel "the benefit is determined by the previous feed." 6 201003613 V ' a AW 23494twf.doc/n According to the value of the feedthrough voltage cvD), (4) Crane (4) (4) Common voltage (Vcom) 2. Use the scan voltage of 3 or 4 p Technology. The above-mentioned technology 1 is applicable to the material reduction of the material (10) and the payment of the money. It is observed and adjusted by the designer using the optical measurement, and is not corrected by the panel. Minimize the noise in the central part of the display panel. Then, after fixing the above shared voltage v_, fine-tune the gamma correction private voltage outside the source driver to compensate for the difference. The gray-scale cross-voltage causes the liquid crystal capacitance CL to change, and the value of the feedthrough voltage (Δ%) drifts. It is worth mentioning that the above-mentioned technique 1 has minimized the noise of the central portion of the display panel. However, the flicker noise on both sides of the display panel is not completely solved. Figure 3 shows the mode of the above technology i Waveform diagram. Please also show FIG. 1 to FIG. 3 at the same time. The analog waveform diagram of FIG. 3 includes the waveform of the scanning voltage Vg and the waveform of the data voltage Vs (that is, the source terminal of the thin film transistor 101 receives the data provided by the source driver). The voltage), the voltage Vd (that is, the display voltage of the 汲 extreme d of the thin film transistor 101) and the waveform of the common voltage v. Among them, it is apparent from the waveform showing the money vD that the I capacitor Cgd is generated. The feedthrough voltage generated by the consuming effect.

As described above, when the above technique i is applied to alleviate the problem of the feedthrough voltage AVd, 'manual manual measurement must be performed to pay the most common voltage V of the panel in the panel, and each slice is == the same' Therefore, the optimum shared voltage v_ determined by the above and the gamma correction voltage of the fine-tuned source drive externally are not necessarily fully valid for every 7 201003613 w/ vV 23494 twf.doc/n display panel. In addition to this, the above technique 2 is only applicable to the upper 200. Fig. 4 depicts an analog waveform diagram of the above technique 2 (using a driving technique of a voltage). Please refer to FIG. 2 and FIG. 4 at the same time, the scanning voltage % of the white scanning front-strip scanning line Gm.! is the scale branch m is scanned by the in-position scanning red V-), and the scanning line _卩 is the ^ feeding voltage Μ After that, in the scan line 〇 = = 扫 = = LVG1 (4)) raise a voltage level Vp to the low level scan voltage field. In addition, through the voltage coupling effect of the storage capacitor Cs, Gm itself is boosted by the low level scan voltage LVgi (10) - Electricity; the potential field T to, the level scan voltage LVg2 (10), and through the parasitic capacitance ^ voltage P t effect to simultaneously compensate for the drift of the feedthrough voltage. Regarding the above-mentioned technology 2 mentioned above, the boosting voltage level v Yougu Ba Shishi Shi Shi Qiu +.· . P ^ ,,,~8~代甩/翌^ can be calculated according to the formula, the formula As shown below: AVr

Sd__ Cgd +Cs+ CLC

AFn c

Cgd+Cs+Cw △fg AVg (7)(3) However, the designer wants to design the above technique 2 to produce the following problems: L, when the designer wants to design the multi-step of the above technique 2 (for example, 3rd order, 4th order When scanning voltage driving technology, it is conceivable that the design complexity of the gate driver will increase. 2. When the gate driver cannot accurately generate the above-mentioned boosted voltage level vp, then the feedthrough voltage Δν〇 will be insufficiently compensated or overcompensated, thus increasing the uncertainty in design and measurement. 8 201003613 υ / χ ^ 23494twf.doc/n The technology of Di τ t ί must also be used in conjunction with the gamma 垦 外部 微 微 以 以 以 以 以 以 以 以 以 以 以 以 , , , , , , , , , , , , , , , , , , , , The drift of the feedthrough voltage (avd). Lc = The above-mentioned technique 2 does not take into account the feedthrough voltage drift caused by the delay of the transmission line == RC. 〆 提供 提供 提供 种 种 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出The quality of the noodles. The present invention proposes an output stage circuit having an output terminal, and the output stage circuit includes a first transistor, a second transistor, a third transistor, and a body ##曰曰The body of a body / 汲 extreme coupling of the first - voltage, : source / 汲 is extremely coupled to the output of the output stage circuit, and its gate = signal. The second transistor of the second transistor has an output terminal whose output terminal receives the clock signal. No.: Nen: voltage, in which the terminal receives the clock signal, and ί: the end is reduced to the second electrode of the first transistor. The fourth transistor ^ 汲 is extremely coupled to the second source/汲 terminal of the second transistor, and the fourth terminal and the second source are respectively receiving the current control signal and the lighter two money, and the second second core At the first voltage. In addition, a question-driven driver module is proposed, which is suitable for generating scanning signals, so that it can be lightly connected to a plurality of elements on the scanning line. The 'moving module' includes a round-out circuit and a comparison feedback unit. Output stage circuit 9 201003613 \J 1 L ViSJ^L· L· ^ 23494twf.doc/n is coupled to the input end of the scan line, and generates a scan signal to the scan line according to the clock signal. The comparison feedback unit is coupled to the output end of the scan line to generate a current to the output stage circuit according to the waveform of the scan signal at the output end of the scan line, so as to modulate the waveform of the scan signal, so that each pixel is enabled from The time elapsed until the ban is roughly the same. The invention further provides a control method for a scan line, which is suitable for controlling a plurality of pixels coupled to a scan line. The control method includes: inputting a scan signal from the input end of the scan line to respectively enable a plurality of pixels; detecting a waveform of the scan signal at the output end of the scan line; and adjusting the scan according to the waveform of the scan signal at the output end of the scan line The signal makes the time it takes for each pixel to go from being enabled to being disabled. The invention uses the gate driving module to adjust the waveform of the scanning signal of the scanning line so that the voltage waveform of the input end of the scanning line is substantially the same as that of the output terminal, so as to reduce the flicker noise generated by the RC delay. The scanning enable unit then generates a new enable signal to avoid the problem of data overwriting between adjacent scan lines. The above and other objects, features and advantages of the present invention will become more <RTIgt; Embodiments FIG. 5 is a block diagram of a liquid crystal display according to an embodiment of the present invention. Referring to FIG. 5, the liquid crystal display 5 of the present invention includes a plurality of gate driving modules 510-1 to 51 and a panel 520, and the panel 52 includes a plurality of scanning lines 530J to 530_n. Wherein, each of the gate driving modules respectively produces 201003613 υ/iw^ii vV 23494twf.doc/n to the corresponding scan line 'to enable _ on the scan line 5'0 is convenient to be clear' in this embodiment The gate driving module 5HU and the sensing line 530J are taken as an example. As shown in the figure, the ":, 1 circuit of the liquid crystal display of FIG. 5 includes the gate driving module 51 (the U and the scanning lines are not coupled to each other). Alizarin circuit). ~ f

Cj = continued reference to Fig. 6 'Gate drive training' includes an output stage circuit 630 and a comparison feedback unit 650. The output stage circuit 630 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor, and generates a scan shout to the scan line according to the pulse signal VTGI. In this embodiment, The transistor M1 and the third transistor M3: such as a NMOS PMOS transistor, and the second transistor M2 and the fourth transistor M4 may be NMOS transistors. In addition, the first source/汲 terminal of the first transistor M1 is coupled to the first voltage Vdd, and the second source/汲 terminal is coupled to the input end of the scan line 53 and the terminal receives the clock signal Vtci. The first source/drain of the second transistor M2 is lightly connected, and the input terminal of the line 530-1 receives the clock signal tci. The first source/source of the third transistor M3 is coupled to the first voltage plus_the gate terminal receives the clock signal vTcl′ and the second source/汲 terminal is coupled to the first source of the first transistor M2/&gt And extreme. The first source/deuterium terminal of the fourth transistor M4 is coupled to the second source/汲 terminal of the second transistor M2, and the gate 柒 receives the current control signal, and the second source/not the terminal is coupled to the second voltage VEE . Wherein, the voltage value of the second voltage Vee is smaller than the voltage value of the first voltage of 201003613 --.W 23494twf.doc/n. In this embodiment, the comparison feedback unit 650 includes a first comparator=1, a fifth transistor]VI5, a sixth transistor M6, a seventh transistor M7, a battery valley ci, and a first single gain amplifier 652. The eighth transistor M8, the first valley C2, and the chirp gain amplifier 655. The first comparator 651 receives the reference signal Vref, and the negative input receives the voltage Vth of the pixel. The first source/turner terminal of the fifth transistor M5 is coupled to the first 源il source II', and its gate terminal is connected to the wheel terminal of the first comparator 651. The first source of the first Ba body M6 is not connected to the third voltage, the second source/汲 terminal is connected to the first current source n, and the gate terminal thereof is coupled to the output end of the first comparator 651. In addition, the first source/汲 terminal of the seventh transistor M7 is coupled to the third voltage V3, and the gate terminal thereof is coupled to the output end of the first comparator 651. The first capacitor is used to ground the second source/drain terminal of the fifth transistor M5 and the seventh transistor M7. The positive input terminal of the first single gain amplifier 652 is coupled to the second source/汲 terminal of the seventh transistor M7, and the negative input terminal and the output terminal are coupled to each other as a buffer. The first source/turner terminal and the gate terminal of the eighth transistor M8 are coupled to the outputs of the first single gain amplifier 652 and the first comparator 651, respectively. The second power, C2, is used to ground the second source/汲 terminal of the eighth transistor M8. ^ The negative input of the gain amplifier 655 is coupled to the second of the eighth transistor M8. Referring to FIG. 6, the comparison feedback unit 65 further includes a second comparator 653, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor [12, 201003613" "N 23494twf.doc/n.

Mil, a third capacitor C3, a second single gain amplifier 654, a twelfth transistor M12, and a fourth capacitor C4. The positive input terminal of the second comparator 653 is coupled to the output end of the scan line 530-1, and the negative input terminal is coupled to the threshold voltage Vth. The first source/turner terminal of the ninth transistor M9 is coupled to the second current source 12' and its gate terminal is connected to the output terminal of the second comparator 653. In addition, the first source of the tenth transistor M10 / is not extremely lightly connected to the third power C V3 , the first source / not the second current source 12 is extremely exhausted, and the gate terminal thereof is coupled to the second comparator 653 Output. The first source/turner of the eleventh transistor MU is coupled to the third voltage V3, and the gate terminal thereof is coupled to the output terminal of the second comparator 6. The third capacitor C3 is used to couple the ninth transistor %9 and the Mil second source/汲 terminal of the eleventh transistor to the ground. The positive input terminal of the second single gain amplifier 654 is coupled to the second eleventh transistor Mil. The source/汲 is extreme, while the negative input if and the output are lightly connected to each other as a buffer. The first source/turner terminal and the gate terminal of the twelfth transistor M12 are coupled to the input terminals of the second comparator 653 and the second single gain amplifier 654, respectively. One end of the fourth capacitor C4 is grounded, the other end is coupled to the twelfth crystal, the second source/汲 terminal of M12 and the positive input of the high gain amplifier 655 are in the present embodiment, the fifth transistor M5, The eighth transistor, the ninth transistor M9, and the twelfth transistor M12 are, for example, a facet 8 transistor, and the sixth transistor M6, the seventh transistor M7, the tenth transistor M1〇, and the eleventh transistor Mil may be a PMOS transistor, and the current values of the first current source II and the second current source 12 are the same. * Next, the voltage waveform of the reference voltage Vref is set as shown in FIG. 7A, which is a square wave waveform of the distortion of the output end of the scanning line 530-1. Where time τι 13 201003613 υ / ιυυ^ιι vV 23494twf.doc/n = the potential of the voltage vref is greater than the elapsed time of the threshold voltage ν. And the second comparison _ 4 = template 51. : The signal is not driven by the gate. The potential of the scanning signal is greater than the threshold voltage. The output of the second σσ 3 of the first comparator 651 will control the regions of the fifth transistor Μ5 and the ninth thunder body 分别9, respectively. Into your 'When the first comparator' 651 * The second comparator' 653 rounds out the low voltage, then the fifth transistor milk, the eighth transistor _, the ninth Thunder # twelfth transistor The crucibles 12 are all in a closed state, and the sixth electrocautery body 6, the seventh transistor Μ7, the tenth transistor _, and the eleventh body body Mu are all in an on state. At this time, the sixth transistor Μ6* tenth electric=

The currents on the first current source 11 and the second current source 12 are respectively currents. The seventh transistor Μ7 and the eleventh transistor Mil respectively charge the capacitor C1 and the third capacitor C3 to the electricity of the third cake V3, and when the first comparator 651 and the second comparator 653 turn high, At the time of voltage, the fifth transistor M5, the eighth transistor M8, the ninth solar day 1VT9, and the twelfth transistor M12 are all turned on, and -0, the seventh transistor M7, and the tenth transistor M10 And the tenth-transistor is off. At this time, the first capacitor C1 and the third capacitor ^ are respectively charged by the first current source II and the second current source 12, and the increased voltages are I1*T1/C1*I2*T2/C3, respectively, and are linearly charged. ^ 14 201003613 w/ 23494twf.doc/n The form rises as shown in Figure 8Α and Figure 8Β. Since the eighth transistor M8 and the twelfth transistor mu are turned on, the voltage drop across the first capacitor 匚丨 and the third capacitor C3 will be transmitted to the second capacitor via the first and second single gain amplifiers 652, 654, respectively. C2 and the fourth capacitor C4 have voltage waveforms as shown in FIGS. 9A and 9B, respectively. In addition, when the outputs of the first and second comparators 65, 65 3 return to the low level voltage, the voltage drops on the first and third capacitors C1, C3 will return to the voltage of the third voltage V3. Level. The voltages on the second and fourth capacitors C2 and C4 are maintained as V3+(I1*T1/C1) and v3+(I2*T2/c3), respectively, and the negative input and positive input of the high gain amplifier 655 are input. Input. Since the gain of the high-increasing sharp 655 is very large, the high-gain amplification crying 655 has a virtual short-circuit effect on the positive and negative inputs, resulting in positive: then (four) ban = and two: the time that the dan is enabled to disable the T1 Same on the same. 6 (four) four transistor M4 gate extremes to control the fourth electrical output: electricity: : is a constant current source, so that when the scanning line 530-1 discharges: system. Therefore, the "scan line 530" discharges the same point "C", which will suppress the feed current = slope white to reduce the flicker noise of the overall surface. The resulting U-shape occurs, and the green color of Fig. 10 is a timing chart of one way in the time gate Tc while referring to Figs. 6 and 10 as an embodiment of the present invention. When the voltage is low, the first transistor VTO1 is turned on, so that the voltage on the scan line 53〇J is charged; the second guide 15 23494twf.doc/n 201003613 and the second transistor M2 is turned off. The transistor M4 is turned on, then -, six flows through the third transistor milk via the first voltage VDD, and the fourth transistor = the second voltage vEE. At that time, the pulse signal Vtci is converted into a high-level voltage, and the second transistor M1 and the third transistor M3 are turned off, while the second M2 and the fourth transistor M4 are turned on, and the scan line 53 is discharged through the second transistor. M2, the fourth transistor M4 to the second ink Vee, and one of the transistors M4 is a constant current source. Fourthly, in the present embodiment, in order to prevent the voltage of the adjacent two scanning lines 530J from linearly dropping and turning it off, the scanning line 53〇: ^ is raised to the first-parent vDD, and the surface is generated (. reading ρρ_writing ^ Situation. Therefore, the gate drive module 51 (U~51〇_n also includes scanning the moon at 1100', such as ® η, to enable the write-on problem of the production of _. A circuit diagram of a scan enabling unit according to an embodiment of the present invention is shown. Referring to FIG. 11 'This scan enabling unit 1100 includes a third comparison cry 1110, a fourth comparator 112G, an inverter 113 〇, and a gate 114 〇, Comparing the waveform of the scan signal of the input end of the scan line 530-2 and the output end of the scan line 53 〇j to generate an enable signal to determine the enable time of the scan signal. The positive input end of the third comparator mo Lightly connected to the output end of the scan line 530-1, and the negative input end is coupled to the threshold voltage of the pixel. The positive input terminal of the fourth comparator 1120 is coupled to the input end of the scan line 53〇~2, and the negative input end. The vehicle is connected to the threshold voltage. The inverter 113 receives the output of the fourth comparator 1120. The gate 1140 receives the third ratio. The output of the device lu〇 and the inverting ^1130 to generate the enable signal 〇E. ° 16 201003613 ---------W 23494twf.doc/n The success of the tea photo U, first, the scan line The last voltage of the 53G-1, the time voltage waveform VS1 is input to the third comparator 111, and is compared with the threshold voltage Vth received at its negative input terminal to obtain the first time value signal. Then, the first pixel on the scan line 530-2 causes the monthly voltage waveform VS2 to be input to the positive input terminal of the fourth comparator 10(10) and is compared with the threshold voltage Vth received at the negative input terminal thereof. Obtaining a second time value signal X2. In addition, the voltage waveforms VS1, VS2 are cut into four intervals I, II, III, IV (as shown in FIG. U), and the first and second time values are imaginary, X2 also It is also divided into phase_four intervals. Then, analyzing the voltage waveforms of vsi and Guan, it can be seen that the enable signal 〇e must be inserted in the In zone, otherwise there will be repeated writes. Therefore, the second The time value signal χ 2 ^ is obtained by the signal obtained after the inverter 1130 and the first time value signal is simultaneously input to the gate 1140. After the operation, the enable signal 〇E appearing in the third region can be generated. The enable signal 〇E can control the clock signal of the output stage circuit to determine whether the scan signal of the scan line is enabled. From the above description, the preferred operational flow of the present embodiment can be summarized as follows. FIG. 12 is a flow chart showing a method for controlling a scan line according to an embodiment of the present invention. In step S1201, the scan signal 'is input from the input end of the scan line to respectively enable the pixel. In the step, the waveform of the scan signal at the output end of the scan line is detected. In the step, the scanning signal is modulated according to the waveform of the scanning signal at the output end of the scanning line, so that the time elapsed from the enabling to the disabling of each element is substantially the same. 201003613 u Λ w 23494twf.doc/n In the above, in step S1204, the time of the last pixel enable on the scan line is detected, and the first time value signal is obtained. In step S1205, the time of the first pixel enable on the scan line is detected, and the second time value 汛·5 tiger is obtained. In step sl2〇6, the second time value signal is inverted. In step S1207, the first time value signal and the inverted second time value signal are logically ANDed to generate an enable signal. In step si2〇8, it is determined whether the scan signal is enabled according to the enable signal. Then, those skilled in the art can solve the problem of flicker noise and repeated writing of the feedthrough voltage caused by the RC delay in the display by the above-mentioned flowchart and the corresponding circuit. , thereby improving the quality of the LCD display. In summary, the present invention is driven by a gate drive module.

1 line scan signal waveform to reduce because of RC

No-information and elimination of (four) noise problems. A new enabling signal is generated by the scanning unit to avoid scanning lines. , the case of writing. Therefore, the overall picture of the display can be effectively improved. Although the present invention has been disclosed above in the preferred embodiment, it is obvious that those skilled in the art can not make a difference, and can make some changes and reliance on the inside and outside of the wear and tear. Therefore, the scope of the present invention is to be regarded as a scale. ... [Simple description of the diagram] Figure. Figure 1 shows the structure of a conventional thin film transistor liquid crystal display. 18 201003613

sV 23494twf.doc/n Figure Composition. 2 is shown as a conventional thin film transistor liquid crystal display. . ,. Fig. 3 shows the analog waveform of the above technique 1. Fig. 4 shows the analog waveform driving technique of the above technique 2. FIG. 5 is a liquid crystal display showing an embodiment of the present invention. FIG. 6 is a circuit diagram showing an embodiment of the present invention. FIG. 7B is a block diagram of a reference voltage of the embodiment of the present invention. FIG. 7B is a diagram of the waveform of the scan line of the embodiment of the present invention. FIG. FIG. 9B is a voltage waveform diagram of a third capacitor according to an embodiment of the present invention. FIG. 9A is a voltage waveform diagram of a second capacitor according to an embodiment of the present invention.

FIG. 9B illustrates a voltage waveform diagram of the fourth capacitor of the embodiment. FIG. 10 is a timing diagram of a wheel-out stage circuit according to an embodiment of the present invention. 11 is a circuit diagram of a scan enabling unit according to an embodiment of the present invention. FIG. 12 is a flow chart showing a method for controlling a scan line according to an embodiment of the present invention. [Main component symbol description] 100, 200: Alizarin structure 101: Thin film transistor CLc: Liquid crystal capacitor Cs: Storage capacitor 23494twf.doc/n 201003613

\J I X W^~TA X cgd: parasitic capacitance CE : common electrode

Gm, Gw, 530j~530-η: scan line 500: liquid crystal display 510_1~510_n: gate drive module 520: panel 630: output stage circuit 650: comparison feedback unit

M1 to M12: first to twelfth transistors C1 to C4: first to fourth capacitors 651: first comparator 653: second comparator 652: first single gain amplifier 654: second single gain amplifier 655: High gain amplifier 11: first current source 12: second current source Vro: first voltage VEE • second voltage V3: third voltage Vref: reference signal Vtfi: threshold voltage

VtCI, VtC2, VtC3. Clock signal TC: time when the clock signal is low level voltage 20 201003613 υ/ιυυζ^ϋ vV 23494twf.doc/n 1100: scan enable unit 1110: third comparator 1120: fourth Comparator 1130: Inverter 1140: AND gate OE: Enable signal VS1, VS2: Voltage waveform XI: First time value signal X2: Second time value signal S1201~S1208: Scan line control method according to an embodiment of the present invention Step 21

Claims (1)

201003613 υ/iuuzHnvV 23494twf.doc/n X. Patent application scope: The output stage circuit k is an output stage circuit having an output terminal, comprising: ^ a first-transistor whose first source/汲 terminal is coupled to one a first voltage, the second source/汲 is coupled to the output terminal, and the gate terminal receives the two-clock source and the terminal is connected to the output terminal, and the gate is a transistor, and the terminal is received at the extreme end. a third transistor, the first source/turner terminal is coupled to the first voltage, the terminal is connected to the clock signal, and the second source/extreme is lightly connected to the first crystal a second source/deuterium pole; and wherein the first to fourth anode has a first source/turner terminal coupled to the f source/deuterium terminal of the second transistor, and the gate terminal and the fourth transistor of the fourth transistor The two sources/no poles respectively receive a current control signal and are coupled to each other—the second voltage second power is smaller than the first voltage. Wherein &amp; 2. The output stage circuit-electrode as described in claim 1 and the third transistor are weight (10) transistors. The output stage circuit described in claim 1, wherein the second transistor and the fourth transistor are NM〇S (four). 4.- Kind of gate drive module, suitable for the line, so that she can reduce the current-W---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 4 pulse signal generation - scan signal = ^ trace line wheel input, and according to the time to the input line of the child; and 22 201003613 23494twf.d〇c / n U / 1 υ κ / ζ. ^ 1 1 comparison The feedback unit is connected to the waveform of the scan signal at the output end of the scan line to be based on the signal to the output circuit of the wheel, and (4) change: the current-current control 5 - such as - tf can pass substantially the same time . The output stage circuit comprises: a drain driving module, wherein the first, 7^^日日's first source/no extreme light connection, the m source, the source/汲 is extremely coupled to the input power of the scan line a pulse signal; /, reading the extreme receiving end, a third transistor 'its first source / 汲 extreme domain of the first: ==:= number and _ a second voltage, of which 6. As stated in the patent scope 5 The gate driving module, wherein the first transistor and the third transistor are read 电8 transistors., ”二#7. The gate driving module according to claim 5 Wherein the second transistor and the fourth transistor are NM〇s transistors. 8. The gate drive module of claim 4, wherein the comparison feedback unit comprises: ^ 23 201003613 \j / i 'V 23494twf.doc/n a first comparator, which is being wheeled in The terminal receiving-table input receives the threshold voltage of the pixels; Now, while it is negative, a fifth transistor has its first source/汲 terminal coupled to it - its gate terminal receives the output of the first comparator; Le-% source, a sixth transistor, and its first source /汲Extreme coupling - the second source stage is extremely secretive to the first current source, and the axis is the output of the comparator; the ringing (1) is coupled to the 苐-seventh transistor 'its first source level extreme transit gate terminal receives the The output of the first comparator; the second voltage, a first capacitor for grounding the fifth transistor and the second source/汲 terminal; the second of the λ-seven transistors: a single gain amplifier, The positive input is connected to the first source/汲 terminal of the seventh life, and its negative input terminal and output terminal are electrically connected to each other - the eighth transistor, its first source terminal and the Μ | first single gain amplifier and The first comparator is turned out; the knife 妾 § K Kj a second capacitor for the ground of the eighth transistor; and the brother-source/汲 extreme connection-high growth device End to the two source / 汲 extreme. The next day's brother-in-law 9·If you apply for the service drive _&amp; as described in item 8 of the patent application scope, the comparison feedback unit further includes: , , , , , , and - the second comparator 'the positive input terminal Lightly connected to the sweep end, and the negative input terminal is coupled to the threshold voltage; output a ninth transistor, the first source/汲 terminal is coupled to a current source, 24 201003613 υ / W 23494twf.doc /n its gate terminal receives the output of the second comparator; the first-tenth transistor 'its first source/secret is connected to the third voltage, and the second source/no extreme handle is connected to the second current source, and The terminal receives the output of the second comparator; a tenth-transistor's H-th flips the third voltage, and the gate terminal receives the output of the second comparator; - a third capacitor The ninth transistor and the second source/汲 are extremely grounded; the electric day 曰 bottle has a second single increase H, red is, and its negative input end and lose _=' to the first, comparator and The second single gain amplifier is connected to a fourth capacitor, one end of which is grounded, and the second source/汲 terminal of the transistor and the high gain amplification The positive input XXII electrically = younger brother of eight entry two transistors, the ninth transistor and the second member are electrically day NMOS transistor. Ding — The gate drive module described in item 9 of the patent scope, _ shoulder brother, transistor, the seventh transistor, and/or the transistor are all PMOS transistors. The μ electric body and the tenth--===== pole drive the waveform of the scan signal and the ==== time at which the output is enabled. The gate drive module of claim 12, wherein the scan enabling unit comprises: , a mountain and a second comparator, The positive input terminal is coupled to the output end of the scan line, and the negative input terminal is coupled to the threshold voltage of the pixels; * - the fourth comparison ϋ 'the positive input terminal is reduced to the input end of the casting line, and the negative input thereof The terminal is coupled to the threshold voltage; an inverter coupled to the output of the fourth comparator; and an output of the third comparator and the inverter to generate the enable signal. The thread of the line is suitable for controlling the lazy sweep to hide the faint eve of the eve, and the control method includes: some of the scan line of the human input-scanning signal to enable the The waveform of the signal at the output of the scan line; and substantially the same. - the time elapsed from the date of the ban on the ban. 15. If the application of the Scope of the Patent Law, the control of the scan line of the item is generated - the enable signal; and the decision is based on the enable signal. Such as the application of the Yuan brake r bucket ^ to this know the signal. The method of generating the enable signal in the control unit of the scan line of the above-mentioned scan line includes the detection of the last time of the enablement of the element on the scan line, and obtain a 26 23494 twf. Doc/n 201003613 _________w first time value signal; detecting the time of the first pixel enable on the scan line, and obtaining a second time value signal; inverting the second time value signal; and the first The time value signal is logically ANDed with the inverted second time value signal to generate the enable signal. 27