201001170 九、發明說明： 【發明所屬之技術領域】 本發明係有關於快閃記憶體，特別是有關於快閃記憶 體的寫入方法。 【先前技#?】 目前的快閃記憶體(flash memory)有兩種型式，其中之 一為單階單元(Single Level Cell，SLC)記憶體，另一則為多 階單元(Multiple Level Cell, MLC)記憶體。單階單元記憶體 包括多個記憶單元區塊，每一記憶單元區塊包含多個記憶 單元，而每一記憶單元僅可儲存一位元資料，因此單階單 元記憶體所包含的記憶單元區塊稱之為單階單元區塊。多 階單元記憶體亦包括多個記憶單元區塊，每一記憶單元區 塊包含多個記憶單元，但每一記憶單元可儲存多位元之資 料，因此多階單元記憶體所包含的記憶單元區塊稱之為多 階單元區塊。 由於單階單元記憶體之記憶單元僅可儲存一位元資 料’因此單階單元記憶體所能儲存的資料量較低。然而， 單階單元記憶體卻有較快的存取速度及較高的可讀寫次數 (endurance)。可讀寫次數係表示一記憶單元區塊經過多少 次寫入尚不會失效的概略值，用以衡量一記憶體的穩定 度。反之，由於多階單元記憶體之記憶單元可儲存多位元 資料，因此多階單元記憶體所能儲存的資料量較高。然而， 多階單元記憶體卻有較慢的存取速度及較低的可讀寫次 SMI-08-012/9031-A41783-TW/Final 201001170 數口此單階單元記憶體與多階單元記憶體各有不同的 優缺點’需要域线的應財式決定制單階單元記情 體或多階單元記憶體以儲存資料，以達到线的最佳效能。 目前-般的快閃記憶體裝置僅包含單—單階單元 體或多階單71記憶體。若—記憶«置可同時包含單階單 元忑，體與夕P白單元§己憶體，則此種記憶體裝置可以同時 單元記憶體之高存取速度及高讀寫次數的優點以 及夕^早兀記憶體之高資料儲存量的優點，因而其效能優 口：包Γ一單階單元記憶體或多階單元記憶體的記 憶肢衣置H為了發揮單階單元記憶體與多 自的優點’必須有效地同時管理單階單元記憶 ，故這㈣管理方法料今技術急迫需要 【發明内容】 置的τ广在於提供一種快閃記憶體裝 、乍方法’⑽決習知技術存在之㈣，即 憶體裝置必須能區分所儲存之資料的性質，而將資 性質儲存於最適當的記憶财。換句㈣，高存㈣= 貝枓應儲存於單階單元記憶體巾，以發料 尚讀：次數的優點；而低存取頻率之資料應儲存於=二 兀兄fe體中，以發揮其高資料儲存量的優點:夕白早 明提供-種快閃記憶體裝置，以結合單階單 ’本發 階單元記憶體之優點。。於—實 D k'體與多 SMI-08-012/9031-A41783-TW/Final 置包括一單pb軍元⑻，τ詞中亥快閃記'_ 匕栝早Ρ白早7〇(Slngle Level Cell, SLC)記憶體及一多 7 201001170 階單元(MultipleLevelCell，MLc)記憶體。首先 機欲寫入—邏輯區塊位址之一區塊更新 = 該邏輯區塊位扯夕g Φ t ^ 接者，檢查 累毅新錄。當該累毅新次數心 檢查該邏輯區塊位址對應之實 = 才曰向該多階單域憶體之—多階單⑽塊 二否 階單元記憶體;指ϋ該多階單元區塊，自該單 應到該單階單元區塊之二：::免’將忒邏輯區塊位址對 料寫入該單階單元區塊£塊位址’並將該區塊更新資 本發明提供一種快閃記憶體裝置。於一實施 快閃記憶體裝置包括一單階單元(Smgie Levei⑽= 記憶體，-多階單元(MultipleLeveiceii，MLc 體、） 及一控制器。該單階單元記憶體包括多個單階單；區场m 儲存資料。該多階單元$,产雕6 &龙以 存資料。奸制哭接/多階單元區塊以儲 仔貝料幻工制杰接收—主機欲寫一兩 區塊更新資料，檢查是否該邏輯區塊位址之累積更二； 超過-界限值，複檢查該邏輯區塊位址對 ^數 址是否指向該多階單元記憶體之-多階單:厂:體£槐位 積更新次數超過該界限值，且該邏：:塊。當該累 體區塊位址指向該多階軍元區塊時，應之該實 元記億體獅—㈣單元_，將該該f階單 該單階單元區塊之實體區塊位址 塊 入該單階單元區塊。 鬼更新貝科寫 為了讓本發明之上述和其他目的、贿、和優點能更 SMI-08^012/9031 -A41783-TW/Final 8 201001170 明顯易懂，下文特舉數較佳實施例，並配合所附圖示，作 詳細說明如下： 【實施方式】 第1圖為依據本發明之快閃記憶體裝置104的區塊 圖。於一實施例中，該快閃記憶體裝置104為一記憶卡或 一固態硬碟（Solid State Disk)。一主機102藉由快閃記憶體 裝置104儲存資料，並自快閃記憶體裝置104讀取資料。 f 於一實施例中，該快閃記憶體裝置104包括一控制器106， 一單階單元（Single-Level-Cell, SLC)記憶體108，以及一多 階單元(Multiple-Level-Cell, MLC)記憶體110。單階單元記 憶體108包括多個單階單元區塊，每一單階單元區塊包含 多個單階記憶單元，每一單階記憶單元可儲存一位元之資 料。多階單元記憶體110包括多個多階單元區塊，每一多 階單元區塊包含多個多階記憶單元，每一多階記憶單元可 儲存多位元之資料。控制器106耦接於主機102與單階單 ( 元記憶體108及多階單元記憶體110之間，依據主機102 的指令，將主機102傳送的資料儲存或寫入至單階單元記 憶體108及多階單元記憶體110,或自單階單元記憶體108 及多階單元記憶體110讀取資料以傳送回主機102。 第2圖為依據本發明之資料區塊之位址的對應關係的 示意圖。同一資料區塊對不同的裝置會有不同的位址作為 存取該資料區塊的依據。對於主機102而言，主機102係 依據資料區塊的邏輯區塊位址（Logic Block Address, LBA)202以存取該資料區塊。對於單階單元記憶體108而 SMI-08-012/9031-A41783-TW/Final 9 201001170 言，單階單元記憶體108係依據資料區塊的單階單元實體 區塊位址（SLC Physical Block Address, SPBA)21〇 以存取节 資料區塊。對於多階單元記憶體110而言，多階單元記情 體110係依據資料區塊的多階單元實體區塊位址（Mlc Physical Block Address，MPBA)208 以存取該資料區塊。 由於控制器106需作為主機102、單階單元記憶體1 〇8 及多階單元記憶體110之間存取資料的中介者，控制器1〇6 須知道同一資料區塊的邏輯位址（LBA) 202與實體位址 (physical block address，ί>ΒΑ) 204 間的對應關係。此外，由 於記憶體裝置104包含有單階單元實體區塊位址21〇與多 階單元實體區塊位址208兩種實體區塊位置，造成使用 的不便，因此控制器106將單階單元實體區塊:址21〇鱼 多階單元實體區塊位址2〇8皆編排為一系列^ 綱。於-實施例中，單階單元實體區触址⑽先= =元實體區塊位址206,該虛擬多階單元“ 址206被分派到次序在前之實體區塊位址綱， 元實體區塊位址期被分派到次序在後之實體 = 控制器106必須紀錄邏輯區塊位置202盘實體 階單元實體區塊位 ： 塊位址210的對應關係。於-- 靶例中，該控制器1〇6以— 只 202盥與舻卩抬/ 止對應表储存邏輯區塊位置 ，、灵體&塊位置208的對應關係。 罝 3。。二為依據/發明之快閃記憶體裳細 的錢，㈣謂㈣W寫入— SMI-08-012/9031-Α41783-TW/Final 201001170201001170 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to flash memory, and more particularly to a method of writing to a flash memory. [Previous Technique #?] There are two types of flash memory available, one of which is Single Level Cell (SLC) memory and the other is Multi Level Cell (MLC). )Memory. The single-order unit memory includes a plurality of memory unit blocks, each memory unit block includes a plurality of memory units, and each memory unit can store only one bit of metadata, and thus the memory unit area included in the single-order unit memory A block is called a single-order unit block. The multi-level cell memory also includes a plurality of memory cell blocks, each memory cell block includes a plurality of memory cells, but each memory cell can store multi-bit data, and thus the memory cells included in the multi-level cell memory A block is called a multi-level cell block. Since the memory unit of the single-stage unit memory can store only one bit of material, the amount of data that can be stored by the single-stage unit memory is low. However, single-stage cell memory has faster access speeds and higher endurance. The number of readable and writable numbers represents a rough value of how many times a memory cell block has not been written, and is used to measure the stability of a memory. Conversely, since the memory unit of the multi-level cell memory can store multi-bit data, the amount of data that can be stored by the multi-level cell memory is high. However, multi-level cell memory has slower access speed and lower read/write times SMI-08-012/9031-A41783-TW/Final 201001170. This single-order cell memory and multi-level cell memory Each body has different advantages and disadvantages. It is necessary to determine the single-order unit or multi-level unit memory of the domain line to store data to achieve the best performance of the line. Current-like flash memory devices include only single-single-order cells or multi-stage single-seven memories. If the memory-memory includes both the single-order unit 忑, the body and the eve P-white unit § the memory, the memory device can simultaneously have the advantages of high access speed and high read/write times of the unit memory and the evening ^ The advantage of high data storage capacity of early memory, so its performance is excellent: the memory of a single-order unit memory or multi-level unit memory is set to H. In order to exert the advantages of single-order unit memory and multi-self 'It is necessary to effectively manage the single-order unit memory at the same time. Therefore, this (4) management method is urgently needed [invention]. The τ is widely used to provide a flash memory device and a method of 乍 (10). That is, the memory device must be able to distinguish the nature of the stored data and store the property in the most appropriate memory. In other words (4), Gao Cun (4) = Bessie should be stored in a single-stage unit memory towel to the advantage of the number of times the material is read; the data of the low access frequency should be stored in the body of the second brother to play The advantages of its high data storage capacity: Xi Bai Zaiming provides a kind of flash memory device to combine the advantages of single-order single-in-one-order unit memory. . In the real D k 'body and multi-SMI-08-012/9031-A41783-TW/Final set including a single pb military (8), τ words in the fast flash '_ 匕栝 Ρ early white 7 〇 (Slngle Level Cell, SLC) memory and a multi-level 7 201001170 order unit (MultipleLevelCell, MLC) memory. First, the machine wants to write - one of the logical block addresses is updated = the logical block is bit g Φ t ^ Receiver, check the tired new record. When the tired new number of times checks the logical block address corresponding to the real = to the multi-order single-domain memory - multi-order single (10) block two non-order unit memory; refers to the multi-order unit block From the single to the single-order unit block 2:::free 'write the logical block address to the single-order unit block block address' and provide the block update capital invention A flash memory device. The flash memory device includes a single-order unit (Smgie Levei (10) = memory, - multi-level unit (MultipleLeveiceii, MLC body), and a controller. The single-stage unit memory includes a plurality of single-order units; Field m to store data. The multi-level unit $, production of carving 6 & dragon to save information. raped crying / multi-level unit block to store the receipt of the blind material illusion - host to write a two-block update Data, check whether the logical block address is accumulated more than two; exceed the - limit value, check whether the logical block address pair ^ address points to the multi-level cell memory - multi-order single: factory: body £ The number of times of product expansion exceeds the limit value, and the logic:: block. When the location of the tired block points to the multi-order military block, the real element should be the lion lion - (four) unit _, The physical order block of the single-order unit block is inserted into the single-order unit block. The ghost update is written in order to make the above and other purposes, bribes, and advantages of the present invention more SMI-08. ^012/9031 -A41783-TW/Final 8 201001170 It is obvious to understand, the following is a preferred embodiment, and with the accompanying The following is a block diagram of a flash memory device 104 in accordance with the present invention. In one embodiment, the flash memory device 104 is a memory card or a Solid State Disk. A host 102 stores data by flash memory device 104 and reads data from flash memory device 104. f In one embodiment, the flash memory device 104 includes A controller 106, a Single-Level-Cell (SLC) memory 108, and a Multi-Level-Cell (MLC) memory 110. The single-stage unit memory 108 includes a plurality of singles. a unit cell block, each of the single-order unit blocks includes a plurality of single-order memory cells, and each of the single-order memory cells can store one-bit data. The multi-level cell memory 110 includes a plurality of multi-level cell blocks, each A multi-level cell block includes a plurality of multi-level memory cells, and each multi-level memory cell can store multi-bit data. The controller 106 is coupled to the host 102 and the single-order single (meta-memory 108 and multi-level cell memory) Between the bodies 110, according to the instruction of the host 102, the host 1 02 The transferred data is stored or written to the single-stage unit memory 108 and the multi-level unit memory 110, or the data is read from the single-stage unit memory 108 and the multi-level unit memory 110 for transmission back to the host 102. A schematic diagram of the correspondence between the addresses of the data blocks according to the present invention. The same data block has different addresses for different devices as the basis for accessing the data blocks. For the host 102, the host 102 is The data block is accessed according to a logical block address (LBA) 202 of the data block. For single-order unit memory 108 and SMI-08-012/9031-A41783-TW/Final 9 201001170, single-order unit memory 108 is based on the single-order unit physical block address of the data block (SLC Physical Block Address). , SPBA) 21〇 to access the section data block. For the multi-level cell memory 110, the multi-order cell ticker 110 accesses the data block according to the multi-level cell physical block address (MPBA) 208 of the data block. Since the controller 106 needs to act as an intermediary for accessing data between the host 102, the single-stage unit memory 1 〇 8 and the multi-level unit memory 110, the controller 1 〇 6 must know the logical address of the same data block (LBA). ) 202 corresponds to a physical address (physical block address, ί > ΒΑ) 204. In addition, since the memory device 104 includes two physical block locations, a single-order unit physical block address 21〇 and a multi-level unit physical block address 208, causing inconvenience in use, the controller 106 will be a single-order unit entity. Block: Site 21 squid multi-order unit physical block address 2 〇 8 are arranged into a series of ^. In an embodiment, the single-order unit physical area address (10) first == meta-physical block address 206, the virtual multi-order unit "address 206 is assigned to the prior physical block address class, the meta-real area The block address period is assigned to the entity whose order is followed = the controller 106 must record the logical block position 202 disk physical order unit physical block bit: the correspondence of the block address 210. In the target case, the controller 1〇6———— Only the 202盥 and 舻卩// stop correspondence tables store the logical block position, the corresponding relationship between the spirit & block position 208. 罝3. The second is the basis/invention of the flash memory Money, (four) said (four) W write - SMI-08-012/9031-Α41783-TW/Final 201001170
邏輯區塊位址的—F 106檢查該邏輯區° ΐ料(步驟3〇2)。接著，控制器 步驟304)。=止之一累積更新次數（Update -邏輯區塊位址時、二'例中，每當主機1G2要求寫入 該邏輯區塊位址對庫102便將—累積更新次數表中 更新次數表。因而=累積更新次數加一，而維持該累積 該累積更新次數表Γ 3〇4中’控制器106可藉由查詢 數。 而件到該邏輯區塊位址之累積更新次 f 主機過—界限離請），則 輯區塊位址。由；品龙位址被視為高存取頻率的邏 單元記憶體10δ儲;子：的邏輯區塊位址適合㈣ 塊位址對應之-〜「^制器106繼續檢查該邏輯區 體區塊位址係指位址；f驟3〇8)’以判斷是否該實 (步驟於—實施例多階單元區塊 位址與實體區塊:址:對觸位 實體區塊::詢到該邏輯區塊位址對應之 所包含之多個單階單元區塊對應 址2 06，而多階單元記憶體i i 2 ;體£塊位 :對應到次序在後之實體區塊位址二：二::= 塊位址係屬於次序在後之實體區塊位址， 址係指向多階單元記憶體㈣之多階單元區^ °。4位 由於高存取頻率的邏輯區塊位址適合以單階單元記情 SMI-08-012/9031-A41783-TW/Final 11 201001170 體108儲存，因此若主機1〇2欲寫入的該邏輯區塊位址係 才曰向多階單元記憶體110之多階單元區塊，則控制器1 不應將該邏輯區塊位址之區塊更新資料寫入其原本指向的 多階單7L區塊，而應將該邏輯區塊位址之區塊更新資料轉 而寫入一單階單元區塊，才能發揮單階單元記憶體高存取 速度及高穩定性的優點。因此，控制器1〇6自單階單元記 憶體108選取一單階單元區塊（步，驟312)，接著將該邏輯區 塊位址對應到選取之該單階單元區塊之實體區塊位址（步 驟314) ’絲㈣塊更新㈣寫人料階單元區塊（步驟 = 16)’才完成該區塊更新資料之寫入動作。於一實施例中， «玄控制益106包括紀錄所有邏輯區塊位址與實體區塊位址 的對應關係之-位址對應表，而控制器1〇6藉由更改該位 2對應表中該邏輯區塊位址與受選取之該單階單元區塊之 實體區塊位址之對應關係，而達成步驟314之動作。 比。口至於步，驟312中如何自單階單元記憶體1〇8選取一單 :ί元，塊有夕種方式。於一實施例中，控制器檢 -單階單元記憶體1G8所包含之多個單階單元區塊所對應 ^累積更新次數，並自該#多個單階單4塊中選取具有 取小之累積更新次數者’以作為步驟312所選取之單階單 實施例中，控制111G6檢查單階單元記憶 =10:所包括之多個單階單元區塊所對應的累積更新次 多個單階單元區塊中選取累積更新次數小於 一預疋值者’作為步驟312所選取之單階單元區塊。 此外，當控制器106於步驟312中選取該單階單元區 SMl-08-012/9031-A417§3-TW/Final 12 201001170 塊後’控㈣106還必須檢查該 :了：。若選取之該單階單元區埃已有；已儲存 益106於步驟316將該區塊更新 广貝抖犄，控制 前，必須備份該單階單元區塊已儲存==單階單元區塊 寫入完畢後，控制器106還需更改位址二:當步驟316 階早π區塊原本對應之邏輯區塊位址對應^ ’以將該單 原本指向之多階單元區塊之f體d塊Μ ;區塊位址 階單元區塊原本儲存之資料寫人該多，將選取之單 選取之單階單元區塊與該邏輯區塊位二原’以完成 元區塊兩者間資料的互換。 、3向之多階單 街皇虿尚存取頻率的邏 階單元記憶體⑽儲存，因此步驟306卜址適合以單 入的該邏輯區塊位址之累積更新次數未超❹3102欲寫 控制器106可將該區塊更新資料直接寫入該=限值，則 原本所對應之實體區塊位址指向之區塊，:^區塊位址 該邏輯區塊位址原本所指向之 去判斷是否 【元區塊(步驟318)。同樣的二於僅Γ以:或多階 :塊位址適合以單階單元記憶體⑽儲存，因：率的邏辑 令若:物欲寫入的該邏輯區塊 驟二 ^己憶體⑽之一單階單元區塊 =#曰向早階單 區塊更新資料寫入該單階單元區塊(步; 的憶體裝置的運作方法 階單元J 閃記憶體裝置包含-單 °憶體術與一多階單元記憶體404。單階單元記 MI 〇8'〇12/9〇31-A41783-TW/Final 201001170 憶體402自；^ v y 別為心 單階單元區塊，其中有邏短「 I為SLBa〇、SLBa 、輯區塊位址分 塊。邏輯區塊位址為SLBA。：草：:SL，的單階單元區 *其累積更新次數為2 ^早70區塊儲存資料Dp， 元區塊儲存資料IV 之單階單 位址為SLBA2之單階單元區為60。邏輯區塊 新次數為100。邏輯區塊位 子:枓’而其累積更 儲存㈣，叫累毅新錢=BAX之單階單元區塊未 ，階單元記憶體404包括H ^ 邏輯區塊位址分別為mlBa〇、Mlba^早70區塊，其中有 :工!:元區塊。邏輯區塊位址為紙bal:a:、...、mlba-臉貝料D!，而其累 ：咖。之多階單元區塊 之多階單元區塊儲存資=5〇。邏輯區塊位址為 】99。邏輯區塊位址為⑽a : '其累積更新次數為 DK，而其累積更新次數為抑。2 ^多階單元區塊錯存資料 多階單元區塊未儲存資料，而;區塊位址為机^之 第5圈顯示依據本發明之快門3新次數為〇。 的-實施例的第二階段示、思體裝置的運作方法 資料％寫入邏輯區塊位 ，权―主機欲將區魏更新 繼U己憶體裝置之控制器A區：多階單元區塊。因 夕階早το區塊之資料改寫為〇 ，、區鬼位址為MLBAl之 而成為200。此時控制器檢杳二f將其累積更新次數加】 多階單元區塊之累積更新次數已 =區德位址為机％之 於單階單元記億體4〇2 °過一界限值2〇〇，因此 取一早階單元區城，作為錯存 SMI-08^012/9031-A41783~TW/Final 14 201001170 邏輯區塊位址為MLBA]之資 元記憶體402所包含的多個單/的對象。由於在單階單 位址為SLBAX之單p比置- ^早凡區塊t，以邏輯區塊 控制器選取邏輯區塊位址為▲之累積更新次數最小，因此 儲存邏輯區塊位址為之單階單元區塊作為 第6圖顯示依據本㈣= = 的對象。 的—實施例的第三階段示音、A记憶體裝置的運作方法 區塊位址為SLBAX之單。控制器首先將原本之邏輯 MLBAl，接著將邏輯兀區塊對應到邏輯區塊位址 單階單元區塊。另外，九之資料域存至該 更新次數由〇改為15〇。之所=:該單階單兀區塊之累積 2 0 〇，係避免該單階單元區塊之w =將其累積更新次數改為 值⑽。接著，控制器將原本之^更^次數不斷超過界限 多階單元區塊對應到邏輯區塊位址s；；龙位址4 MLBAl之 區塊位址為SLBAx之區塊未锉,X。由於原本邏輯 存於該多階單元區塊之資制器清空儲 /然本發明已以較佳實施例揭露如上 限定本發明，任何熟習此項技術者， ’、…、&用Μ 抽4 & ΙΕ1 h 在不脫離本發明之掉 可作些許之更動與潤飾，因此本發明之： 4軌圍㊂視後附之申請專利範圍所界定者為準。 呆 【圖式簡單說明】 第1圖為依據本發明之快閃記憶體 第2圖為依據本發明之資料區 示意圖； 貝虹塊之位址的對應關係的 SMI-08-o 12/9〇31-A41783-TW/Final 201001170 第3圖為依據本發明之快閃記憶體裝置的運作方法的 流程圖； 第4圖為依據本發明之快閃記憶體裝置的運作方法的 一實施例的第一階段示意圖； 第5圖為依據本發明之快閃記憶體裝置的運作方法的 一實施例的第二階段示意圖； 第6圖為依據本發明之快閃記憶體裝置的運作方法的 一實施例的第三階段示意圖。 【主要元件符號說明】 (第1圖） 102〜主機； 104〜快閃記憶體裝置； 106〜控制器； 108〜單階單元記憶體；以及 110〜多階單元記憶體。 SMI-08-012/9031-A41783-TW/Final 16The -F 106 of the logical block address checks the logical area (step 3〇2). Next, the controller proceeds to step 304). = One of the cumulative update counts (Update - logical block address, in the second example, whenever the host 1G2 requires the logical block address to be written to the library 102 - the cumulative update count table in the update times table. Thus = cumulative update number plus one, while maintaining the cumulative cumulative update count table Γ 3〇 4 'controller 106 can use the number of queries. And the cumulative update time to the logical block address f host over-bound Leave), then edit the block address. The product address is regarded as the high access frequency of the logical unit memory 10δ storage; the sub: logical block address is suitable for the (four) block address corresponding to - "" controller 106 continues to check the logical area The block address refers to the address; f (3) 8)' to determine whether the real (step - embodiment multi-level cell block address and physical block: address: for the touch bit entity block:: inquiry The logical block address corresponds to a plurality of single-order unit block corresponding addresses 2 06, and the multi-level unit memory ii 2; body £ block: corresponds to the physical block address 2 of the order: 2::= The block address belongs to the physical block address in the order, and the address points to the multi-level cell area of the multi-level cell memory (4) ^. 4 bits are suitable for the logical block address of the high access frequency. The SMI-08-012/9031-A41783-TW/Final 11 201001170 body 108 is stored in a single-order unit, so if the logical block address of the host 1〇2 is written to the multi-level cell memory For a multi-level cell block of 110, controller 1 should not write the block update data of the logical block address to the multi-order single 7L block pointed to by it, but should The block update data of the logical block address is converted into a single-order unit block, so that the advantages of high access speed and high stability of the single-stage unit memory can be exerted. Therefore, the controller 1〇6 is from the single-order unit. The memory 108 selects a single-order unit block (step, step 312), and then maps the logical block address to the selected physical block address of the single-order unit block (step 314) 'silk (four) block update (4) Writing the human-level unit block (step = 16)' to complete the writing operation of the block update data. In an embodiment, «Xuan control benefit 106 includes recording all logical block addresses and physical block bits. The corresponding address-address correspondence table of the address, and the controller 1〇6 corresponds to the corresponding physical block address of the selected single-order unit block by changing the logical block address in the bit 2 correspondence table Relationship, and the action of step 314 is reached. Compared with the step, in step 312, how to select a single order from the single-order unit memory 1〇8: ί元, the block has an evening mode. In an embodiment, the controller checks - The accumulation of multiple single-order unit blocks included in the single-stage unit memory 1G8 a new number of times, and selecting from the plurality of single-order single-four blocks, the one having the small cumulative update number as the single-order single embodiment selected in step 312, the control 111G6 checks the single-order unit memory=10: The cumulative update number of the plurality of single-order unit blocks corresponding to the plurality of single-order unit blocks is selected to be less than one pre-valued one as the single-order unit block selected in step 312. In addition, when controlling After the unit 106 selects the single-order unit area SM1-08-012/9031-A417§3-TW/Final 12 201001170 in step 312, the control (four) 106 must also check the::. If the single-order unit area is selected, the stored unit 106 has been updated in step 316. Before the control, the single-order unit block must be backed up and stored == single-order unit block write After the completion of the process, the controller 106 also needs to change the address 2: when the logical block address corresponding to the original π block in step 316 corresponds to ^ ' to point the single original to the multi-order unit block of the f-body d block Μ ; Block address level unit block originally stored in the data of more people, the selected single-order unit block and the logical block bit two original 'to complete the meta-block exchange of data . 3, the multi-step single-segment single-story 虿 虿 access frequency of the logical unit memory (10) is stored, so the step 306 is suitable for the single-input of the logical block address, the cumulative number of updates is not more than 3102 to write controller 106 can directly write the block update data to the = limit value, and then the physical block address corresponding to the original block points to the block, : ^ block address, the logical block address originally pointed to determine whether [The metablock (step 318). The same two are only: or multi-order: the block address is suitable for storage in the single-order unit memory (10), because: the logic of the rate is: the logic block to be written by the object is the second part of the memory (10) A single-order unit block=#曰writes the early-stage single-block update data into the single-order unit block (step; the operation method of the memory device is replaced by a step-unit J flash memory device) A multi-level unit memory 404. The single-order unit records MI 〇8'〇12/9〇31-A41783-TW/Final 201001170 memory 402 from; ^ vy is a single-order unit block, which has a short logic I is SLBa〇, SLBa, and block address block. The logical block address is SLBA.: Grass::SL, the single-order unit area* has a cumulative update count of 2 ^ early 70 block storage data Dp, The single-order unit address of the meta-block storage data IV is SLBA2, and the single-order unit area is 60. The logical block new number is 100. The logical block position: 枓' and its accumulation is more stored (four), called tired new money = BAX The single-order unit block is not, and the order unit memory 404 includes H ^ logical block address addresses of mlBa〇, Mlba^ early 70 blocks, among which: work!: meta block. The block address is paper bal:a:,...,mlba-face material D!, and its tired: coffee. Multi-order unit block of multi-order unit block storage resource = 5〇. Logical block The address is 99. The logical block address is (10)a: 'The cumulative update number is DK, and the cumulative update count is suppressed. 2 ^Multi-order block block data The multi-level cell block does not store data. The block address is the fifth circle of the machine, and the new number of shutters 3 according to the present invention is shown as 〇. The second stage of the embodiment shows that the operation method of the body device is % written into the logical block position. ―The host wants to update the area Wei in the controller A area of the U-recalling device: the multi-level unit block. The data of the early το block is rewritten as 〇, and the area of the ghost is MLBAl and becomes 200. At this point, the controller checks the second f to increase its cumulative update times.] The cumulative update number of the multi-level unit block has been = the area address is the machine % to the single-order unit. The unit is 4 〇 2 ° over a limit value of 2 〇〇, therefore take the early-stage unit area city, as the wrong SMI-08^012/9031-A41783~TW/Final 14 201001170 logical block address is MLBA] A plurality of single/objects included in the body 402. Since the single-order unit address is the single-p ratio of the SLBAX--the early block t, the logical block controller selects the logical block address as the cumulative update of ▲ The number of times is the smallest, so the storage logic block address is the single-order unit block as the object shown in Figure 6 according to the (4) ==. The third stage of the embodiment, the operation method area of the A memory device The block address is a single SLBAX. The controller first maps the original logical MLBAl, and then the logical block to the logical block address single-order unit block. In addition, the number of data fields stored in the nine is changed from 〇 to 15〇. The == 累积 of the single-order single-block block, which avoids the w = of the single-order unit block and changes its cumulative update count to the value (10). Then, the controller continuously passes the original number of times to exceed the limit. The multi-level unit block corresponds to the logical block address s; the block address of the dragon address 4 MLBAl is the block of the SLBAx, X. Since the original logic is stored in the multi-level unit block, the present invention has been disclosed in the preferred embodiment as defined above. Anyone skilled in the art, ',...,&& ΙΕ 1 h Some modifications and retouchings may be made without departing from the invention, and thus the invention is as follows: 4, which is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view of a flash memory according to the present invention. FIG. 2 is a schematic diagram of a data area according to the present invention; SMI-08-o 12/9 of the correspondence relationship of addresses of a Bayon block 31-A41783-TW/Final 201001170 FIG. 3 is a flow chart showing a method of operating a flash memory device according to the present invention; FIG. 4 is a view showing an embodiment of a method for operating a flash memory device according to the present invention. 1 is a schematic diagram of a second stage of an embodiment of a method for operating a flash memory device according to the present invention; FIG. 6 is an embodiment of a method for operating a flash memory device according to the present invention; The third stage schematic. [Main component symbol description] (Fig. 1) 102~ host; 104~ flash memory device; 106~ controller; 108~ single-order cell memory; and 110~multi-level cell memory. SMI-08-012/9031-A41783-TW/Final 16