200950245 六、發明說明 【發明所屬之技術領域】 本發明係關於保護串聯連接之複數電池之電池保護電 路及電池裝置。 【先前技術】 筆記型電腦或行動電話等攜帶機器，有的具有串聯連 II 接的複數個電極及具有第1〜第2電池保護電路之電池裝 置。第1電池保護電路，控制電池的充放電而保護電池。 在第1電池保護電路應該動作而萬一未動作的場合，電池 成爲過充電狀態，第2電池保護電路會以電池不引起著火 的方式停止電池裝置的功能。第2電池保護電路擔任電池 的最終保護功能，所以第2電池保護電路動作的話，電池 裝置變成無法使用（例如參照專利文獻1 )。 具體而言，如圖4所示，第2電池保護電路1〇監視 φ 電池BAT1〜BAT4的電壓，其電壓成爲特定電壓以上 時，第2電池保護電路10切斷被設於充放電路徑之保險 絲20，切斷充放電路徑，電池裝置因而停止。 [專利文獻1]日本專利特開2000-295777號公報 【發明內容】 [發明所欲解決之課題] 此處，如圖4所示，第2電池保護電路1〇，具有被 連接於中間端子VC2之P型井12a與N型基板（N sub)之 200950245 間之寄生二極體。此外，第2電池保護電路1〇，具有把 基極（base)作爲N型基板，將射極（emitter)作爲P型井 12a而將集極（collect)作爲P型井12b之寄生雙極電晶體 12。此外’最上段之電池BAT 1之正極端子爲電源端子 VDD，最下段之電池BAT4之負極端子爲接地端子VSS， 電池BAT2〜BAT3之端子爲中間端子VC1〜VC3» 如此一來，例如僅中間端子VC2及接地端子VSS被 連接於電池的場合，由中間端子VC2往電源端子VDD中 介著寄生二極體流著順方向電流，由於此順方向電流（基 極電流）使寄生雙極電晶體12動作，所以邏輯電路11會 有誤動作。藉由此誤動作，第2電池保護電路1〇會輸出 使電池裝置成爲無法使用的訊號。 因而，第2電池保護電路10的各端子與各電池之連 接的順序相關的限制是有所必要的，使得電池裝置的製造 程序變得複雜而生產率變低，電池裝置的製造成本變高。 本發明，有鑑於前述課題，提更了可以使製造成本降 低之電池保護電路及電池裝置。 [供解決課題之手段] 本發明爲了解決前述課題，提供一種電池裝置，係具 備保護串聯連接的複數電池，具有最上段的前述電池之正 極端子中介著開關群而被連接之電源端子與最下段的前述 電池之負極端子中介著前述開關群而被連接之接地端子與 前述電池間之連接點中介著前述開關群被連接的中間端子 -6- 200950245 之電池保護電路之電池裝置；其特徵爲具備：具有監視各 前述電池的電壓之複數監視電路、當前述電池的電壓成爲 特定電壓以上時，以各前述電池之充放電路徑被遮斷的方 式動作之邏輯電路、設於前述中間端子之第一井、不設於 前述中間端子而被接近配置於前述第一井之第二井、以及 不設於前述中間端子，而被接近配置於前述第一井，以包 圍前述第一井的方式被配置之第三井的前述電池保護電 @ 路，以及，複數之前述電池、前述開關群。 此外，本發明爲了解決前述課題，提供一種電池裝 置，係具備保護串聯連接的複數電池，具有最上段的前述 電池之正極端子中介著開關群而被連接之電源端子與最下 段的前述電池之負極端子中介著前述開關群而被連接之接 地端子與前述電池間之連接點中介著前述開關群被連接的 中間端子之電池保護電路之電池裝置；其特徵爲具備：具 有監視各前述電池的電壓之複數監視電路、當前述電池的 Ο 電壓成爲特定電壓以上時，以各前述電池之充放電路徑被 遮斷的方式動作之邏輯電路、設於前述中間端子之第一 井、不設於前述中間端子而被接近配置於前述第一井之第 二井、以及不設於前述中間端子，而被接近配置於前述第 一井，以包圍前述第一井的方式被配置之第三井的前述電 池保護電路，以及，複數之前述電池、前述開關群。 [發明之效果] 在本發明，電池保護電路之所有的端子分別被連接於 200950245 各電池之前’依照這些之連接的順序，使得即使第一井及 第二井導致的寄生雙極電晶體之動作導致邏輯電路誤動 作’也藉由第一井及第三井導致的寄生雙極電晶體之動作 使邏輯電路重設（reset)，所以藉由這些之連接順序，電池 的充放電路徑不會被遮斷。因而，關於這些連接的順序之 限制被消除，電池裝置的製造程序變得簡單生產率變高， 電池裝置的製造成本變低。 【實施方式】 以下，參照圖面說明本發明之實施型態。 (第1實施型態） 首先，說明電池保護電路之構成。圖1係顯示電池保 護電路之圖。圖2係顯示電池保護電路之配置圖。 電池裝置，具有電池 BAT1〜BAT4，開關 SW1〜 SW5，電池保護電路30以及保險絲20。電池保護電路 30，具備電源端子VDD、中間端子VC1〜VC3、接地端子 VSS以及輸出端子VOUT。此外，電池保護電路30’具備 下拉電阻34、比較電路36〜39、基準電壓電路36a〜39a 以及邏輯電路31。邏輯電路31，具有重設電路31a。比 較電路及基準電壓電路，發揮作爲監視電路的功能。 比較電路38，具有P型井32a及P型井33b。邏輯電 路31，具有P型井32b。電池保護電路30，具有被連接 於中間端子VC2之P型井32a與N型基板（N sub)之間之 -8- 200950245 寄生二極體。此外，電池保護電路30，具有把基極（base) 作爲N型基板（N sub)將射極（emitter)作爲P型井32a而 將集極（collect)作爲P型井32b之寄生雙極電晶體32。此 外，電池保護電路30，具有把基極（base)作爲N型基板（N sub)將射極（emitter)作爲P型井32a而將集極（collect)作 爲P型井32b之寄生雙極電晶體33。 電池BAT1〜BAT4，依序被串聯連接。電池BAT1之 @ 正極端子’中介著開關SW1被連接於電源端子VDD。電 池BAT2之正極端子，中介著開關SW2被連接於中間端 子VC1。電池BAT3之正極端子，中介著開關SW3被連 接於中間端子VC2。電池BAT4之正極端子，中介著開關 SW4被連接於中間端子VC3。電池BAT4之負極端子，中 介著開關SW5被連接於接地端子VSS。此外，電池BAT1 之正極端子，中介著保險絲20被連接於充電器（未圖 示）或負荷（未圖示）。電源端子VDD與中間端子VC1 〇 與中間端子VC2與中間端子VC3分別被連接於比較電路 36〜39之非反轉輸入端子。基準電壓電路36a〜39a之輸 出端子，分別被連接於比較電路36〜39之反轉輸入端 子。比較電路36〜39之輸出端子，分別被連接於邏輯電 路31之各輸入端子。邏輯電路31之輸出端子，被連接於 輸出端子V0UT。輸出端子V0UT與電池BAT1之正極端 子之間設有保險絲20。下拉電阻34，一端被連接於接地 端子VSS，另一端被連接於P型井33b及重設電路31a之 輸入端子。 -9- 200950245 寄生雙極電晶體32，基極被連接於電源端子VDD’ 射極被連接於P型井32a，集極被連接於32b。寄生雙極 電晶體33，基極被連接於電源端子VDD，射極被連接於 P型井32a，集極被連接於3 2b。P型井32a，被連接於中 間端子 VC2。下拉電阻34，一端被連接於接地端子 VSS，另一端被連接於P型井33b及重設電路31a之輸入 端子。 又，電源端子VDD與邏輯電路31之間，設有由電源 端子VDD之電壓產生比電源端子VDD的電壓還低的一定 電壓之電壓調節器（未圖示）。此外，於比較電路36〜 39與邏輯電路31之間，設有使比較電路36〜39之輸出 電壓的位準降低移位的位準偏移（level-shifter )電路 (未圖示）。此外，於邏輯電路31與輸出端子VOUT之 間，設有使邏輯電路31之輸出電壓的位準升高移位的位 準偏移（level-shifter)電路（未圖示）。 此處，P型井32a，被設於中間端子VC2。P型井 3 2b，不設於中間端子VC2，被配置於接近P型井32a。P 型井33b，不設於中間端子VC2，被配置於接近P型井 32a，以包圍P型井32a的方式被配置。 此外，重設電路31a，以使P型井33b的電壓到達中 間端子VC2的電壓附近時使重設電路31a的.輸出端子的 電壓成爲高（high)的方式設計電路。 此外，基準電壓電路36a〜39a產生基準電壓。根據 基準電壓，基準電壓電路36a〜39a以及比較電路36〜39 -10- 200950245 分別監視電池 BAT1〜BAT4之電壓。電池 BAT1〜BAT4 的電壓成爲基準電壓以上時，邏輯電路31以遮斷電池 BAT1〜BAT4的充放電路徑的方式動作。 此外，比較電路36〜39以及基準電壓電路36a〜39a 之電源電壓，係電源端子VDD之電壓。總之，比較電路 36〜39以及基準電壓電路36a〜39a，位於高電位區域。 邏輯電路31之電源電壓，係比藉由電壓調節器產生的電 U 源端子VDD的電壓還要低的一定之電壓。總之，邏輯電 路3 1，位於低電位區域。 此外，電池保護電路30，被形成於N型基板（N sub)。 其次，說明電源端子VDD被連接之前有中間端子 VC2被連接，電池保護電路30成爲與電池BAT1〜BAT4 連接中，僅開關SW3與開關SW5爲打開（ON)，中間端 子VC2被連接於電池BAT3之正極端子，接地端子VSS φ 被連接於電池BAT4之負極端子的場合之電池保護電路30 的動作。 P型井32a成爲電池保護電路30的最高電壓，所以 由中間端子VC2對電源端子VDD中介著寄生二極體流動 著順方向電流，藉由此順方向電流（基極電流）使寄生雙 極電晶體32動作。藉此，電流由作爲射極之P型井32a 往作爲集極之P型井32b流動，P型井32b之電壓成爲中 間端子VC2之電壓。 此時，與前述同樣，寄生雙極電晶體33也動作，電 -11 - 200950245 流由作爲射極之P型井32a往作爲集極之P型井33b流 動，P型井33b之電壓也成爲中間端子VC2之電壓，重設 電路31a之輸入端子的電壓成爲高位準。如此一來，重設 電路31a強制地重設羅極電路31內部的特定之雙穩態多 諧震盪器（flip-flop)(未圖示）等，所以邏輯電路31被重 設，邏輯電路31不輸出使電池裝置成爲不能使用的訊 號。 此處，中間端子VC2的電壓，藉由寄生雙極電晶體 32〜33成爲與電源端子VDD之電壓幾乎相等。此電源端 子VDD之電壓，係邏輯電路31及重設電路31a之電源電 壓，中間端子VC2隻電壓，變成邏輯電路31以及重設電 路31a之電源電壓。藉此，P型井33b的電壓成爲中間端 子VC2的電壓附近時，邏輯電路31以及重設電路31a認 識到P型井33b的電壓成爲高（high)。 其次，說明電池保護電路30結束連接至電池BAT 1〜 BAT4，開關SW1〜SW5打開（ON )，接地端子VDD被 連接於電池BAT1之正極端子，中間端子VC1〜VC3被連 接於電池BAT2〜BAT4之正極端子，接地端子VSS被連 接於電池BAT4之負極端子的場合之電池保護電路30的 動作。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery protection circuit and a battery device for protecting a plurality of batteries connected in series. [Prior Art] A portable device such as a notebook computer or a mobile phone, and some have a plurality of electrodes connected in series and a battery device having first to second battery protection circuits. The first battery protection circuit controls charging and discharging of the battery to protect the battery. When the first battery protection circuit is to be operated and the battery is not operating, the battery is in an overcharged state, and the second battery protection circuit stops the function of the battery device so that the battery does not ignite. Since the second battery protection circuit functions as the final protection function of the battery, the battery device becomes unusable when the second battery protection circuit operates (see, for example, Patent Document 1). Specifically, as shown in FIG. 4, when the voltage of the φ batteries BAT1 to BAT4 is monitored by the second battery protection circuit 1 and the voltage is equal to or higher than the specific voltage, the second battery protection circuit 10 cuts the fuse provided in the charge and discharge path. 20. The charging and discharging path is cut off, and the battery unit is thus stopped. [Problem to be Solved by the Invention] Here, as shown in FIG. 4, the second battery protection circuit 1A is connected to the intermediate terminal VC2. A parasitic diode between the P-well 12a and the N-type substrate (N sub) 200950245. Further, the second battery protection circuit 1A has a base as an N-type substrate, an emitter as a P-well 12a, and a collector as a parasitic bipolar of the P-well 12b. Crystal 12. In addition, the positive terminal of the uppermost battery BAT 1 is the power supply terminal VDD, the negative terminal of the lowermost battery BAT4 is the ground terminal VSS, and the terminals of the battery BAT2 to BAT3 are the intermediate terminals VC1 to VC3», such as only the intermediate terminal When VC2 and ground terminal VSS are connected to the battery, a forward current flows through the intermediate terminal VC2 to the power supply terminal VDD via the parasitic diode, and the parasitic bipolar transistor 12 operates due to the forward current (base current). Therefore, the logic circuit 11 may malfunction. By this malfunction, the second battery protection circuit 1 outputs a signal that makes the battery device unusable. Therefore, restrictions on the order in which the respective terminals of the second battery protection circuit 10 are connected to the respective batteries are necessary, the manufacturing procedure of the battery device is complicated, the productivity is lowered, and the manufacturing cost of the battery device is increased. The present invention has been made in view of the above problems, and provides a battery protection circuit and a battery device which can reduce the manufacturing cost. [Means for Solving the Problem] In order to solve the above-described problems, the present invention provides a battery device including a plurality of batteries that are connected in series, and a power supply terminal and a lowermost portion that are connected to each other with a switch group of a positive electrode terminal of the uppermost battery. a battery device of a battery protection circuit in which an intermediate terminal -6-200950245 to which the switch group is connected is connected to a connection point between the ground terminal and the battery through which the switch terminal of the battery is connected; a logic circuit that monitors a voltage of each of the batteries and a voltage that is interrupted by a charge/discharge path of each of the batteries when the voltage of the battery is equal to or higher than a specific voltage, and is provided in the first terminal of the intermediate terminal The well is disposed not in the intermediate terminal, is disposed in the second well of the first well, and is disposed not in the intermediate terminal, and is disposed close to the first well, and is disposed to surround the first well The aforementioned battery protection electric @路 of the third well, and the foregoing plurality of batteries, the aforementioned switch group . Further, in order to solve the above problems, the present invention provides a battery device including a plurality of batteries that are connected in series, and has a power supply terminal to which a positive electrode terminal of the battery of the uppermost stage is connected via a switch group, and a negative electrode of the lowermost battery. a battery device for a battery protection circuit in which an intermediate terminal to which the switch group is connected is connected to a connection point between the ground terminal and the battery through which the switch group is connected; and a battery device having a voltage for monitoring each of the batteries a logic circuit that operates such that the charge/discharge path of each of the batteries is blocked, and a first well provided in the intermediate terminal, not provided in the intermediate terminal, when the Ο voltage of the battery is equal to or higher than a specific voltage a battery that is disposed in the second well of the first well and is not disposed in the intermediate terminal, and is disposed close to the first well, and is disposed in a third well that is disposed to surround the first well. a circuit, and a plurality of the foregoing batteries and the aforementioned switch group. [Effects of the Invention] In the present invention, all the terminals of the battery protection circuit are connected to each of the 200950245 batteries, respectively, in accordance with the order of the connections, so that even the first and second wells cause the action of the parasitic bipolar transistor. The logic circuit malfunctions. The logic circuit is reset by the action of the parasitic bipolar transistor caused by the first well and the third well. Therefore, the charging and discharging paths of the battery are not covered by the connection sequence. Broken. Therefore, the restriction on the order of these connections is eliminated, the manufacturing process of the battery device becomes simple and the productivity becomes high, and the manufacturing cost of the battery device becomes low. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. (First embodiment) First, the configuration of a battery protection circuit will be described. Figure 1 is a diagram showing a battery protection circuit. 2 is a configuration diagram showing a battery protection circuit. The battery device has batteries BAT1 to BAT4, switches SW1 to SW5, a battery protection circuit 30, and a fuse 20. The battery protection circuit 30 includes a power supply terminal VDD, intermediate terminals VC1 to VC3, a ground terminal VSS, and an output terminal VOUT. Further, the battery protection circuit 30' includes a pull-down resistor 34, comparison circuits 36 to 39, reference voltage circuits 36a to 39a, and a logic circuit 31. The logic circuit 31 has a reset circuit 31a. The comparator circuit and the reference voltage circuit function as a monitor circuit. The comparison circuit 38 has a P-type well 32a and a P-type well 33b. The logic circuit 31 has a P-type well 32b. The battery protection circuit 30 has a -8-200950245 parasitic diode between the P-well 32a and the N-substrate (Nsub) connected to the intermediate terminal VC2. Further, the battery protection circuit 30 has a base (base) as an N-type substrate (N sub), an emitter as a P-well 32a, and a collector as a parasitic bipolar of a P-well 32b. Crystal 32. Further, the battery protection circuit 30 has a base (base) as an N-type substrate (N sub), an emitter as a P-type well 32a, and a collector as a P-type well 32b. Crystal 33. The batteries BAT1 to BAT4 are sequentially connected in series. The @ positive terminal of the battery BAT1 is connected to the power supply terminal VDD via the switch SW1. The positive terminal of the battery BAT2 is connected to the intermediate terminal VC1 via the switch SW2. The positive terminal of the battery BAT3 is connected to the intermediate terminal VC2 via the switch SW3. The positive terminal of the battery BAT4 is interposed with the switch SW4 connected to the intermediate terminal VC3. The negative terminal of the battery BAT4 is connected to the ground terminal VSS via the switch SW5. Further, the positive terminal of the battery BAT1 is connected to a charger (not shown) or a load (not shown) via the fuse 20. The power supply terminal VDD and the intermediate terminal VC1 〇 and the intermediate terminal VC2 and the intermediate terminal VC3 are connected to the non-inverting input terminals of the comparison circuits 36 to 39, respectively. The output terminals of the reference voltage circuits 36a to 39a are connected to the inverting input terminals of the comparison circuits 36 to 39, respectively. The output terminals of the comparison circuits 36 to 39 are connected to the respective input terminals of the logic circuit 31. The output terminal of the logic circuit 31 is connected to the output terminal VOUT. A fuse 20 is provided between the output terminal V0UT and the positive terminal of the battery BAT1. The pull-down resistor 34 has one end connected to the ground terminal VSS and the other end connected to the P-well 33b and the input terminal of the reset circuit 31a. -9- 200950245 Parasitic bipolar transistor 32, the base is connected to the power supply terminal VDD'. The emitter is connected to the P-well 32a, and the collector is connected to 32b. The parasitic bipolar transistor 33 has a base connected to the power supply terminal VDD, an emitter connected to the P-well 32a, and a collector connected to the 3 2b. The P-well 32a is connected to the intermediate terminal VC2. The pull-down resistor 34 has one end connected to the ground terminal VSS and the other end connected to the P-well 33b and the input terminal of the reset circuit 31a. Further, a voltage regulator (not shown) having a constant voltage lower than the voltage of the power supply terminal VDD by the voltage of the power supply terminal VDD is provided between the power supply terminal VDD and the logic circuit 31. Further, between the comparison circuits 36 to 39 and the logic circuit 31, a level-shifter circuit (not shown) for shifting the level of the output voltage of the comparison circuits 36 to 39 is provided. Further, a level-shifter circuit (not shown) for shifting the level of the output voltage of the logic circuit 31 is provided between the logic circuit 31 and the output terminal VOUT. Here, the P-type well 32a is provided in the intermediate terminal VC2. The P-type well 3 2b is not disposed at the intermediate terminal VC2 and is disposed close to the P-type well 32a. The P-type well 33b is disposed not close to the intermediate terminal VC2, and is disposed close to the P-type well 32a so as to surround the P-type well 32a. Further, the circuit 31a is reset so that the voltage of the P-type well 33b reaches the vicinity of the voltage of the intermediate terminal VC2, and the voltage of the output terminal of the reset circuit 31a is made high. Further, the reference voltage circuits 36a to 39a generate a reference voltage. Based on the reference voltage, the reference voltage circuits 36a to 39a and the comparison circuits 36 to 39 - 10 200950245 monitor the voltages of the batteries BAT1 to BAT4, respectively. When the voltages of the batteries BAT1 to BAT4 become equal to or higher than the reference voltage, the logic circuit 31 operates to block the charge and discharge paths of the batteries BAT1 to BAT4. Further, the power supply voltages of the comparison circuits 36 to 39 and the reference voltage circuits 36a to 39a are the voltages of the power supply terminals VDD. In short, the comparison circuits 36 to 39 and the reference voltage circuits 36a to 39a are located in the high potential region. The power supply voltage of the logic circuit 31 is a certain voltage lower than the voltage of the electric U source terminal VDD generated by the voltage regulator. In summary, logic circuit 3 1, is located in the low potential region. Further, the battery protection circuit 30 is formed on an N-type substrate (Nsub). Next, the intermediate terminal VC2 is connected before the power supply terminal VDD is connected, the battery protection circuit 30 is connected to the batteries BAT1 to BAT4, only the switch SW3 and the switch SW5 are turned on (ON), and the intermediate terminal VC2 is connected to the battery BAT3. The operation of the battery protection circuit 30 when the positive terminal and the ground terminal VSS φ are connected to the negative terminal of the battery BAT4. Since the P-type well 32a becomes the highest voltage of the battery protection circuit 30, the forward terminal current flows through the intermediate terminal VC2 to the parasitic diode through the parasitic diode, and the parasitic bipolar current is caused by the forward current (base current). The crystal 32 operates. Thereby, the current flows from the P-type well 32a which is the emitter to the P-type well 32b which is the collector, and the voltage of the P-type well 32b becomes the voltage of the intermediate terminal VC2. At this time, the parasitic bipolar transistor 33 also operates in the same manner as described above, and the electric -11 - 200950245 flow flows from the P-type well 32a which is the emitter to the P-type well 33b which is the collector, and the voltage of the P-type well 33b becomes The voltage of the intermediate terminal VC2 and the voltage of the input terminal of the reset circuit 31a become a high level. In this manner, the reset circuit 31a forcibly resets a specific flip-flop (not shown) or the like inside the pole circuit 31, so the logic circuit 31 is reset, and the logic circuit 31 is reset. The signal that makes the battery device unusable is not output. Here, the voltage of the intermediate terminal VC2 is almost equal to the voltage of the power supply terminal VDD by the parasitic bipolar transistors 32 to 33. The voltage of the power supply terminal VDD is the power supply voltage of the logic circuit 31 and the reset circuit 31a, and the intermediate terminal VC2 is only the voltage, which becomes the power supply voltage of the logic circuit 31 and the reset circuit 31a. Thereby, when the voltage of the P-type well 33b becomes near the voltage of the intermediate terminal VC2, the logic circuit 31 and the reset circuit 31a recognize that the voltage of the P-type well 33b becomes high. Next, the battery protection circuit 30 is terminated to be connected to the batteries BAT 1 to BAT4, the switches SW1 to SW5 are turned on (ON), the ground terminal VDD is connected to the positive terminal of the battery BAT1, and the intermediate terminals VC1 to VC3 are connected to the batteries BAT2 to BAT4. The operation of the battery protection circuit 30 when the positive terminal and the ground terminal VSS are connected to the negative terminal of the battery BAT4.
N型基板成爲電池保護電路30的最高電壓，所以並 不由中間端子VC2對電源端子VDD中介著寄生二極體流 動著順方向電流，而寄生雙極電晶體32〜33不動作。因 而’消費電流減少了這一部份。此處，下拉電阻34把P -12- 200950245 型井33b下拉（pull-down)，所以P型井33b之電壓被確定 在接地電壓附近。 此外，電池BAT1〜BAT4被充電，電池BAT1〜BAT4 之電壓變高，電池BAT1〜BAT4之中之任一個之電池， 例如電池BAT3之電壓變成基準電壓電路38 a之基準電壓 以上時，比較電路38之輸出電壓變成高位準。此時，電 池BAT3之狀態爲過充電狀態。此高位準訊號，藉由邏輯 ❹ 電路31施以延遲處理等，由輸出端子VOUT作爲過充電 檢測訊號而輸出。 此外，根據邏輯電路31之延遲處理中，電池BAT3 之電壓未達基準電壓電路38a的基準電壓時，比較電路 38的輸出電壓變成低位準。此時之電池BAT3之狀態爲通 常狀態。此低位準訊號，輸入至重設電路31a之輸入端子 作爲過充電檢測解除訊號。 如此一來，電池保護電路30之所有的端子分別被連 接於各電池BAT1〜BAT4之前，依照這些之連接的順 序，使得即使P型井32a〜32b導致的寄生雙極電晶體32 之動作導致邏輯電路31誤動作，也藉由P型井3 2a及P 型井33b導致的寄生雙極電晶體33之動作使邏輯電路31 被重設（reset)，所以藉由這些之連接順序，電池BAT1〜 BAT4的充放電路徑不會被遮斷。因而，關於這些連接的 順序之限制被消除，電池裝置的製造程序變得簡單生產率 變高，電池裝置的製造成本變低。 此外，僅藉由設置P型井33b及下拉電阻34，邏輯 -13- 200950245 電路31就不會誤動作，所以使用複雜的製造過程以使邏 輯電路31不要誤動作的方式分離元件變成不再是必要， 複雜的製造過程變成非必要。因而，製造成本降低。 又，於圖2,僅記載關於中間端子VC2之寄生二極體 以及寄生雙極電晶體，但雖未圖示，但關於中間端子VC 1 以及中間端子VC3之寄生二極體以及寄生雙極電晶體也 是存在的。此時，被連接於各中間端子的各P型井，亦可 以1個P型井包圍，亦可以分別的P型井分別包圍。 此外，邏輯電路31具有P型井32b，但基準電壓電 路或比較電路亦可具有P型井32b。 此外，於圖2使用4個電池，但亦可使用不滿4個或 者5個以上之電池。此時，配合電池之數目，設置包圍開 關與中間端子與被連接於中間端子的P型井之P型井。 此外，過充電檢測解除訊號被電路設計爲高（High)訊 號的場合，過充電檢測解除訊號之節點亦可被連接於P型 井33b。此時，過充電檢測訊號即使被輸出P型井33b之 電壓成爲高位準，邏輯電路31也不會輸出使電池裝置成 爲不能使用的訊號。 此外，來自其他重設功能的輸出端子也可以被連接於 P型井3 3b。此時，即使其他的重設功能動作使P型井 3 3b之電壓成爲高位準，邏輯電路31也不會輸出使電池 裝置成爲不能使用的訊號。 此外，電池保護電路30被形成於N型基板（N sub)， 電源端子VDD與中間端子VC1〜VC3與接地端子VSS依 200950245 序分別被連接於電池BAT1〜BAT4時，邏輯電路31不輸 出使電池裝置無法使用的訊號。 此外，電池保護電路30被形成於P型基板（P sub) ’ 接地端子VSS與中間端子VC3〜VC1與電源端子VDD依 序分別被連接於電池BAT4〜BAT1時，邏輯電路3 1不輸 出使電池裝置無法使用的訊號。 ❹ (第2實施型態） 此處，電池保護電路30被形成於N型基板，但如圖 3所示，電池保護電路40亦可被形成於P型基板。如此 一來，寄生雙極電晶體，在圖2係PNP雙極電晶體，但 在圖3爲NPN雙極電晶體。此外，保險絲20，在圖2係 設於輸出端子VOUT與電池BAT1之正極端子之間，但在 圖3，係被設於輸出端子VOUT與電池BAT4之負極端子 之間。 0 首先，說明電池保護電路之構成。圖3係顯示電池保 護電路之配置圖。 電池裝置，具有電池 BAT1〜BAT4，開關 SW1〜 SW5，電池保護電路40以及保險絲20。電池保護電路 40，具備電源端子VDD、中間端子VC1〜VC3、接地端子 VSS以及輸出端子VOUT。此外，電池保護電路40，具備 上拉電阻44、比較電路（未圖示）、基準電壓電路（未 圖示）以及邏輯電路41。邏輯電路41，具有重設電路 41a。比較電路及基準電壓電路，發揮作爲監視電路的功 -15- 200950245 比較電路42，具有N型井42a及N型井43b。邏輯 電路41，具有N型井42b。電池保護電路40，具有被連 接於中間端子VC2之N型井42a與P型基板（P sub)之間 之寄生二極體。此外，電池保護電路40，具有把基極 (base)作爲P型基板（p sub)將射極（emitter)作爲N型井 42a而將集極（collect)作爲N型井42b之寄生雙極電晶體 42。此外，電池保護電路40，具有把基極（base)作爲P型 基板（P sub)將射極（emitter)作爲N型井42a而將集極 (collect)作爲N型井42b之寄生雙極電晶體43。 此處，N型井42a，被設於中間端子 VC2。N型井 42b ’不設於中間端子VC2，被配置於接近N型井42a。N 型井43b，不設於中間端子VC2，被配置於接近N型井 42a，以包圍N型井42a的方式被配置。 此外，重設電路41a，以使N型井43 b的電壓到達中 間端子VC2的電壓附近時使重設電路41a的輸出端子的 電壓成爲低（low)的方式設計電路。 其次，說明接地端子VSS被連接之前有中間端子 VC2被連接，電池保護電路40成爲與電池BAT1〜BAT4 連接中，僅開關SW1與開關SW3爲打開（ON)，電源端 子VDD被連接於電池BAT1之正極端子，中間端子VC2 被連接於電池BAT3之正極端子的場合之電池保護電路40 的動作。 N型井42 a之電壓成爲中間端子VC2之電壓，P型基 200950245 板之電壓成爲比N型井42a的電壓更高時’由接地端子 VSS往中間端子VC2中介著寄生二極體流有順方向電 流，藉由此順方向電流（基極電流）使寄生雙極電晶體 42動作。藉此，電流由作爲集極之N型井42b往作爲射 極之N型井42a流動，N型井42b之電壓成爲中間端子 VC2之電壓。 此時，與前述同樣，寄生雙極電晶體43也動作，電 流由作爲集極之N型井43b往作爲射極之N型井42a流 動，N型井43b之電壓也成爲中間端子VC2之電壓，重 設電路41a之輸入端子的電壓成爲低位準。如此一來，重 設電路31a強制地重設羅極電路41內部的特定之雙穩態 多諧震盪器（flip -flop)(未圖示）等，所以邏輯電路41被 重設’邏輯電路41不輸出使電池裝置成爲不能使用的訊 號。 ❹ 【圖式簡單說明】 圖1係顯示電池保護電路之圖。 圖2係顯示電池保護電路之配置圖。 圖3係顯示電池保護電路之配置圖。 圖4係顯示從前之電池保護電路之配置圖。 【主要元件符號說明】 BAT1〜BAT4 :電池 SW1〜SW5 :開關 -17- 200950245 VDD :電源端子 VC1〜VC3 :中間端子 V S S :接地端子 VOUT :輸出端子 20 :保險絲 3 0 :電池保護電路 3 1 :邏輯電路 3 1 a :重設電路 32〜33 :寄生雙極電晶體 32a 〜32b,33b : P 型井 3 4 :下拉電阻 3 6〜3 9 :比較電路 36a〜39a:基準電壓電路Since the N-type substrate becomes the highest voltage of the battery protection circuit 30, the forward current flows through the parasitic diode via the intermediate terminal VC2 to the power supply terminal VDD, and the parasitic bipolar transistors 32 to 33 do not operate. Therefore, the consumption current has reduced this part. Here, the pull-down resistor 34 pulls down the P -12-200950245 type well 33b, so the voltage of the P type well 33b is determined to be near the ground voltage. Further, when the batteries BAT1 to BAT4 are charged, the voltages of the batteries BAT1 to BAT4 become high, and the battery of any one of the batteries BAT1 to BAT4, for example, the voltage of the battery BAT3 becomes equal to or higher than the reference voltage of the reference voltage circuit 38a, the comparison circuit 38 The output voltage becomes a high level. At this time, the state of the battery BAT3 is an overcharged state. This high-order signal is outputted by the output terminal VOUT as an overcharge detection signal by delay processing or the like by the logic circuit 31. Further, in the delay processing of the logic circuit 31, when the voltage of the battery BAT3 does not reach the reference voltage of the reference voltage circuit 38a, the output voltage of the comparison circuit 38 becomes a low level. At this time, the state of the battery BAT3 is a normal state. The low level signal is input to the input terminal of the reset circuit 31a as an overcharge detection release signal. In this way, before the terminals of the battery protection circuit 30 are respectively connected to the respective batteries BAT1 to BAT4, the logic of the parasitic bipolar transistor 32 caused by the P-type wells 32a to 32b is caused in accordance with the order of the connections. The circuit 31 malfunctions, and the logic circuit 31 is reset by the action of the parasitic bipolar transistor 33 caused by the P-well 32a and the P-well 33b. Therefore, the battery BAT1 to BAT4 are connected by these connections. The charge and discharge path will not be interrupted. Therefore, the restriction on the order of these connections is eliminated, the manufacturing process of the battery device becomes simple and the productivity becomes high, and the manufacturing cost of the battery device becomes low. In addition, the logic-13-200950245 circuit 31 does not malfunction by merely providing the P-type well 33b and the pull-down resistor 34, so it is no longer necessary to separate the components by using a complicated manufacturing process so that the logic circuit 31 does not malfunction. Complex manufacturing processes become unnecessary. Thus, the manufacturing cost is lowered. 2, only the parasitic diode and the parasitic bipolar transistor of the intermediate terminal VC2 are described. However, although not shown, the parasitic diode and the parasitic bipolar of the intermediate terminal VC1 and the intermediate terminal VC3 are shown. Crystals are also present. At this time, each P-type well connected to each intermediate terminal may be surrounded by one P-type well, or may be separately surrounded by separate P-type wells. Further, the logic circuit 31 has a P-type well 32b, but the reference voltage circuit or comparison circuit may also have a P-type well 32b. Further, four batteries are used in Fig. 2, but batteries of less than four or five or more may be used. At this time, a P-type well surrounding the switch and the intermediate terminal and the P-type well connected to the intermediate terminal is provided in accordance with the number of batteries. Further, when the overcharge detection release signal is designed as a high signal, the node of the overcharge detection release signal may be connected to the P-type well 33b. At this time, even if the overcharge detection signal is turned to the high level of the voltage output from the P-type well 33b, the logic circuit 31 does not output a signal for making the battery device unusable. In addition, output terminals from other reset functions can also be connected to the P-well 3 3b. At this time, even if the other reset function operates to bring the voltage of the P-type well 3 3b to a high level, the logic circuit 31 does not output a signal that makes the battery device unusable. Further, when the battery protection circuit 30 is formed on the N-type substrate (Nsub), the power supply terminal VDD and the intermediate terminals VC1 to VC3 and the ground terminal VSS are respectively connected to the batteries BAT1 to BAT4 in the order of 200950245, and the logic circuit 31 does not output the battery. A signal that the device cannot use. Further, when the battery protection circuit 30 is formed on the P-type substrate (P sub) 'the ground terminal VSS and the intermediate terminals VC3 to VC1 and the power supply terminal VDD are sequentially connected to the batteries BAT4 to BAT1, respectively, the logic circuit 31 does not output the battery. A signal that the device cannot use.第 (Second Embodiment) Here, the battery protection circuit 30 is formed on the N-type substrate. However, as shown in FIG. 3, the battery protection circuit 40 may be formed on the P-type substrate. As a result, the parasitic bipolar transistor is a PNP bipolar transistor in Figure 2, but in Figure 3 is an NPN bipolar transistor. Further, the fuse 20 is provided between the output terminal VOUT and the positive terminal of the battery BAT1 in Fig. 2, but is provided between the output terminal VOUT and the negative terminal of the battery BAT4 in Fig. 3 . 0 First, the structure of the battery protection circuit will be explained. Fig. 3 is a view showing the configuration of the battery protection circuit. The battery device has batteries BAT1 to BAT4, switches SW1 to SW5, a battery protection circuit 40, and a fuse 20. The battery protection circuit 40 includes a power supply terminal VDD, intermediate terminals VC1 to VC3, a ground terminal VSS, and an output terminal VOUT. Further, the battery protection circuit 40 includes a pull-up resistor 44, a comparison circuit (not shown), a reference voltage circuit (not shown), and a logic circuit 41. The logic circuit 41 has a reset circuit 41a. The comparison circuit and the reference voltage circuit function as a monitoring circuit -15-200950245 The comparison circuit 42 has an N-type well 42a and an N-type well 43b. The logic circuit 41 has an N-well 42b. The battery protection circuit 40 has a parasitic diode connected between the N-well 42a and the P-type substrate (Psub) connected to the intermediate terminal VC2. Further, the battery protection circuit 40 has a base as a P-type substrate (p sub), an emitter as an N-well 42a, and a collector as a parasitic bipolar of the N-well 42b. Crystal 42. Further, the battery protection circuit 40 has a base as a P-type substrate (Psub), an emitter as an N-type well 42a, and a collector as a parasitic bipolar of an N-type well 42b. Crystal 43. Here, the N-type well 42a is provided at the intermediate terminal VC2. The N-type well 42b' is not provided in the intermediate terminal VC2, and is disposed close to the N-type well 42a. The N-type well 43b is disposed not in the intermediate terminal VC2, but is disposed adjacent to the N-type well 42a, and is disposed to surround the N-type well 42a. Further, the reset circuit 41a is designed such that the voltage of the N-type well 43b reaches the vicinity of the voltage of the intermediate terminal VC2, and the voltage of the output terminal of the reset circuit 41a is made low. Next, the intermediate terminal VC2 is connected before the ground terminal VSS is connected, and the battery protection circuit 40 is connected to the batteries BAT1 to BAT4. Only the switch SW1 and the switch SW3 are turned on (ON), and the power supply terminal VDD is connected to the battery BAT1. The positive electrode terminal and the operation of the battery protection circuit 40 when the intermediate terminal VC2 is connected to the positive terminal of the battery BAT3. The voltage of the N-type well 42 a becomes the voltage of the intermediate terminal VC2, and when the voltage of the P-type base 200950245 is higher than the voltage of the N-type well 42a, the parasitic diode flow is mediated by the ground terminal VSS to the intermediate terminal VC2. The directional current causes the parasitic bipolar transistor 42 to operate by the forward current (base current). Thereby, the current flows from the N-type well 42b as the collector to the N-type well 42a which is the emitter, and the voltage of the N-type well 42b becomes the voltage of the intermediate terminal VC2. At this time, the parasitic bipolar transistor 43 also operates in the same manner as described above, and the current flows from the N-type well 43b as the collector to the N-type well 42a which is the emitter, and the voltage of the N-type well 43b also becomes the voltage of the intermediate terminal VC2. The voltage at the input terminal of the reset circuit 41a becomes a low level. In this way, the reset circuit 31a forcibly resets a specific flip-flop (not shown) or the like inside the pole circuit 41, so the logic circuit 41 is reset to the 'logic circuit 41'. The signal that makes the battery device unusable is not output. ❹ [Simple description of the diagram] Figure 1 shows the diagram of the battery protection circuit. 2 is a configuration diagram showing a battery protection circuit. Fig. 3 is a configuration diagram showing a battery protection circuit. Fig. 4 is a configuration diagram showing a prior art battery protection circuit. [Description of main component symbols] BAT1 to BAT4: Battery SW1 to SW5: Switch-17- 200950245 VDD: Power supply terminal VC1 to VC3: Intermediate terminal VSS: Ground terminal VOUT: Output terminal 20: Fuse 3 0 : Battery protection circuit 3 1 : Logic circuit 3 1 a : reset circuit 32 to 33: parasitic bipolar transistor 32a to 32b, 33b: P-type well 3 4: pull-down resistor 3 6 to 3 9 : comparison circuit 36a to 39a: reference voltage circuit