TW200947676A - Method and device for improving stability of 6T SGT CMOS SRAM cell - Google Patents

Method and device for improving stability of 6T SGT CMOS SRAM cell Download PDF

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TW200947676A
TW200947676A TW098110603A TW98110603A TW200947676A TW 200947676 A TW200947676 A TW 200947676A TW 098110603 A TW098110603 A TW 098110603A TW 98110603 A TW98110603 A TW 98110603A TW 200947676 A TW200947676 A TW 200947676A
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sgt
transistor
current path
sram
gate
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Fujio Masuoka
Keon-Jae Lee
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Unisantis Electronics Jp Ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
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    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

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Abstract

Provided are a device structure of 6T SGT CMOS SRAM cell having sufficiently high SNM, and a manufacturing method thereof. The SGT device of the present invention includes an access NMOS device having a first crystallization surface as side wall so as to have a first carrier mobility, a pull-down NMOS device having a second crystallization surface as side wall so as to have a second carrier mobility, and a pull-up PMOS device having a third crystallization surface as side wall so as to have a third carrier mobility, wherein at least one of the first, the second and the third crystallization surfaces is different from the other two crystallization surfaces. This is because it is formed with a SGT transistor having a surface with low carrier mobility and having a relatively low gain, and a SGT transistor having a surface with high carrier mobility and having a relatively high gain. The SGT having a surface with high mobility has a higher gain than the SGT having a surface with low mobility.

Description

200947676 、 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種改善6T SGT ( Surrounding Gate Transistor ;環繞閘極式電晶體）CMOS ( Complementary Metal-Oxide Semiconductor ;互補式金屬氧化物半導體） SRAM ( Static random access memory ;靜態隨機存取記憶 體）單元（cell)的安定性的方法及其構造。 【先前技術】 ❹ SRAM最常作為積體電路内的嵌入式記憶體來使 用’其面積約占晶片總面積的60%至70%，且約占]V1PU (micro processing unit ;微處理器）的總電晶體數的75〇/〇 至85%。以往，SRAM單元係以讀出時不會改變單元的資 料’且寫入時能迅速地改變單元的狀態之方式來設計。 SRAM讀出時的安定性是由存取NMOS以及下拉NM0S (NPD (NMOS pull-down)或驅動電晶體）的驅動能力的 〇 相對強度來決定。另一方面，SRAM寫入時的安定性主要 是由上拉（pull-up)PMOS(或負載電晶體）以及下拉NM〇s 電晶體的驅動能力的相對強度來決定。然而，當增大不拉 NMOS電晶體的強度時，雖會增加讀出時的安定性，但卻 會降低寫入時的安定性。對於讀出與寫入之這種相反的要 求’在裝置（device)的設計中，係以取得相對強度的平 衡之方式來對應。一般而言，SRAM單元的讀出動作對於 電性的外部干擾承受力非常的弱。 大部分在SRAM單元中所產生故障是因為靜態雜訊 320109R1 4 200947676 „ 容限（SNM : Static Noise Margin )小所引起的故障。所謂 靜態雜訊容限係定義為使存在於單元的各記憶節點之單元 狀態反轉所需的最小雜訊電壓。存取NMOS電晶體係與上 拉PMOS並排配置，藉此降低讀出動作時SRAM反相器的 增益。結果’ SRAM的記憶有「〇」的節點會因為按照存取 NM0S以及下拉NMOS的電壓分割而上升至比接地電壓還 高的電屢。亦即，驅動NMOS電晶體的電導相對於存取 0 NM0S電晶體的電導之比，係有用以得知SRAM單元的讀 出安定性的基本作用。此比在CMOS SRAM的設計領域中 稱為「貝他比（万比）」。由於各個電晶體的驅動能力（0 ) 係與yCoxW/L (移動率X電容X通道寬度/閘極長度）相 .等，因此召比如以下所示。 [數學式1]200947676, VI. Description of the Invention: [Technical Field] The present invention relates to an improved 6T SGT (Surrounding Gate Transistor) CMOS (Complementary Metal-Oxide Semiconductor) SRAM (Static random access memory; static random access memory) cell stability method and its construction. [Prior Art] ❹ SRAM is most often used as an embedded memory in an integrated circuit. 'The area is about 60% to 70% of the total area of the chip, and it occupies about 1 part of the V1PU (micro processing unit; microprocessor). The total number of transistors is 75 〇 / 〇 to 85%. Conventionally, SRAM cells have been designed so that the state of the cell is not changed when reading, and the state of the cell can be quickly changed when writing. The stability of the SRAM readout is determined by the relative intensity of the drive capability of the NMOS and the pull-down NM0S (NPD (NMOS pull-down) or drive transistor). On the other hand, the stability of the SRAM write is mainly determined by the relative strength of the pull-up PMOS (or load transistor) and the pull-down NM〇s transistor. However, when the strength of the NMOS transistor is not increased, the stability at the time of reading is increased, but the stability at the time of writing is lowered. The opposite requirement for read and write 'in the design of the device corresponds to achieving a balance of relative intensities. In general, the readout action of the SRAM cell is very weak against electrical external interference. Most of the faults in the SRAM unit are caused by static noise 320109R1 4 200947676 „ SNM: Static Noise Margin is small. The so-called static noise tolerance is defined as the memory nodes present in the unit. The minimum noise voltage required for the cell state reversal. The access NMOS transistor system and the pull-up PMOS are arranged side by side, thereby reducing the gain of the SRAM inverter during the read operation. As a result, the memory of the SRAM has a "〇" The node rises to a higher frequency than the ground voltage by dividing the voltage by accessing the NM0S and the pull-down NMOS. That is, the ratio of the conductance of the driving NMOS transistor to the conductance of the access 0 NMOS transistor is useful for understanding the basic function of the read stability of the SRAM cell. This ratio is called "beta beta (Wanbi)" in the design field of CMOS SRAM. Since the driving ability (0) of each transistor is the same as yCoxW/L (mobility X capacitance X channel width/gate length), etc., the call is as follows. [Math 1]

(有關更詳細的資訊，請參.照Seevinck等著之r MOS SRAM單元的靜態雜訊容限解析」、IEE]E JSSC, sc —22卷， 第5號，1987年1〇月，第748頁） 更詳而言之’讀出動作中的電流係通過位元線、存取 NMOS、以及下拉NM〇s而流入接地。因此，記憶節點的 電壓（Vs)係由泠比來決定，並以以下的數學式表示。 320109R1 200947676 [數學式2] vds < vd6at (linear) [數學式3](For more detailed information, please refer to the static noise tolerance analysis of the r MOS SRAM unit by Seevinck," IEE]E JSSC, sc-22, No. 5, 1987, January, 748 Page) In more detail, the current in the read operation flows into the ground through the bit line, the access NMOS, and the pull-down NM〇s. Therefore, the voltage (Vs) of the memory node is determined by the 泠 ratio and is expressed by the following mathematical formula. 320109R1 200947676 [Math 2] vds < vd6at (linear) [Math 3]

^ =^(V〇-Vtk)2 (yVAs牟 VG-VJ ❹ Vds 〉 Vdsat (Sat) [數學式4] {linear) = βάήνβ x (VG - Vth -xVs 2 [數學式5] (針對存取NMOS不會因為反向閘極偏壓（back gate bias ) 而受干擾之SOI ( silicon-on-insulator ;絕緣層上覆石夕）晶 圓的情形） [數學式6] 1 drive (linear) = Iaocess {saturated ) 6 320109R1 200947676 [數學式7] βdm^ =^(V〇-Vtk)2 (yVAs牟VG-VJ ❹ Vds 〉 Vdsat (Sat) [Math 4] {linear] = βάήνβ x (VG - Vth -xVs 2 [Math 5] (for access The NMOS does not interfere with the SOI (silicon-on-insulator) wafer due to the back gate bias. [Math 6] 1 drive (linear) = Iaocess {saturated ) 6 320109R1 200947676 [Math 7] βdm

A ratioA ratio

在上述的關係中，冷比係用以決定讀出時記憶為「〇」 的節點電壓Vs會上升多少。yj比愈大（冷比> 1或者 a P drive > Θ access ) ’傳達至下拉NMO S之記憶節點的電壓（％ ) 上升就愈小，用以反轉單元所需的雜訊電壓就愈高。換言 之，沒比愈大單元愈安定，且SNM愈大。然而，在平面 型的MOS裝置中’當增大冷比時，所需的wdrive會增大， 結果會使單元尺寸變大（因而亦會增加成本）。因此，取 得單元尺寸與SRAM安定性之間的平衡，為設計最隹的 SRAM單元時重要的重點。 為了提供由高性能的複數個電晶體所構成的積體電 © 路，已提案有一種稱為環繞閘極式電晶體（以下稱為 「SGT」）之 FET (Field Effect Transistor;場效電晶體） (「IEEE Trans. Electron Dev·」、第 38 卷（3)、第 579 頁至第 583 頁（1991 年）；「IEDMTech. Dig.」、第 736 頁（1987年）；日本應用物理學會誌、第43 ( 10)卷、第 6904頁（2004年）；以及美國專利第5,258,635號）。藉 由使用SGT來抑制「短通道效應（SCE: Short Channel Effects )」並減少漏電流，而能獲得理想的切換（switching ) 動作。並且’在SGT中，由於閘極面積增大，因此不用增 7 320109R1 200947676 v 大裝置的閘極長度即可獲得良好的電流控制。此外，亦提 案有一種多面 SGT CMOS ( multiple plane SGT CMOS )， 係藉由將SGT柱（pillar)的側壁作成高移動率的結晶面， 而能縮小裝置密度。 已提案有一種由SGT所構成的SRAM (參照美國專 利第5,994,735號）。第4圖係顯示由兩個驅動電晶體 (NMOS) 1001、兩個存取鰭式電晶體1〇〇2、以及兩個負 載電晶體1003所構成的SGT SRAM之佈局圖。符號1004 為接觸部。第5圖（a)係顯示具有四個驅動電晶體（DR1、 DR2、DR3、DR4)、兩個存取鰭式電晶體（TR1、TR2)、 以及兩個負載電晶體（L01、L02 )之FINEFT ( Fin Field Effect Transistor ;鰭式場效電晶體）SRAM單元。第5 圖（b )係顯示具有兩個驅動電晶體（NPD、NPD2 )、兩 個存取籍式電晶體（Access、Access〗）、以及兩個負載電 晶體（Load、Load2)之 6T FINFET SRAM 單元（參照 © Gangwal等、「IEEE訂製積體電路會議」、2006年9月、 第433頁）。驅動電晶體（NPD、NPD2)係作成根據所對 應的結晶面會有不同的增益，而成為相對於存取電晶體 (Access、Access2 )與負載電晶體（ Load、Load2 )旋轉 45°的結晶面。第5圖（c)係顯示具有兩個驅動電晶體 (N102、N103)、兩個存取鰭式電晶體（ν100、Ν101)、 以及兩個負載電晶體（P100、Pl〇l)之6T FINFET SRAM 單元（參照美國專利第6,967,351號）。此外，包含有兩 個下拉NMOS 1011、兩個存取NMOS 1012、以及兩個上 8 320109R1 200947676 拉PMOS 1013。驅動電晶體（N102、N101}係作成會根In the above relationship, the cold ratio is used to determine how much the node voltage Vs that is stored as "〇" during reading will rise. The larger the yj ratio (cold ratio > 1 or a P drive > Θ access ) 'The voltage (%) that is transmitted to the memory node of the pull-down NMO S rises as small as it is to reverse the noise voltage required by the unit. The higher the height. In other words, no bigger and stronger unit, and the larger the SNM. However, in a planar MOS device, when the cold ratio is increased, the required wdrive is increased, and as a result, the cell size is increased (and thus the cost is increased). Therefore, the balance between cell size and SRAM stability is an important focus when designing the most stringent SRAM cells. In order to provide an integrated circuit composed of a plurality of high-performance transistors, a FET (Field Effect Transistor) called a surround gate transistor (hereinafter referred to as "SGT") has been proposed. ("IEEE Trans. Electron Dev.", Vol. 38 (3), pp. 579-583 (1991); "IEDMTech. Dig.", p. 736 (1987); Japanese Society of Applied Physics , vol. 43 (10), p. 6904 (2004); and U.S. Patent No. 5,258,635). By using SGT to suppress "SCE: Short Channel Effects" and reduce leakage current, an ideal switching operation can be obtained. And in the SGT, since the gate area is increased, good current control can be obtained without increasing the gate length of the large device. In addition, a multi-faceted SGT CMOS (Multiplane SGT CMOS) is also proposed, which can reduce the device density by making the sidewall of the SGT pillar a high mobility crystal plane. An SRAM consisting of SGT has been proposed (see U.S. Patent No. 5,994,735). Fig. 4 is a layout view showing an SGT SRAM composed of two driving transistor (NMOS) 1001, two access fin transistors 1, 2, and two load transistors 1003. Symbol 1004 is the contact portion. Figure 5 (a) shows four drive transistors (DR1, DR2, DR3, DR4), two access fin transistors (TR1, TR2), and two load transistors (L01, L02). FINEFT (Fin Field Effect Transistor) SRAM cell. Figure 5 (b) shows a 6T FINFET SRAM with two drive transistors (NPD, NPD2), two access registers (Access, Access), and two load transistors (Load, Load2). Unit (Refer to © Gangwal et al., "IEEE Customized Integrated Circuit Conference", September 2006, p. 433). The driving transistor (NPD, NPD2) is formed to have a different gain depending on the corresponding crystal plane, and becomes a crystal plane rotated by 45° with respect to the access transistor (Access, Access2) and the load transistor (Load, Load2). . Figure 5(c) shows a 6T FINFET with two drive transistors (N102, N103), two access fin transistors (ν100, Ν101), and two load transistors (P100, Pl〇l) SRAM unit (refer to U.S. Patent No. 6,967,351). In addition, there are two pull-down NMOS 1011, two access NMOS 1012, and two upper 8 320109R1 200947676 pull PMOS 1013. Driving transistor (N102, N101} is made into a root

W 據對應的結晶面會有不同的增益，而成為相對於存取電晶 體（N100、N101)與負載電晶體（P100、P101)旋轉45。 之結晶面。 專利文獻1 :美國專利第5,258,635號 專利文獻2 :美國專利第5,994,735號 專利文獻3 :美國專利第6,967,351號 _ 專利文獻4 :美國專利第3,603,848號 ❹ 一 專利文獻 5 : PCT/JP2007/021052 非專利文獻1 : Seevinck等著之「MOS SRAM單元的 靜態雜訊容限解析」、IEEE JSSC，sc-22卷，第5號，1987 年10月，第748頁 非專利文獻 2 :「IEEE Trans· Electron Dev.」、第 ％ 卷（3)、第579頁至第583頁（1991年）· 非專利文獻 3:「IEDMTech. Dig.」、第 736 頁（1987 ©年） 非專利文獻4 :日本應用物理學會誌、第43 ( 10)卷、 第 0904 頁（2004 年） 非專利文獻5 : Gangwal等、「IEEE訂製積體電略會 議」、2006年9月、第433頁 非專利文獻6 : Cullity等著之「X線折射要素」、第 2 版、Addison-Wisley Publishing company Inc·、第 76 夷、 1978 年 【發明内容】 9 32〇1〇9Ri 200947676 (發明所欲解決之課題） 然而，在習知的SGT中，皆無法提供能有效率地解 決在安定的SGT SRAM單元的設計中所產生的幾個問題 之解決方法。 本發明的目的係提供一種具有非常高的SNM之6T SGT CMOS SRAM單元的裝置構造及其製造方法。 (解決課題的手段） 為了達成上述目的，本發明的SGT半導體係包含有： ❿ SGT本體部，係包含有：第一部分，係具有賦予第一 載子移動率之側壁的第一面方位；以及第二部分，係具有 賦予第二載子移動率之前述侧壁的第二面方位； 存取電晶體，係形成於前述SGT本體部的前述第一 部分；以及 驅動電晶體，係形成於前述SGT本體部的前述第二 部分；其中， ® 前述存取電晶體係η通道電晶體，. 前述驅動電晶體係η通道電晶體； 前述存取電晶體及驅動電晶體係記憶體單元的一部 分; 前述存取電晶體係為了傳送資料而連接至前述驅動 電晶體。2 前述，第一載子移動率係能作成比前述第二載子移動 率還小。 ' . 前述存取電晶體及閂鎖電晶體係具有增益，且由於前 10 320109R1 200947676 乂 述第一載子移動率比前述第二載子移動率還小，因此前述 存取電晶體增益能作成比前述閂鎖電晶體還小。 前述第一面方位係能作成{110}面，前述第二面方 位係能作成{100}面。 前述記憶體單元係例如為SRAM記憶體單元^ 為了達成上述目的，本發明係—種包含有複數個 之SGT半導體記憶體，係包含有： ❹ 第〆及第二SGT，係具有作為閘極之第—線，且各個 SGT的電流路徑的一端連接於供铪有基準電位的基準電 極； 土. Ι三及第四SGT，#、具有作為閘極之第二線，且各個 SGT的電流路梭的一端連接於前述基準電極. 帛玉SGT ’係具有作為閘極之第一字線，且SGT電 流路徑的一端連接於前述第一及第一乂 一 汉弟一 ^GT的前述電流路 徑的另〆侧； © 第六SGT，係具有作為閘極之第二字線，且sgt電 流路彳H端連接於_第三及第四SGT的前述電流路 徑的另〆侧； 第七場效電晶體’係具有前述第一線作為閘極；以及 第八場效電晶體’係具有前述第二線作為閘極；其中， 前述第-及第二SGT的前述電流路徑係並聯連接於 前述第五SGT的前述電流路徑的前述一端與前述基準電 極之間； 前述第二及第四SGT的前述電流路徑係連接於前述 Π 320109R1 200947676 、 第六SGT的前述電流路徑的前述一端與前述基準電極之 間。 前述第一、第二、第三、以及第四電晶體各者係能形 成驅動電晶體’前述第五及第六電晶體各者係能形成存取 電晶體。 前述第七及第八SGT電流路徑的一端係連接於例如 供給有電源電壓之電源電極。 ❹ 本發明的實施形態較佳為各個電晶體具有不同的增 益，且可應用於各種裝置。在這種裝置中，包含有例如問 鎖這類廣範圍的邏輯電路。在本發明的一個實施形態中， 係應用於「靜態隨機存取記憶體（SRAM)」單元的設計 及其製造。 本發明的第一實施形態為SGT裝置，係包含有：存 取NMOS裝置，係以成為第一載子移動率之方式將侧壁面 作成第一結晶面；下拉NMOS裝置，係以成為第二載子移 ❹ 動率之方式將側壁面作成第二結晶面；以及上拉PMOS裴 置，係以成為第三載子移動率之方式將侧壁面作成第三結 晶面；其中，第一、第二、以及第三結晶面中的至少一個 結晶面與其他兩個結晶面不同。此實施形態係由具有低栽 子移動率之增益相對較低的SGT電晶體、以及具有高載子 移動率之增益相對較高的SGT電晶體所形成。具有高移動 率之面的SGT係具有比具有低移動率之面的S GT還焉的 增益。因此，6TSGT SRAM單元的第一實施形態不會不利 地增大SRAM單元面積，而能提供一種利用具有不同的增 12 320109R1 200947676 益來改善SNM之裝置及其設計方法。 作為第一實施形態的實施例，係以η型SGT的矩形 柱的侧壁的面方位會成為{110}，而另一個η型SGT的 矩形柱的側壁的面方位會成為U〇〇}之方式來形成。在 { 110}面中電子的移動率約為在{ 100}面中電子的移動 率的一半。因此，將{ 110 }面作為側壁而形成的η型SGT 係具有將{ 100}面作為側壁所形成的η型SGT大約一半 的增益。對於SRAM這種特定用途，作為傳輸裝置來使用 © 的η型SGT的本體部係沿著{ 110}面而形成。作為記憶 用閂鎖來使用的η型SGT以及ρ型SGT的本體部係沿著 { 100}面而形成。在{ 100}面中電洞的移動率係比在{ 110} 面中電子的移動率的一半還小。藉由將負載PMOS的面方 位作為{ 100}面來形成，能不對SRAM單元尺寸造成影 響而加大依存於上拉PMOS (或負載電晶體）以及下拉 NMOS電晶體的相對性強度之寫入雜訊容限。 ❹ 作為第一實施形態的另一個實施例，係能以各種結晶 面來形成η型SGT的圓柱狀柱的侧壁，而另一個η型SGT 的矩形柱的侧壁係以面方位會成為{100}面之方式來形 成。圓柱狀柱的電子移動率大約為{ 100}面的電子移動率 的3/4。亦即，圓柱狀柱的η型SGT係具有側壁為{ 100} 面之η型SGT大約3/4的增益。藉由利用這種設計方法， 能維持讀出的高安定性，且與上述的實施例栢比，能增大 寫入安定性。換言之，存取NFET的相對增益係能以不會 對單元尺寸造成影響，而謀求寫入/讀出安定性的平衡的 13 320109R1 200947676 方式來選擇。 本發明的第二實施形態係一種SGT裝置及其設計方 法，該SGT裝置係包含有：兩個存取NM〇s裝置，各個 存取NMOS係具有單一的SGr柱；四個下拉_〇3裝置， 各個下拉NM〇S係具有單一❸咖柱：以及兩個上拉 mos裝置m拉PMQS係具有單—的滞柱。 【實施方式】 ❹ 以下參照附圖詳細㈣本發㈣實施形態。 〈概要&gt; 地配固體的結晶中形成結晶之各原子係被遇期性 配置’禮_轉簡為晶袼 體 向量成分相同的三個的Γ係藉由與其方位相同的 基本向量成分料數^來表示。三個向量成分係以 的這種立方日格;表示。例如，在具有鑽石構造切 此括弧〔〕係表示特=著對角線〔111〕方向而存在。在 於軸方位的選擇方2的方向。然而，在結晶中，係依存 如，立方晶格中‘曰’在多個方向對稱變換中為等效。例 在結晶學上皆為等：ae方位〔間、〔_〕、以及〔0〇1〕 其等效的财方位。/此，妹弧表示某方饭及 皆包含等效的方位此，在以〈丨㈨〉來指定的情形中， 這些方位存在於原點10:〕地〔=〕、以及〔’〕。由於 本申請案中未有意 任意地疋義）的負侧，因此只要在 含正與負兩方的整的說明或另外的指示，結晶方位皆包 。因此，例如在以&lt;100&gt;所指定的情 14 32〇1〇9Ri 200947676 .形中’除了〔100〕、〔_〕、以及〔叫之外還包含 有〔-_〕、〔〇—1〇〕、以及〔〇〇—n各方位。結晶中 的面方位係能以-_三個整數來特定。用以指定一組平 行的平面所使用之括弧（）中的三個整數的組係指定特定 的平面。藉由特定的三個整數所指定的平面係與藉由相同 的二個整數所特定的方位垂直。例如，與方位〔刚〕垂直 的平面係以（100)來表示。因此，只要立方晶格的方向或 ❹平面為已知者’垂直於其的對象不需計算即可得知。與方 向的情形相同’晶格内的多個平面係根據對稱變換而等 效。例如（100)面、（010)面、以及（〇〇1)面係固有之 左右對稱的平面。在本申請案中，以括弧{}來表示平面 2其等效的所有平面。因此，以{1叫所指定的平面係包 含〇00)面、（010)面、以及（001)面。與結晶方位的 情形相同，只要未有其他說明或另外指示，本申請案中的 、Ό曰曰面白包含正與負的整數。因此，例如平面{ 1〇〇 }除了 ⑩（100)面、（010)面、以及(〇〇1)面之外，還包含：― 1〇〇)面、⑼一10)面、以及（00-1)面。 〔第一實施形態〕 、本發明的第一實施形態係為了藉由最佳化移動率、且 視需要在特疋的裝置中降低移動率以維持可容許或較佳的 14:而針相· FET電流通道及柱形狀使用各種的結晶面， 月谷易地應用於用以在相同的基板上製造cM〇s 之各種方法中。 第1圖係顯示在矽晶圓的（1〇〇)面（第1圖（a)) 15 320109R1 200947676 以及（110 )面（第1圖（b ))上所製造的Si SGT柱的侧 壁的各種平面方位（參照Cullity等著之「X線折射要素」、 第 2 版、Addison-Wisley Publishing company Inc.、第 76 頁、1978年）。第2圖係顯示與第12圖關連性說明的對 應於SGT柱的側壁的面方位之電子與電洞的移動率（參照 授與Sato等的美國專利第3,603,848號）。晶圓的（1〇〇) 面上的裝置係使用左侧的曲線（〇。/ ( 011 )至45。/ ( 001 ) 〇 侧壁’ 〔100〕區）’而（110)上的裝置則使用右侧的曲 線（0°/ (011)至 90。/ (001)側壁，〔110〕區）。電 流的流動方向在任一情形中乾與晶圓面垂直。 第3圖係顯示PCT/JP2007/071052所記載之各種 CMOS SGT的組合的正規化電流值之表。係顯示改變形狀 且旋轉形狀之25種CMOS的組合，且各組合具有不同的 柱形狀及其對應的面方位。在Vg_Vth=〇.6V以及vd== 0.05V下的圓形NMOS的絕對電流值係被選擇為基準值 © ( = 100)。 在SRAM單元的設計中一個重要的參數為存取NFET ^相對增益°例如’在存取NFET的相對增益過弱的情形 時（亦即石值小的情形），雖欲將資料記憶於Sram記憶 閃鎖内’但難謂具有足以信賴的寫入安定性。而在存取 NFET的相對增益過強的情形時（亦即β值大的情形）， 記憶閃鎖會有因為外部雜訊源或位元線的内部電容而導致 出乎意料之外的反轉之可能性。因此，f慎重決定存取 NFET的相對增益。在通常的設計參數中，存取Μ·的 320109R1 16 200947676 • 增益需作成大約為記憶閂鎖中的NFET的增益的一半。 在習知的平面型MOSFET中，係改變裝置間的相對 尺寸以對和存取NFET的增益之間賦予差值。例如’為了 增加特定裝置的強度，係增大裝置的寬度v因此，為了增 加相對於傳輸NFET之上述電晶體的增益’係增大記憶閂 鎖NFET的寬度。作為另一種方法，亦能加長傳輪NFET 的閘極長度’並減少上述NFET的相對增益。然而，在這 ❹些方法中，已增加強度的ΪΈΤ裝置的尺寸會增大，而無法 提高裝置密度。 在本發明中’不會對多個裝置的尺寸造成不良影響， 且可形成具有不同增益的NFET。尤其是對於存取η型 SGT，係藉由形成於低載子移動率面，而相對性地減少增 益。另一方面，對於記憶閂鎖η型SGT係藉由形成於高裁 子移動率面，而相對地增大增益。 亦即’為了根據用途來改善SRAM的SNM，或者為 ❹ 了調節讀出安定性與寫入安定性的平衡，係可根據第6圖 來選擇與其用途相符合的SGT SRAM的組合，藉此能獲得 需要或期望的SRAM的SNM。 與習知的平面型]MOS裝置或FINFET裝置不同，在 本貫施形態的SGT中，如第7圖所示，僅改變驅動NMOS 電晶體與存取NM0S電晶體之間的側壁的面方位，即能使 增益不同（亦即冷比）。藉由利用SGT固有的這種物理性 特性，能改善SNM，且不會如同在平面型裝置中所 招致的單元尺寸增大。 320109R1 200947676 ‘ 第8 (a)圖係顯示針對從第6圖所示的SRAM組合 中最佳化的一個SRAM例（第6圖的SRAM 12)，顯示 經凡成的SGT SRAM的電路圖與裝置的平面圖。队趟係 形成於矽晶圓的（100)面上。如第8(a)圖所示，此SRAM 係由兩個正方形存取NM〇s(N12、N22，四角柱的四個侧 壁皆為（110)面）、兩個正方形負載PMOS (P12、P22， 四角柱的四個侧壁皆為（100)面）、以及兩個正方形驅動 ❹ NM0S ( N32、N42，四角柱的四個侧壁皆為（1〇〇 )面） 所構成。負載PFET (P12及P22)與驅動NFET (N12及 N22 )係形成用以將資料記憶於SRAM單元内之記憶閂 鎖，而存取NFET (N32、N42)係達到作為用以在與記憶 問鎖之間傳輸資料之傳輸裝置的作用。 在第8 (a)圖所示的SRAM單元中，係以下述的連 接方式來構成SGT SRAM單元。首先，驅動NMOS (N32) 係具有與閘極共通的第一閘極線，且電流路徑的一端係連 ❿ 接於供給有基準電位Vss的基準電極。驅動nm〇S (N42) 係具有與閘極共通的第二閘極線，且電流路徑的一端係連 接於供給有基準電位Vss的基準電極。存取nm〇S (N12) 的閘極連接有第一字線，且存取NMOS (N12)的電流路 徑的一端係連接於上述驅動NMOS (N32)的電流路徑的 相反侧。存取NMOS (N22)的閘極連接有第二字線，且 存取NMOS ( N22 )的電流路徑的一端係連接於上述驅動 NMOS (N42)的電流路徑的相反側。 驅動NMOS (N32)的電流路徑係連接於存sNM〇s 320109R1 18 200947676 ' (N12)的電流路徑的一端與基準電極之間。驅動NM〇s (N42)的電流路徑係連接於存取NM〇s (N22)的電流路 徑與基準電極之間。 負載PMOS ( P12 ) 1係具有作為閘極的第一閘極線， 且電流路徑的一端係連接於供給有電源電壓的電源電極。 負載PMOS (P22)係具有作為閘極的第二閘極線，且電流 路徑的一端係連接於供給有電源電壓的電源電極。 ❾ 驅動NMOS (N32)的電流路徑的另一端係連接於負 載PMOS (P12)的電流路徑的另一端。上述驅動NM〇s (N42)的電流路徑的相反侧係連接於上述負載pm〇s (P22 )的電流路徑的相反側。 驅動NMOS (N32)與負載PMOS (P12)的閘極係連 接於上述驅動NMOS (N42)的電流路徑的相反側。驅動 NMOS (N42)與負載PMOS (P22)的閘極係連接於上述 負載PMOS (P12)的電流路徑的相反侧。 ❹ 第8 (b)圖至第8 (e)圖係顯示沿著第8 (a)圖的 A—A，、B —B，、C —C，、D —D’剖線所剖取之完成後的 6T SGT CMOS SRAM 裝置的縱剖面圖。NMOS(N12、N22、 N32、N42)的矽柱與PMOS (P12、P22)的矽柱係形成於 SOI晶圓上，且被閘極氧化膜131與閘極導體132包圍。 元件符號81為埋入氧化物，元件符號82為處理矽晶圓 (Handle Si Wafer)。NMOS (N12、N22、N32、N42)係 包含有N+型的源極與汲極118，PMOS (P12、P22)係包 含有P +型的源極與汲極116。藉由自對準矽化物 19 320109R1 200947676 (Self-Aligned Silicide) 120 與金屬線 152 連接各個 SGT SRAM裝置，形成第8 (a)團所示的SGT CMOS SRAM。 電介質130、136係將導體間予以分離。 第9 ( a )圖係顯示第一實施形態的第二實施例的SGT SRAM裝置構造（第6圖的SRAM15)。第9 (a)圖係形 成於石夕晶圓的（100)面之SRAM的電路圖與裝置的平面 圖。本實施例的SRAM係由兩個圓柱狀存取NMOS ( N11、 N21 )、矩形柱的西個侧壁皆為（1 〇〇 )面的兩個正方形負 载PMOS ( P11、P21 )、以及四個側壁皆為（1 〇〇 )面的兩 個正方形驅動NMOS (N31、N41)所構成。 第9 ( b )圖至第9 ( e )圖係顯示沿著第9 ( a)圖的 A—A，、B —B’、C一 C’、D —D’剖線所剖取之完成後的 6TSGTCMOSSRAM裝4的縱剖面圖。N]V[OS(Nll、N21、 N31、N41)的矽柱與PMOS (Pll、P21)的矽柱係形成於 s〇I晶圓上，且被閘極氧化膜231與導體232包圍。元件 β 符號181為埋入氧化膜，元件符號182為處理矽晶圓。 NMOS (Nil、Ν21、Ν31、Ν41 )係包含有Ν+型的源極與 汲極218，PMOS (Pll、P21)係包含有P+型的源極與汲 極216。藉由自對準矽化物220與金屬線252連接各個SGT SRAM裝置，形成第9 ( a)圖所示的SGT CMOS SRAM。 電介質236、230係將導體間予以分離。 第10(a)圖係顯示第一實施形態的第三實施例的SGT SRAM裝置構造（第6圖的SRAM 14)。第10 (a)圖係 形成於矽晶圓的（100)面之SRAM的電路圖與裝置的平 20 320109R1 200947676 面圖。本實施例的SRAM係由兩個圓柱狀存取NMOS (N10、N20)、兩個圓柱狀負載PMOS(P10、P20)、以 及兩個正方形驅動NMOS (N30、N40，矩形柱的四個側壁 皆為（100)面）所構成。 第10 (b)圖至第8 (e)圖係顯示沿著第10 (a)圖 的A—A，、B —B，、C—C’、D —D’剖線所剖取之完成後 的6T SGT CMOS SRAM裝置的縱剖面圖。NMOS ( N10、 N20、N30、N40)的石夕柱與PMOS (P10、P20)的石夕柱係 形成於SOI晶圓上，且被閘極氧化膜331與導體332包圍。 元件符號281為埋入氧化膜，元件符號282為處理矽晶圓。 NMOS (N10、N20、N30、N40)係包含有N+型的源極與 汲極318，PMOS (P10、P20)係包含有P+型的源極與汲 極316。藉由自對準矽化物320與金屬線352連接各個SGT SRAM裝置，形成第10(a)圖所示的SGT CMOS SRAM。 電介質336、330係將導體間予以分離。 ❿ 〔第二實施形態〕 接著，說明包含有本發明的第二實施形態的SRAM之 半導體記憶體。第11 (a)圖係第二實施形態的SRAM電 路的電路圖以及完成後的SGT SRAM裝置的平面圖。如第 11(a)圖所示，在SRAM單元中，具有驅動電晶體（N33、 N43、N53、N63)的四個柱、NMOS (N13、N23)的兩個 柱、以及負載PMOS (P13、P23)的兩個柱。晶圓的面方 位係能使用例如矽（100)、矽（110)、矽（111)這種在 此領域中廣泛所使用之面方位。此外，能使用圓柱狀、正 21 320109R1 200947676 . 方形、矩形等之各種種類的矽柱形狀以及對應的側壁的面 方位。W has a different gain depending on the corresponding crystal plane, and is rotated 45 with respect to the access transistor (N100, N101) and the load transistor (P100, P101). Crystallized surface. Patent Document 1: U.S. Patent No. 5,258,635, Patent Document 2: U.S. Patent No. 5,994,735, Patent Document 3: U.S. Patent No. 6,967,351, Patent Document 4: U.S. Patent No. 3,603,848, Patent Document 5: PCT/JP2007/021052 Non-Patent Document 1: Seevinck et al. "Static noise tolerance analysis of MOS SRAM cells", IEEE JSSC, sc-22, No. 5, October 1987, page 748 Non-Patent Document 2: "IEEE Trans Electron Dev.", vol. % (3), pp. 579 to 583 (1991) · Non-Patent Document 3: "IEDMTech. Dig.", p. 736 (1987 © Year) Non-Patent Document 4: Japanese Application Physics Society, Vol. 43 (10), p. 0904 (2004) Non-Patent Document 5: Gangwal et al., "IEEE Customized Integrated Meeting", September 2006, p. 433 Non-Patent Document 6: "X-ray refraction elements" by Cullity, 2nd edition, Addison-Wisley Publishing company Inc., 76th, 1978 [invention content] 9 32〇1〇9Ri 200947676 (problem to be solved by the invention) However, In the conventional SGT, it is impossible to provide efficiency. Solve several problems of the solution in stable design SGT SRAM unit produced. It is an object of the present invention to provide a device configuration of a 6T SGT CMOS SRAM cell having a very high SNM and a method of fabricating the same. (Means for Solving the Problem) In order to achieve the above object, an SGT semiconductor according to the present invention includes: a GTSGT main body portion including: a first portion having a first plane orientation that imparts a sidewall of a first carrier mobility; a second portion having a second plane orientation of the sidewalls imparting a second carrier mobility; an access transistor formed in the first portion of the SGT body portion; and a drive transistor formed in the SGT The second portion of the body portion; wherein: the access transistor system n-channel transistor, the driving transistor system n-channel transistor; the access transistor and a portion of the driving transistor system memory unit; The access cell system is connected to the aforementioned driver transistor for transferring data. 2 As described above, the first carrier mobility can be made smaller than the aforementioned second carrier mobility. The access transistor and the latch cell system have gains, and since the first 10 320109R1 200947676 cites that the first carrier mobility is smaller than the second carrier mobility, the access transistor gain can be made. It is smaller than the aforementioned latching transistor. The first plane orientation can be made into a {110} plane, and the second plane side can be made into a {100} plane. The memory unit is, for example, an SRAM memory unit. To achieve the above object, the present invention includes a plurality of SGT semiconductor memories, including: ❹ 〆 and second SGT, having a gate a first line, and one end of each current path of the SGT is connected to a reference electrode for which a reference potential is supplied; earth. Ι3 and 4th SGT, #, has a second line as a gate, and a current path shuttle of each SGT One end is connected to the aforementioned reference electrode. The Saitama SGT ' has a first word line as a gate, and one end of the SGT current path is connected to the aforementioned current path of the first and first first Han dynasty GT The sixth SGT has a second word line as a gate, and the sgt current path is connected to the other side of the current path of the third and fourth SGTs; the seventh field effect transistor 'the first line as the gate; and the eighth field effect transistor' has the second line as the gate; wherein the current paths of the first and second SGTs are connected in parallel to the fifth SGT The aforementioned current path Between the end of the reference electrode; the current path of the second and fourth SGT is connected to the system Π 320109R1 200947676, between the end of the reference electrode and the current path of a sixth SGT. Each of the first, second, third, and fourth transistors described above is capable of forming a drive transistor. Each of the fifth and sixth transistors described above is capable of forming an access transistor. One ends of the seventh and eighth SGT current paths are connected to, for example, a power supply electrode to which a power supply voltage is supplied.实施 Embodiments of the present invention preferably have different gains for each of the transistors and are applicable to various devices. In such a device, a wide range of logic circuits such as a lock are included. In one embodiment of the present invention, it is applied to the design and manufacture of a "Static Random Access Memory (SRAM)" unit. According to a first embodiment of the present invention, an SGT device includes: an access NMOS device configured to form a first crystal plane as a first carrier mobility; and a pull-down NMOS device to be a second carrier The sidewall surface is formed as a second crystal plane by the sub-movement method; and the pull-up PMOS device is configured to form the third crystal plane by the sidewall surface in such a manner as to become the third carrier mobility; wherein, the first and the second And at least one of the crystal faces of the third crystal face is different from the other two crystal faces. This embodiment is formed by an SGT transistor having a relatively low gain of a low plant mobility and an SGT transistor having a relatively high gain with a high carrier mobility. The SGT system with a high mobility plane has a gain that is more than the S GT with a low mobility plane. Therefore, the first embodiment of the 6TSGT SRAM cell does not disadvantageously increase the SRAM cell area, but can provide a device and a design method thereof that utilize different gains to improve the SNM. In the embodiment of the first embodiment, the plane orientation of the side wall of the rectangular column of the n-type SGT is {110}, and the plane orientation of the side wall of the rectangular column of the other n-type SGT becomes U〇〇} Way to form. The mobility of electrons in the {110} plane is about half of the mobility of electrons in the {100} plane. Therefore, the n-type SGT formed by using the {110} plane as the sidewall has a gain of about half of the n-type SGT formed by the {100} plane as the sidewall. For the specific use of SRAM, the body portion of the n-type SGT used as a transmission device is formed along the {110} plane. The body portions of the n-type SGT and the p-type SGT used as the memory latches are formed along the {100} plane. The mobility of the hole in the {100} plane is less than half of the mobility of the electrons in the {110} plane. By forming the plane orientation of the load PMOS as the {100} plane, it is possible to increase the relative intensity of the pull-up PMOS (or load transistor) and the pull-down NMOS transistor without affecting the size of the SRAM cell. The tolerance of the message. ❹ As another embodiment of the first embodiment, the side walls of the cylindrical column of the n-type SGT can be formed by various crystal faces, and the side walls of the rectangular column of the other n-type SGT are in the plane orientation. 100} face to form. The electron mobility of a cylindrical column is approximately 3/4 of the electron mobility of the {100} plane. That is, the n-type SGT of the cylindrical column has a gain of about 3/4 of the n-type SGT having a {100} plane. By using this design method, the high stability of reading can be maintained, and the writing stability can be increased as compared with the above-described embodiment. In other words, the relative gain of the access NFET can be selected in a manner that does not affect the cell size and seeks to balance the write/read stability. A second embodiment of the present invention is an SGT device and a design method thereof. The SGT device includes: two access NM〇s devices, each access NMOS system has a single SGr column; and four pull-down_〇3 devices Each pull-down NM〇S system has a single 柱 柱 column: and two pull-up mos devices m pull PMQS system with a single stagnation column. [Embodiment] ❹ Hereinafter, the embodiment (4) of the present invention will be described in detail with reference to the accompanying drawings. <Summary> The atomic system in which the crystals are formed in the solid crystals are arranged in a continuation manner. The three lanthanoids having the same composition of the crystal body are the same as the basic vector component number of the same orientation. ^ to express. The three vector components are represented by this cubic day; For example, in the case of a diamond structure, the brackets are represented by the diagonal [111] direction. In the direction of the selection side 2 of the axis orientation. However, in crystallization, depending on, the '曰' in the cubic lattice is equivalent in symmetric transformation in multiple directions. Examples are crystallographically equal: ae orientation [inter, [_], and [0〇1] their equivalent financial position. / This, the sister arc indicates that both the rice and the equivalent orientation are included. In the case of designation by <丨(九)>, these orientations exist at the origin 10:][=], and [’]. Since the negative side of the application is not intended to be arbitrarily arbitrarily defined, the crystal orientation is included as long as it contains a full or negative indication of both positive and negative. Therefore, for example, in the case of &lt;100&gt; specified 14 32〇1〇9Ri 200947676. In addition to [100], [_], and [calling also contains [-_], [〇-1 〇], and [〇〇-n all parties. The plane orientation in crystallization can be specified by -_ three integers. A group of three integers in parentheses () used to specify a set of parallel planes specifies a particular plane. The plane specified by a particular three integers is perpendicular to the orientation specified by the same two integers. For example, a plane perpendicular to the orientation [just] is represented by (100). Therefore, as long as the direction of the cubic lattice or the pupil plane is known, the object perpendicular to it can be known without calculation. As in the case of the direction, a plurality of planes within the crystal lattice are equivalent to the symmetry transformation. For example, the (100) plane, the (010) plane, and the (〇〇1) plane are inherently symmetrical planes. In the present application, all planes equivalent to plane 2 are represented by parentheses {}. Therefore, the plane specified by {1 is called 〇00), (010), and (001). As in the case of the crystal orientation, the facet white in the present application contains positive and negative integers unless otherwise stated or otherwise indicated. Therefore, for example, the plane {1〇〇} includes: “1”), (9)–10), and (00) in addition to the 10 (100) plane, the (010) plane, and the (〇〇1) plane. -1) Face. [First Embodiment] The first embodiment of the present invention is to maintain an allowable or preferable 14 by optimizing the mobility and, if necessary, reducing the mobility in a special device: The FET current path and the column shape use various crystal faces, and Moon Valley is easily applied to various methods for manufacturing cM〇s on the same substrate. Figure 1 shows the sidewalls of a Si SGT column fabricated on the (1) plane (Fig. 1(a)) 15 320109R1 200947676 and (110) plane (Fig. 1(b)) of the tantalum wafer. Various planar orientations (see "X-ray Refraction Elements" by Cullity, 2nd ed., Addison-Wisley Publishing company Inc., pp. 76, 1978). Fig. 2 is a view showing the movement ratio of electrons and holes corresponding to the plane orientation of the side wall of the SGT column as described in connection with Fig. 12 (refer to U.S. Patent No. 3,603,848 to Sato et al.). The device on the (1〇〇) side of the wafer uses the curve on the left side (〇. / ( 011 ) to 45. / ( 001 ) 〇 sidewall ' [100] area) and the device on (110) Use the curve on the right (0° / (011) to 90. / (001) side wall, [110] area). The flow direction of the current is either perpendicular to the wafer face in either case. Fig. 3 is a table showing normalized current values of combinations of various CMOS SGTs described in PCT/JP2007/071052. A combination of 25 CMOS shapes that change shape and rotate shape is shown, and each combination has a different column shape and its corresponding face orientation. The absolute current value of the circular NMOS at Vg_Vth = 〇.6V and vd == 0.05V is selected as the reference value © (= 100). An important parameter in the design of the SRAM cell is the access NFET ^ relative gain ° such as 'in the case where the relative gain of the access NFET is too weak (that is, the case where the stone value is small), although the data is to be memorized in the Sram memory. Inside the flash lock 'but it's hard to have enough write stability. In the case where the relative gain of the access NFET is too strong (that is, the case where the β value is large), the memory flash lock may have an unexpected reversal due to the external noise source or the internal capacitance of the bit line. The possibility. Therefore, f carefully decides the relative gain of the access NFET. In the usual design parameters, the access port 320109R1 16 200947676 • The gain needs to be approximately half the gain of the NFET in the memory latch. In conventional planar MOSFETs, the relative dimensions between the devices are varied to impart a difference between the gain and the gain of the access NFET. For example, in order to increase the strength of a particular device, the width v of the device is increased. Therefore, the width of the memory latch NFET is increased in order to increase the gain with respect to the transistor of the NFET. Alternatively, the gate length of the passer NFET can be lengthened and the relative gain of the NFET described above can be reduced. However, in these methods, the size of the device having increased strength is increased, and the density of the device cannot be increased. In the present invention, 'the size of a plurality of devices is not adversely affected, and NFETs having different gains can be formed. In particular, for accessing the n-type SGT, the gain is relatively reduced by forming on the low carrier mobility plane. On the other hand, the memory latch n-type SGT is relatively increased in gain by being formed on the high-cut mobility plane. That is, in order to improve the SNM of the SRAM according to the use, or to adjust the balance between read stability and write stability, a combination of SGT SRAMs compatible with the use can be selected according to FIG. Obtain the SNM of the SRAM that is needed or desired. Unlike the conventional planar type MOS device or FINFET device, in the SGT of the present embodiment, as shown in FIG. 7, only the plane orientation of the sidewall between the driving NMOS transistor and the access NMOS transistor is changed. That is, the gain can be different (that is, the cold ratio). By utilizing this physical property inherent to the SGT, the SNM can be improved without increasing the size of the cells as incurred in a planar device. 320109R1 200947676 ' Figure 8 (a) shows an example of an SRAM optimized from the SRAM combination shown in Figure 6 (SRAM 12 of Figure 6) showing the circuit diagram and device of the SGT SRAM Floor plan. The team system is formed on the (100) side of the germanium wafer. As shown in Figure 8(a), the SRAM is accessed by two squares NM〇s (N12, N22, the four sides of the four-corner post are all (110) faces), and two square-loaded PMOSs (P12, P22, the four side walls of the square column are all (100) faces, and two square drive ❹ NM0S (N32, N42, the four side walls of the four corner posts are all (1 〇〇) faces). The load PFET (P12 and P22) and the driving NFET (N12 and N22) form a memory latch for storing data in the SRAM cell, and the access NFET (N32, N42) is used as a lock for memory and memory. The role of the transmission device between the transmission of data. In the SRAM cell shown in Fig. 8(a), the SGT SRAM cell is constructed by the following connection method. First, the driving NMOS (N32) has a first gate line common to the gate, and one end of the current path is connected to the reference electrode to which the reference potential Vss is supplied. The drive nm 〇 S (N42) has a second gate line common to the gate, and one end of the current path is connected to the reference electrode to which the reference potential Vss is supplied. The gate of the access nm 〇 S (N12) is connected to the first word line, and one end of the current path of the access NMOS (N12) is connected to the opposite side of the current path of the drive NMOS (N32). The gate of the access NMOS (N22) is connected to the second word line, and one end of the current path for accessing the NMOS (N22) is connected to the opposite side of the current path of the driving NMOS (N42). The current path of the driving NMOS (N32) is connected between one end of the current path of the sNM〇s 320109R1 18 200947676 ' (N12) and the reference electrode. The current path driving NM〇s (N42) is connected between the current path of the access NM〇s (N22) and the reference electrode. The load PMOS (P12) 1 has a first gate line as a gate, and one end of the current path is connected to a power supply electrode to which a power supply voltage is supplied. The load PMOS (P22) has a second gate line as a gate, and one end of the current path is connected to a power supply electrode to which a power supply voltage is supplied.另一 The other end of the current path driving the NMOS (N32) is connected to the other end of the current path of the load PMOS (P12). The opposite side of the current path of the above-described driving NM〇s (N42) is connected to the opposite side of the current path of the above load pm〇s (P22). The gate of the driving NMOS (N32) and the load PMOS (P12) is connected to the opposite side of the current path of the driving NMOS (N42). The gate of the driving NMOS (N42) and the load PMOS (P22) is connected to the opposite side of the current path of the load PMOS (P12). ❹ Sections 8(b) through 8(e) show the cut along the line A-A, B-B, C-C, D-D' in Figure 8(a) Longitudinal section of the completed 6T SGT CMOS SRAM device. The NMOS (N12, N22, N32, N42) mast and the PMOS (P12, P22) mast are formed on the SOI wafer and surrounded by the gate oxide film 131 and the gate conductor 132. The component symbol 81 is a buried oxide, and the component symbol 82 is a handle wafer (Handle Si Wafer). The NMOS (N12, N22, N32, N42) includes an N+ source and a drain 118, and the PMOS (P12, P22) package includes a P+ source and a drain 116. Each SGT SRAM device is connected to the metal line 152 by self-aligned germanide 19 320109R1 200947676 (Self-Aligned Silicide) 120 to form the SGT CMOS SRAM shown in group 8 (a). Dielectrics 130, 136 separate the conductors. The ninth (a)th diagram shows the SGT SRAM device structure (SRAM 15 of Fig. 6) of the second embodiment of the first embodiment. Figure 9(a) is a plan view of the circuit diagram and device of the SRAM of the (100) plane of the Shixi wafer. The SRAM of this embodiment is composed of two cylindrical access NMOSs (N11, N21), two square-loaded PMOS (P11, P21), and four sides of the west side wall of the rectangular column. The side walls are composed of two square drive NMOS (N31, N41) of (1 〇〇) plane. Figures 9 (b) through 9 (e) show the completion of the cut along the line A-A, B-B', C-C', D-D' of Figure 9 (a) Rear longitudinal section of the 6TSGTCMOSSRAM package 4. The pillars of N]V[OS (N11, N21, N31, N41) and the pillars of PMOS (P11, P21) are formed on the s〇I wafer, and are surrounded by the gate oxide film 231 and the conductor 232. The element β symbol 181 is a buried oxide film, and the element symbol 182 is a processed germanium wafer. The NMOS (Nil, Ν21, Ν31, Ν41) includes a Ν+ type source and a drain 218, and the PMOS (P11, P21) includes a P+ type source and a drain 216. The SGT CMOS SRAM shown in Fig. 9(a) is formed by connecting the SGT SRAM devices to the metal lines 252 by self-aligning the germanide 220. Dielectrics 236, 230 separate the conductors. Fig. 10(a) shows the SGT SRAM device configuration (SRAM 14 of Fig. 6) of the third embodiment of the first embodiment. Figure 10 (a) is a plan view of the circuit diagram of the SRAM formed on the (100) side of the germanium wafer and the flat 20 320109R1 200947676. The SRAM of this embodiment is composed of two cylindrical access NMOSs (N10, N20), two cylindrical load PMOSs (P10, P20), and two square drive NMOSs (N30, N40, four sides of the rectangular column are It is composed of (100) faces). Figures 10(b) through 8(e) show the completion of the cut along the line A-A, B-B, C-C', D-D' of Figure 10 (a) Longitudinal section of the rear 6T SGT CMOS SRAM device. The XI (N10, N20, N30, N40) Shi Xizhu and the PMOS (P10, P20) Shi Xizhu are formed on the SOI wafer, and are surrounded by the gate oxide film 331 and the conductor 332. The component symbol 281 is a buried oxide film, and the component symbol 282 is a processed germanium wafer. The NMOS (N10, N20, N30, N40) includes an N+ type source and a drain 318, and the PMOS (P10, P20) includes a P+ type source and a drain 316. The SGT CMOS SRAM shown in Fig. 10(a) is formed by connecting the SGT SRAM devices to the metal lines 352 by the self-aligned germanide 320. Dielectrics 336, 330 separate the conductors. [Second Embodiment] Next, a semiconductor memory including an SRAM according to a second embodiment of the present invention will be described. Fig. 11 (a) is a circuit diagram of the SRAM circuit of the second embodiment and a plan view of the completed SGT SRAM device. As shown in Figure 11(a), in the SRAM cell, there are four columns for driving transistors (N33, N43, N53, N63), two columns for NMOS (N13, N23), and a load PMOS (P13, Two columns of P23). The face orientation of the wafer can use, for example, 矽(100), 矽(110), 矽(111), which are widely used in the field. Further, it is possible to use various shapes of the column shape of the columnar shape, the square shape, the rectangular shape, and the like, and the surface orientation of the corresponding side wall.

第11 (b)圖至第11 (f)圖係顯示沿著第11 (a)圖 的 A — A，、B — B，、C — C，、D_D，、E — E’剖線所剖取之 完成後的6T SGT CMOS SRAM裝置的縱剖面圖。NMOS (N13、N23、N33、N43、N53、N63)的石夕柱與PMOS(P13、 P23)的矽柱係形成於SOI晶圓上，且被閘極氧化膜431 與導體432包圍。元件符號381為埋入氧化膜，元件符號 〇 382 為處理石夕晶圓。NMOS (N13、N23、N33、N43、N53、 ]Si63 )係包含有N+型的源極與汲極418，PMOS( P13、P23 ) 孫包含有P+型的源極與沒極416。藉由自對準發化物420 與金屬線452連接各個SGT SRAM裝置，形成第η (a) 圖所示的SGT CMOS SRAM裝置。電介質436、430係將 導:艨間予以分離。 本發明的第二實施形態的SRAM單元係具有使用並 ❹赠的驅動電晶體來取代第4圖所示的6T SRAM單元的驅 動電晶體之構造。在SGT中，由於柱係被矽柱徑固定，故 通道寬度一般也為固定。在本實施形態中，由於並聯連接 雨侧SGT柱’因此有效通道寬度為以—個柱所形成的驅動 電晶體的兩倍。因此，本實細·形態的兩個驅動電晶體的所 有元件電阻會變成具有一個電晶體之存取電晶體的一半。 国此’ 比為2，能獲得南SNM。在本實施形態中，驅動 電晶體的數目的比為2’係針對各個存取電晶體配置兩個 麟動電晶體。然而，此比並未限定於2，例如亦能為3、4、 320109R1 22 200947676 或者比3、4大者。 如第12 ( a )圖所示’能將本發明的第二實施形態與 第一實施形態予以結合。在第12 ( a)圖的SRAM單元中， 四個驅動電晶體（N34、N44、N54、N64，柱的四個側壁 皆為（110)面）、兩個存取NMOS (N14、N24，柱的四 個側壁皆為（110 )面）、以及兩個負載PMOS ( P14、P24， 柱的四個侧壁皆為（100)面）係形成於矽晶圓的（1〇〇) 面上。 第12(b)圖至第12(f)圖係顯示沿著第12(a)圖 的 A —A，、B —B，、C—C,、D —D，、E —E’剖線所剖取之 完成後的6T SGT CMOS SRAM裝置的縱剖面圖。NMOS (N14、N24、N34、N44、N54、N64 )的發柱與 pm〇S( P14、 P24)的梦柱係形成於SOI晶圓上，且被閘極氧化膜531 與導體532包圍。元件符號481為埋入氧化膜，元件符號 482 為處理梦晶圓。NMOS ( N14、N24、N34、N44、N54、 ❹ N64)係包含有N+型的源極與汲極518，PMOS(P14、P24) 係包含有P+型的源極與汲極516。藉由自對準矽化物52〇 與金屬線552連接各個SGT SRAM裝置，形成第12 (a) 圖所示的SGT CMOS SRAM。電介質536、530係將導體 間予以分離。 第13圖係顯示用以形成SGT SRAM的實際裝置構 造’而將本發明的較佳方法100作成流程圖之圖。第14 圖至第23圖係時間序列地顯示使用第13圖的方法之步驟 的圖’在各圖中，上方的圖為平面圖，下方的圖為沿著平 23 320109R1 200947676 面圖中的A — A’剖線所剖取時的.縱剖面圖。 毳 在使用本發明的方法100來形成SGT SRAM時的步 驟係如下述。首先’準備具有第一結晶方位之面的基板。 此基板係用以之後能利用預定的結晶面來作為通道者。尤 其在方法100的第一步驟102中，例如準備之後能利用結 晶面来製作FET的通道、且具有{ ι10}面或{ 100}面這 種第一結晶方位之適當的基板。結晶晶格的適當對準 (alignment)會因為對载子移動率等電性特性或其他材料 與化學處理產生何種反應等而對基板的重要特性產生重大 影響。如同後述，可藉由準備例如{ 11〇丨面或{ 1〇〇丨面 的基板，並根據方法1〇〇，而形成將之後可形成的結晶夜 作為通道來利用的SGT。 因此’使用本發明的方法1〇〇 ’能以將具有例如 {100} ( I10丨、{ 111丨這種方位的面作為侧壁之所有Figures 11(b) through 11(f) show the section taken along the line A-A, B-B, C-C, D_D, E-E' of Figure 11(a) Take a longitudinal section of the completed 6T SGT CMOS SRAM device. The pillars of the NMOS (N13, N23, N33, N43, N53, and N63) and the PMOS (P13, P23) are formed on the SOI wafer, and are surrounded by the gate oxide film 431 and the conductor 432. The component symbol 381 is a buried oxide film, and the component symbol 〇 382 is a processing stone wafer. The NMOS (N13, N23, N33, N43, N53, ]Si63) includes an N+ type source and a drain 418, and the PMOS (P13, P23) includes a P+ type source and a dipole 416. The SGT CMOS SRAM device shown in the nth (a) figure is formed by connecting the respective SGT SRAM devices to the metal wires 452 by the self-aligned hair 420. Dielectrics 436, 430 are separated from each other. The SRAM cell of the second embodiment of the present invention has a structure in which a driving transistor used and replaced with a driving transistor of the 6T SRAM cell shown in Fig. 4 is used. In the SGT, since the column system is fixed by the column diameter, the channel width is generally fixed. In the present embodiment, since the rain side SGT column is connected in parallel, the effective channel width is twice that of the driving transistor formed by the one column. Therefore, the resistance of all the elements of the two driving transistors of the present embodiment can become one half of the access transistor having one transistor. The country’s ratio is 2, and the South SNM can be obtained. In the present embodiment, the ratio of the number of driving transistors is 2', and two kinetic transistors are arranged for each access transistor. However, the ratio is not limited to 2, for example, it can be 3, 4, 320109R1 22 200947676 or larger than 3 or 4. The second embodiment of the present invention can be combined with the first embodiment as shown in Fig. 12(a). In the SRAM cell of Figure 12 (a), four drive transistors (N34, N44, N54, N64, the four sides of the column are all (110) faces), two access NMOS (N14, N24, column) The four sidewalls are all (110) planes, and the two load PMOSs (P14, P24, the four sidewalls of the pillar are all (100) planes) are formed on the (1) plane of the germanium wafer. Figures 12(b) through 12(f) show the A-A, B-B, C-C, D-D, E-E' lines along the 12th (a) A longitudinal section of the completed 6T SGT CMOS SRAM device is taken. The pillars of the NMOS (N14, N24, N34, N44, N54, N64) and the dream pillar of pm〇S (P14, P24) are formed on the SOI wafer, and are surrounded by the gate oxide film 531 and the conductor 532. The component symbol 481 is a buried oxide film, and the component symbol 482 is a dream wafer. The NMOS (N14, N24, N34, N44, N54, ❹ N64) includes an N+ source and a drain 518, and the PMOS (P14, P24) includes a P+ source and a drain 516. The SGT CMOS SRAM shown in Fig. 12(a) is formed by connecting each SGT SRAM device to the metal line 552 by self-aligned germanide 52A. Dielectrics 536, 530 separate the conductors. Figure 13 is a diagram showing a flow chart for forming the actual device configuration of the SGT SRAM and the preferred method 100 of the present invention. Fig. 14 to Fig. 23 are diagrams showing the steps of the method using the method of Fig. 13 in a time series. In each of the figures, the upper diagram is a plan view, and the lower diagram is A along the plane of the flat 23 320109R1 200947676. A'. A longitudinal section of the section taken at the section line. The steps in forming the SGT SRAM using the method 100 of the present invention are as follows. First, a substrate having a face having a first crystal orientation is prepared. This substrate is used to be able to utilize a predetermined crystal plane as a channel. In particular, in a first step 102 of the method 100, for example, a suitable substrate can be fabricated using a crystal plane to form a channel of the FET and having a first crystal orientation such as a {1010} plane or a {100} plane. The proper alignment of the crystal lattice can have a significant impact on the important properties of the substrate due to the isoelectric properties of the carrier mobility or other materials reacting with the chemical treatment. As will be described later, an SGT which is used as a channel by forming a crystal night which can be formed later can be formed by preparing, for example, a substrate of {11〇丨 or {1〇〇丨, and according to the method 1〇〇. Therefore, the method of the present invention can be used to use a face having, for example, {100} (I10丨, {111丨) as the side wall.

的組合來製作nit道存取SGT⑽Ετ)、讀道驅動sg] jNFET)、qp通道負載SGT(pFET)的所有組合。 的電子移動率係藉由在形成於⑦晶圓的（議） 化上ST SGT中’將{ 11〇}面作為側壁而予以最佳 (，面上的正方形』:率係藉由在形成於石夕晶圓的 以最佳化。户 7 ，將{ 100}面作為侧壁而予 的(間面上動率係根據形成切晶圓 {31〇丨、{加}、{320}等面（例如UllH5l〇}、 的電子移料係藉由將形成於 32〇1〇呢1 24 200947676The combination is to make all combinations of nit channel access SGT(10) Ετ), read track driver sg] jNFET), qp channel load SGT (pFET). The electron mobility is optimized by using the {11〇} plane as the sidewall in the ST SGT formed on the 7-wafer (the square on the surface): the rate is formed in The optimization of the Shixi wafer. The household 7 and the {100} surface are used as the side wall (the surface dynamic rate is based on the formation of the sliced wafer {31〇丨, {plus}, {320}, etc. (For example, UllH5l〇}, the electronic material transfer system will be formed at 32〇1〇1 24 200947676

形SGT的{100丨面作為侧壁而予以最佳化。此外 而降低。 來調即寫入動作與讀出動作之間的 SNM 參照第Η圖所示的基板的實施形態。 晶圓，但亦可作成單結晶的塊—114 ^示的 晶圓係由上部㈣114、埋人氧化膜層81、斤= ❹ 所構成。使用_晶㈣的步驟除了分離膜等細 J差/、卜大致與SOI晶圓的步驟相同。 在第14圖中，晶圓114雖顯示最低限度的複雜性， 但亦可使用複雜性不同的各種晶圓。晶圓係能使用&amp;、 Ge、GaP、InAs、InP、GaAs等m族八族化合物只要 為合適的材料’可使用任何的半導體材料。晶圓係具有第 -結晶面，在第-結晶©上形成FET通道用的面。作為較 佳的實施形態，能將SOI的上部矽層設成單結晶矽，且將 ❹SOI的上部石夕層的面方位設成{100}。在第15圖所示的 下個步驟中，使用硬質遮罩薄膜121並將半導體層114予 以非等向性蝕刻，而形成分離膜與矽柱128。如同後述， 矽柱128 (亦即柱本體）的局部係成為電晶體的本體部。 月b僅以任意的數目於基板上形成柱（亦即SGT)，此外作 為柱的形成方法，亦可使用習知的各種方法。在本實施形 態中，於步驟104中，使甩以下的方法從s〇I晶圓1〇4形 成柱。第一步驟係將硬質遮罩薄膜113予以圖案化。硬質 遮罩薄膜113 ( S^N4或Si〇2 )係具有作為蝕刻停止層的功 320109R1 25 200947676 T個步驟係使用硬質遮罩薄膜Π3將半導體114予 向_刻’藉此形財柱128。此時，能使用適用 半導體114之反應性離子姓刻（RIE : reactive ion etching)法來進行。 π A # ^在之刖的步驟預先決定遮罩的方位，而能將側壁 二二的結晶面，藉此改善SRAM的SNM，並根據用 ❹ s爾二出2入的安定性，而能獲得較佳或期望的 ，柱本體的側壁係能以藉由對稱變換使第一、 妗曰^及第三結晶面的至少一個結晶面不會與其他兩個 、曰曰。#效之方式，來作成賴得不同_子移動率之結 日日。柱本體的側壁係能設成第一特定面 以及第三特定面。 特疋面、 缝據需要對柱進行摻雜。此方法—般為離子植入， 能於柱形成P井（㈣）構造與N井構造。p =雜等級一般為1〇n5xl〇lw、範“為 形成N财與應。在本實施形態的SR·:構:二 例，係能使用固有的矽晶圓，且將複數個Nfet^ 卿積體於共通的基板。 屬個 第16圖與第17圖係顯示S/D區域（源極區域與沒 極區域）的摻雜方法。在第〆步驟中，使用習知的間隔物 形成（亦即，均勻的RIE蝕刻）技術。首先，以電介質ιΐ9 來覆蓋矽柱，接著，於NMOS半導體區域117内植入摻雜 劑，形成NMOS S/D區域118。此外，於PM〇s半導體 320109R1 26 200947676 區域125植入受體（accept〇r)，形成pm〇S S/D區域116。 受體與摻雜劑的量及分布係根據設計上的需要來決定。在 形成S/D區域的方法中，已開發有各種方法，在本實施 形態中只要從這些方法中選擇適當的方法且針對特定的性 能要件來調整即可。在形成S/D區域的方法中，有複雜 程度不同的各種方法。在本實施形態中，能從這些方法中 使用例如離子植入來形成S/D區域。因此，關於NFET， Ο 例如能以IkeV至5keV範圍的能量且5xlO〗4cnT3至2x 1015cm_3範圍的劑量來使用p、As、或Sb。同樣地，關於 PFET，例如能以〇.5keV至3keV範圍的能量且5xl014cm_ 至2χ 10 cm 3範圍的劑量來使用b、In、或Ga。 第18圖係顯示形成NMOS裝置區域與PMOS裝置區 域兩者的S/D矽化物（自對準矽化物）的接觸件12〇之 方法。現在所使用的低電阻且接觸電阻亦小之矽化物的例 子，為 TiSi2、CoSi2、以及 NiSi。 ❹ 接著’參照第圖。雖在方法1〇〇的步驟1〇6中形 成閘極絕緣膜131，但在此之前使用CMP ( Chemical Mechanical Polishing;化學機械研磨）及之後的回蝕處理， 將平坦的氮化物層（或氧化物層）13〇形成為比矽柱的高 度還低。此製程的目的係用以降低閘極及汲極下部的重疊 部分的寄生電限。因此’在步驟1〇6中，將閘極絕緣膜ι31 形成於石夕柱128上。閘極絕緣膜13ι係能藉由在750°c至 800°C溫度中的熱氧化或者藉由層疊電介質薄膜來形成。作 為本實施形態的閘極絕緣膜131，係能使用公知的si〇2、 27 320109R1 200947676 -氮氧化物材料、高介電率（Mgh-Κ)電介質材料、或者 合這些材料的材料。 、、 參照第20圖。在方法100的步驟1〇7至1〇9中，带 成閘極導體。形成緣膜131後，使用公知的光微^ 與钱刻來層昼閘極導體層132。對於閑極導體層的 成-般雖使用多晶石夕材料，但亦可使用非晶石夕、非晶石夕與 多晶梦的組合、以及多晶石夕—錯等所有適合的材料。本發 明的其他實施形態，係能使用使用有w、MG、Ta或其他 的高熔點金屬之金屬閘極導體m，或者包含添加有Ni或 Co的多晶石夕之石夕化物閘極導體。在㈣1〇8中，在閑極導 體層132包圍石夕材料的情形中，能層疊這種層來作為摻雜 層（原位掺雜（in situ doping))。在閘極導體層132為 金屬層的情形中，係能使用物理氣相沉積法、化學氣相沉 積法、或者本領域技術公知的所有方法。如此，以接觸氧 化物層131且與柱128的垂直侧壁相對向之方式來形成閘 φ 極構造。 接著，層疊足夠厚度的氧化物層134，並如第21圖所 示，藉由αν〇&gt;處理將氧化物層丨34研磨達至金屬層132 為止。在方法100的步驟1〇9中，使用電漿蝕刻（第22 圖）來蝕刻露出的閘極導體層，藉此將間極導體層予以形 成圖案化。接著，層疊足夠厚度的氧化物層130，並在最 後步驟中汉置之後的接觸孔。接著.，如第24圖所示，根據 方法100的步驟110,通過接觸孔來連接各個SRAM電晶 體’完成本實施形態的SGT SRAM。 320109R1 200947676 〜本發明並非限定於本說明書中所朗的特定實施形 態，只要未脫離本發明的範圍，本發明可進行各種變更， 且這些變更亦包切由巾料祕圍的記韻定義之本發 明的範圍内。 【圖式簡單說明】 ❹ ，第1圖係顯示雜的側壁的面方位之平面圖，（a) 係對應在♦ (100)晶圓上所製造的雜，（b)係對應在 矽O10)晶圓上所製造的矽柱。 /第2圖係顯示電晶體的活性區域的結晶面與移動率的 關係之曲線圖（橫軸為面方位的角度，縱轴為載子的移動 :)，U)為载子為電子的情形，⑴為載子為電洞的 情形。 第3圖係形成在矽晶圓的（1〇〇)面上，且各種cM〇s SGT的組合之已正規化的電流密度表（參照PCT/JP2〇〇7 /071052 ’ 將 Vg—Vth：=〇 6v 與 vd=〇 〇5v 中的圓柱狀 © MOS的vg- vd曲線的絕對電流值作為基準值（=1 〇〇 ))。 第4圖係顯示各個電晶體由單一 SGT柱所構成，且 以兩個驅動電晶體、兩個存取電晶體 、以及兩個負載電晶 體所形成的6TSGT CMOS SRAM佈局的習知技術之圖。 第5(a)圖係顯示FINFETCMOS SRAM的習知技術， 為由四個驅動電晶體（DR1、DR2、DR3、DR4 )、兩個 存取電晶體（TR1、TR2)、以及兩個負載電晶體（L〇1、 L02)所形成的finfetsram佈局及其等效電路之圖。 第5(b)圖係顯示FINFET CMOS SRAM的習知技術， 29 320109R1 200947676 且為為了利用不同的結晶面所產生的不同增益，而將驅動 電晶體（NPD、NPD2)從存取電晶體（Access、Access2) 以及負載電晶體（Load、Load2)旋轉45。之6T FINFET SRAM佈局及其等效電路之圖。 第5 (c)圖係顯示具有兩個驅動電晶體（N1 〇2、 N103)、兩個存取鰭式電晶體（N1〇〇、m〇1)、以及兩 個負載電晶體（P100、P101 )之6T FINFET SRAM單元。 ❹ 第6圖係顯示SRAM的25種組合的例子之表，且在 各個SRAM的組合中利用不同的結晶面方位，且亦為在第 3圖所示的矽（1〇〇)上所製造的各種SGT CMOS SRAM 的正規化電流密度之表。 第7圖係顯示與習知的平面型FET不同，僅藉由使 SGT的驅動NMOS電晶體與存取電晶體之間的角度旋轉 而為不同之比之圖，且顯示石比以及正方形存取電晶體 從正方形驅動電晶體（全部的侧壁為（100))旋轉的旋轉 ❹ 角度之關係。 第8 (a)圖係顯示驅動電晶體（N32、N42)從存取 電晶體（N12、N22)以及負載電晶體（pi2、p22)旋轉 45而成為因不同的結晶面會有不同的增益、且為由本發明 的第一貫施形態的兩個正方形驅動電晶體（N32、N42)、 兩個正方形存取電晶體（N12、N22)、以及兩個正方形負 載電晶體（P12、P22)所形成的在矽（1〇〇)晶圓上所製 造的SGT CMOS SRAM佈局及其等效電路之圖。 第8 (b)圖係沿著第8 (a)圖的A_A，剖線所剖取 320109R1 30 200947676 之已完成的CMOS SGT裝置的縱剖面圖。 第8 ( c )圖係沿著第8 ( a)圖的B — b，剖線所剖取之 已完成的CMOS SGT裝置的縱剖面圖。 第8 (d)圖係沿著第8 (a)圖的c—C’剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 第8 (e)圖係沿著第8 (a)圖的；D—D，剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 第9 ( a )圖係顯示驅動電晶體（N31、N41 )以及負 ® 載電晶體（P11、P21 )之柱側壁為使用相同結晶配向、且 為由本發明的第一實施形態的兩個圓形驅動電晶體 (N31、N41)、兩個圓形存取電晶體（nii、N21)、以 及兩個正方形負載電晶體（Pll、P21)所形成的在矽（1〇〇) 晶圓上所製造的SGT CMOS SRAM佈局及其等效電路圖。 第9 (b)圖係沿著第9 (a)圖的A — A，剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 ❹第9 ( c )圖係沿著第9 ( a)圖的B — B’剖線所剖取之 已完成的CMOS SGT裝置的縱剖面圖。 第9 (d)圖係沿著第9 (a)圖的C—C，剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 第9 (e)圖係沿著第9 (a)圖的D — D，剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 第10 (a)圖係顯示由本發明的第一實施形態的兩個 圓形驅動電晶體（N30、N40)、兩個圓形存取電晶體（N1〇、 N20)、以及兩個圓形負載電晶體（ρι〇、p2〇)所形成的 31 320109R1 200947676 » . 在矽（100)晶圓上所製造的SGT CMOS SRAM佈局及其 等效電路圖。 第10 (b)圖係沿著第10 (a)圖的A—A’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 第10 (c)圖係沿著第10 ( a)圖的B — B’剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 第10 (d)圖係沿著第10 (a)圖的C—C’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 第10 (e)圖係沿著第10 (a)圖的D — D’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 第11 (a)圖係顯示由本發明的第二實施形態的四個 圓形驅動電晶體（N33、N43、N53、N63 )、兩個圓形存 取電晶體（N10、N20)、以及兩個圓形負載電晶體（P10、 P20)所形成的在矽（100)晶圓上所製造的SGT CMOS SRAM佈局及其等效電路圖。 ❹ 第11 (b)圖係沿著第11 (a)圖的A-A’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 第11 (c)圖係沿著第11 (a)圖的B — B’剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 第11 (d)圖係沿著第11 (a)圖的C-C’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 第11 (e)圖係沿著第11 (a)圖的D-D’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 第Π (f)圖係沿著第11 (a)圖的E-E’剖線所剖取 32 320109R1 200947676 之已完成的CMOS SGT裝置的縱剖面圖。 第12 (a)圖係顯示驅動電晶體（N34、N44、N54、 N64)從存取電晶體（N12、N22)以及負載電晶體（P12、 P22 )旋轉45。而成為用以利用不同的結晶面會有不同的增 益、且為由本發明的第一實施形態的四個圓形驅動電晶體 (N34、N44、N54、N64)、兩個正方形存取電晶體（N14、 N24)、以及兩個正方形負載電晶體（P14、P24)所形成 的在矽（100)晶圓上所製造的SGT CMOS SRAM佈局及 〇 其專效電路之圖。 . 第12 (b)圖係沿著第12 (a)圖的A — A’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 第12 (c)圖係沿著第12 (a)圖的B — B’剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 第12 (d)圖係沿著第12 (a)圖的C—C’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 ❹第12 (e)圖係沿著第12 (a)圖的D — D’剖線所剖 取之已完成的CMOS SGT裝置的縱剖面圖。 第12 (f)圖係沿著第12 (a)圖的E—E’剖線所剖取 之已完成的CMOS SGT裝置的縱剖面圖。 第13圖係顯示本發明的製造方法之流程圖。 第14圖係顯示沿著平面圖的A — A’剖線所剖取之縱 剖面圖、且為第13圖的製造方法中的本發明的半導體構造 的實施形態的平面圖與對應的縱剖面圖。 第15圖係顯示沿著平面圖的A-A’剖線所剖取之縱 320109R1 33 200947676 « 剖面圖、且為第13圖的製造方法中的本發明的半導體構造 的實施形態的平面圖與對應的縱剖面圖。 第16圖係顯示沿著平面圖的a— A，剖線所剖取之縱 剖面圖、且為第13圖的製造方法中的本發明的半導體構造 的實施形態的平面圖與對應的縱剖面圖。 ❹ 第17圖係顯示沿著平面圖的A — A，剖線所剖取之縱 剖面圖、且為第13圖的製造方法中的本發明的半導體構造 的實施形態的平面圖與對應的縱剖面圖。 第18圖係顯示沿著平面圖的a — a，剖線所剖取之縱 剖^圖、且為第13圖的製造方法中的本發明的半導體構造 的實施形態的平面圖與對應的縱剖面圖。 第19圖係顯示沿著平面圖的A_A，剖線所剖取之縱 W面圖且為第13 _製造方法中的本發明的半導體構造 的實施形態的平面圖與對應的縱剖面圖。 ❹ 第20圖係顯示沿著平面圖的a — a，剖線所剖取之縱 口丨J面圖、且為第13圖的赞丄主方法由 的眚絲带能的巫 k方法中的本發明的半導體構造 的貫施形態的千面圖與對應的縱剖面圖。 第21圖係顯示沿著平面圖的A-A，剖線所之縱 剖面圖、且為第13圖沾制、生+丄丄 深所d取之縱 的實施形態的平面圖與對應的縱剖面圖。K體構仏 第22圖係顯示沿著 itlJS|SI&gt; e Λ m 圖的A —入剖線所剖取之縱 4面圖、且為第13圖的製造方法中的本發 的實施形㈣平_與對應的縱剖㈣。+導體構仏 第23圖係顯示沿著平面圖的A —A，剖線所剖取之縱 320109R1 34 200947676 剖面圖、且為第13圖的製造方法中的本發明的ψ導趲 的實施形態的平面圖與對應的縱剖面圖。 攝逢 第24圖（a)係使用第13圖的製造方决所形成 導體構造的電路圖及.平面圖° 第24圖（b)係使用第13圖的製造方法所 118 、 218 、 318 、 418 、 518 Q 119、130、136、230、236、330、336 120 ' 220、320、420 ' 520 導體構造的剖面圖。 【主要元件符號說明】 81 、 181 、 281 、 381 、 481 82、182、282、382、482 104 113、 121 114 116 117 125 128 130 131 、 231 、 331 、 431 、 531 132 134 、 136 152、252、352、452、552 形成的 埋入氧化物 處理矽晶圓 SOI晶圓 硬質遮罩薄膜 上部&gt;5夕層（半導體層） 源極與没極 NMOS半導體區域 源極與汲極 430、436、530、536 電介質 自對準ί夕化物 PMOS半導體區域 矽柱 氮化物層 閘極氧化膜 閘極導體層 氧化物層 金屬線 半 35 320109R1 200947676 * 216、316、416、516 源極與汲極 232、332、432、532 導體 N10、ΝΠ、N12、N14、N20、N2 卜 N22、N24 存取丽03·The {100 facet of the SGT is optimized as a side wall. In addition, it is reduced. The SNM between the write operation and the read operation is referred to the embodiment of the substrate shown in the figure. The wafer, but it can also be made into a single crystal block - 114 ^ The wafer is composed of the upper part (four) 114, the buried oxide film layer 81, and the pinch = ❹. The step of using _crystal (four) is the same as the step of separating the film and the like, and is substantially the same as the step of the SOI wafer. In Fig. 14, the wafer 114 exhibits minimal complexity, but various wafers having different complexity can be used. The wafer system can use any of the semiconductor materials such as &amp;, Ge, GaP, InAs, InP, GaAs, and the like as long as it is a suitable material. The wafer has a first-crystal plane, and a surface for the FET channel is formed on the first crystal. As a preferred embodiment, the upper 矽 layer of the SOI can be set to a single crystal 矽, and the surface orientation of the upper shi 层 layer of the ❹SOI can be set to {100}. In the next step shown in Fig. 15, a hard mask film 121 is used and the semiconductor layer 114 is anisotropically etched to form a separation film and a column 128. As will be described later, the portion of the mast 128 (i.e., the pillar body) becomes the body portion of the transistor. The column b forms the column (i.e., SGT) on the substrate in an arbitrary number, and as a method of forming the column, various conventional methods can be used. In the present embodiment, in step 104, the following method is formed from the 〇I wafer 1〇4 into a pillar. The first step is to pattern the hard mask film 113. The hard mask film 113 (S^N4 or Si〇2) has a function as an etch stop layer. 320109R1 25 200947676 T steps use a hard mask film Π3 to advance the semiconductor 114 to form a column 128. In this case, it can be carried out by using a reactive ion etching method (RIE) of the applicable semiconductor 114. The step of π A # ^ predetermines the orientation of the mask, and the crystal plane of the sidewalls can be used to improve the SMN of the SRAM, and can be obtained according to the stability of the ❹ 尔2 Preferably, it is preferred that the side walls of the column body are such that at least one of the crystal faces of the first, third and third crystal faces is not symmetrical with the other by symmetrical transformation. #效之方式, to make a different _ sub-mobility rate of the day. The side wall of the column body can be set to a first specific surface and a third specific surface. The special surface and the seam need to be doped with the column. This method is generally ion implantation, which can form a P well ((4)) structure and a N well structure in the column. p = miscellaneous grade is generally 1〇n5xl〇lw, norm "for the formation of N money and should. In this embodiment of SR:: structure: two cases, can use the inherent germanium wafer, and will be a plurality of Nfet ^ Qing The integrated substrate is shown in Figures 16 and 17. The doping method of the S/D region (source region and the electrodeless region) is shown. In the second step, a conventional spacer is used ( That is, a uniform RIE etching technique. First, the pillar is covered with a dielectric ΐ9, and then a dopant is implanted in the NMOS semiconductor region 117 to form an NMOS S/D region 118. Further, in the PM〇s semiconductor 320109R1 26 200947676 Region 125 implants receptors (accept〇r) to form pm〇SS/D region 116. The amount and distribution of acceptors and dopants are determined according to design needs. Methods for forming S/D regions Various methods have been developed, and in this embodiment, an appropriate method is selected from these methods and adjusted for specific performance requirements. In the method of forming an S/D region, various methods having different degrees of complexity are available. In this embodiment, it can be used from these methods. For example, with respect to the NFET, Ο can, for example, use p, As, or Sb in a range of energy in the range of 1 keV to 5 keV and in a range of 5 x 10 cn 4 cn T 3 to 2 x 10 15 cm _ 3 . Similarly, regarding the PFET For example, b, In, or Ga can be used in a dose ranging from ke5 keV to 3 keV and a dose ranging from 5 x 1 014 cm to 2 χ 10 cm 3 . Figure 18 shows S/D forming both the NMOS device region and the PMOS device region. A method of contacting a germanium compound (self-aligned telluride) with a germanium. The examples of germanium compounds which are low-resistance and have low contact resistance are TiSi2, CoSi2, and NiSi. ❹ Next, refer to the figure. The gate insulating film 131 is formed in the step 1〇6 of the method 1〇〇, but a flat nitride layer (or oxide) is used before the CMP (Chemical Mechanical Polishing) and subsequent etch back treatment. The layer 13) is formed to be lower than the height of the column. The purpose of this process is to reduce the parasitic capacitance of the overlap between the gate and the lower portion of the gate. Therefore, in step 1〇6, the gate insulating film is used. Ip31 is formed on Shi Xizhu 128 The gate insulating film 13 can be formed by thermal oxidation at a temperature of 750 ° C to 800 ° C or by laminating a dielectric film. As the gate insulating film 131 of the present embodiment, a well-known si 能 can be used. 2. 27 320109R1 200947676 - Nitrogen oxide materials, high dielectric constant (Mgh-Κ) dielectric materials, or materials of these materials. ,, refer to Figure 20. In steps 1〇7 to 1〇9 of method 100, a gate conductor is provided. After the edge film 131 is formed, the gate conductor layer 132 is layered using well-known light micro and vacuum. Although a polycrystalline material is used for the formation of the idler conductor layer, all suitable materials such as a combination of amorphous austenite, amorphous australis and polycrystalline dreams, and polycrystalline stone-to-error can be used. In another embodiment of the present invention, a metal gate conductor m using a high melting point metal of w, MG, Ta or the like, or a polycrystalline stone cerifide gate conductor to which Ni or Co is added may be used. In (4) 1-8, in the case where the idler conductor layer 132 surrounds the stone material, such a layer can be laminated as a doping layer (in situ doping). In the case where the gate conductor layer 132 is a metal layer, physical vapor deposition, chemical vapor deposition, or all methods known in the art can be used. Thus, the gate φ pole structure is formed in contact with the oxide layer 131 and opposed to the vertical sidewalls of the pillars 128. Next, an oxide layer 134 of a sufficient thickness is laminated, and as shown in Fig. 21, the oxide layer 丨 34 is ground to the metal layer 132 by the αν〇&gt; treatment. In step 1 〇 9 of method 100, the exposed gate conductor layer is etched using plasma etching (Fig. 22), whereby the interpole conductor layer is patterned. Next, an oxide layer 130 of a sufficient thickness is laminated, and the subsequent contact holes are placed in the final step. Next, as shown in Fig. 24, the SGT SRAM of the present embodiment is completed by connecting the respective SRAM transistors through the contact holes in accordance with step 110 of the method 100. The present invention is not limited to the specific embodiments of the present invention, and various modifications can be made without departing from the scope of the invention, and these modifications also encompass the definition of the rhyme of the towel. Within the scope of the invention. [Simple description of the diagram] ❹ , Fig. 1 shows a plan view of the surface orientation of the miscellaneous sidewalls, (a) corresponds to the impurity produced on the ♦ (100) wafer, and (b) corresponds to the 矽O10) crystal. The mast made on the circle. / Fig. 2 is a graph showing the relationship between the crystal plane and the mobility of the active region of the transistor (the horizontal axis is the angle of the plane orientation, the vertical axis is the movement of the carrier:), and U) is the case where the carrier is an electron. (1) is a case where the carrier is a hole. Figure 3 is a normalized current density meter formed on the (1〇〇) plane of a germanium wafer and combined with various cM〇s SGTs (refer to PCT/JP2〇〇7 /071052 'Vg-Vth: =〇6v and the absolute value of the vg-vd curve of the cylindrical © MOS in vd=〇〇5v as the reference value (=1 〇〇)). Figure 4 is a diagram showing a conventional technique in which each transistor is composed of a single SGT column and is constructed of two drive transistors, two access transistors, and two load transistors. Figure 5(a) shows a conventional technique for FINFETCMOS SRAM, consisting of four drive transistors (DR1, DR2, DR3, DR4), two access transistors (TR1, TR2), and two load transistors. (L〇1, L02) The finfetsram layout and its equivalent circuit diagram. Figure 5(b) shows a conventional technique for FINFET CMOS SRAM, 29 320109R1 200947676 and is to drive the transistor (NPD, NPD2) from the access transistor (Access) in order to utilize the different gains produced by the different crystal faces. , Access2) and load transistor (Load, Load2) rotate 45. A 6T FINFET SRAM layout and its equivalent circuit diagram. Figure 5 (c) shows two drive transistors (N1 〇2, N103), two access fin transistors (N1〇〇, m〇1), and two load transistors (P100, P101) ) 6T FINFET SRAM unit. ❹ Figure 6 shows a table of examples of 25 combinations of SRAMs, and uses different crystal plane orientations in the combination of SRAMs, and is also manufactured on 矽(1〇〇) shown in Fig. 3. A table of normalized current densities for various SGT CMOS SRAMs. Fig. 7 is a view showing a ratio of different ratios by rotating the angle between the driving NMOS transistor of the SGT and the access transistor, and displaying the stone ratio and square access, unlike the conventional planar FET. The relationship of the angle of rotation of the transistor from the square drive transistor (all sidewalls are (100)). Figure 8 (a) shows that the drive transistor (N32, N42) is rotated 45 from the access transistor (N12, N22) and the load transistor (pi2, p22) to have different gains due to different crystal faces. And formed by two square drive transistors (N32, N42), two square access transistors (N12, N22), and two square load transistors (P12, P22) according to the first embodiment of the present invention. A diagram of the SGT CMOS SRAM layout and its equivalent circuit fabricated on a 矽 (1 〇〇) wafer. Figure 8(b) is a longitudinal cross-sectional view of the completed CMOS SGT device taken along line A_A of Figure 8(a), taken along line 320109R1 30 200947676. Figure 8 (c) is a longitudinal section of a completed CMOS SGT device taken along line B-b of Figure 8(a). Fig. 8(d) is a longitudinal sectional view of the completed CMOS SGT device taken along the line c-C' of Fig. 8(a). Fig. 8(e) is a longitudinal sectional view of the completed CMOS SGT device taken along the line D-D along line D (D). The 9th (a) diagram shows that the column sidewalls of the driving transistor (N31, N41) and the negative® carrier transistor (P11, P21) are two circular shapes using the same crystal alignment and according to the first embodiment of the present invention. Driven by a drive transistor (N31, N41), two circular access transistors (nii, N21), and two square-loaded transistors (P11, P21) on a 矽 (1〇〇) wafer The SGT CMOS SRAM layout and its equivalent circuit diagram. Fig. 9(b) is a longitudinal sectional view of the completed CMOS SGT device taken along the line A-A of Fig. 9(a). ❹9 (c) is a longitudinal section of a completed CMOS SGT device taken along line B-B' of Figure 9(a). Fig. 9(d) is a longitudinal sectional view of the completed CMOS SGT device taken along the line C-C of Fig. 9(a). Fig. 9(e) is a longitudinal sectional view of the completed CMOS SGT device taken along the line D-D of Fig. 9(a). Figure 10 (a) shows two circular drive transistors (N30, N40), two circular access transistors (N1 〇, N20), and two circular loads according to the first embodiment of the present invention. 31 320109R1 200947676 formed by transistor (ρι〇, p2〇). SGT CMOS SRAM layout and its equivalent circuit diagram fabricated on 矽(100) wafer. Fig. 10(b) is a longitudinal sectional view of the completed CMOS SGT device taken along the line A-A' of Fig. 10(a). Figure 10 (c) is a longitudinal cross-sectional view of the completed CMOS SGT device taken along line B - B' of Figure 10 (a). Fig. 10(d) is a longitudinal sectional view of the completed CMOS SGT device taken along the line C-C' of Fig. 10(a). Fig. 10(e) is a longitudinal sectional view of the completed CMOS SGT device taken along the line D-D' of Fig. 10(a). Figure 11 (a) shows four circular drive transistors (N33, N43, N53, N63), two circular access transistors (N10, N20), and two according to the second embodiment of the present invention. The SGT CMOS SRAM layout and its equivalent circuit diagram fabricated on a germanium (100) wafer formed by a circular load transistor (P10, P20). ❹ Section 11(b) is a longitudinal section of the completed CMOS SGT unit taken along the line A-A' of Figure 11(a). Figure 11 (c) is a longitudinal cross-sectional view of the completed CMOS SGT device taken along line B - B' of Figure 11 (a). Fig. 11(d) is a longitudinal sectional view of the completed CMOS SGT device taken along the line C-C' of Fig. 11(a). Fig. 11(e) is a longitudinal sectional view of the completed CMOS SGT device taken along the line D-D' of Fig. 11(a). Figure (f) is a longitudinal cross-sectional view of the completed CMOS SGT device taken along line E-E' of Figure 11 (a). Figure 12 (a) shows the drive transistor (N34, N44, N54, N64) rotated 45 from the access transistor (N12, N22) and the load transistor (P12, P22). The four circular drive transistors (N34, N44, N54, N64) and the two square access transistors (the N34, N44, N54, N64) according to the first embodiment of the present invention have different gains for utilizing different crystal faces. N14, N24), and two square-loaded transistors (P14, P24) formed on the 矽 (100) wafer SGT CMOS SRAM layout and its dedicated circuit diagram. Fig. 12(b) is a longitudinal sectional view of the completed CMOS SGT device taken along the line A-A' of Fig. 12(a). Figure 12(c) is a longitudinal cross-sectional view of the completed CMOS SGT device taken along the line B-B' of Figure 12(a). Fig. 12(d) is a longitudinal sectional view of the completed CMOS SGT device taken along the line C-C' of Fig. 12(a). Fig. 12(e) is a longitudinal sectional view of the completed CMOS SGT device taken along the line D-D' of Fig. 12(a). Fig. 12(f) is a longitudinal sectional view of the completed CMOS SGT device taken along the line E-E' of Fig. 12(a). Figure 13 is a flow chart showing the manufacturing method of the present invention. Fig. 14 is a plan view and a corresponding longitudinal cross-sectional view showing an embodiment of the semiconductor structure of the present invention in the manufacturing method of Fig. 13 in a longitudinal sectional view taken along line A - A' of the plan view. Fig. 15 is a plan view showing a plan view of a semiconductor structure according to the present invention in a manufacturing method of Fig. 13 and a vertical plan taken along the line A-A' of the plan view. Longitudinal section. Fig. 16 is a plan view and a corresponding longitudinal cross-sectional view showing an embodiment of the semiconductor structure of the present invention in the manufacturing method of Fig. 13 taken along the line a-A, the longitudinal cross-sectional view taken along the line. Fig. 17 is a plan view and a corresponding longitudinal sectional view showing an embodiment of the semiconductor structure of the present invention in the manufacturing method of Fig. 13 taken along line A - A of the plan view, a longitudinal sectional view taken along the line . Fig. 18 is a plan view and a corresponding longitudinal sectional view showing an embodiment of the semiconductor structure of the present invention in the manufacturing method of Fig. 13 taken along the line a - a of the plan view, the longitudinal section taken along the line drawing; . Fig. 19 is a plan view and a corresponding longitudinal cross-sectional view showing an embodiment of the semiconductor structure of the present invention in the 13th manufacturing method, taken along line A_A of the plan view and a vertical W-plane view taken along the line. ❹ Fig. 20 shows the vertical 丨J-side view taken along the line a - a of the plan view, and is the k 丄 丄 丄 丄 丄 丄 丄 丄 丄 丄A schematic view of a cross-sectional view of a semiconductor structure according to the invention and a corresponding longitudinal cross-sectional view. Fig. 21 is a plan view and a corresponding longitudinal cross-sectional view showing a longitudinal section of the plan view taken along the line A-A, the longitudinal section of the section line, and the longitudinal drawing of Fig. 13 and the depth of d. The K-body structure Fig. 22 shows a vertical 4-sided view taken along the A-input line of the itlJS|SI&gt; e Λ m diagram, and is the embodiment of the present invention in the manufacturing method of the 13th figure (4) Flat _ and corresponding longitudinal section (four). Fig. 23 is a cross-sectional view taken along line A - A of the plan view, taken along the line 320109R1 34 200947676 taken along the line, and is an embodiment of the present invention in the manufacturing method of Fig. 13 Plan view and corresponding longitudinal section view. Fig. 24(a) is a circuit diagram and a plan view of a conductor structure formed using the manufacturing method of Fig. 13. Fig. 24(b) shows the manufacturing method 118, 218, 318, 418 of Fig. 13 518 Q 119, 130, 136, 230, 236, 330, 336 120 '220, 320, 420 ' 520 cross-sectional view of the conductor structure. [Description of main component symbols] 81, 181, 281, 381, 481 82, 182, 282, 382, 482 104 113, 121 114 116 117 125 128 130 131 , 231 , 331 , 431 , 531 132 134 , 136 152 , 252 352, 452, 552 formed buried oxide treatment 矽 wafer SOI wafer hard mask film upper part _ 5 layer (semiconductor layer) source and IGBT semiconductor region source and drain 430, 436, 530, 536 Dielectric self-alignment PMOS PMOS semiconductor region pillar nitride layer gate oxide gate gate conductor layer oxide layer metal line half 35 320109R1 200947676 * 216, 316, 416, 516 source and drain 232, 332, 432, 532 conductor N10, ΝΠ, N12, N14, N20, N2 卜 N22, N24 access 丽 03·

P10、P11、P12、P13、P14、P20、P2卜P22、P23、P24 負載PMOS N30、N3卜N32、N33、N40、N41、N42、N43、N53、N63 _NM〇S o ❹ 36 320109R1P10, P11, P12, P13, P14, P20, P2, P22, P23, P24 Load PMOS N30, N3, N32, N33, N40, N41, N42, N43, N53, N63 _NM〇S o ❹ 36 320109R1

Claims (1)

200947676 七、申請專利範圍： 1. 一種SGT半導體構造，係包含有： SGT本體部，係包含有：第一部分，係具有賦予 第一载子移動率之側壁的第一面方位；以及第二部 分，係具有賦予第二載子移動率之前述側壁的第二面 方位； 存取電晶體，係形成於前述SGT本體部的前述第 一部分；以及 驅動電晶體，係形成於前述SGT本體部的前述第 二部分；其中， 前述存取電晶體係η通道電晶體； 前述驅動電晶體係η通道電晶體； .前述存取電晶體及驅動電晶體係記憶體早元的一 部分； 前述存取電晶體係為了傳送資料而連接至前述驅 ❹ 動電晶體。 2. 如申請專利範圍第1項之SGT半導體構造，其中，前 述第一載子移動率係比前述第二載子移動率還小。 3. 如申請專利範圍第2項之SGT半導體構造，其中， 前述存取電晶體與閃鎖電晶體係具有增益，且由 於前述第一載子移動率比前述第二載子移動率小，因 此前述存取電晶體的增益比前述閂鎖電晶體的增益還 /J、〇 4. 如申請專利範圍第1項之SGT半導體構造，其中， 37 320109R1 200947676 前述第一面方位為{110}面；_ 前述第二面方位為{100}面。. 5. 如申請專利範圍第1項之SGT半導體構造，其中，前 述記憶體單元係SRAM記憶體單元。 6. —種SGT半導體記憶體，為包含有複數個SGT之SGT 半導體記憶體，係包含有： 第一及第二SGT，係具有作為閘極之第一線，且 各個SGT的電流路徑的一端連接於供給有基準電位的 ❹基準電極； 第三及第四SGT，係具有作為閘極之第二線，且 各個SGT的電流路徑的一端連接於前述基準電極; 第五SGT，係具有作為閘極之第一字線，且SGT 電流路徑的一端連接於前述第一及第二SGT的前述電 流路徑的另一側； 第六SGT，係具有作為閘極之第二字線，且SGT ❹ 電流路徑的一端連接於前述第三及第四SGT的前述電 流路徑的另一侧； 第七場效電晶體，係具有前述第一線作為閘極； 以及 第八場效電晶體，係具有前述第二線作為閘極； 其中， 前述第一及第二SGT的前述電流路徑係並聯連接 .於前述第五SGT的前述電流路徑的前述一端與前述基 準電極之間； 38 320109R1 200947676 前述第三及第四SGT的前述電流路徑係連接於前 述第六SGT的前述電流路徑的前述一端與前述基準電 極之間。 7.如申請專利範圍第6項之SGT半導體記憶體，其中， 前述第一、第二、第三、以及第四電晶體各者係 形成驅動電晶體； 前述第五與第六電晶體各者係形成存取電晶體。 8·如申請專利範圍第6項之SGT半導體記憶體，其中， 前述第七與第八SGT的電路路徑的一端係連接於供給 有電源電壓的電源電極。 ❹ 39 320109R1200947676 VII. Patent Application Range: 1. An SGT semiconductor structure, comprising: an SGT body portion, comprising: a first portion having a first surface orientation imparting a sidewall of a first carrier mobility; and a second portion a second surface orientation of the sidewalls that impart a second carrier mobility; an access transistor formed in the first portion of the SGT body portion; and a drive transistor formed in the aforementioned SGT body portion a second part; wherein: the access transistor system n-channel transistor; the driving transistor system n-channel transistor; the access transistor and a portion of the driving transistor system memory early; the access transistor The system is connected to the aforementioned driving electromagnet for transmitting data. 2. The SGT semiconductor structure according to claim 1, wherein the first carrier mobility is smaller than the second carrier mobility. 3. The SGT semiconductor structure of claim 2, wherein the access transistor and the flash-locked crystal system have gain, and since the first carrier mobility is smaller than the second carrier mobility, The gain of the access transistor is greater than the gain of the latching transistor /J, 〇4. The SGT semiconductor structure of claim 1 wherein 37 320109R1 200947676 the first surface orientation is {110} plane; _ The aforementioned second face orientation is {100} face. 5. The SGT semiconductor structure according to claim 1, wherein the memory unit is a SRAM memory unit. 6. An SGT semiconductor memory, comprising SGT semiconductor memory comprising a plurality of SGTs, comprising: first and second SGTs having one end of a first line of gates and one current path of each SGT Connected to the ❹ reference electrode to which the reference potential is supplied; the third and fourth SGTs have a second line as a gate, and one end of each SGT current path is connected to the reference electrode; and the fifth SGT has a gate a first word line of the pole, and one end of the SGT current path is connected to the other side of the current path of the first and second SGTs; the sixth SGT has a second word line as a gate, and the SGT ❹ current One end of the path is connected to the other side of the current path of the third and fourth SGTs; the seventh field effect transistor has the first line as a gate; and the eighth field effect transistor has the foregoing The second line serves as a gate; wherein the current paths of the first and second SGTs are connected in parallel between the one end of the current path of the fifth SGT and the reference electrode; 38 320109R1 200947676 The current path of the third and fourth SGTs is connected between the one end of the current path of the sixth SGT and the reference electrode. 7. The SGT semiconductor memory of claim 6, wherein each of the first, second, third, and fourth transistors forms a driving transistor; each of the fifth and sixth transistors An access transistor is formed. 8. The SGT semiconductor memory of claim 6, wherein one end of the seventh and eighth SGT circuit paths is connected to a power supply electrode to which a power supply voltage is supplied. ❹ 39 320109R1
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