TW200947216A - Job-based structure for processing and transmitting data - Google Patents

Abstract

The present invention provides a job-based structure for processing and transmitting data. The structure comprises a host and a RAID system. Further, an interface controller is disposed on the host and connected to the RAID system. Also, the RAID system comprises a job queue controller, a physical region descriptor table controller, a DMA controller, and a storage device connected thereto by a DMA bus. According to the request sent by the host, the DMA controller executes a command through the interface controller. Besides, the command is divided into a plurality of jobs, which are then transmitted to the job queue controller to save/store the storage device. Meanwhile, the saved/stored data can be transmitted to the job queue controller to save/store the storage device and respond to the host in order. Therefore, the processing efficiency of the system host can be improved.

Description

200947216 IX. Description of the Invention: [Technical Field] The present invention relates to a structure in which a work element is a data processing and transfer unit, and particularly to a disk array system having a Serial interface, to improve data storage of a host computer. / Take the efficiency. [Prior Art] With the rapid development of computer technology, computer manufacturers are continually pursuing hardware devices with faster computing speed and better performance. However, in addition to the pursuit of faster and more efficient computer hardware devices, another key to the performance of computer operations is the speed of data storage/removal; therefore, if there is no appropriate data storage/access in the computer system® The architecture, even with the most advanced hardware devices, does not provide a comprehensive improvement in the overall operational performance of the computer system. Referring to FIG. 1, the architecture includes a host 50 and a disk array system 60. The host 50 further includes a system processor 51, a system memory 52, and a host terminal supporting Serial ATA (Serial). The interface controller 53 of the Advanced Technology Attachment protocol, the system processor 51 sends an instruction to execute the data read/store command to the disk array system 60 through the seriai interface controller 53, and after the processing is completed The data is transmitted back to the system memory 52. The disk array system 60 is connected to the interface controller 53 of the host 50 via the communication line 55. Further, the disk array system 60 further includes a disk array. The controller 61 and the plurality of disks 62, but the architecture uses the Serial interface as a channel for high-speed data transmission. Although the data transmission efficiency is improved, the disk array controller 61 receives the commands from the host 50. Performing data storage/fetching to the disk 62, because some instructions perform simple actions 'but some instructions perform a relatively complicated number of actions, such a When the disk array system 60 processes a more complicated instruction, it needs to wait for all the actions in the instruction to be returned to the host 5, so when part of the action of the instruction is completed, it must still wait for the instruction. After the other action of the heart towel is completed, it will be returned to the domain 5G. @This cannot effectively improve the operational efficiency of the host. 200947216 SUMMARY OF THE INVENTION In view of the lack of implementation of the above architecture, the inventors have carefully studied and further developed the structure of the work data processing and transmission unit. SUMMARY OF THE INVENTION: It is an object of the present invention to provide a method of executing a host, disassembling the instruction into a plurality of execution units-job-based, and performing a store/fetch operation on the storage device. In still another object of the present invention, the job-based will be transmitted back to the host in sequence on the principle of FIFO/First in First Out after the storage/storage operation of the storage device is completed.又一 Another object of the present invention is to perform a program compiled by a PRD Table Controller to improve data conversion capability before executing an instruction action or transferring data for completing an instruction action. The present invention is an architecture for a data processing and transfer unit that includes a host and a disk array system. The host is provided with an interface controller and a system for processing. And a system memory, and the interface controller, the system processor and the system memory system are connected through the system bus, and the system processor sends data to the disk array system through the interface controller according to the instruction to be executed. Depositing/retrieving the request, and storing the response data in the system memory; wherein 'the disk array system is connected to the interface controller by a communication line' and the disk array system further includes a file / decoding controller (c 〇 DEC compression / decompression), a receiving controller (Receiver such as the small - transmission controller (Transmitter Controller), - work element control device (j〇b Queue

Controller), a physical location description table controller (pRD under the oil "c〇ntr〇Uer", a direct 6 memory memory / controller (Direct Memory Access Controller / DMA controller) and connected through the DMA bus The storage device; the encoding/decoding controller executes the instruction transmitted from the host through the interface controller. The instruction format conforms to the frame information architecture (Fis), and the 200947216 decodes the program according to the decoding mechanism of 8b/10b. The receiving controller disassembles the decoded program instructions into a plurality of independently-performable units - the work element (Changru (4); the transmission controller will complete the data of the saved/fetched action still with the work element (j〇 M is a processing unit responsive to the host; the work element queue controller is to sequentially execute the instruction work element or the processed data work element to be executed or respond to the host; the leg controller is to obtain the system bus After the master control, the work to be executed by the work cell controller is sequentially written to the ^^ stream, that is, the storage/fetch of the pure data is performed or the processed data work element is transferred to the The controller is arranged in a sequence of 'waiting for response to the host, and the difficult bus is connected to the storage device or the memory controller or the PCI controller; the physical location description table controller (10) describes the processing to be processed. Conversion address of instruction and data (Transfer Add) and conversion capacity (τ·Know

Count) 'The description of the physical location description table (10)) causes the leg controller to write data to the connected storage device. The invention is an independent transfer of the oil of the age, and the data processing and transfer unit is not required to complete the return of the host after the completion of all the actions in the instruction as in the prior art. The coffee can greatly improve the efficiency of the host operation. [Embodiment] Please refer to FIG. 2, which is a preferred embodiment of the present invention. The architecture includes, - Host H, a disk array system. The host controller 1 is provided with an interface controller u (in this embodiment, an interface controller supporting the Serial ATA specification), a system processor 12, and a system memory 13; the interface controller U and the system The processor 12 and the system memory 13 are connected through the system bus 14 , and the system processor 12 sends a data save/fetch request to the disk array system 20 through the interface controller 11 according to the instruction to be executed, and The response data is stored in the system memory 13; wherein the disk array system 20 is connected to the interface controller ij via the communication line 15 and the disk array system 2 further includes The encoding/decoding controller 21, a receiving control 7 200947216 22, a transmission controller 23, a working element column controller 24, a physical position description table controller 25, a DMA controller 26, and a DMA busbar 27 The connected storage device (not shown in the figure, the storage device in the embodiment supports the NCQ (NativeC〇BHnandQueuing) protocol); the coded decoding controller 21 is transmitted from the host 1 through the interface controller 11. 7 refers to the frame information architecture (Fraffle 〖nf〇rfflati〇n structure / pig) format, and according to the decoding mechanism of 8b / l 〇 b decoding process; its receiving controller 22 will be decoded The instructions of the program are disassembled into a plurality of independently-performing units-job-based; the transmission controller 23 responds to the data of the stored/extracted operations by the job-based unit. The working unit controller 24 is configured to sequentially execute the instruction working elements to be executed or the processed instructions to be executed in units of data working elements, and wait for execution or response to the host 1; 26 is to obtain DMA convergence After the master control of the row 27, the work element to be executed sequentially arranged by the work unit queue controller 24 is written into the leg busbar 27, that is, data storage/fetching is started, or the processed data work element is transmitted to The work cell controller 24 sequentially arranges 'waiting for the host 10' and the leg bus 27 is connected to a storage device or a memory controller or a PCI controller or the like (not shown); φ the physical location description The table controller (PRD) 25 describes the transfer address and transfer count of the instruction and data to be processed, by which the DMA controller 26 writes the data to the remaining connection. device. Furthermore, the instruction received by the receiving controller 22 from the encoding/decoding controller 21 conforms to the frame information architecture format and disassembles the command into a plurality of working elements, which are sequentially arranged in the working unit. The column controller 24 'puts the data to be processed by the system processor 12, and uses the transfer address and transfer count described by the physical location description table controller (PRD) to make the DMA controller 26 writing the data to the connected storage device 200947216 will be used when the drive controller 26 will execute the completed data work element back to the host, and the data will be completed. _渺 work = Γ 'receive the transfer controller 23 through the work unit (4) controller 24, at the same time, 26 will process the data, as described in the _ _ _ _ (10)) ==6 will be the lion's axis (4) The invention shown in the attached figure 3 is disassembled into a number of t from the instruction of the _, or the processing action of the _ controller 26 is used as the principle of the first side _ (touch) of the heart side splicer 24 With Jing or Noodle _ 26, in the work of this fine t, the example is 4DW0RD type. Belle ^ / Referring to Figure 4, which is a processing diagram of the receiving controller 22 of the present invention when receiving the Fis format of the interface = 1, the conforming information structure (10) format can be For the instruction transmitted by the host, the receiving control 22 sets the value of the memory (4) 'the space 3G contains A, β_ 3ι, the offense, the a pointer 31 is the memory _ 〇 internal frame information The total number of architectures (FIS), and the b-pointer & is the indication == the current execution position within the hidden work room 30; at the initial actuation, the a, b positioner 3 is equal to the value of the 'but when When the frame information structure (10) transmitted by the interface controller u is transmitted to the receiving controller by the editing/decoding controller 21, the controller 22 updates the message. Box information architecture ((10) The total number is A. In this case, B and bit 32 will execute jlb pointer 321 in sequence; meanwhile, when the receiving controller receives 24, receive the second frame information architecture (FIS). The a pointer 31 in the memory space 3() will be updated to 312 'at the same time. The B pointer 321 is sequentially executed to the B pointer micro, and so on. Please refer to FIG. 5, which is a working element controller of the present invention for explaining the action of the executed data. 'The working element queue controller 24 is provided with a working element for the column memory space 200947216 40 'The working element queue memory f4 40 & contains A, B positioner 41, guilty, the a pointer 4i is the total number of data in the memory space 40 to be transferred to the host, and The β positioner 42 is for indicating the work done in the working space (4) memory space 4; in the initial operation, the A, Β finger position (4), 42 series is the initial pure 'but the program execution is transmitted to Wang Zuoyuan When the controller 24 is in the controller 24, the work unit queue controller 24 will update the total number of jobs to be the positioner 4 ιι, and the program will continuously execute the work elements in the bribe list, and each work unit will be independent. The transmission frame structure is 'simultaneous' and notifies the transmission controller 23 to be transmitted to the host ι; when the program performs the above work, the A, B positioners 411, 421 will be #; meanwhile, when the program is succeeded In the new work, the work element is listed in the memory space. The device 4 will be updated to be the same, the program will execute and update the B positioner 421 to the β positioner, and so on. Please - and refer to Figure 6 The schematic diagram of the operation process of the data processing and transmission unit includes: (1) the host issuing instruction 51; (2) receiving control on the disk array (4) receiving the instruction 'and disassembling the instruction into several independently workable tasks Element unit 52; _ (3) The working element controller receives several pieces of instructions that have been disassembled into several independently executable instructions, and performs data storage/fetching in sequence on a first-in, first-out basis; 4) Transfer the completed save/fetch action to the work unit as the unit of the work unit. (5) The work tree is difficult __Several completed data data processing elements and the data work element transfer 55 in principle; It will refer to _ into a number of independently completed Wei Zuoyuan, with Wei Zuoyuan as the data department, single % 'do not have to be like the first button, all the actions are finished with the command towel and start to return the main 'reduced the waiting instruction action _, can greatly improve the efficiency of the host operation. On the Z, the material (4) of the invention (4), when the pure mosquitoes of the present invention are similar to the changes or replacements, or according to the same (4) materials, the equivalent of 200947216 changes and modifications, should still be covered by the invention patent The scope. [Simple description of the diagram] Figure 1 is a schematic diagram of a conventional architecture. Figure 2 is a schematic diagram of the architecture of the present invention. Fig. 3 is a schematic view showing the arrangement of the working elements of the present invention. Figure 4 is a schematic diagram of the operation of the FIS architecture pointer of the receiving controller of the present invention. FIG. 5 is a schematic diagram of the operation of the positioner of the working unit of the receiving controller of the present invention. Figure 6 is a schematic diagram showing the operation flow of the data processing and transfer unit of the present invention. [Main component symbol description] 主机 Host interface controller system processor system memory system bus line communication line disk array system encoding/decoding controller © receiving controller transmission controller working unit queue controller entity position description table controller DMA controller DMA bus instruction bus memory space A pointer 10 11 12 13 14 15 20 21 22 23 24 25 26 ' 27 28 30, 40 31, 31 312, 41, 411, 412 11 200947216 B 32, 321, 322, 42, 42

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Claims (1)

200947216 X. Patent application scope: 1. The structure of the data processing and transmission unit is as follows: A host, which further includes: the system processor sends data to/from the instruction according to the instruction to be executed. Request; a system memory, which stores the processed data; = the disk array system's system is electrically connected to the host computer, and according to the system, the data is stored and fetched. The disk array system further includes: a receiving controller, which receives the instruction from the host, and disassembles the instruction into a plurality of independently executable working elements as an execution unit; © - the transmission control, which is completed The /fetch action responds to the host with the data work unit as a unit; a = element (four) controller' accepts the command work 7G from the receive control to be executed or sequentially processes the data work elements Returning the transmission controller; - physical location description table controller, which describes the translation address and conversion capacity of the instruction and data to be processed; one leg controller 'which further includes The leg S is discharged, and the DMA controller sequentially arranges the working instruction elements to be executed by the working 7G queue controller through the physical position description table ❹ controller description writer DMA bus, that is, starting data storage / fetch, or transfer the processed data work element to the work element queue controller through the description of the actual position description table controller. 2. If the work unit is the data processing and transmission unit structure as described in the application scope of the patent scope, the host has an interface (four) device, and through the age dragon _ to establish a telecommunications connection with the magnetic miscellaneous system. 3. As described in the second paragraph of the patent application, the work element is the data processing and transmission unit architecture, and the interface controller supports the communication interface of the Serial ΑΤΑ specification. 4. If you apply for the structure of Wang Zuoyuan's processing and transmission unit as described in the special section, 13 200947216, there is an encoding/decoding controller on the disk array system, and the encoding/decoding controller is the host computer. The data transmitted or returned to the host is translated according to the decoding mechanism of 8b/1〇bΜ# 〇5. The structure of the data processing and transmission unit as described in the third paragraph of the patent scope is as requested. The disk array system is provided with a storage device that supports the NCQ protocol. 6. If the work element is the data processing and transfer unit architecture as described in the scope of the patent application, the work elements arranged in the work element queue are executed on the principle of first-in-first-out (FIF〇). 7. A method of processing a data processing and transmitting unit in a host computer and a disk array system, wherein the host includes a system processor, a system memory, and the magnetic system includes - a relay, a transmission control K, a physical position description table controller and a DMA controller, the method comprising the following steps: (1) a host issuing an instruction; (2) a disk array system The receiving controller receives the instruction and disassembles the instruction into a plurality of work unit units that can be independently completed; (3) the working element queue controller receives a plurality of instruction units that have been disassembled into a plurality of independently executable instructions. Data storage/removal is performed in order of first-in-first-out principle; (4) The save/fetch action has been completed, and the data work unit is transmitted to the work element queue controller; (5) The work element queue controller receives several The processed data work elements have been completed, and the data work elements are transmitted to the host in sequence according to the principle of first-in, first-out. 8. The method of applying the work element to the data processing and transfer unit as described in item 7 of the patent application is in the form of a 4DTORD type.