TW200945973A - Method for fabricating electronic component carrier - Google Patents

Abstract

A method of fabricating an electronic component carrier is provided. A first patterned metal layer is formed on a first surface of a substrate. A first patterned solder resist layer is formed over the first surface of the substrate and the first patterned metal layer, and exposes part of the first patterned metal layer. At least a through hole is formed and passes through the substrate and the first patterned metal layer. A second metal layer is formed over a second surface of the substrate opposite to the first surface. A second patterned solder resist layer is formed over the second metal layer, and exposes part of the second metal layer. Part of the second metal layer is etched with the second patterned solder resist layer as a mask to form a second patterned metal layer.

Description

200945973 -----------i〇c/n IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating an electronic component carrier. [Prior Art] With the development of semiconductor technology, the junction density of IC chips is becoming higher and higher, so that a carrier for chip packaging must also be developed corresponding to a high junction density. Currently, conventional carrier boards for chip packaging include a lead frame, a rigid circuit carrier, and a flexible circuit carrier (flexibie circuit carrier). For flexible line carriers, the currently developed chip on film (COF) package is a package that packages the chip on a flexible line carrier. Because of its small size, thin thickness, light weight, and flexibility, flip-chip packages are ideal for packaging small wafers or other small electronic components such as inkjet wafers and imaging drivers. Wafers and RF chips, etc. SUMMARY OF THE INVENTION The present invention provides a method for fabricating an electronic component carrier. One embodiment of the present invention provides a method of fabricating an electronic component carrier to form a first patterned metal layer on a first side of a substrate. Forming a first pattern of the solder resist layer on the first side of the substrate and the first patterned metal layer wherein the first patterned anti-glaze layer exposes a portion of the first patterned metal layer. Forming at least a through hole through the substrate and the first patterned metal layer. Forming 5 200945973

I MM V » 1 *·· j-OC/H -;: Relative to the second side of the first face. Formed on the second metal layer, wherein the second patterning is resistant to the second metal layer. The second patterned solder resist layer is used as a mask ': a portion of the second metal layer' is engraved to form a second patterned metal layer. In an embodiment of the invention, the substrate can be a flexible dielectric substrate. Further, the material of the substrate may include polyamidamine. In an embodiment of the invention, the step of forming the first patterned metal layer may include attaching a first metal layer to the first side of the substrate and patterning the metal layer. In addition, the step of patterning the first metal layer may include lithography and surname. In an embodiment of the invention, the step of forming the first patterned solder resist layer may include forming a solder resist layer on the first side of the substrate and the first patterned metal layer 'subsequent exposure, development, and curing solder resist Layers to form a first patterned anti-frying layer. In an embodiment of the invention, the material of the first patterned solder resist layer comprises a thermoset solder resist material. In an embodiment of the invention, the step of forming the through holes may include stamping or engraving. In an embodiment of the invention, the through holes extend through the first patterned solder mask. In an embodiment of the invention, the manufacturing method may further include forming a first patterned portion of the first anti-solder layer exposed by the first anti-solder layer after forming the first patterned solder resist layer. On the metal layer. Further, the first oxidation resistant layer may be a nickel gold laminate. 200945973 ^\f / rv i.\*oc/n In an embodiment of the invention, the step of forming the second metal layer can include attaching a metal foil to the second side of the substrate. In an embodiment of the invention, the step of forming the second patterned solder resist layer may include forming a solder resist layer on the second metal layer, and then exposing, developing, and curing the solder resist layer to form a second patterned anti-solder Solder layer. In an embodiment of the invention, the material of the second patterned solder resist layer comprises a thermoset solder resist material. In an embodiment of the invention, the fabrication method may further include forming a first protective layer on the first patterned metal layer. After forming the second patterned solder mask, a second protective layer is formed on the second metal layer, wherein the second patterned solder resist layer and the second protective layer expose a portion of the second metal layer. A second patterned metallization layer is etched by the second patterned solder resist layer and the second protective layer to form a second patterned metal layer. The first protective layer is removed, wherein the first patterned solder mask exposes a portion of the first patterned metal layer. The second protective layer is removed, wherein the second patterned solder mask exposes a portion of the second patterned: genus layer.

In an embodiment of the invention, the manufacturing method may further include: after removing the second protective layer, forming a portion of the second patterned metal layer exposed by the second anti-solder layer. on. In the present invention, the second anti-oxidation layer may be a gold stack. The above-described embodiment of the present invention discloses a method of fabricating an electronic component carrier for fabricating a wiring carrier having a through hole. The above features and advantages of the present invention will become more apparent and understood. The following is a detailed description of the embodiments of the present invention, which is described in detail below with reference to the accompanying drawings. [Embodiment] Figs. 1 to 11 are cross-sectional views showing a method of fabricating an electronic component carrier according to an embodiment of the present invention. This embodiment discloses a method for fabricating an electronic component carrier board for fabricating a line carrier having a through hole. Referring to Figure 1, a substrate 100 is first provided. In this embodiment, the substrate 100 is a flexible dielectric substrate, and the material thereof may include polyimide (1). Further, in order to facilitate the conveyance of the substrate 1?0, a plurality of transmission holes l?h may be formed on the substrate 100, which may be formed by punching. In another embodiment not shown, other modes of transport may be employed to omit the fabrication of the drive apertures l〇〇h. Referring to FIG. 1 and FIG. 2, a first patterned metal layer 102 is formed on a first surface 100a of the substrate 1A. In this embodiment, a metal foil may be attached to the first surface 丨 00a of the substrate 100 by an adhesive layer, and then the metal foil is patterned to form a first patterned metal layer 1 , 2, wherein the pattern The steps of forming the metal layer include lithography and etching. Further, the material of the first patterned metal layer 1〇2 may include copper. In another embodiment, not shown, the first side 1a of the substrate 1 can directly form the first patterned metal layer 1〇2 without additionally passing through an adhesive layer. Referring to FIG. 2 and FIG. 3, a first patterned solder resist layer 1〇4 is formed on the first surface i〇〇a of the substrate 1〇〇 and the first patterned metal layer 102, wherein the first patterned anti-solder layer The solder layer 1〇4 exposes a portion of the first patterned metal layer 8 200945973 z.\j / ^z, twi..uOC/n 102. In this embodiment, in the step of forming the first patterned solder resist layer 〇4, a solder resist layer may be formed on the first surface of the substrate 100 and the first patterned metal layer 102. In the above, the material of the solder resist layer is made of a photo solder resist material. The solder resist layer is then exposing, devei〇ping, and curing to form a first patterned solder mask layer 104. In another embodiment not shown, the material of the first patterned solder resist layer 1〇4 may also be a thermosetting anti-fresh material. Referring to FIG. 3 and FIG. 4 , when the material of the first patterned metal layer 1 2 is made of copper or other easily oxidizable metal, the first patterned solder resist may be formed after the first patterned solder resist layer 104 is formed. A first anti-oxidation layer 1〇6 is formed on a portion of the patterned metal layer 102 exposed by the layer 1〇4. In this embodiment, the first oxidation resistant layer 106 can be a nickel gold stack. * Referring to Figures 4 and 5, a plurality of through holes 108 are formed through the substrate 1 and the patterned metal layer 102. In this embodiment, some of the through holes 1 〇 8 〇 pass through the first patterned solder resist layer 104, and some of the through holes 1 〇 8 do not pass through the second patterned solder resist layer 104 ′ and form these The step of the through hole 1 〇 8 can be packaged = rushed or buttoned. In addition, these vias should be used as holes for the wafer or electronic components required for packaging. Referring to FIG. 5 and FIG. 6, a second metal layer 110 is formed on the second surface 100b of the substrate 1A with respect to the first surface 1A. In the present embodiment, a metal foil is attached to the second surface i〇〇b of the substrate 1 to form a metal layer 110. In addition, the material of the second metal layer 11A may include copper. It should be noted that, in this embodiment, in order to form the second 9 200945973 〇 c / n metal layer 110 ′ described above, the first surface 10 Gb of the substrate m may be formed before the through holes 1 〇 8 are formed. - an adhesive layer, and after forming the through holes (10), 'via the adhesive layer--a metal foil is attached to the second surface io〇b of the substrate 1〇〇 to form the second metal layer described above, thus being adhered These through holes (10) also pass through the layer before the layer is attached with the metal foil. Referring to FIG. 6 and FIG. 7, a second solder layer 112 is formed on the second metal layer n, and the second solder mask layer 112 is exposed to the second metal layer 11G. In the step of forming the second patterned solder resist layer m, the solder resist layer may be formed first on the second metal layer 11G, wherein the material of the recording layer is made of a solder resist material. The solder resist layer is then sequentially exposed, developed, and cured to form a second patterned sacrificial layer 112. In a further embodiment, the second patterned solder mask 112 is a solder resist material. Heat of use, please refer to FIG. 7 and FIG. 8'. In order to pattern the second metal layer 110, a first protective layer 114 may be formed in the first patterned metal layer.

The second layer of i,1, the second protective layer 116 is in the second metal genus 110, the second patterned layer and the second protective layer U layer U. . In this embodiment, the first protective layer = 濩 116 " can be made by coating or pressing acrylic glue. 8 and FIG. 9, after forming the first protective layer 114 and the second: 2-12, the second patterned solder resist layer 112 and the second protective layer 116 are the second metal of the mask portion. m to form a second layer of the gold layer 110. In the wipe of this embodiment, the first protective layer 114 protects the line formed by the first patterned metal layer 1G2 from being flanked. ... iuc/n 200945973 Please refer to Figure 9 and Figure ι〇, too 士士,结_德德' 铭广笼only female a $ into the second patterned metal layer 11〇, Ϊ a protective layer 114' its tenth - The patterned solder resist layer 104 exposes the exiting knives a patterned metal layer 1 〇 2 and its Η 6). In addition, the second protective layer 116 is further removed, and the second layer of the layer 12 is removed by the exposure 2, patterned solder resist (4) FIG. 11 'When the second patterned metal layer (4), the material of which is easily oxidized Forming a second patterned gold layer 暴露 i ι ί Ι Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Layer 118 is a nickel gold laminate. At this point, the = carrier board is almost complete. The above embodiment of the present invention which has been subjected to the present invention has been disclosed as "a type of electric board produced by a chip; a j-chip having a through-hole material array" for carrying a wafer on the wafer package. And let the wire connecting Crystal # pass through itself. The singularity of the present invention has been disclosed in the above embodiments. However, it is not intended to limit the scope of the present invention, and it is possible to make a few changes without departing from the spirit and scope of the present invention. Retouching, the protection of the present invention is subject to the definition of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS A sub-element === surface shows an electric power of an embodiment of the present invention. 200945973 [Description of main component symbols] 100: Substrate 100a: First surface 100b: Second surface 100h: Transmission hole 102 : first patterned metal layer 104: first patterned solder mask

106: first oxidation resistant layer 108: through hole 110: second metal layer 110': second patterned metal layer 112: second patterned solder resist layer 114: first protective layer 116: second protective layer 118: Second antioxidant layer

12

Claims (1)

200945973 Know xx, one%% * · a •^*oc/n X. Patent application scope: L A method for manufacturing an electronic component carrier board, comprising: forming a first patterned metal layer on a substrate - first Forming a -first patterned solder mask on the first face c of the substrate wherein the first patterned solder resist is exposed:; the first patterned metal layer; Forming at least a second surface; a uniform hole passing through the substrate and the first patterned metal layer; and a second metal layer forming a second patterned solder resist on the substrate opposite to the first surface a layer on the second metal layer, wherein the second patterned solder resist layer exposes a portion of the second metal layer; and/or the first patterned solder resist layer is used as a mask to etch a portion of the second gold layer, To form a second patterned metal layer. The method of fabricating an electronic component carrier according to claim 1, wherein the substrate is a flexible dielectric substrate. 3. The method of producing an electronic component carrier as described in claim 1, wherein the material of the substrate comprises polyamine. The method for fabricating an electronic component carrier as described in claim 1, wherein the step of forming the first patterned metal layer comprises: attaching a metal layer to the first side of the substrate; The first metal layer is patterned. 5. The method of fabricating an electronic component carrier as described in claim 4, wherein the step of patterning the first metal layer comprises lithography and etching. 6. The method of claim 13, wherein the forming the first patterned solder resist layer comprises: forming a solder resist layer on the substrate And the first patterned metal layer; exposing the solder resist layer; developing the solder resist layer; and curing the solder resist layer to form the first patterned solder resist layer. 7. The method of fabricating an electronic component carrier according to claim 1, wherein the material of the first patterned solder resist layer comprises a thermosetting solder resist. 8. The method of producing an electronic component carrier according to claim 1, wherein the step of forming the through hole comprises stamping. 9. The method of fabricating an electronic component carrier according to claim 1, wherein the step of forming the via comprises etching. For example, the method for manufacturing an electronic component carrier according to the first aspect of the invention, wherein the through hole is more than the first patterned solder resist layer.制作作ΙΐΙΙ 电子 电子 之 之 之 = = = ======================================================================================== on. 14. The method of fabricating an electronic component carrier according to claim 1, wherein the forming the second patterned solder resist layer comprises: forming a anti-cup layer on the second metal layer; exposing the solder resist a layer; developing the solder resist layer; and curing the solder resist layer to form the second patterned solder resist layer. 15. The method for producing an electronic component carrier board according to item (4) of the invention is as follows. The material f of the second patterned solder resist layer comprises a touch-type anti-friction material. a method of forming a first protective layer on the first patterned metal layer; forming a second protective sound after forming the second patterned anti-front layer a patterning solder resist layer and the first; the second patterned anti-friction layer and the second protective layer are masks, and the second metal layer is formed to form the second patterned metal layer. The first-patterned solder resist layer exposes a portion of the layer (wherein the second (four) solder resist layer is exposed to the electronic component carrier plate as described in item 16 of the scope of interest; 200925973 ^\JI VT i.. v*〇C/rj is formed by removing the second protective layer from the second patterning prevention exposure. The second anti-oxidation layer is in the portion of the second patterned metal layer. The method for fabricating an electronic component carrier as described in claim 17 wherein the second oxidation resistant layer is a nickel gold laminate. 16