TW200945562A - Single gate nonvolatile memory cell with transistor and capacitor - Google Patents

Single gate nonvolatile memory cell with transistor and capacitor Download PDF

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TW200945562A
TW200945562A TW097115609A TW97115609A TW200945562A TW 200945562 A TW200945562 A TW 200945562A TW 097115609 A TW097115609 A TW 097115609A TW 97115609 A TW97115609 A TW 97115609A TW 200945562 A TW200945562 A TW 200945562A
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region
doped
gate
doping type
capacitor
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TW097115609A
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TWI376792B (en
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Cheng-Chi Lin
Shih-Chin Lien
Chin-Pen Yeh
Shyi-Yuan Wu
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Macronix Int Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell

Abstract

A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory device.

Description

200945562 九、發明說明： 【發明所屬之技術領域】 本發明係有關於非揮發記憶體積體電路，特別是具有包 含-電晶體及-電容器兩者之單閘極記憶胞的非揮發記憶體 5 積體電路。 【先前技術】 ❾ 非揮發記憶胞的實例’像是單次程式化（OTP)記憶胞 係該單閘極記憶胞，而其包含一電晶體及一電容器。該等非 10 揮發記憶胞的實例揭露於美國專利第6,054,732 ^專利；第 6,875,648號專利’第6，G25,625號專利；第5,896,315號專利， 以及美國專利申請案第2006/0022255號的專利公開說明書 中〇 15 【發明内容】 本發明之一目的係揭露一種非揮發記憶體積體電路，包 ❹ 含一半導體基板，以及一非揮發記憶裝置在該半導體基板 上。該非揮發記憶體裝置包含一電晶體在該半導 以及-電容器在該半導體基板上，該電晶體 20 一源極區域及一汲極區域所控制。該電晶體被一閘極區域所 控制。該電晶體具有多重摻雜區域。一摻雜區域係在該閘極 區域之兩侧以及定義該源極及該汲極區域，並具有一摻雜類 型像是η-型。至少具有三種以上的捧雜區域，並位在該問極 區域之兩側，及覆蓋該源極及該汲極區域，此兩者具有與該 25 源極及汲極區域相同的摻雜類型（像是η-型），而第三者具^ 與該源極及汲極區域相反的摻雜類型（像是ρ—型）。一共享浮 5 200945562 動閘極連接該電晶體的該閘極區域以及該電容器之該閘極區 域0 在一些實施例中，該基板具有與該閘極及汲極區域相反 的一掺雜類型（像是P-型> 在一些實施例中’更包含具有與該閘極及汲極區域相反 的一摻雜類型（像是P_型）之一磊晶層。在各種實施例中， G 該蟲晶層做為像是該電晶體及該電容器結構之基底。 10 " 在各種實施例中，具有與該閘極及汲極區域相反的一摻 雜類型（像是p_型）以及與該閘極及汲極區域相同的一摻雜 類型（像是η-型）之一井區，或是兩者都有。一些實施例中， 具有-電晶體在-此種井區之上、—電容器在—此種井區之 15 上、電晶體及電容器兩者在一此種井區之上以及電晶I#及雷 容器兩者在不同的此種井區之上。 m 20 在一些實施例中包含鄰近於該電晶體之該_區域之間 隔物，並在該源極及汲極區域料分地覆蓋該摻雜區域。 在一些實施例中包含施加記憶體操作 揮發記健路。 偏壓至該非 包含本發明所述之一 一非揮發記憶體積體 本發明之另一目的係揭露具有多重 電晶體及一電容器的非揮發記憶裝置之 電路。 6 25 200945562 憶裝另一目的係揭露-造本發明所述非揮發記 【實施方式] 電容第1圓至第13圖中製造具有—電晶體及一 的製程之一二並具有曰不同摻雜類型之一單閘極記憶胞 4面圖式，特別是植入一 η-型井區8。 ❹ 10 15 Ο 第2囷繪示在第丨圖至第13圖中製造具 二區並具有不同摻雜類型之-單閘極曰記憶胞 的氣程之-剖面圖式，特別是植入—卜型井區a。 電容不在第1圖至第13圖中製造具有—電晶體及一 的製程並具有不同摻雜類型之—單閘極記憶胞 抽圖式，特別是在結構之間長出隔離氧化物16。 電容器/ = ΐ不在第1圖至第13圖中製造具有—電晶體及一 同的井區並具有不同摻雜類型之一單閘極記憶胞 ϊίίϊο圓式’特別是對該電晶體及該電容成長閘極 ㈣示在第1圖至第13圖中製造具有—電晶體及一 同的井區並具有不同摻雜類型之一單閘極記憶胞 αΙ面圖式，特別是沈積多晶矽24及矽化鎢28。 第6圖繪示在第i圖至第13 θ ^ 电日日體及一 社不Π的井Q並具林同摻雜 25 200945562 的製程之-剖面®式’特別是⑽多晶_及♦化鶴以定義該 電晶體之該閘極區域32、36、4G以及該電容器之該閘極區域 33、37、41 〇 5 —第7圖繪示在第⑼至第^圖中製造具有—電晶體及一 電容器在不同的井區並具有不同摻雜類型之—單閘極記憶胞 的製程之一剖面圖式，特別是植入N_摻雜區域44、45 (具有 與即將形成的N+源極及汲極區域之相同掺雜類型）於該電晶 ❹體的該閘極區域之兩侧’以及形成覆蓋於即將形成的源極及 ίο 汲極區域之上。 第8圖繪示在第1圖至第13圖中製造具有一電晶體及一 電容器在不同的井區並具有不同摻雜類型之—: 15 ❹ 的製程之-剖面圖式’特別是植人兩個額外的摻雜區域^該 電晶體的該閘極區域之兩侧，以及形成覆蓋於 ;^ 極娜區域之上，其中一組(48、49)具有與即將 源極及汲極區域相反的摻雜類型（P型），而另外一組/成的 有與即將形成的源極及汲極區域之上相同二2類 第9圖繪示在第】圖至第13圖中製造具有一電θ 電容器在不同的井區並具有不同摻雜類型之一二，及一 的製程之一剖面圖式，特別是沈積一氧化物層58: 己憶胞 第10圖繪示在第1圖至第13圖中製造具有一 一電容器在不同的井區並具有不同摻雜類型之一體及 胞的製程之一剖面圖式，特別是蝕刻該氧化層58以二極記憶 8 25 200945562 w 電晶體該閘極區域之間隔物6〇、61以及形成靠該電容器該 極區域之間隔物62、63。 "Μ 5 10 15 20 J 11圖繪示在第1圖至第13圖中製造具有一電晶體及 一電容器在不同的井區並具有不同摻雜類型之一單閘極記憶 胞的製程之式’制是植人該雜及汲極區域 在該電晶體之該閘極區域的賴，以及具有相同摻雜 類K +)之該區域64、65摘電容器之該閘極區域的兩側。 圖繪示在第1圖至第13圖中製造具有—電晶 -電容器在不_賴並具林同摻賴型之—單閘極 剖面圖式’特別是植人具有與該源極及没極i 域相反的摻雜類型（P+)之一區域68。 -電在//圖至第13财製造具有—電晶體及 胞Si::二具有不同摻雜類型之-單閘極記憶 曰辦及命卜β圖式’特別是沈積該單閘極72以連結該電 日日體及該電谷器之該閘極區域。200945562 IX. INSTRUCTIONS: [Technical Field] The present invention relates to a non-volatile memory volume circuit, in particular, a non-volatile memory 5 product having a single gate memory cell including both a transistor and a capacitor. Body circuit. [Prior Art] An example of a non-volatile memory cell, such as a single-programmed (OTP) memory cell, is a single-gate memory cell, which includes a transistor and a capacitor. Examples of such non-volatile volatile memory cells are disclosed in U.S. Patent No. 6,054,732, U.S. Patent No. 6, 875, 648, the disclosure of which patents No. BRIEF DESCRIPTION OF THE DRAWINGS [Embodiment] One object of the present invention is to disclose a non-volatile memory volume circuit comprising a semiconductor substrate and a non-volatile memory device on the semiconductor substrate. The non-volatile memory device includes a transistor on the semiconductor and a capacitor on the semiconductor substrate, the transistor 20 being controlled by a source region and a drain region. The transistor is controlled by a gate region. The transistor has multiple doped regions. A doped region is on both sides of the gate region and defines the source and the drain region, and has a doping type η-type. There are at least three types of doping regions, which are located on both sides of the interrogation region, and cover the source and the drain region, which have the same doping type as the 25 source and drain regions ( Like η-type), the third has a doping type (like ρ-type) opposite to the source and drain regions. A shared floating 5 200945562 is connected to the gate region of the transistor and the gate region 0 of the capacitor. In some embodiments, the substrate has a doping type opposite to the gate and drain regions ( Like P-type > In some embodiments, 'an embodiment further comprises an epitaxial layer having a doping type (e.g., P_type) opposite to the gate and drain regions. In various embodiments, G The seed layer acts as a substrate for the transistor and the capacitor structure. 10 " In various embodiments, having a doping type (like p_type) opposite the gate and drain regions and a well region of the same doping type (such as η-type) as the gate and drain regions, or both. In some embodiments, having a transistor above the well region, - the capacitor is on - 15 of the well region, the transistor and the capacitor are both above the well region and both the electromorphic I# and the lightning vessel are above the different well regions. m 20 In some embodiments Having a spacer adjacent to the region of the transistor, and in the source and drain regions The doped region is covered by a land. In some embodiments, the memory is operated by a memory. The bias is applied to the non-volatile memory volume of the present invention. The other object of the present invention is to have multiple A circuit for a non-volatile memory device of a transistor and a capacitor. 6 25 200945562 Recalling another object of the invention - forming a non-volatile memory according to the present invention [Embodiment] Capacitor 1st to 13th having a transistor One of the processes of one and two has a single-gate memory cell 4-side pattern of different doping types, especially implanted into an η-type well region 8. ❹ 10 15 Ο The second 囷 is shown in the third Figure to Figure 13 shows a cross-sectional profile of a single-gate 曰 memory cell with two regions and different doping types, especially the implant-type well region a. The capacitance is not in Figure 1 Figure 13 shows a single-gate memory cell pattern with a transistor and a process with different doping types, especially with an isolation oxide 16 between the structures. Capacitor / = ΐ is not in the first Figure to Figure 13 made with --transistor and together a well region and having a single gate memory cell of a different doping type ίίϊο round type, in particular, the transistor and the growth gate of the capacitor (four) are shown in Figures 1 to 13 to have a transistor and together The well region has a single gate memory cell αΙ surface pattern of different doping types, especially depositing polysilicon 24 and tungsten germanium 28 . Figure 6 shows the solar image in the i-th to thirteenth θ ^ An uncompromising well Q and a forest-doped 25 200945562 process-section® type, in particular (10) polycrystalline _ and ♦ a crane to define the gate region 32, 36, 4G of the transistor and The gate region 33, 37, 41 〇 5 of the capacitor - Fig. 7 shows that in the (9) to the second figure, a single gate having a transistor and a capacitor in different well regions and having different doping types is fabricated. a cross-sectional view of a process of a very memory cell, in particular implanted N-doped regions 44, 45 (having the same doping type as the N+ source and drain regions to be formed) in the electromorphic body The sides of the gate region 'and the formation overlying the source to be formed and the ίο 区域 region. Figure 8 is a cross-sectional view showing the process of manufacturing a transistor having a transistor and a capacitor in different well regions and having different doping types in the first to the thirteenth drawings. Two additional doped regions ^ on both sides of the gate region of the transistor, and formed overlying the region; wherein a group (48, 49) has an opposite polarity to the source and drain regions The doping type (P type), and the other group/formed is the same as the source and the drain region to be formed. The second type and the second figure are shown in Fig. 13 to Fig. 13 to have one Electrical θ capacitors in different well regions and having one of two different doping types, and one of the processes of the profile, in particular, the deposition of an oxide layer 58: Figure 10 is shown in Figure 1 to Figure 13 is a cross-sectional view showing a process for fabricating a body and a cell having different capacitor types in different well regions, in particular etching the oxide layer 58 to a diode memory of 8 25 200945562 w. Spacers 6〇, 61 of the gate region and spacers 62 forming the pole region of the capacitor 63. "Μ 5 10 15 20 J 11 shows a process for fabricating a single-gate memory cell having a transistor and a capacitor in different well regions and having different doping types in FIGS. 1 to 13 The system is formed by implanting the impurity and drain regions in the gate region of the transistor, and the regions 64, 65 having the same doping class K +) are on both sides of the gate region of the capacitor. The figure shows that in the first to the thirteenth figure, a single gate cross-section pattern is produced with a -electric crystal-capacitor in a type that does not rely on the same type. In particular, the implant has a source and a One of the opposite doping types (P+) of the pole i domain is 68. - electricity in the / map to the thirteenth manufacturing with - transistor and cell Si:: two with different doping types - single gate memory and life - β pattern 'in particular, the single gate 72 is deposited The electric solar body and the gate region of the electric grid are connected.

1 =分，蓋P+植入窗1〇0。氧化物定義窗81部二:覆 摻雜* % ° N場雜W 96部分地覆蓋Ν·_窗84、P 97 /推㈣92。氧化物定義窗80部分地覆蓋Ν+ 極72番植入窗97部分地覆蓋Ν-井捧雜窗76。浮動閘 1 -MB ^ 8〇 ' 81 ° ^ ^ 1及14C -14C’指出第14A圖至第14c圖的剖面圖。 9 25 200945562 第14Α圖至第]4Γ固认 電容器在不_絲並第14圖之具有—電晶體及一 之一剖賴。不同摻雜麵之—單閘極記憶胞 剖面。第14B圖_ = ^應第14圖剖面線14A’-14A’之 第⑽___ /H14圖顯線14B，_14B，之剖面。 頂弟14圖剖面線14CM4C，之剖面。 ❹ 10 15 Ο 20 第15圖緣示在第15 一電容器在相同的井第26圖中製&具有—電晶體及 式’特別是植人閘極記憶胞的製程之1面圖 p i井& 12，其類似第2圖之製程步驟。 第16圖繪示在第15圖 —電容器在相同的井區之 ®中製心、有—電晶體及 式，姓之一單閘極記憶胞的製程之一与丨而m 步驟別疋在結構中成長隔離氧化物16，類似第3圖;:: ^ Π圖繪示在第15囫至第％目中製造具有 電：器在相同的井區之一單開極記憶胞的製程之一 對該電晶體及該電容器成長閘極氧化物it 罘4圖之製程步驟。 頸似1 = minute, cover P + implant window 1 〇 0. Oxide Definition Window 81 Part 2: Doping * % ° N Field Miscellaneous W 96 partially covers Ν·_Window 84, P 97 /Push (4) 92. The oxide definition window 80 partially covers the Ν+ pole 72. The implant window 97 partially covers the Ν-well holding window 76. The floating gate 1 - MB ^ 8 〇 ' 81 ° ^ ^ 1 and 14C - 14C' indicates the sectional views of Figs. 14A to 14c. 9 25 200945562 The 14th to the 4th Γ Γ 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器 电容器Single gate memory cell profile with different doping surfaces. Fig. 14B is a cross section of the line (14)___ / H14 of the section line 14A'-14A' of Fig. 14 showing the line 14B, _14B. Top brother 14 figure section line 14CM4C, the section. ❹ 10 15 Ο 20 Figure 15 shows the first surface of the 15th capacitor in the same well. Figure 26 has a pattern of the transistor and the equation, especially the implanted gate memory cell. 12, which is similar to the process steps of Figure 2. Figure 16 shows one of the processes of making a single-gate memory cell in the same well area, in the same well area, and one of the processes of the single-gate memory cell. Medium Growth Isolation Oxide 16, similar to Figure 3;:: ^ Π Diagram showing one of the processes for fabricating a single open-cell memory cell with electricity in the same well zone from the 15th to the 1st The transistor and the capacitor grow gate oxide it 罘 4 diagram process steps. Neck like

Jl8圖繪示在第15圖至第26圖中製造具 電：器在相同的井區之—單閑極記憶胞的製程之一： l特別是沈積多晶㈣切化鶴28，類似第5圖之 第19圖繪示在第15圖至第26财製造具有一電晶體及 25 200945562 :電-剖面圖 域32、36、4G以及兮電容# 義該電晶體之該閘極區 圖之製程步^ 之該區域33、37、41，類似第6 第20圖繪不在第15圖至第％圖由先·』λ ;電容器在相同的井區之— ❹ 10 15 20 源極及汲極區域之相同摻雜類型)於(電有:即:形成的N+ =’以及形成覆蓋於即將形域 類似第7圖之製程步驟。 久次蚀h域之上， ，21圖緣示在第15圖至第26圖 將===二:換(52，則具咖 第8圖之製程步驟。 相_摻雜類型（Ν型），類似 ，22圖繪示在第15圖至第％圖中製造具有—電晶 二電„相_井區之—單閘極記憶胞的製程之一剖二 ;寺別疋沈積-氧化物層58，類似第9圖之製程步驟。 第23圖繪示在第15圖至第％ 一電容器在相_絲之—單_記憶胞㈣程之 25 200945562 w 式，特別是蝕刻該氧化層58以形成靠該電晶體之該閘極區域 之間隔物60、61以及形成靠該電容器之該閘極區域之間隔物 62、63 ’類似第1〇圖之製程步驟。 5 ，24圖繪示在第15圖至第26圖中製造具有一電晶體及 一電容器在相同的井區之一單閘極記憶胞的製程之一剖面圖 式’特別是植入該源極及汲極區域（N+) 64、65在該電晶體 之該閘極區__ ’以及具有相_雜_ (N+)之該區 ❹，64、65在該電容H之該閘極區域的兩側’類1 10 製程步驟。 $ 25圖繪示在第15圖至第26圖中製造具有一電Jl8 diagram shows one of the processes for fabricating electricity in the same well area as in Figure 15 to Figure 26: l Especially depositing polycrystalline (four) cut crane 28, similar to the fifth Figure 19 is a diagram showing the manufacturing process of the gate region of the transistor in Fig. 15 to Fig. 26, which has a transistor and 25 200945562: electro-section fields 32, 36, 4G and tantalum capacitors. The area 33, 37, 41 of the step ^, similar to the 6th 20th drawing, is not in the 15th to the 1stth, and the capacitor is in the same well area - ❹ 10 15 20 source and drain regions The same doping type) is (electrically: ie: formed N+ = ' and forming a process step covering the near-shaped field similar to Figure 7. Above the long-order etch h domain, 21 is shown in Figure 15 To figure 26, === two: change (52, then the process steps of Figure 8 of the coffee. Phase _ doping type (Ν type), similar, 22 figure is shown in the 15th to the %th figure One of the processes of having a single crystal cell of a single crystal cell, a single gate, and a single gate memory cell; a depositional-oxide layer 58 of the temple, similar to the process steps of Fig. 9. Fig. 23 is shown in the figure 15 to the first A capacitor is in the form of a phase-to-wire-to-cell (4) process, in particular etching the oxide layer 58 to form spacers 60, 61 of the gate region of the transistor and forming a capacitor therewith. The spacers 62, 63' of the gate region are similar to the process steps of Figure 1. Figure 5, Figure 24 shows one of the same well regions fabricated in Figures 15 through 26 having a transistor and a capacitor. A cross-sectional view of a single gate memory cell process, in particular implanting the source and drain regions (N+) 64, 65 in the gate region __ ' of the transistor and having phase _ (N+ In the region 64, 64, 65 are on both sides of the gate region of the capacitor H. The process of class 1 10 is shown in Fig. 15 to Fig. 26.

第27圖繪示具有一電晶體及一 植入窗96部分地覆蓋N_摻雜窗84 92。氧化物定義窗8〇部分地覆蓋n 氧化物定義窗82部分地覆蓋 81部分地覆蓋N+植入窗96。 _ 窗 84、p 放秘命 〇〇 n . 單閘極記憶胞之一頂視圖。氧 摻雜窗100。氧化物定義窗81 重疊在氧化物定義窗之間。 電各器在相同的井區之一 [P+ 。N+ M、p摻雜窗88及N摻雜窗 -N+摻雜窗97。浮動閘極72 剖面線27A，-27A，、27B，-27B, 200945562 * 以及27C，-27C’指出第27A圖至第27C圖的剖面圖。 第27A圖至第27C圖繪示第27圖之具有一電晶體及一 電容器在不同的井區並具有不同摻雜類型之一單閘極記憶胞 5 之一剖面圖。第27A圖繪示對應第27圖剖面線27Α，_27^之 剖面。第27Β圖繪示對應第27圖剖面線27Β’-27Β，之剖面。 第27C圖繪示對應第27圖剖面線27C’-27C，之剖面。 〇 第28圖繪示具有一電晶體及一電容器在不同的井區並具 10 有不同摻雜類型之一單閘極記憶胞之一剖面圖，類似第26 圖，但包含一蠢晶表面104。 第29圖繪示具有一電晶體及一電容器在相同的井區之一 單閘極記憶胞之一剖面圖，類似第26圖’但包含一磊晶表面 15 104。 下方表1顯示本發明所述具有5V單次程式化記憶胞之示 © 範非揮發記憶胞的實驗數據。依據該表之上部，製程1僅植 入區域44、45，製程2具有兩組植入區域44、45，製程3具 20 有植入區域44、45 ; 52、53 ’以及製程4具有植入區域44、 45 ; 48、49 ; 52、53。Vt係指臨界電壓，BVD係指一長通道 的崩潰電壓或擊穿電壓。Ids係指通道電流。Isb係指基板電 流’及對於程式化該記憶胞熱載子之一指標^ Vpt係指一短通 道的擊穿電壓或崩潰電壓。Id係指漏電流。 25 200945562 表1: 5V單次程式化記憶胞 製程1 製程2 製程3 製程4 植入區域44,45 (e.g.， N-LDD) X X X X 21%入區域44,45 (e.g. N-LDD) X 植入區域52,53 (e.g., N-熱載子） X 植入區域48,49,52,53 (e.g.，P-口袋，N-熱載 子） X 範例 1 數據:W/L20um/20um Vt(V) 0.75 0.74 0.76 0.76 BVD(V) 11.5 12.3 10.6 10.1 範例 2 數據：W/L 20um/0.5um Vt(V) 0.72 0.63 0.77 0.76 Ids (mA) Vgs=Vds=5V 9.11 12.8 10.7 11.2 Isb (uA) Vds=5.5V -58.2 -308.8 -341.6 -517 Vpt(V)在 lOOnA 11.5 5.5 10.6 10.1 Id (pA) Vd=6V 22.1 4X10-6 53.3 57.4 範例 3 數據:W/L 20um/0.45um Vpt(V)在lOOnA 11.5 2.4 10.6 10.1 下方表2顯示本發明所述具有3V單次程式化記憶胞之示 範非揮發記憶胞的實驗數據。 14 200945562 表2 : 3V單次程式化記憶胞 製程1 製程2 製程3 製程4 植入區域44,45 (e.g., N-LDD) X X X X 2¾入區域44,45 (e.g. N-LDD) X 植入區域52,53 (e.g., N-熱載子） X 植入區域48,49,52,53 (e.g.，P-口袋，N-熱載 子） X 範例 1 數據:W/L20um/20um Vt(V) 0.55 0.56 0.56 0.56 BVD(V) 12.2 11.6 9.9 9.6 範例 2 數據:W/L 20um/0.5um Vt(V) 0.55 0.50 0.54 0.61 Ids(mA) Vgs=Vds=3V 7.2 9.8 9.2 8.7 Isb (uA) Vds=3.3V -4 11.14 -16.08 -19.95 Vpt(V)@100nA 12 5.8 9.9 9.6 Id (pA) Vd=4V 27 3034 62 17 範例 3 數據:W/L20um/0.45um Vpt(V)@100nA 12 2.5 7.4 9.6 表1及表2顯示對於具有植入區域44、45 ; 48、49 ; 52、 15 200945562 ❹ 53之製程4 ’ Isb具有該最大的幅度。 化該圮情腧埶取八刃1!1田度因為Isb或基板係程式 =^己Jt胞熱载子之—指標，*製程 憶胞之高度程式化雜。㈣㈣非揮發兄 高基板電狀高奴式化鱗發記憶胞之3的高擊穿電—2 r表私3及4具有良好的短通道效應。 、 時^日日圓之不例範圍係在8-100 〇hms之間。 10❹ —-------表3·植入^劑晉 植入區域8 (e.g.，η-井） l〇U-1〇13 -2 植入區域12(e.g.，p-井） v av/ Lm 1011 -1〇13 cm 2 植入區域 44,45 (e.e. Ν-ΤΓ>τη l〇12-l〇13cm2 植入區域48,49(e.g.，P-口袋） l〇n-l〇14cm'2 植入區域 52,53(e.g.，N^#w l〇12-l〇14cm2 1015 cm2 一 |入區域 64,65(e.g.，：N+ 源極、 第3〇圖繪示具有—電日日日航_電容ϋ之-單閘極記憶胞 之-非揮發記㈣频電路的—實施例。該積體電路3〇5〇包 含實施使雜式^織胞之—記憶陣列3_，每—記憶胞係 本發明所述之-單-閘極場效電晶體（服）及電容器記憶胞 在該電晶體中具有至少四個摻雜域…觸碼器麵係輕 接至在該記憶_中3_沿著列安置的複數個衫線3〇〇2。 一行解碼器3003係耦接至在該記憶陣列中3〇〇〇沿著行安置 的複數個位元線3004。位址係經由一匯流排3〇〇5而提供至一 行解碼器3003與一列解碼器3〇〇1。在方塊3〇〇6中的感測放 大器與資料輸入結構係經由一資料匯流排3〇〇7而耦接至行解 15 20 200945562 碼器3003 »資料係從積體電路3050的輸入/輸出埠、或積體 電路内部與外部之其他資料來源，而經由資料輸入線3011以 將資料傳輸至方塊中的資料輸入結構。資料係從方塊3006中 的感測放大器、經由資料輸出線3 015、而傳輸至積體電路3050 5 之輸入/輸出埠或其他位於積體電路3050内部或外部之資料 目的地。一偏壓安排狀態機器3009，控制了偏壓安排供應電 壓3008的應用。 〇 使用P-通道電晶體另一實施例，以及關於p-區域交換η- 10 區域，和η-區域交換ρ_區域。 操作的實例敘述於下方。 第13圖之一實施例具有以下操作上示例電壓設定： 通道F-N抹除至低臨界電壓（電子直接由該電晶體的該 閘極區域進入該Ρ_Λ 1，、Figure 27 illustrates a portion of the N-doped window 84 92 partially covered by a transistor and an implant window 96. The oxide defining window 8 〇 partially covers the n oxide defining window 82 partially covering 81 partially covering the N+ implant window 96. _ Window 84, p put a secret 〇〇 n. A top view of a single gate memory cell. Oxygen doping window 100. The oxide definition window 81 overlaps between the oxide definition windows. The electric units are in one of the same well areas [P+. N+M, p-doped window 88 and N-doped window -N+ doped window 97. Floating gate 72 section lines 27A, -27A, 27B, -27B, 200945562 * and 27C, -27C' indicate sectional views of Figs. 27A to 27C. 27A to 27C are cross-sectional views showing a single gate memory cell 5 having a transistor and a capacitor in different well regions and having different doping types. Figure 27A shows a section corresponding to the section line 27Α, _27^ of Figure 27. Figure 27 is a cross-sectional view corresponding to the section line 27Β'-27Β of Figure 27. Fig. 27C is a cross-sectional view corresponding to the section line 27C'-27C of Fig. 27. Figure 28 is a cross-sectional view showing a single gate memory cell having a transistor and a capacitor in different well regions and having 10 different doping types, similar to Figure 26, but including a stupid surface 104 . Figure 29 is a cross-sectional view of a single gate memory cell having a transistor and a capacitor in the same well region, similar to Figure 26 but comprising an epitaxial surface 15104. Table 1 below shows experimental data of a non-volatile memory cell with a 5V single stylized memory cell according to the present invention. According to the upper part of the table, the process 1 is only implanted in the regions 44, 45, the process 2 has two sets of implanted regions 44, 45, the process 3 has 20 implanted regions 44, 45; 52, 53 ' and the process 4 has implants Areas 44, 45; 48, 49; 52, 53. Vt refers to the threshold voltage, and BVD refers to the breakdown voltage or breakdown voltage of a long channel. Ids refers to the channel current. Isb refers to the substrate current 'and one of the indicators for stylizing the memory cell heat carrier ^ Vpt refers to the breakdown voltage or breakdown voltage of a short channel. Id refers to leakage current. 25 200945562 Table 1: 5V Single Stylized Memory Cell Process 1 Process 2 Process 3 Process 4 Implanted Area 44, 45 (eg, N-LDD) XXXX 21% Into Area 44, 45 (eg N-LDD) X Implant Area 52, 53 (eg, N-hot carrier) X Implanted area 48, 49, 52, 53 (eg, P-pocket, N-hot carrier) X Example 1 Data: W/L20um/20um Vt (V 0.75 0.74 0.76 0.76 BVD(V) 11.5 12.3 10.6 10.1 Example 2 Data: W/L 20um/0.5um Vt(V) 0.72 0.63 0.77 0.76 Ids (mA) Vgs=Vds=5V 9.11 12.8 10.7 11.2 Isb (uA) Vds =5.5V -58.2 -308.8 -341.6 -517 Vpt(V) at lOOnA 11.5 5.5 10.6 10.1 Id (pA) Vd=6V 22.1 4X10-6 53.3 57.4 Example 3 Data: W/L 20um/0.45um Vpt(V) lOOnA 11.5 2.4 10.6 10.1 Table 2 below shows experimental data of an exemplary non-volatile memory cell having a 3V single stylized memory cell of the present invention. 14 200945562 Table 2: 3V Single Stylized Memory Process 1 Process 2 Process 3 Process 4 Implanted Area 44, 45 (eg, N-LDD) XXXX 23⁄4 Into Area 44, 45 (eg N-LDD) X Implanted Area 52,53 (eg, N-hot carrier) X Implanted area 48, 49, 52, 53 (eg, P-pocket, N-hot carrier) X Example 1 Data: W/L20um/20um Vt(V) 0.55 0.56 0.56 0.56 BVD(V) 12.2 11.6 9.9 9.6 Example 2 Data: W/L 20um/0.5um Vt(V) 0.55 0.50 0.54 0.61 Ids(mA) Vgs=Vds=3V 7.2 9.8 9.2 8.7 Isb (uA) Vds= 3.3V -4 11.14 -16.08 -19.95 Vpt(V)@100nA 12 5.8 9.9 9.6 Id (pA) Vd=4V 27 3034 62 17 Example 3 Data: W/L20um/0.45um Vpt(V)@100nA 12 2.5 7.4 9.6 Tables 1 and 2 show that for a process having implanted regions 44, 45; 48, 49; 52, 15 200945562 ❹ 53 4' Isb has this maximum amplitude. This sensation takes eight-edge 1!1 field because Isb or substrate system program = ^ Jt cell hot carrier - index, * process memory high memory. (4) (4) Non-volatile brothers High-substrate electric high-nuclearized scales The high breakdown of the memory cells 3 - 2 r Tables 3 and 4 have good short-channel effects. The range of the Japanese yen is between 8-100 〇hms. 10❹ —------- Table 3· Implantation ^ Implantation area 8 (eg, η-well) l〇U-1〇13 -2 Implanted area 12 (eg, p-well) v av / Lm 1011 -1〇13 cm 2 Implantation area 44,45 (ee Ν-ΤΓ>τη l〇12-l〇13cm2 Implantation area 48,49 (eg, P-pocket) l〇nl〇14cm'2 Into the area 52, 53 (eg, N ^ #wl 〇 12-l 〇 14cm2 1015 cm2 a | into the area 64, 65 (eg,: N + source, the third picture shows that there is a day, day, day, day, _ capacitance ϋ - a single-gate memory cell - a non-volatile (four) frequency circuit - an embodiment. The integrated circuit 3〇5〇 includes a memory cell 3_, each memory cell system of the present invention Said - single-gate field effect transistor (mechanical) and capacitor memory cells have at least four doping domains in the transistor... the coder surface is lightly connected to the 3_ along the column in the memory_ A plurality of shirt lines 3〇〇2. A row of decoders 3003 is coupled to a plurality of bit lines 3004 disposed along the row in the memory array. The address is via a bus 3〇〇5 Provided to a row of decoders 3003 and a column of decoders 3〇〇1. At block 3〇 The sense amplifier and data input structure of 6 is coupled to the line solution via a data bus 3〇〇7. 20 20 200945562 code 3003 » data is from the input/output port of the integrated circuit 3050, or the integrated circuit Internal and external sources of data are transmitted to the data entry structure in the block via data entry line 3011. The data is transmitted from the sense amplifier in block 3006 to the integrated circuit via data output line 3 015. The input/output port of the 3050 5 or other data destination located inside or outside of the integrated circuit 3050. A bias arrangement state machine 3009 controls the application of the bias voltage supply voltage 3008. 〇 uses a P-channel transistor and another Embodiments, and for the p-region exchange η-10 region, and the η-region exchange ρ_ region. An example of the operation is described below. One embodiment of Figure 13 has the following operational example voltage settings: Channel FN erase to a low threshold voltage (electrons directly enter the Ρ_Λ 1, from the gate region of the transistor),

足夠的正電壓Sufficient positive voltage

(電子直接由該電晶體的該 65的方向） 17 200945562 終端 電壓 控制閘極67 足夠的負電壓 没極64 浮動 源極65 足夠的正電壓 主體68 接地 通道F-N抹除至高臨界電壓（電子直接由該P-井12進入 該電晶體的該閘極區域） 終端 電壓 控制閘極67 足夠的正電壓 汲極64 浮動 源極65 足夠的負電壓 主體68 足夠的負電壓 5 熱電子程式化至高臨界電壓（電子直接由該P_井12進入 該電晶體的該閘極區域） 終端 電壓 控制閘極67 足夠的正電壓 没極64 足夠的正電壓 源極05 接地 主體68 接地(Electron directly from the direction of the 65 of the transistor) 17 200945562 Terminal voltage control gate 67 Sufficient negative voltage no pole 64 Floating source 65 Sufficient positive voltage body 68 Ground channel FN erased to high threshold voltage (electron directly by The P-well 12 enters the gate region of the transistor) terminal voltage control gate 67 sufficient positive voltage drain 64 floating source 65 sufficient negative voltage body 68 sufficient negative voltage 5 thermal electrons stylized to high threshold voltage (Electronics directly enters the gate region of the transistor from the P_well 12) Terminal voltage control gate 67 Sufficient positive voltage no pole 64 Sufficient positive voltage source 05 Grounding body 68 Ground

第13圖之一實施例具有以下操作上示例電壓設定： 通道F-N抹除至低臨界電壓（電子直接由該電晶體的該 閘極區域進入該P-井12) 18 10 200945562 終端 電壓 控制閘極67 足夠的負電壓 没極64 浮動 源極65 足夠的正電壓 主體68 足夠的正電壓 邊緣F-N抹除至低臨界電壓（電子直接由該電晶體的該 閘極區域進入該P-井12在該源極65的方向） 終端 電壓 控制閘極67 足夠的負電壓 没極64 浮動 源極65 足夠的正電壓 主體68 接地 通道F-N抹除至高臨界電壓（電子直接由該P_井12進入 該電晶體的該閘極區域） 終端 電壓 控制閘極67 足夠的正電壓 没極64 浮動 源極65 足夠的負電壓 主體68 足夠的負電壓 熱電子程式化至高臨界電壓（電子直接由該P-井12進入 該電晶體的該閘極區域） 19 10 200945562 終端 電壓 控制閘極67 足夠的正電壓 汲·極64 足夠的正電壓 源極65 接地 主體68 — - —--」 接地 © ^在一些實施例中多重控制閘極，像是控制閘極66、67接 5 受該控制閘極電壓已達到該電容器區域之更一致的電壓押 本發明係已參照較佳示範實施例來加以描述，、 解的這些實施例中係一種示範性的而非限制本發明、。可以理 技藝中所做各種的修飾、結合，而這些修飾、妹厶t在習知 ^發明之精神範脅’以及係亦落在本發明二皆不脫離 及其均等物所界定的範疇之中。 、、申請專利範 15 【圖式簡單說明】 電容器在1圖至第13圖中製造具有~電日 的製程之獅記㈣ 第2圖獪示在第 電容器在不同的井 至第13圖中製造具有 的製程之入雜跑 20 20 200945562 第3_示在第1圖至第丨 電容器在不同的井區並具有不中裝，、電日日體及- 的製程之-剖面圖式，特別是雜類相極記憶胞 号W疋在結構之間長出隔離氧化物。 第4圖繪示在第1圖至篦η =器在不同的井區並具有不同摻 =之-剖面圖式，特別是對該二 ❹ 10 15 =輯示在第旧至第13 有 =不=並具有不同摻咖之-單閘極二 的从之—剖面圖式’ _是沈财射及魏鶴。 Φ — f ^圖θ示在第1圖至第13 _中製造具有—電晶體及-在不同的井區並具有不同摻雜_之一單閘極記憶胞 的裝程之-剖面圖式，特別是麵刻多晶石夕及⑦化鎢以定義該 電晶體之該閘極區域以及該電容器之該閘極區域。 —，7圖繪示在第1圖至第13圖中製造具有—電晶體及一 電容器在不同的井區並具有不同摻雜類型之一單閘極記憶胞 的製程之一剖面圖式’特別是植入Ν_摻雜區域（具有與即將 形成的Ν+源極及汲極區域之相同摻雜類型）於該電晶體的該 閘極區域之兩侧，以及形成覆蓋於即將形成的源極及汲極區 域之上。 第8圖繪示在第1圖至第π圖中製造具有一電晶體及一電 容器在不同的井區並具有不同摻雜類型之一單閘極記憶胞的 21 25 200945562 製程之一剖面圖式，特別是植入兩個額外的 ，以及形成覆蓋於即 及及極&域之上，其中一組具有與即將形成的 域相反的摻雜類型（Ρ型）’而另外—組則旬幵二 源極及汲極區域之上相同的摻雜類型⑺型）有，、ρ料成的 第9圖繪示在第1圖至第13圖中製造具有 ❹ 10 15 ❹ 電容器在不_井區並具有不同摻雜類型之_單閘:記憶胞 的製程之-剖面圖式，特別是沈積—氧化物層。° 第10 _示在第1圖至第13圖中製造 -電容器在不同的井區並具有不同摻雜翻之—單H隐 胞的製程之-剖面圖式，特別是_該氧化層以形成靠該電 晶體之該閘極區域之間隔物以及形成靠該電容器之該問極區 域之間隔物。 第11圖繪示在第1圖至第13圖中製 -電容器在不_井區並具有不同摻雜類型之—單己憶 胞的製程之-剖韻式’特岐植人該_及祕 =電晶體之該閘=域的兩側，以及具有相同摻雜類型 (N+)之麟極及汲祕域在難容器之該閘極區域的兩側。 ，12圖繪示在第1圖至第13圖中製造具有—電晶體及 器在不同？具有不同摻雜類型之-單閘極記憶 :的製程之-剖面圖式’特別是植入具有與該源極及汲極區 域之相反掺雜類型（Ρ+)之一區域。 22 25 200945562 第13圖繪示在第1圖至第13圖中製造具有一電晶體及 一電容器在不同的井區並具有不同摻雜類型之一單閘極記憶 胞的製程之一剖面圖式，特別是沈積該單閘極以連結該電晶 體及該電容器之該閘極區域。 5 第14圖繪示具有一電晶體及一電容器在不同的井區並具 有不同摻雜類型之一單閘極記憶胞之一頂視圖。 Q 第14A圖至第14C圖繪示第14圖之具有一電晶體及一 10 電容器在不同的井區並具有不同摻雜類型之一單閘極記憶胞 之一剖面圖。 第15圖繪示在第15圖至第26圖中製造具有一電晶體及 一電容器在相同的井區之一單閘極記憶胞的製程之一剖面圖 15 式，特別是植入一 P_型井區，類似第2圖之製程步驟。 第16圖繪示在第15圖至第26圖中製造具有一電晶體及 〇 一電容器在相同的井區之一單閘極記憶胞的製程之一剖面圖 式，特別是在結構之間長出隔離氧化物，類似第3圖之製程 20 步驟。 第17圖繪示在第15圖至第26圖中製造具有一電晶體及 一電容器在相同的井區之一單閘極記憶胞的製程之一剖面圖 式，特別是對該電晶體及該電容成長閘極氧化物，類似第4 25 圖之製程步驟。 第18圖繪示在第15圖至第26圖中製造具有一電晶體及 23 200945562 一電容器在相同的井區之一單閘極記憶胞的製程之一剖面圖 式，特別是沈積多晶矽24及矽化鎢28，類似第5圖之製程步 ❹ 10 15 ❹ 第19圖繪示在第15圖至第26圖中製造具有一電晶體及 、電谷器在相同的井區之一單閘極記憶胞的製程之一剖面圖 式，特別是蝕刻多晶矽及矽化鎢以定義該電晶體之該閘極區 域以及該電容器之該閘極區域，類似第6圖之製程步驟。 ，20圖繪示在第15圖至第26圖中製造具有一電晶體 二電，器在相同的井區之—單閘極記憶胞的製程之 別，N顧域(具有與即將形成的N+源：： 以二2=雜類型）於該電晶體的該閘極區域之兩侧， 以及形成覆錢即將形成的馳及没㈣域之上。 一電圖圖中製造具有—電晶體及 式，特別是棺A 皁閘極記憶胞的製程之一剖面圖 域之兩側，以及兩個額^的摻雜區域在該電晶體的該閘極區 上’其中一組耳^2覆蓋於即將形成的源極及汲極區域之 類型（P型）/而與即將形成的源極及汲極區域相反的摻雜 域之上相同的掺雜類型(乂f)有極區 第22圖綠示在 一電容器在相同的 圖至^第26圖中製造具有一電晶體及 式，特別是沈稽一备/區之一單閘極記憶胞的製程之一剖面圖 谓氧化物層’類似第9圖之製程步驟。 24 25 200945562 f f圖繪示在第15圖至第26圖中製造具有一電晶體及 二電谷器在相同的井區之一單閘極記憶胞的製程之一刹面圖 式，特別是侧該氧化層58以形成靠該電晶體之該閘極區域 之間隔物以及形成靠該電容||之該_區域之間隔物，類似 5 第圖之製程步驟。 ❹ 10 圖繪示在第15圖至第26圖中製造具有一電晶體及 二電容器在相同的井區之-單閘極記憶胞的製程之一剖面圖 式，特別是植入該源極及汲極區域（N+)在該電晶體之該閘 極區域的兩侧’以及具有相畴雜類型（N+)之該源極 極區域在該電容器之該閘極區域的兩侧，類似第丨丨圖之製程 第25圖繪示在第15圖至第26圖中製造具有一電曰 15 一電容器在相同的井區之一單閘極記憶胞的製程之一=及 式，特別是植入具有像是該源極及汲極區域之相對二面圖 (P+)之一區域68，類似第12圖之製程步驟。/雜類型 ❹ 第26圖缘示在第15圖至第26圖中製造具有一 20 一電容器在相同的井區之一單閘極記憶胞的製程之一，體及 式，特別是沈積該單閘極以連結該電晶體及該電容°】面圖 極區域’類似第13圖之製程步驟。 之該閘 第27圖繪示具有一電晶體及一電容器在相同 25 單閘極記憶胞之一頂視圖。 开區之 第 至第 之具有一電晶體及一 25 200945562 電容器在不同的井區並具有不同摻雜類型之一單閘極記憶胞 之一剖面圖。 第28圖繪示具有一電晶體及一電容器在不同的井區並具 5 有不同摻雜類型之一單閘極記憶胞之一剖面圖，類似第26 圖，但包含一蟲晶表面。 第29圖繪示具有一電晶體及一電容器在相同的井區之一 > 單閘極記憶胞之一剖面圖，類似第26圖，但包含一磊晶表面。 〇 第30圖繪示具有一電晶體及一電容器之一單閘極記憶胞 之一非揮發記憶體積體電路的一實施例。 【主要元件符號說明】 15 8 η-型井區 12 ρ-型井區 16 隔離氧化物 20 閘極氧化物 24 多晶矽 20 28 矽化鎢 32、33、36、37、40、41 閘極區域 44、45 N-摻雜區域 48、49、52、53 額外的摻雜區域 58 氧化物層 25 60、61、62、63 間隔物 64、 66 源極區域 65、 67 汲極區域 26 200945562 68 該源極及汲極區域之相反摻雜類型（P+)之區域 72 單閘極（浮動閘極） 76 N-井摻雜窗 80 > 81、82 氧化物定義窗 5 84 N-摻雜窗 88 P摻雜窗 92 N摻雜窗 96 > 97 N+植入窗 ❹ 100 P+植入窗 10 3000 記憶陣列 3001 列解碼器 3003 行解碼器 3006 方塊 3007 資料匯流排 15 3008 偏壓安排供應電壓 3009 偏壓安排狀態機構 3011 資料輸入線 ❹ 3015 資料輸出線 20 3050 積體電路 27An embodiment of Figure 13 has the following operational example voltage settings: Channel FN is erased to a low threshold voltage (electrons enter the P-well 12 directly from the gate region of the transistor) 18 10 200945562 Terminal Voltage Control Gate 67 sufficient negative voltage no pole 64 floating source 65 sufficient positive voltage body 68 sufficient positive voltage edge FN erased to a low threshold voltage (electrons directly from the gate region of the transistor into the P-well 12 at Source 65 direction) Terminal voltage control gate 67 Sufficient negative voltage no pole 64 Floating source 65 Sufficient positive voltage body 68 Ground channel FN is erased to high threshold voltage (electron directly enters the transistor from the P_well 12 The gate region) terminal voltage control gate 67 sufficient positive voltage no pole 64 floating source 65 sufficient negative voltage body 68 sufficient negative voltage thermal electrons stylized to high threshold voltage (electron directly enters by P-well 12 The gate region of the transistor) 19 10 200945562 Terminal voltage control gate 67 Sufficient positive voltage 汲·pole 64 Sufficient positive voltage source 65 Grounding body 68 — - - - - " Grounding ^ ^ In some embodiments multiple control gates, such as control gates 66, 67 connected to 5 by the control gate voltage has reached a more consistent voltage of the capacitor region. The preferred embodiments are described in the following examples, which are illustrative and not limiting of the invention. Various modifications and combinations can be made in the art, and these modifications, sisters, and the spirit of the invention are also within the scope defined by the present invention. . Patent application No. 15 [Simple description of the diagram] Capacitors manufactured in the 1st to 13th drawings with the process of ~Electric Day (4) Figure 2 shows the fabrication of the capacitors in different wells to Figure 13 There is a process of entering the run 20 20 200945562 3 - shown in Figure 1 to the 丨 capacitor in different well areas and has a medium, cross-section, and The heterogeneous phase memory cell number W疋 grows an isolation oxide between the structures. Figure 4 shows the pattern in Figure 1 to 篦η = in different well areas and with different blending = section profiles, especially for the second 10 15 = in the old to the 13th = no = and has a different blend of coffee - single gate two from the - profile " _ is Shen Cai shot and Wei He. Φ - f ^ Figure θ shows the process-section profile of a single-gate memory cell with a transistor and a different doping _ in a different well region, in Figures 1 through 13 In particular, the polycrystalline spine and the tungsten are surfaced to define the gate region of the transistor and the gate region of the capacitor. -, Figure 7 shows a cross-sectional view of a process for fabricating a single-gate memory cell with a transistor and a capacitor in different well regions and having different doping types in Figures 1 to 13 Is implanted in a germanium-doped region (having the same doping type as the germanium + source and drain regions to be formed) on both sides of the gate region of the transistor, and formed to cover the source to be formed And above the bungee area. FIG. 8 is a cross-sectional view showing a process of manufacturing a 21 25 200945562 process having a transistor and a capacitor in a different well region and having a single gate memory cell of different doping types in FIGS. 1 to π. , in particular, implanting two additional, and forming overlying the sum and the polar & domains, one of which has a doping type (Ρ type) opposite to the domain to be formed' and the other is a group The same doping type (7) type on the two source and drain regions is, and the ρ material is shown in Fig. 9 to show that the capacitor has ❹ 10 15 ❹ in the first to the thirteenth. And with different doping types - single gate: the process of the memory cell - profile, especially the deposition - oxide layer. ° 10th - shown in Figures 1 to 13 - a process - a cross-sectional view of a process in which capacitors are in different well regions and have different doping - single H cryptic cells, in particular - the oxide layer is formed A spacer of the gate region of the transistor and a spacer formed by the region of the capacitor. Figure 11 is a diagram showing the process of the -capacitor in the non-well region and having different doping types in the first to the thirteenth drawings. = both sides of the gate = domain of the transistor, and the ridges and the cryptic domains of the same doping type (N+) are on either side of the gate region of the difficult container. Figure 12 shows that the fabrication of the transistors in Figures 1 to 13 is different. A process-cross-sectional pattern of a single gate memory having different doping types is implanted, in particular, with a region having a doping type (Ρ+) opposite to that of the source and drain regions. 22 25 200945562 Figure 13 is a cross-sectional view showing a process for fabricating a single-gate memory cell having a transistor and a capacitor in different well regions and having different doping types in Figures 1 to 13; In particular, the single gate is deposited to connect the transistor and the gate region of the capacitor. 5 Figure 14 is a top plan view of a single-gate memory cell having a transistor and a capacitor in different well regions and having different doping types. Q Figures 14A through 14C are cross-sectional views of a single gate memory cell having a transistor and a 10 capacitor in different well regions and having different doping types, as shown in Fig. 14. Figure 15 is a cross-sectional view showing a process of fabricating a single-gate memory cell having a transistor and a capacitor in the same well region in Figures 15 to 26, in particular, implanting a P_ The well zone is similar to the process steps of Figure 2. Figure 16 is a cross-sectional view showing a process for fabricating a single-gate memory cell having a transistor and a capacitor in the same well region in Figures 15 to 26, particularly between structures. The isolation oxide is removed, similar to the process 20 of Figure 3. Figure 17 is a cross-sectional view showing a process for fabricating a single gate memory cell having a transistor and a capacitor in the same well region in Figures 15 to 26, particularly the transistor and the transistor The capacitor grows as a gate oxide, similar to the process steps in Figure 4 25 . Figure 18 is a cross-sectional view showing a process for fabricating a single gate memory cell having a transistor and 23 200945562 a capacitor in the same well region, in particular, a deposition of polysilicon 24 and Tungsten-tungsten 28, similar to the process of Figure 5, 10 15 ❹ Figure 19 shows a single-gate memory with a transistor and an electric grid in the same well area in Figures 15 to 26. A cross-sectional view of a cell process, particularly etching polysilicon and tungsten telluride to define the gate region of the transistor and the gate region of the capacitor, similar to the process steps of FIG. Figure 20 shows the process of fabricating a single-gate memory cell with a transistor and two cells in the same well region from the 15th to the 26th, N-domain (with the upcoming N+) The source: is in the form of two 2 = heterogeneous) on both sides of the gate region of the transistor, and on the free (4) domain where the formation of the money is to be formed. An electrogram is fabricated on both sides of a cross-sectional view of a process having a transistor and a pattern, particularly a 棺A soap gate memory cell, and two doped regions of the gate are at the gate of the transistor The upper doping type 2 covers the type of source and drain regions to be formed (P type) / the same doping type above the doping domain opposite to the source and drain regions to be formed. (乂f) Polar Region Figure 22 Green shows one of the processes for fabricating a single transistor with a transistor and a single gate in the same figure to ^26. The cross-sectional view of the oxide layer is similar to the process steps of Figure 9. 24 25 200945562 ff diagram shows one of the brake face diagrams of the process of manufacturing a single gate memory cell with a transistor and two electric grids in the same well region, especially in the side view The oxide layer 58 forms a spacer that is adjacent to the gate region of the transistor and a spacer that forms the region of the capacitor ||, similar to the process steps of FIG. Figure 10 is a cross-sectional view showing a process for fabricating a single-gate memory cell having a transistor and a capacitor in the same well region in Figures 15 to 26, in particular, implanting the source and The drain region (N+) on both sides of the gate region of the transistor and the source region having the phase impurity type (N+) are on both sides of the gate region of the capacitor, similar to the first diagram Figure 25 of the process diagram shows one of the processes for fabricating a single-gate memory cell having an electric 曰15-capacitor in the same well region from Fig. 15 to Fig. 26, in particular, the implant has an image Is a region 68 of the opposite dihedral (P+) of the source and drain regions, similar to the process steps of Figure 12. / Miscellaneous type ❹ Figure 26 shows one of the processes for fabricating a single-gate memory cell having a 20-capacitor in the same well region from Figure 15 to Figure 26, in particular, depositing the single The gate is connected to the transistor and the capacitor is in the same manner as in the process of FIG. The gate is shown in Figure 27 as a top view of one of the same 25 single-gate memory cells with a transistor and a capacitor. The first to the first of the open areas have a transistor and a 25 200945562 capacitor in different well regions and have a profile of one of the single gate memory cells of different doping types. Figure 28 is a cross-sectional view showing a single gate memory cell having a transistor and a capacitor in different well regions and having different doping types, similar to Figure 26, but containing a crystal surface. Figure 29 is a cross-sectional view of a single gate cell with a transistor and a capacitor in the same well region, similar to Figure 26, but including an epitaxial surface. 〇 Figure 30 illustrates an embodiment of a non-volatile memory volume circuit having a single crystal cell and a single gate memory cell. [Main component symbol description] 15 8 η-type well region 12 ρ-type well region 16 isolation oxide 20 gate oxide 24 polysilicon 20 28 tungsten oxide 32, 33, 36, 37, 40, 41 gate region 44, 45 N-doped regions 48, 49, 52, 53 additional doped regions 58 oxide layers 25 60, 61, 62, 63 spacers 64, 66 source regions 65, 67 drain regions 26 200945562 68 the source And the opposite doping type (P+) region of the drain region 72 single gate (floating gate) 76 N-well doping window 80 > 81, 82 oxide definition window 5 84 N-doped window 88 P doping Miscellaneous window 92 N doping window 96 > 97 N+ implant window P 100 P+ implant window 10 3000 memory array 3001 column decoder 3003 row decoder 3006 block 3007 data bus 15 3008 bias arrangement supply voltage 3009 bias arrangement State mechanism 3011 data input line ❹ 3015 data output line 20 3050 integrated circuit 27

Claims (1)

200945562 十、申請專利範圍 1. 一種非揮發記憶積體電路，包含： 一半導體基板； 一非揮發記錄置在該半導體基板上，包括： 5 一電晶體在該半導體基板上並由一閘極區域及具 有第摻雜類型之一源極區域和一沒極區域所控制， 包含： ❹ 複數個具有該第一摻雜類型之第一摻雜區 域，該第一摻雜區域位於該閘極區域之兩側，而該 10 第一摻雜區域覆蓋於該源極區域及該汲極區域之 上； 複數個具有與該第一摻雜類型相反的第二摻 雜類型之第二摻雜區域，該第二摻雜區域位於該閘 極區域之兩側，而該第二摻雜區域覆蓋於該源極區 15 域及該汲極區域之上； 複數個具有該第一摻雜類型之第三摻雜區 ❹ 域，該第三摻雜區域位於該閘極區域之兩側，而該 第二摻雜區域覆蓋於該源極區域及該汲極區域之 上； 20 複數個具有該第一摻雜類型之第四摻雜區 域，該第四摻雜區域位於該閘極區域之兩侧，而該 第四摻雜區域定義該源極區域及該汲極區域； 一電谷器在該半導體基板之上並由一閘極區域所 控制； 25 一共享浮動閘極連接該電晶體的該閘極區域及該 電容的該閘極區域； 一井區在該基板之上並具有該第二摻雜類型，其中 28 3. φ 10 15200945562 X. Patent application scope 1. A non-volatile memory integrated circuit comprising: a semiconductor substrate; a non-volatile recording disposed on the semiconductor substrate, comprising: 5 a transistor on the semiconductor substrate and a gate region And controlling the source region and the gate region of the first doping type, comprising: ❹ a plurality of first doped regions having the first doping type, the first doped region being located in the gate region On both sides, the 10 first doped region covers the source region and the drain region; a plurality of second doped regions having a second doping type opposite to the first doping type, a second doped region is located on both sides of the gate region, and the second doped region covers the source region 15 region and the drain region; a plurality of third dopings having the first doping type a third doped region is located on both sides of the gate region, and the second doped region covers the source region and the drain region; 20 plurality of having the first doping Type fourth doping a region, the fourth doped region is located on both sides of the gate region, and the fourth doped region defines the source region and the drain region; a gate is over the semiconductor substrate and is gated Controlled by the region; 25 a shared floating gate connecting the gate region of the transistor and the gate region of the capacitor; a well region above the substrate and having the second doping type, wherein 28 3. φ 10 15 20 200945562 該電晶體及該電容器係在該井區之上；以及 控制電路辆接至該非揮發記憶裝置，該控制電路施加記 憶體之操作調整偏屢至該非揮發記憶裝置。 2.如申請專利範圍第1項所述之積體電路，更包含： 一磊晶層在該基板之上並具有該第二掺雜類型，其中該 電晶體及該電容器係在該磊晶層之上。 如申請專利範圍第1項所述之積體電路，更包含： 物部物料於該電晶體之制極區域，而該間隔 料—雜E域、邮二獅㈣以及該第 包含其中該電容器 5· 種非揮發記憶積體電路，包含： 一半導體基板； 單j式化非揮發記憶裝置在該半導體基板上，包括： -第rff體在該半導縣板上並由—閘極區域及具有 含：A類型之一源極區域和一汲極區域所控制，包 域，該具有該第一摻雜類型之第-摻雜區 第—二—摻雜區域位於該閘極區域之兩側，而診 上雜區域覆蓋於該源極區域及該汲極區域= 複數個具有與該第一摻雜類型相反的第二換 29 25 200945562 摻雜區域’該第二摻雜區域位於該間 域二:i域::第二摻雜區域覆蓋於該源極區 複數個具有該第一摻雜類型之第三摻 域’該第三摻雜區域位於該閘極區域之兩側，而： =二摻雜區域覆蓋於該雜區域及概極區域之 φ 10 制； 複數個具有該第一摻雜類型之第四摻雜區 域，該第四摻雜區域位於該閘極區域之兩側，而該 第四摻雜區域定義該源極區域及該汲極區域； 一電容器在該半導體基板之上並由一閘極區域所控 一共享浮動閘極連接該電晶體的該閘極區域及該電 容的該閘極區域；以及 15 ❿ 20 控制電路耗接至該非揮發記憶裝置，該控制電路施加記 憶體之操作調整偏壓至該非揮發記憶裝置。 6.如申請專利範圍第5項所述之積體電路，其中該基板具 有該第二摻雜類型。 7.如申請專利範圍第5項所述之積體電路，更包含： 一遙晶層在該基板之上並具有該第二摻雜類型，其中該 電晶體係在該磊晶層之上。 25 8·如申請專利範圍第5項所述之積體電路，更包含： 一井區在該基板之上並具有該第二摻雜類型，其中該電 晶體係在該井區之上。 200945562 9. 如申請專利範圍第5項所述之積體電路，更包含： 一磊晶層在該基板之上並具有該第二摻雜類型，其中該 電容器係在該蟲晶層之上。 5 10. 如申請專利範圍第5項所述之積體電路，更包含： 一井區在該基板之上並具有該第一掺雜類型，其中該電 晶體係在該井區之上。 ❹ 10 11.如申請專利範圍第5項所述之積體電路，更包含： 一井區在該基板之上並具有該第二摻雜類型，其中該電 容器係在該井區之上。 12.如申請專利範圍第5項所述之積體電路，更包含： 15 一井區在該基板之上並具有該第二摻雜類型，其中該電 晶體及該電容器係在該井區之上。 〇 13.如申請專利範圍第5項所述之積體電路，更包含： 一磊晶層在該基板之上並具有該第二掺雜類型，其中該 20 電晶體係在該蠢晶層之上，以及 一井區在該磊晶層之上並具有該第二摻雜類型，其中該 電晶體係在該井區之上。 14.如申請專利範圍第5項所述之積體電路，更包含： 25 一磊晶層在該基板之上並具有該第二摻雜類型，其中該 電晶體係在該蠢晶層之上，以及 一井區在該磊晶層之上並具有該第一摻雜類型，其中該 31 200945562 電晶體係在該井區之上。 如申請專利範圍第5項所述之積體電路，更包含： 一第一井區在該基板之上並具有該第一摻雜類 5 該電容器係在該第一井區之上；以及 土 ’其中 一第二井區在該基板之上並具有該第二摻雜_型， 該電晶體係在該第二井區之上。 一中 © 16.如申請專利範圍第5項所述之積體電路，更包含： 10 一磊晶層在該基板之上並具有該第二摻雜類型，其中= 電晶體係在該磊晶層之上；以及 該 一第一井區在該磊晶層之上並具有該第一摻雜類型， 中該電容器係在該第一井區之上； 、 一第二井區在該蠢晶層之上並具有該第一摻雜類型， 15 中該電晶體係在該第二井區之上。 、 17.如申請專利範圍第5項所述之積體電路，更包含： 20 .推雜區域之上。 複數個間隔物鄰近於該電晶體之該閘極區域，而兮 物部分地覆蓋於該第一摻雜區域、該第二摻雜區域以=二= 如申請專利範圍第5項所述之積體電路，其中該電容。 包含複數個接點來控制該電容器之一主體電壓。、μ '今器 19· 一種非揮發記憶積體電路，包含： 一半導體基板； 複數個非揮發記憶裝置在該半導體基板上，每一包括. 32 200945562 一電晶體在該半導體基板上並由一閘極區域及具有 一第一摻雜類型之一源極區域和一汲極區域所控制/，'包 含： 複數個具有該第一摻雜類型之第一摻雜區 5 域，該第一摻雜區域位於該閘極區域之兩側，而該 第一摻雜區域覆蓋於該源極區域及該汲極區域之 上； ~ 複數個具有與該第一摻雜類型相反的第二摻 ❹ 雜類型之第二摻雜區域，該第二摻雜區域位於該閘 10 極區域之兩側，而該第二摻雜區域覆蓋於該源極區 域及該汲極區域之上； 複數個具有該第一摻雜類型之第三摻雜區 域，該第三摻雜區域位於該閘極區域之兩側，而該 第二摻雜區域覆蓋於該源極區域及該汲極區域之 15 上； 複數個具有該第一摻雜類型之第四摻雜區 域，該第四摻雜區域位於該閘極區域之兩侧，而該 & 第四摻雜區域定義該源極區域及該汲極區域； 一電容器在該半導體基板之上並由一閘極區域所控 20 制； 一共享浮動閘極連接該電晶體的該閘極區域及該電 容的該閘極區域； 井區在该基板之上並具有該第二摻雜類型，其中該複 數個非揮發⑽裝置之至少—個非揮發記憶裝置的該電晶體 25 及該電谷器係在該井區之上；以及 控制電路耦接至該非揮發記憶裝置，該控制電路施加記 憶體之操作調整偏壓至該非揮發記憶裝置。 33 200945562 2〇. 一種非揮發記憶積體電路，包含： 一半導體基板； 個單次程式化_發記錄置在該半㈣基板上， 5 2* 括： -電晶體在該半導體基板上並由—間極區域及 -第-摻雜類型之一源極區域和一汲極區域所控制 含： 。 ❹ 、複數個具有該第一摻雜類型之第一摻雜區 10 域，該第一摻雜區域位於該閘極區域之兩側，而該 第一摻雜區域覆蓋於該源極區域及該汲極區域之 上， 複數個具有與該第一摻雜類型相反的第二摻 雜類型之第二摻雜區域，該第二摻雜區域位於該閑 15 ㈣域之_彳’祕第二摻舰域覆蓋於該源極區 域及該汲極區域之上； 複^個具有該第一摻雜類型之第三摻雜區 φ 域，該第二摻雜區域位於該閘極區域之兩側，而該 第二摻雜區域覆蓋於該源極區域及該汲極區域之 20 上’ 複數個具有該第一摻雜類型之第四摻雜區 域，該第四摻雜區域位於該閘極區域之兩側，而該 第四摻雜區域定義該源極區域及該汲極區域； -電容器在該半導體基板之上並由__閘極區域所控 25 制， -共享浮動閉極連接該電晶體的該閘㈣域及該電 容的該閘極區域；以及 34 200945562 憶體 控制電路祕至_揮發記憶裝置 之操作調整麟魏轉發記憶裝置 ’該控制電路施加記 21.— 10 種製造-轉發記憶積體電路之方法，： 提供一半導體基板； 提供-非揮發記憶裝置在料導縣板上包括：域及晶體在該半導體基板上並由-第一閘極區 =具有-第-摻雜類型之—源極區域和—汲極區域所j，以及提供—電晶體在該半導體基板上並由一第二 閘極區域所控制，包含·· 1520 200945562 The transistor and the capacitor are above the well region; and the control circuit is coupled to the non-volatile memory device, the control circuit applying an operational adjustment of the memory to the non-volatile memory device. 2. The integrated circuit of claim 1, further comprising: an epitaxial layer over the substrate and having the second doping type, wherein the transistor and the capacitor are attached to the epitaxial layer Above. The integrated circuit of claim 1, further comprising: the material of the object in the pole region of the transistor, and the spacer material - the impurity E domain, the second lion (four), and the capacitor including the capacitor 5 A non-volatile memory integrated circuit comprising: a semiconductor substrate; a single j-shaped non-volatile memory device on the semiconductor substrate, comprising: - a rff body on the semiconducting plate and by a gate region and having The method includes: a source region of one type A and a drain region controlled by a drain region, wherein the first-doped region of the first doping region is located on two sides of the gate region, And the impurity region covers the source region and the drain region=the plurality of second regions having opposite to the first doping type 29 25 200945562 doped region 'the second doped region is located in the inter-domain : i domain:: the second doped region covers the source region, and the third doped region having the first doping type is located on both sides of the gate region, and: = 2 The doped region covers the φ 10 system of the impurity region and the region of the region a plurality of fourth doped regions having the first doping type, the fourth doped region is located on both sides of the gate region, and the fourth doped region defines the source region and the drain region; a capacitor on the semiconductor substrate and controlled by a gate region, a shared floating gate connected to the gate region of the transistor and the gate region of the capacitor; and 15 ❿ 20 control circuit consuming the non-volatile memory And a device that applies an operational adjustment bias of the memory to the non-volatile memory device. 6. The integrated circuit of claim 5, wherein the substrate has the second doping type. 7. The integrated circuit of claim 5, further comprising: a telecrystalline layer on the substrate and having the second doping type, wherein the electro-crystalline system is above the epitaxial layer. The integrated circuit of claim 5, further comprising: a well region above the substrate and having the second doping type, wherein the electro-crystalline system is above the well region. The integrated circuit of claim 5, further comprising: an epitaxial layer over the substrate and having the second doping type, wherein the capacitor is over the germane layer. 5. The integrated circuit of claim 5, further comprising: a well region above the substrate and having the first doping type, wherein the crystal system is above the well region. 11. The integrated circuit of claim 5, further comprising: a well region above the substrate and having the second doping type, wherein the capacitor is above the well region. 12. The integrated circuit of claim 5, further comprising: 15 a well region above the substrate and having the second doping type, wherein the transistor and the capacitor are in the well region on. The integrated circuit of claim 5, further comprising: an epitaxial layer on the substrate and having the second doping type, wherein the 20-electromorphic system is in the doped layer And a well region above the epitaxial layer and having the second doping type, wherein the electro-crystalline system is above the well region. 14. The integrated circuit of claim 5, further comprising: 25 an epitaxial layer over the substrate and having the second doping type, wherein the electromorphic system is above the stupid layer And a well region above the epitaxial layer and having the first doping type, wherein the 31 200945562 electro-crystalline system is above the well region. The integrated circuit of claim 5, further comprising: a first well region above the substrate and having the first doping class 5, the capacitor being above the first well region; and soil 'One of the second well regions is above the substrate and has the second doping type, and the electro-crystalline system is above the second well region. 16. The integrated circuit of claim 5, further comprising: 10 an epitaxial layer over the substrate and having the second doping type, wherein the = epitaxial system is in the epitaxial layer Above the layer; and the first well region is above the epitaxial layer and has the first doping type, wherein the capacitor is above the first well region; and a second well region is in the stupid crystal Above the layer and having the first doping type, the electro-crystalline system is above the second well region. 17. The integrated circuit as described in claim 5, further comprising: 20 above the push area. a plurality of spacers adjacent to the gate region of the transistor, and the artifact partially covering the first doped region and the second doped region to === as described in claim 5 Body circuit, where the capacitor. A plurality of contacts are included to control the body voltage of one of the capacitors. a non-volatile memory integrated circuit comprising: a semiconductor substrate; a plurality of non-volatile memory devices on the semiconductor substrate, each comprising: 32 200945562 a transistor on the semiconductor substrate and comprising a gate region and a source region and a drain region controlled by one of the first doping types, and comprising: a plurality of first doped regions 5 having the first doping type, the first doping The impurity region is located on both sides of the gate region, and the first doped region covers the source region and the drain region; and the plurality of second doped impurities having opposite to the first doping type a second doped region of the type, the second doped region is located on both sides of the gate 10 region, and the second doped region covers the source region and the drain region; a third doped region of a doping type, the third doped region is located on both sides of the gate region, and the second doped region covers the source region and the drain region 15; Having the first doping type a fourth doped region, the fourth doped region is located on both sides of the gate region, and the & fourth doped region defines the source region and the drain region; a capacitor is over the semiconductor substrate and a gate region controlled by a gate region; a shared floating gate connected to the gate region of the transistor and the gate region of the capacitor; the well region being above the substrate and having the second doping type, wherein The transistor 25 of the at least one non-volatile memory device of the plurality of non-volatile (10) devices and the electric valley device are above the well region; and the control circuit is coupled to the non-volatile memory device, the control circuit applies the memory The operation adjusts the bias voltage to the non-volatile memory device. 33 200945562 2〇. A non-volatile memory integrated circuit comprising: a semiconductor substrate; a single stylized _ record placed on the half (four) substrate, 5 2* including: - a transistor on the semiconductor substrate and - The interpole region and one of the -th doping type source region and one drain region are controlled by: ❹ a plurality of first doped regions 10 having the first doping type, the first doped regions are located on opposite sides of the gate region, and the first doped regions cover the source regions and the Above the drain region, a plurality of second doped regions having a second doping type opposite to the first doping type, the second doped regions being located in the free 15 (four) domain a vessel region overlying the source region and the drain region; a third doped region φ domain having the first doping type, the second doped region being located on both sides of the gate region The second doped region covers the source region and the drain region 20 of the plurality of fourth doped regions having the first doping type, and the fourth doped region is located in the gate region. On both sides, the fourth doped region defines the source region and the drain region; - a capacitor is over the semiconductor substrate and controlled by a __ gate region, - a shared floating closed junction is connected to the transistor The gate (four) domain and the gate region of the capacitor; and 34 200945562 The control circuit secrets to the operation of the volatile memory device to adjust the Lin Wei forwarding memory device. The control circuit applies the method of 21 - 10 manufacturing-forwarding the memory integrated circuit, providing a semiconductor substrate; providing a non-volatile memory device The material guide plate includes: a domain and a crystal on the semiconductor substrate and consisting of - a first gate region = a - doping type - a source region and a - a drain region, and providing a transistor The semiconductor substrate is controlled by a second gate region, including 15 20 ^提供複數個具有該第一摻雜類型之第一摻雜 區域，該第-摻雜區域位於該閘極區域之兩側，而 該第一摻雜區域覆蓋於該源極區域及該汲極區域之 Jl·, 一 提供複數個具有與該第一摻雜類型相反的第 y摻雜類型之第二摻雜區域，該第二摻雜區域位於 該閘極區域之兩側，而該第二摻雜區域覆蓋於該源 極區域及該汲極區域之上； 。提供複數個具有該第一摻雜類型之第三掺雜 區域，該第三摻雜區域位於該閘極區域之兩側，而 该第二摻雜區域覆蓋於該源極區域及該汲極區域之 上； 提供複數個具有該第一掺雜類型之第四摻雜 區域’該第四摻雜區域位於該閘極區域之兩側，而 該第四摻雜區域定義該源極區域及該汲極區域； 提供一共享浮動閘極連接該電晶體的該閘極區域 及該電容的該閘極區域； 35 25 200945562 兮該基板之上並具有該第二摻_型，其中 該電ΒΘ體及該電容器係在該井區之上；以及 Τ 提供控制轉祕㈣轉發記憶 加記憶體之操作· 至該非揮發錢裝置该㈣電路施 22. —種製造一非揮發記憶積體電路之方 提供一半導體基板； 匕3 . ❹ 10 提供：非揮發記憶裝置在該半導縣板上，包括·· 祕月ίΓ冑晶體在該半導體基板上並由—第一閘極區 2具有-第—摻雜類型之—區域之—源極區域和一沒 ΐ區Ϊ所控制’以及提供—電晶體在該半導體基板上並 由一第一閘極區域所控制，包含： 。提供複數個具有該第一摻雜類型之第一摻雜 區域，該第一摻雜區域位於該閘極區域之兩側，而 該第一摻雜區域覆蓋於該源極區域及該汲極區域之 上； ❹ 20 提供複數個具有與該第一摻雜類型相反的第 二摻雜類型之第二摻雜區域，該第二摻雜區域位於 該閘極區域之兩側，而該第二摻雜區域覆蓋於該源 極區域及該汲極區域之上； 提供複數個具有該第一摻雜類型之第三摻雜 區域’該第三摻雜區域位於該閘極區域之兩側，而 該第三摻雜區域覆蓋於該源極區域及該汲極區域之 上； 提供複數個具有該第一摻雜類型之第四摻雜 區域’該第四摻雜區域位於該閘極區域之兩側，而 該第四摻雜區域定義該源極區域及該汲極區域； 36 25 20094556220^ providing a plurality of first doped regions having the first doping type, the first doped regions are located on opposite sides of the gate region, and the first doped region covers the source region and the germanium a plurality of second doped regions having a y-doping type opposite to the first doping type, the second doped region being located on both sides of the gate region, and the first region a second doped region covers the source region and the drain region; Providing a plurality of third doped regions having the first doping type, the third doped regions are located on opposite sides of the gate region, and the second doped region covers the source region and the drain region Providing a plurality of fourth doped regions having the first doping type, the fourth doped region is located on both sides of the gate region, and the fourth doped region defines the source region and the a region of the gate region of the capacitor and a gate region of the capacitor; 35 25 200945562 之上 above the substrate and having the second doped type, wherein the electrode body and The capacitor is on the well area; and Τ provides control transfer (4) forwarding memory plus memory operation · to the non-volatile money device (4) circuit application 22 - a non-volatile memory integrated circuit is provided Semiconductor substrate; 匕3. ❹ 10 provides: a non-volatile memory device on the semi-conductor plate, including ··········································· Type - area - Region and a region not ΐ controlled Ϊ 'and provides - transistors and controlled by a first gate region in the semiconductor substrate, comprising: Providing a plurality of first doped regions having the first doping type, the first doped regions are located on opposite sides of the gate region, and the first doped region covers the source region and the drain region ❹20 providing a plurality of second doped regions having a second doping type opposite to the first doping type, the second doped regions being located on both sides of the gate region, and the second doping a impurity region covering the source region and the drain region; providing a plurality of third doped regions having the first doping type, the third doped region being located on both sides of the gate region, and the a third doped region overlying the source region and the drain region; a plurality of fourth doped regions having the first doping type are provided. The fourth doped region is located on both sides of the gate region And the fourth doped region defines the source region and the drain region; 36 25 200945562 提供一共享浮動閘極連接該電晶體的該閘極區 域及該電容的該閘極區域；以及 提供控制電路耦接至該非揮發記憶裝置，該控制電路施 加記憶體之操作調整偏壓至該非揮發記憶裝置。 37Providing a shared floating gate connected to the gate region of the transistor and the gate region of the capacitor; and providing a control circuit coupled to the non-volatile memory device, the control circuit applying an operation adjustment bias of the memory to the non-volatile Memory device. 37
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