200945191 九、發明說明： 【發明所屬之技術領域】 訊功 匕本發明財_處㈣，雜—種具有㈣提供益線通 此之無線模組的處理器單元以及其相關方法。 【先前技術】 ❹ ，雷，為了符合消費者對於無線通訊的需求，已有越來越 二電子裝置附加有無線通訊的能力…般而言，如第丨圖所示， 最典型的方式是藉由將—電子裝置觸之一處理器卿_ 一個 無線週邊褒置（WirdeSSperipheral) 12〇，來滿足供給電子裝置刚 相關之無線通訊功能(wirelessflmctions)的需求，除此之外，電子 裝置100内更包含有一記憶體13〇。而前述將電子袭置麵接無線週 邊裝置的設計方式’即可滿足一般消費大眾對電子裝置1〇〇大部 分常見的無線應用需求。 然而’習知技術在電子裝置之處理器旁搞接無線週邊裝置的 作法’常常會導致電子裝置的處㈣11G在運作上的困擾， 例如，可能會出現高優先權的工作中斷處理器11〇運作的狀況產 生。 舉例來說，在習知技術中，當一個新系統在除錯(debugging) 或研發的過程中’通常會需要使用到一嵌入式電路模擬器 (In_arcmt Emulator，ICE)，此一嵌入式電路模擬器會透過一事先定 200945191 義好的介面(例如JTAG介面和增強型JTAG(enhanced JTAG)介面) 來達到與此m纟納處理器連結的目的。因此，在實作中， 將铯些除錯工具實體地連結(physicalcontact)到處理器110是不可 避免的再加上這些除錯工具須經由接線（connectingcable)來與 處理器相連結’因此，必須要先取得正確的接線以及適宜之訊號 電壓準位之後，才能開始整個酬滅的除錯運作。 ❹ 然而這些手續不僅繁雜而且造成使用者的不便，因此，便需 要提出一個嶄新的機制以解決前述之問題。 【發明内容】 因此本發明的目的之—即提供了 —種其内包含有無線通訊模 組的處理器’使得處理器得以直接控制該無線模組。 根據本發明之第—實施例，其係揭露—種處理器單元，而在 ❿處理器單㈣包含有—處理龍心以及-直懸接至該處理器核 、之無雜組，其巾該無線模組係㈣提供該處理器核心無線通 根據本發明之第二實施例，其另揭露一種多重處理器 (^oeessG⑽統。該乡重處理器系統包含有—第—處理器單 界一 1且^理叫似及一無線連結(―Unk)。該第一處理 。早7〇〜、-第_處理核^，以及—個直接触於該第一處理 200945191 器核心之第-無線模組，其中該第—無線模組係用以提供該第一 處理器核心無線通訊之運作功能。至於該第二處理器單元7其係 具有-第二處理器核d及-個直_接至該第二處理器核心 之第二無線模組’其中該第二無線模組伽以提供該第二處理二 核心無線通訊之運作魏。該鱗連結係介於該$—無、線模組:乂 及該第二無線模組之間，且該第一處理器係經由該無線連結與該 第二處理器單元彼此交互聯繫。 、Λ ❹ Φ 根據本發明之第三實施例，其係揭露—種提供—處理 無:觀功能之方法，而此方法包含有:提供-處理器核心，以 及將-個無線模組直接墟至該處理器核心。 [實施方式】 在本專利說明書及後續的申請專利範圍當 =來指稱特定的元件。所屬領㈣有通常知 :理:」硬體製造商可能會用不同的名詞來射同一個； :為”明書及後續的申請專利範圍並不以名稱的差異； 刀70件的方式，而是以元件在功能上的差異來作Α 區分的準則D在搞铉始 、來作為 「包含Μ 續的請求項Μ所提及的 定:」。」:外^ 電氣連接手段。：：：包π直接及間接的 右文中描述一第一裝置耦接於—第 200945191 二裝置，則代表該第一裝置可直接電氣連接於該第二裝 置’或透過其他裝置或連接手段間接地電氣連接至該第二 裝置。 為了解決前述之問題以及限制，本發明的目的之一即提供了 具有無線通訊功能之處理器，且該無線通訊功能係直接受控於處 理器。 請參閱第2圖，第2關顯示根據本發明具有無線處理模組 之處理器單元200之一實施例的功能方塊示意圖。處理器單元2〇〇 係用以執行一電子系統所發出之命令，且於處理器單元 朋内包含有-處理器核心210、一無線模組22〇、一功率放大器 (power amplifier)225、-射頻天線阳⑽加加阳？、—快取(cde) 記憶體230以及-區域記憶體⑽al m咖_5。除此之外，在處 理器核心2職更包含有複數個暫存器(register)2i5。 ♦在本實施例中，處理器核心搞接至無線模組220,而滅 椒組220另耦接至功率放大器225。功率放大器225職接至綱 ^ 227。處理器核心以及無線模組22〇分別經由位址/命令 (akddr/e°_n轉輪線232來_至快取記憶體现。除此之 外’處理器核心210以及無線模組_分別經由資料傳輸線_ 處減心21〇内之暫存器215則包含有複數個控制暫存器 200945191 (.、1ΓΓ)狀態暫存器(statusregister)以及資料暫存器(data 制暫存器係用以設_模_ 的、=牛例來5兒’利用控制暫存器來致能或關閉無線模組 的運作。至於狀態暫存器，其内暫存了一些無線模組 ==存_所暫存中的某些特定資訊與儲存於控制暫 予器内的从貝料相結合時，將會觸發處理器核心 210的中斷事 (論卿event)’或者，亦可能導致其他將資料由快取記憶體230 Ο Ο 或區域讀、體235内移進或移出的動作發生。至於資料暫存器， 其用以儲存由無線模組22〇所接收到的資料及/或由無線模組挪 所傳送出㈣資料。由於第2财所示的其他元件(例如記憶體管 理早疋(MMU)、直接記憶體存取單元(DMA)、匯流排介面單元 (BIU)、JTAG/ICE模擬電路以及前端匯流排_)等等)之麵接方式 以及相關運作並非本發明的重點，所以為了簡潔起見，在這裡並 不--加以詳細說明。 在這裡請注意到’在本發明之一實施例中，所有與無線模組 220相關的元件亦可設置於處理器單元之中，也就是說，包含 有無線模組220、神放大器225、天線227在内的整個無線^ 皆可包含於處理器單元200的晶片之内。除此之外，在本發明之 另實％例中，無線系統可以有具一個域一個以上的元件外接於 處理器單it 2GG，蚁其祕關係仍與第2圖中顯示的方塊圖相、 同。舉例來說’在本發明之又一實施例中，天線227為一線型天 線(wire antenna)，其設置於整個處理器單元2〇〇之外，而非如前述 200945191 . 實施例中位於晶片内的天線(chip antenna)。除此之外，在本發明之 另一實施例中’天線227以及功率放大器225皆為處理器單元2〇〇 之封裝的外部元件。除了以上所舉例的元件配置方式之外，亦可 有其他符合本發明精神且符合設計者需求之硬體配置方式，且這 些相關設計變化皆落於本發明的範疇之中。 在本發明中，無線模組220賦予位於處理器單元200 (譬如說 ❹-中央處理器）内的處理器核心21〇可與另一處理器核心21〇或 複數個處理器核心210直接進行無線通訊(directwirdess communication)的功能。在第3圖所示之一實施例中，處理器核心 329以及處理器核心339兩者經由了無線連結323以一主從裝置 (master-slave)的架構來相連接，其中處理器核心329為裝置32〇内 處理器單元325之處理器核心，而處理器核心339為裝置33〇内 處理器單元335之處理器核心。 ❹如第3圖所示，在另一實施例中，處理器核心329、339、349、 359、369'379 經由無線連結 348、354、356、358、387 以一多重 處理器網路(multi-processornetwork)的架構來相連結，在此一實施 例中，處理器核心329、339、349、359、369、379分別為裝置32〇、 330、340、350、360、370 内處理器單元 325、335、345、奶、 365、375之中的處理器核心，此外，這些連結中有—些係透過通 訊網絡380而以無線方式所建構。在這裡請注意到，在通訊網絡 ；380之中，亦可使用橋接器及/或其他巾介裝置來達到相同的目 12 200945191 的，而這些_設計變㈣符合本發明之精神 理器單元325、335、345、355、365、375係操作於_主= 模式下’也就是說，在此多重處理器系統31〇内， 、置的 器單元(如處單元375齡演主控處理_衫個處理 ^處理器單元(如處理器單元345、355以及365)則作為從^其理餘 ❹ 時參照第2圖以及第4圖，第4圖所示為第2 __ 理器核心2U)之無線模組22〇之間建立無線通訊的流程圖 意到，倘若實質上可達到相_結果，並不_定需㈣昭第^ 所示之流程中的步驟順序來依序進行。本流程包含有以下步驟： 步驟410:初始化。 步驟420:搜尋新裝置。 步驟430:認證。 步驟440:將資料以及命令交換至資料暫存器。 步驟450:中斷處理器核心。 步驟460:確認並執行資料暫存器内的無線通訊命令。 步驟470:完成無線通訊命令。 步驟480:回復執行(resume)處理器核心的正常操作。 在此流程中，首先在步驟410,先對需要利用到的處理器核心 執行初始化的動作。在步驟420 ’ 一無線裝置會開始搜尋網域内另 13 200945191 南卜 '固無線裝置以建立起通訊連結。在步驟中，當建立兩個 处理益間的無線連結之後，第—個處理器核心以及第二個處理器 核W皮此之間開始執行機的動作，祕認證錢建立無線通訊 通道的概念為熟習本項技藝之人士所知，在此便不加以贅述。在 步驟44〇，—旦無線連結建立並完成裝置間的認證之後，無線模組 1 «接收封包資步斗(packet)並且將這些資料放置於資料暫存器之 中’接者’並通知處理器核心依據控制暫存器内的設定來運作。 ❹當封包的數目眾多的時候’無線模組可以經由直接記憶體存取 (d贈memory aeeess)_助來將這些封包由賴暫存器中移至區 域記憶體中。在這裡，假設在步驟彻中，第一處理器核心扮演 了主控處理ϋ核心的角色，而第二處理器核心為—從屬處理器核 心的角色’耻欲由姻處驾彳細職行的命令雜步驟· 中經由無線傳輸的方絲傳送，朗這些命令所指派的工作完成 並且沒有其他的命令需要被執行為止（步驟47())。最後，在步驟 480中’當這些命令完成之後’第一處理器核心以及第二處理 心即可回錄行原柄正粒作。在核程騎提㈣方財/ 第-處理器核心210 (亦即主控處理器核心）會中斷一第二處理器 核：(從屬處理If核心)的運作，並指示從顧理馳心根據主控處 理器核心的要求來執行某些特定類型的命令。 在本發明中，無線模組220會在複數個處理器核心之間傳 -組特定指令巾之-鑛―個以上_令，而這些指令係包含 有：用來對處理器核心210執行某些特定的執行控制的中斷指令、 14 200945191 • 為了確保無_誠及軌財之安全的加密及解密指令、用來 於處理器核心則及其他週邊裝置的開發過程中對處理器核心 210進行逐步命令執行(step by _ _論n)純行其他功能的除 錯(debugging)指令(譬如說，設定及重設處理器的中斷點 、 (breakpoint))、對資料封包進行處理的封裝(packing)以及解封裝 (unpacking)^令錢賴提升資㈣輸鱗的麵及賴縮指令。 ❹ 在績技術中’處理器核心般而言會命令—無線週邊 裝置來傳送或者接收資料，並且在必要時會根據處理器單元細 的而求而巾斷其本絲作，然而這樣的架構必須在資料開始傳送 及接收之别，先提供恰當之裝置驅動程式給無線週邊裝置以及其 他並伽輸入輸出介面。本發明藉由將無線模組挪直接雛至 器杉。210’以使來自於無線模、组22〇的資料通訊中斷佔有最 高的執行優先權，因此會被立即執行。舉例來說，當—個處理器 p偵測到另-處㈣單元正被病毒攻擊或被其他惡意的程 式碼所影響時’處理器單元·將會經由無線傳輸的方式接收到 「個中斷請求以及相關命令，來立即中斷處理器單元的運作， ，而避免造成更多損害以及影響。除此之外，舉例來說，另一個 元亦可傳送一個修補軟體或程式給受到病毒攻擊的處理 些惡意的攻擊程式。在此之前，相_知技術 攻擊程it，法立即取回電子裝置的控制權，而且在惡意的 式取传了處職單元駐導微，極可料致這些由益線 核、、且接收崎有情請求均被忽略。 15 200945191 而本發明中此一實施例的另一個範例即是：處理器單元200 本身所處之電子裝置的安全遠端控制(secure rem〇te consol)功能， 在個智慧型安全網格網路(intelligent security grid network)中，當 一個警示感測器無法運作時，其他與此警示感測器相連結之感測 器將會收到一個警示訊號而得知異常狀況的發生。在另一範例 中，執法及緊急處理交通工具（例如警車、救護車、消防車等等） 會配置包含本發明處理器單元200的裝置，因此，這些交通工具 ❹ 便可中斷交通號誌的正常運作以便於處理人員運輸與處理這些緊 急事件。 在本發明之一實施例中，直接連結至處理器核心21〇的無線 模組220更包含有加密及解密指令，以確保無線通訊以及通訊協 定的安全’而這些實施於處理器核心之間的加密操作以及解密操 作可以確保處理器單元和處理器單元所在之裝置間的通訊安全。 ® 除此之外，在另一實施例中，在個別處理器核心21〇中係包 含有-獨特朗碼（u_e identifier·) ’骑行職與驗證，識別碼 係於製造時便加以設定完成(藉由使用像雷射修整細r出刪㈣ 的單次燒錄方法來實現）。此識別碼既然是在製造過程中即設定完 成，因此在完成設定之後，識別碼的設定便無法被複製或更動， 藉此可以提歧個祕的安全性。本發明的另—錄點為：在處 理器核心2H)以及其相對應之無線模组22〇之間的通訊内容不會 被攔截竊取，然而，對於先前技術而言，f知處理器核心以及習 200945191 - 知無線模組兩者間的通訊内容極容易被攔戴。 本發明實施例的另-種應用係於處理器核心2_及其他週 邊裝置_發過程中使齡錯齡，倘若設計所需，在處理器核 心210的正讀作肢下亦可料除錯指令的運作。這些除錯指 令的使用可允許除錯裝置（debugger)或者編譯裝置(c〇mpiier device)施加執行指令與其他功能於處理器核心2i()中，以同時監 ❹測並且修正處理器核心㈣的運作。舉例來說，經由—情點暫 存器（breakpoint呦伽卵抑或多個中斷點暫存器來設定/重設 處理器的執行中斷點，以暫停_處理器核心210的操作，並藉 此控制14些除錯指令的執行。在—實施例中，處理器核心別内 載有-監測程式來在處理器核心則運作時記錄所有關於處理器 核心的即物fl，並且料除錯錢錢行逐步（吟by·卿)的 ❹ 和安全性 本發明更經由無線模組22〇啟用更多其他功能，例如說，提 供了封裝及解縣齡錢驗賴縮指令的魏，這些指令可 應祕資料傳輸、資料封包處理以及提供了更佳的資料傳輸鱗 經由前_鑛_可得知，本發騎提供之財無線模組 心^少包含有幾個優點：可更加便利地對—處理器核 Μ無線方歧行_與_、獨發财最高執行優先權財 17 200945191 -斷來取得處理馳心之控制權，以及可提供處㈣核心之間—個 安全性高的通訊傳輸。此外，更由於將無線模組以 整合於同-個晶片之中，因而具有較低的製造成本，此外:藉由 本發明的實作可翻較小晶以寸和使用較少的電路版面積。 。。請注意到，雖然在本篇說明書中係以運算裝置中的中央處理 器(cpu)作為實施你j ’然而，將無線模組麵接到中央處理器僅作為 ❹範例=明之用’而非本發明的限制條件之一。綜上所述，本發明 所揭露之方法可朗咐知技射擁有無線猶裝置的處理器翠 元，而這些相關設計變化均符合本發明之精神，聽於本發明之 範疇。 以上所述僅為本發明之較佳實施例’凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 ® 【圖式簡單說明】 第1圖為f知技射具有無線通訊魏之電子裝置的示意圖。 第2圖為本發明具有無線模組之處理器單元之—實施例的功能方 塊示意圖。 第3圖為本發明兩個無線通訊組態的之實施例的示意圖 第4圖為本發明建立無線模組之間無線通訊之一 實施例的流程圖。 【主要元件符號說明】 18 200945191 電子裝置 • 100、320、330、340、350、360、370 110 處理器 120 無線裝置 130 記憶體 處理器單元 處理器核心 200、325、335、345、355、365、375 210、329、339、349、359、369、379 215 暫存器 φ 220 無線模組 225 功率放大器 230 快取記憶體 235 區域記憶體 300、310多重處理器系統200945191 IX. Description of the invention: [Technical field to which the invention pertains] 功 匕 发明 发明 ( ( ( 四 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( [Prior Art] ❹, 雷, in order to meet the consumer's demand for wireless communication, more and more electronic devices have the ability to add wireless communication... Generally, as shown in the figure, the most typical way is to borrow The electronic device 100 is equipped with a wireless peripheral device (Wirde SSperipheral) 12 〇 to satisfy the demand for the wireless communication functions (electronicless devices) of the electronic device. In addition, the electronic device 100 further includes Contains a memory 13〇. The above-mentioned design method of connecting the electronic attack surface to the wireless peripheral device can meet the common wireless application requirements of the general consumer to the electronic device 1. However, 'the practice of the prior art to connect the wireless peripheral device to the processor of the electronic device' often causes the operation of the electronic device (4) 11G to be troubled, for example, a high priority work interrupt processor 11 may occur. The situation arises. For example, in the prior art, when a new system is in the process of debugging or development, it is usually necessary to use an embedded circuit simulator (In_arcmt Emulator, ICE), which is an embedded circuit simulation. The device will be connected to the m Canner processor through a pre-defined 200945191 interface (such as the JTAG interface and the enhanced JTAG interface). Therefore, in practice, it is unavoidable to physically connect the debug tools to the processor 110. In addition, these debug tools must be connected to the processor via a connecting cable. Therefore, it is necessary to It is necessary to obtain the correct wiring and the appropriate signal voltage level before starting the debugging operation of the entire reward. ❹ However, these procedures are not only complicated but also inconvenient for the user. Therefore, a new mechanism is needed to solve the aforementioned problems. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a processor that includes a wireless communication module therein such that the processor can directly control the wireless module. According to a first embodiment of the present invention, a processor unit is disclosed, and the processor unit (4) includes a processing core and a direct suspension to the processor core. The wireless module system (4) provides the processor core wireless communication according to the second embodiment of the present invention, and further discloses a multiprocessor (^oeessG(10) system. The township heavy processor system includes a - processor-one boundary 1 And the same as a wireless link (―Unk). The first process. 7 〇 ~, - _ processing core ^, and - directly contact the first processing 200945191 core of the first - wireless module The first wireless unit is configured to provide the operating function of the first processor core wireless communication. The second processor unit 7 has a second processor core d and a direct connection to the a second wireless module of the second processor core, wherein the second wireless module is provided to provide operation of the second processed two-core wireless communication. The scale connection system is between the $-none, line module: And the second wireless module, and the first processor is connected via the wireless Interacting with the second processor unit. Λ ❹ Φ According to a third embodiment of the present invention, a method for providing a processing-free function is provided, and the method includes: providing a processor core And a wireless module will be directly marketed to the processor core. [Embodiment] In the scope of this patent specification and the subsequent patent application, = a specific component is referred to. The subject (4) has a common knowledge: "hardware" Manufacturers may use different nouns to shoot the same one; : "The scope of patent application and subsequent patent application does not differ by name; the way of knife is 70 pieces, but the difference in function of components is used to distinguish The criterion D is in the beginning, as "contains the requirements mentioned in the subsequent request:".: external ^ electrical connection means::: package π direct and indirect right side describes a first device The second device is coupled to the first device, which means that the first device can be directly electrically connected to the second device' or electrically connected to the second device indirectly through other devices or connection means. Limitation, one of the objects of the present invention is to provide a processor having a wireless communication function, and the wireless communication function is directly controlled by a processor. Referring to FIG. 2, the second level shows a wireless processing module according to the present invention. A functional block diagram of an embodiment of the processor unit 200. The processor unit 2 is configured to execute a command issued by an electronic system, and includes a processor core 210 and a wireless module in the processor unit. Group 22〇, a power amplifier 225, an RF antenna yang (10) plus yang, a cache (cde) memory 230, and a region memory (10) alm _5. In addition, processing The core 2 job also contains a plurality of registers 2i5. In this embodiment, the processor core is coupled to the wireless module 220, and the pepper group 220 is coupled to the power amplifier 225. The power amplifier 225 is connected to the class 227. The processor core and the wireless module 22 are respectively represented by an address/command (akddr/e°_n reel 232 to the cache memory. In addition, the processor core 210 and the wireless module _ are respectively The data transfer line _ at the location of the heartbeat 21 之 register 215 contains a plurality of control registers 200945191 (., 1 ΓΓ) status register (statusregister) and data register (data system register is used Set _ _ _, = 牛例来五儿' use control register to enable or disable the operation of the wireless module. As for the state register, some wireless modules are temporarily stored in the == When certain information in the memory is combined with the bait material stored in the control suspend, it will trigger the interruption of the processor core 210 (or the event) or may cause other data to be cached. The operation of the memory 230 Ο 或 or the area read, the body 235 moves in or out. As for the data register, it is used to store the data received by the wireless module 22 and/or by the wireless module. Send out (4) data. Other components as shown in the second fiscal (such as memory management early (MMU) ), direct memory access unit (DMA), bus interface unit (BIU), JTAG/ICE analog circuit and front-end bus _), etc.), and the related operations are not the focus of the present invention, so for the sake of brevity For the sake of details, it is not described in detail here. Please note here that in an embodiment of the invention, all components associated with the wireless module 220 may also be disposed in the processor unit, that is, The entire wireless system including the wireless module 220, the god amplifier 225, and the antenna 227 can be included in the chip of the processor unit 200. In addition, in another example of the present invention, the wireless system There may be one or more elements of one domain circumscribing to the processor single it 2GG, and the ant relationship is still the same as the block diagram shown in Fig. 2. For example, in another embodiment of the present invention, the antenna 227 is a wire antenna disposed outside the entire processor unit 2 instead of the chip antenna located in the wafer as in the aforementioned 200945191. In addition, in the present invention In another embodiment Both the antenna 227 and the power amplifier 225 are external components of the package of the processor unit 2. In addition to the component configuration manners exemplified above, there may be other hardware configurations that conform to the spirit of the present invention and meet the designer's needs. And the related design changes are all within the scope of the present invention. In the present invention, the wireless module 220 is given to the processor core 21 located in the processor unit 200 (for example, the central processing unit). The processor core 21 or a plurality of processor cores 210 directly perform the function of directwirdess communication. In one embodiment shown in FIG. 3, both processor core 329 and processor core 339 are connected via a wireless link 323 in a master-slave architecture, where processor core 329 is The processor 32 is the processor core of the processor unit 325, and the processor core 339 is the processor core of the processor unit 335 within the device 33. As shown in FIG. 3, in another embodiment, the processor cores 329, 339, 349, 359, 369'379 are connected to each other via a wireless connection 348, 354, 356, 358, 387 in a multiprocessor network ( The multi-processor network architecture is coupled. In this embodiment, the processor cores 329, 339, 349, 359, 369, 379 are processor units 32, 330, 340, 350, 360, 370, respectively. Processor cores among 325, 335, 345, milk, 365, 375, and some of these links are constructed wirelessly via communication network 380. It should be noted here that in the communication network; 380, a bridge and/or other device can also be used to achieve the same goal 12 200945191, and these _ design changes (four) comply with the inventive psychology unit 325 , 335, 345, 355, 365, 375 are operating in _ master = mode 'that is, in this multiprocessor system 31 ,, set the unit (such as the unit 375 age master processing _ shirt The processing processor units (e.g., processor units 345, 355, and 365) refer to FIG. 2 and FIG. 4 as the second processing unit, and FIG. 4 shows the second processing unit core 2U). The flow chart for establishing wireless communication between the wireless modules 22A is intended to be performed in the order of the steps in the flow shown in the figure (4). The process includes the following steps: Step 410: Initialize. Step 420: Search for a new device. Step 430: Authentication. Step 440: Exchange data and commands to the data register. Step 450: Interrupt the processor core. Step 460: Confirm and execute the wireless communication command in the data buffer. Step 470: Complete the wireless communication command. Step 480: Resume the normal operation of the processor core. In this flow, first in step 410, an initial action is performed on the processor core that needs to be utilized. At step 420' a wireless device will begin searching for a wireless connection in the domain to establish a communication link. In the step, after establishing the wireless connection between the two processing benefits, the first processor core and the second processor core start to perform the action of the machine, and the concept of establishing the wireless communication channel by the secret authentication money is Those skilled in the art will be familiar with this subject and will not be described here. In step 44, after the wireless connection establishes and completes the authentication between the devices, the wireless module 1 «receives the packet and places the data in the data register 'successor' and notifies the processing. The core operates according to the settings in the control register. When the number of packets is large, the wireless module can move these packets from the scratchpad to the local memory via direct memory access (demonic aeeess). Here, it is assumed that in the steps, the first processor core plays the role of the master processing core, and the second processor core is the role of the slave processor core. In the command miscellaneous steps, the square wire is transmitted via wireless transmission, and the work assigned by these commands is completed and no other commands need to be executed (step 47()). Finally, in step 480, 'when these commands are completed,' the first processor core and the second processing core can log back to the original handle. In the nuclear ride (four) Fangcai / the first processor core 210 (that is, the master processor core) will interrupt the operation of a second processor core: (subordinate processing If core), and instructions from the care of the heart according to the master The processor core is required to execute certain types of commands. In the present invention, the wireless module 220 transmits a set of specific command-to-mine-to-multiple commands between a plurality of processor cores, and these instructions include: used to execute certain functions on the processor core 210. Specific Execution Control Interrupt Instructions, 14 200945191 • Step-by-step instructions for processor core 210 to ensure unsecured and secure encryption and decryption instructions for processor cores and other peripheral devices Execute (step by _ _ on n) pure debugging functions of other functions (such as setting and resetting the processor's breakpoint), packing the data packet, and Unpacking ^Lends money to raise capital (4) scales and subsidies. ❹ In the performance technology, 'the processor core will command the wireless peripheral device to transmit or receive data, and if necessary, it will cut off the wire according to the processor unit. However, such an architecture must Before the data is transmitted and received, the appropriate device driver is provided to the wireless peripheral device and other parallel input and output interfaces. The invention moves the wireless module directly to the cedar. 210' is such that the data communication interrupt from the wireless mode, group 22 is occupied with the highest execution priority, and therefore is executed immediately. For example, when a processor p detects that another (four) unit is being attacked by a virus or is affected by other malicious code, the processor unit will receive an "interrupt request" via wireless transmission. And related commands to immediately interrupt the operation of the processor unit, to avoid causing more damage and impact. In addition, for example, another element can also send a patch software or program to the virus attack. Malicious attack program. Prior to this, the phase-known technology attack process it, the method immediately retrieved the control of the electronic device, and in the malicious way to pass the unit to the station, it is expected that these benefits line The core and the receiving request are ignored. 15 200945191 Another example of this embodiment of the present invention is the secure remote control of the electronic device in which the processor unit 200 itself is located (secure rem〇te consol) Function, in an intelligent security grid network, when a warning sensor is not working, other senses connected to the warning sensor The device will receive an alert signal to learn of an abnormal condition. In another example, law enforcement and emergency handling vehicles (eg, police cars, ambulances, fire engines, etc.) will be configured to include the processor unit 200 of the present invention. Devices, therefore, these vehicles can interrupt the normal operation of traffic signs to facilitate handling and handling of these emergency events. In one embodiment of the invention, the wireless module 220 is directly coupled to the processor core 21A. It also includes encryption and decryption instructions to ensure wireless communication and communication protocol security. These encryption operations and decryption operations between processor cores ensure communication security between the processor unit and the device in which the processor unit resides. In addition, in another embodiment, in the individual processor cores 21, a unique code (u_e identifier) is included, and the identification code is set at the time of manufacture. (This is achieved by using a single-shot method like laser trimming and thinning (4).) This identification code is set in the manufacturing process. The completion is completed, so after the setting is completed, the identification code setting cannot be copied or moved, thereby making it possible to distinguish the secret security. The other recording point of the present invention is: in the processor core 2H) and its corresponding The communication content between the wireless modules 22〇 is not intercepted and stolen. However, for the prior art, the communication content between the processor core and the learning module is extremely easy to be blocked. Another application of the embodiment of the present invention is to make the age of the processor core 2_ and other peripheral devices _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The operation of the instructions. The use of these debugging instructions may allow a debugger or a compiler device to apply execution instructions and other functions to the processor core 2i() to simultaneously monitor and correct the processing. The operation of the core (4). For example, the execution interrupt point of the processor is set/reset via a breakpoint register or a plurality of interrupt point registers to suspend the operation of the processor core 210 and thereby control Execution of some debugging instructions. In the embodiment, the processor core carries a monitoring program to record all the contents of the processor core when the processor core is operating, and the money is deleted. Step by step (吟by···················································································· Data transmission, data packet processing and providing better data transmission scales. According to the former _ mine _, it can be known that the wireless module of the hair supply has several advantages: it can be more convenient to the processor. Check the wireless side of the line _ and _, the single highest financial execution priority financial 17 200945191 - break to obtain control of the processing heart, and can provide a high security communication between the (four) core. In addition, because Wireless module Integrated in the same wafer, thus having a lower manufacturing cost, in addition: by the implementation of the present invention, it can be turned into smaller crystals and used less circuit board area. Please note that although in this In the specification, the central processing unit (cpu) in the computing device is used as an implementation. However, the connection of the wireless module to the central processing unit is only used as an example of the invention, and is not one of the limitations of the present invention. In summary, the method disclosed in the present invention can be used to understand the technology of the wireless device, and these related design changes are in accordance with the spirit of the present invention, and are only in the scope of the present invention. For the preferred embodiment of the present invention, the equivalent variations and modifications made by the scope of the present invention should be within the scope of the present invention. ® [Simple Description] Figure 1 shows that the technology is wireless. 2 is a schematic diagram of a functional block of an embodiment of a processor unit having a wireless module according to the present invention. FIG. 3 is a schematic diagram of an embodiment of two wireless communication configurations of the present invention. Figure 4 is a flow chart of an embodiment of establishing wireless communication between wireless modules according to the present invention. [Description of main components] 18 200945191 Electronic device • 100, 320, 330, 340, 350, 360, 370 110 processors 120 Wireless Device 130 Memory Processor Unit Processor Core 200, 325, 335, 345, 355, 365, 375 210, 329, 339, 349, 359, 369, 379 215 Register φ 220 Wireless Module 225 Power Amplifier 230 cache memory 235 area memory 300, 310 multiprocessor system
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