200938991 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種時脈信號切換電路（cl〇ck signal switch circuit)，特別地，在此時脈信號切換電路 中，依據至少接收的一第一時脈信號及一第二時脈信號 的正緣或負緣變化來決定該等時脈信號切換之一的時段 點。 、 【先前技術】 為人所熟知的，在現今電腦系統包含許多的複雜的 數位電路(digital circuit)，而這些數位電路運作通常由 某一固定的頻率的時脈信號(clock signal)所控制。需了 解的’由一石英振盪器（crystal oscillator)所產生的時脈 信號係在一高位準(high)及一低位準(low)狀態之間進行 振盈，且該時脈信號通常具有50%工作周期(duty cycle) 並以方波(square wave)形式顯示。該些數位電路如微處 理器(microprocessor)亦由外部而來的時脈信號所驅動， 以利内部運作的定時(time)及同步(synchronization)的目 的’其中同步係依照該時脈信號的正緣（positive edge)、負緣（negative edge)甚或兩者而被觸發 (trigger)。 以目前較複雜的電腦系統而論，皆提供多種不同的 時脈信號，以個人電腦而言’時脈信號的頻率有 8MHz、12 MHz、16 MHz、20 MHz、25 MHz、30 6 200938991 MHz、33MHz 等等。 ❹ ❹ 的時電腦系統中，通常需要將祕運作時所需 使用者^』攸目前的頻率切換至另一頻率。一範例中， 作下，行某繪圖程式，卻發現以目前的時脈信號運 卻發規執行太慢，使用者正在執行某繪圖程式，但 高執行迷2時脈信號運作下’速度太慢。使用者欲提 頻率（如將時脈信號由低頻率（如8mhz)轉換至高 高頻率n^Hz)°或另—範例中，於某—遊戲程式在 將時齡=1，使用者無法跟上遊戲速度時，也必需 應時段來低料者’赠贿者得讀慢的反 作法而電腦系統進行多個切換時脈信號時，習知的 的電路，此H圖所示，該圖為—種習知切換時脈信號 叫10依L t係以一 2對1多工器（multi細er， 態來完^ _號16 (以二進制表示)所輸入的狀 -時脈_ 7英振i器此類型的時脈產生器產生的-第 軟與一第二時脈信號14相互切換，其中在 的-時二產生的_信號16控制之下，將欲得 提及 制”〇，，時，工器依據該控制信號16為二進 為二進制，ΐΓΓ時脈信號14及該控制信號w 時，選擇輸出該第一時脈信號12。 上，請一併參考第1Λ圖及第1Β圖 中’該圖續示二個時脈信號12及14分別輪 7 200938991 夕器之兩輸入端匕及A與在該俨號Μ Ί8卜所 輸出的一輸出時脈㈣㈣以m =机號線18上所 波來圖。Mm 4 0CK W之時脈信號之切換 =處於，:於時段T1期間，首先，-控制 對^多工器H立準狀態二進制表示為“Ο輸入至該2 ❹ ❹ ==:=準狀態)使得該第二時脈： 換的此2對1多工111G能達到兩時脈信號切 2目的’但可惜的事，該2對1多工器Π)為一種數 ^路’其包含的電子元件如多個正反器(峋對 —〇Ρ)β’係由一脈波(Pulse)所觸發。假如該脈波短於一特 ^最ί的時段時，職脈波稱之為嶋⑻減)雜訊。 "而s，閃動雜訊通常造成微處理器或其它電子元件 ^生誤動作的情況’因而影想到電腦系統正常的運作狀 ，。此，如能提出一種時脈信號切換電路係在切換該 、脈#號的同時能解決閃動雜訊的問題應是重要的。 【發明内容】 因此本發明的目的就是在提供一種時脈信號切換電 主要由一取樣頻率選擇器、一同步切換控制器及一 :控制頻率輸出選擇器所組成，在設計此些數位電路， 二需較少的數位電路元件，大幅地減少製造成本，進而 減低該時脈信號切換電路上功率的消耗。 200938991 路，針二t = 提供-種時脈信號切換電 -—種時脈信號切換電路。_(g丨iteh)雜訊而提出 - 根據本發明之上述目的， 電路，其包含-取樣頻二;:Γ信號切換 -第-器。該取樣頻率選擇器接收至少 號之狀態“榦脈信號且根據-頻率選擇信 β 。時脈信號及該第二時脈信號其 =難制11，無來自棘_率選擇 :之該第一時脈信號及該第二時脈信號其令之一 第-時來自該取樣頻率選擇器之該 第時脈信號及該第二時脈信號之 信號而分別輸出-頻率選摞批餘彳效緣之同步 •該可_率==:= =;:腺信號及來自該同步切換控制器之該頻= °出:制信號之狀態決定是否輪出該第-時脈信號:ί: 二時脈信狀其巾之—。 mm 【實施方式】 枯龙為ϋ進—步朗本㈣為達成默目的所採取之 與二請參閱以下有關本發明之詳細說明 與附圖，撼本發明之目的、特徵與特點，當可由此得 -深入且具體之瞭解，料所_式僅提供參考與說 用，並非用來對本發明加以限制者。 在許多複雜_體電路中，使用—時脈信號⑻❹冰 9 200938991 signal)是為了同步化此積體電路不同部分。特別地，在 同步數位電路中’―時脈信號通常作為一種用於協調 - (coordinate)兩個或兩個以上的電路之運作的信號。 • 再者，隨著科技的進步，對於電腦系統上的晶片功 月b的需求日益增加之下，使得這些積體電路在硬體的線 路上變得更複雜，而施加在這些電路内的邏輯運算單元 的時脈信號由於閃動(gliteh)雜訊的經常發生，其信號的 ^確性也隨之不準確。有鑒於此，本發明提出一種時脈 彳§號切換電路係解決先前習知技術的缺失。 首先，先需了解的，以一個人電腦作業系統為例， 在主機板上的微處理器用以提供整個電腦系統運作之多 個時脈彳e號，係由如石英振盈器（crystal 〇scillat沉)此類 型的時脈產生器（cl〇ck generat〇r)所產生。於本實施例 中，由石英振盪器產生如2〇〇 MHz之一第一時脈信號 及如2 MHz之一第二時脈信號為代表說明。 請一併參考第2A圖及第2B圖，第2A圖為本發明 © 之時脈錢切換電路之電·及第2B圖為根據第2A圖 而繪示本發明之時脈信號切換電路之該等時脈信號之波 形圖。從此第2A圖可知，本發明之時脈信號切換電路 2包含一取樣頻率選擇器20、一同步切換控制器21及 一可控制頻率輸出選擇器22。其中，該取樣頻率選擇器 2〇係接收來自該時脈產生器（未繪示)之一第一時脈信號 CLIC1(200 MHz)及一第二時脈信號 CLK2(2 MHz)，且 該取樣頻率選擇器2〇係依據由軟體程式或硬體所產生 200938991 一頻率選擇信號s〇之狀態以決定輸出來自該時脈產生器 所產生的該第一時脈信號CLK1及該第二時脈信號200938991 IX. Description of the Invention: [Technical Field] The present invention relates to a cpu signal switching circuit, in particular, in a pulse signal switching circuit, according to at least one received A positive or negative edge change of the first clock signal and a second clock signal determines a time point of one of the clock signal switching. [Prior Art] It is well known that today's computer systems contain many complex digital circuits that are typically controlled by a fixed frequency clock signal. It is to be understood that the clock signal generated by a crystal oscillator is excited between a high level and a low level state, and the clock signal usually has 50%. The duty cycle is displayed in the form of a square wave. The digital circuits, such as microprocessors, are also driven by external clock signals to facilitate the timing of internal operations and the purpose of synchronization. The synchronization is based on the positive of the clock signal. Triggers are triggered by positive edges, negative edges, or even both. In the current more complex computer systems, a variety of different clock signals are provided. For personal computers, the frequency of the clock signal is 8 MHz, 12 MHz, 16 MHz, 20 MHz, 25 MHz, 30 6 200938991 MHz, 33MHz and so on. In the computer system of ❹ ,, it is usually necessary to switch the current frequency of the user to the other frequency. In one example, if you do a drawing program, you find that the current clock signal is too slow to execute, and the user is executing a drawing program, but the high execution fan 2 clock signal is running too slow. . The user wants to mention the frequency (such as switching the clock signal from low frequency (such as 8mhz) to high frequency n^Hz) or another example, in the case - the game program is in age = 1, the user can not keep up When the game speed is high, it is necessary to take the time to come to the low-sellers. The bribe-offer has to read the slow reverse method and the computer system performs multiple switching clock signals. The conventional circuit, as shown in the H-picture, is - The conventional switching clock signal is called 10 according to the L t system with a 2-to-1 multiplexer (multi-fine er, state is finished ^ _ number 16 (in binary representation) input - clock _ 7 ying i The soft-to-second clock signal 14 generated by the clock generator of this type is switched to each other, wherein under the control of the -signal 16 generated by the second-time, the system will be referred to as "〇,,, The worker selects and outputs the first clock signal 12 according to the control signal 16 being binary into binary, the clock signal 14 and the control signal w. Please refer to the first diagram and the first diagram together. 'The figure continues with two clock signals 12 and 14 respectively. The two inputs 匕 and A of the 200938991 eve are outputted at the 俨 Μ Ί8 An output clock (4) (4) is plotted with m = the wave on the line 18 of the machine. The switching of the clock signal of Mm 4 0CK W = at: during the period T1, first, the control aligns the multiplexer H The binary representation is "Ο input to the 2 ❹ ❹ ==:= quasi-state" so that the second clock: the two-to-one multiplex 111G can be switched to two clock signals to cut 2 goals', but a pity, A 2-to-1 multiplexer is a type of circuit that contains electronic components such as multiple flip-flops (峋-〇Ρ) β' that are triggered by a pulse. If the pulse is shorter than a period of one utmost, the job pulse is called 嶋 (8) minus noise. " and s, flashing noise usually causes the microprocessor or other electronic components to malfunction, thus thinking about the normal operation of the computer system. Therefore, it can be important to propose a clock signal switching circuit that can solve the problem of flashing noise while switching the pulse number. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a clock signal switching power mainly composed of a sampling frequency selector, a synchronous switching controller and a control frequency output selector, in designing such digital circuits, The need for fewer digital circuit components greatly reduces manufacturing costs, thereby reducing power consumption on the clock signal switching circuit. 200938991 Road, pin 2 t = provide - kind of clock signal switching - a kind of clock signal switching circuit. According to the above object of the present invention, the circuit includes - sampling frequency two;: Γ signal switching - the first device. The sampling frequency selector receives the state of at least the number "dry pulse signal and selects the signal according to the -frequency. The clock signal and the second clock signal have a difficulty of 11 and no selection from the spine rate: the first time And the pulse signal and the second clock signal are respectively outputted from the first clock signal of the sampling frequency selector and the signal of the second clock signal to output a frequency-selection batch Synchronization • The _ rate ==:= =;: gland signal and the frequency from the synchronous switching controller = ° out: the state of the signal determines whether the first-clock signal is rotated: ί: two-time signal The method of the present invention is as follows: And the features, which can be derived from the in-depth and specific understanding, are only for reference and use, and are not intended to limit the invention. In many complex _ body circuits, use - clock signal (8) ❹冰9 200938991 signal) is to synchronize different parts of this integrated circuit. In a synchronous digital circuit, a clock signal is usually used as a signal for coordinating the operation of two or more circuits. • Furthermore, as technology advances, wafers on computer systems The increasing demand for power month b makes these integrated circuits more complicated on the hardware circuit, and the clock signals of the logic units applied in these circuits are often due to flashing (gliteh) noise. The occurrence of the signal is also inaccurate. In view of this, the present invention provides a clock circuit switching circuit to solve the lack of the prior art. First, it is necessary to understand that the personal computer operating system is For example, a microprocessor on a motherboard is used to provide a plurality of clocks for the operation of the entire computer system, such as a quartz oscillator (crystal 〇scillat sink), a type of clock generator (cl〇ck generat) 〇r) is generated. In this embodiment, a first clock signal such as 2 〇〇 MHz and a second clock signal such as 2 MHz are generated by a quartz oscillator as a representative description. Please refer to 2A together. Figure 2B, FIG. 2A is a diagram showing the waveforms of the clock signals of the clock signal switching circuit of the present invention according to FIG. 2A, and FIG. 2B is a waveform diagram of the clock signals of the clock signal switching circuit of the present invention. As can be seen from FIG. 2A, the clock signal switching circuit 2 of the present invention includes a sampling frequency selector 20, a synchronous switching controller 21, and a controllable frequency output selector 22. The sampling frequency selector 2 is configured to receive a first clock signal CLIC1 (200 MHz) and a second clock signal CLK2 (2 MHz) from the clock generator (not shown), and the sampling frequency selector 2 is based on a software program or The hardware generates 200938991 a state of the frequency selection signal s〇 to determine the output of the first clock signal CLK1 and the second clock signal generated by the clock generator.
. CLK2其中之一，而此取樣頻率選擇器20係為於第2C 圖（其中，第2C圖為第2B圖之各電路方塊之實現電 路，以下請同時參閱第2A圖、第2B圖及第2C圖）中 所顯示的一第一 2對1多工器20(multiplexer，mux)為 代表，而為人所熟知的，該第一 2對1多工器20為一 種邏輯電路(logic circuits)係由2個AND閘、2個OR ❹ 閘及一個NOT閘所組成。而前述頻率選擇信號S()為一 . 二進制(binary)信號’而在數位電路中，此第一 2對1 . 多工器20依據該二進制信號S0之0或1的邏輯值以選 擇出一期望的時脈信號。 在第2Β圖中也一併繪示此二進制信號s〇之波形 圖，於T1時期，該二進制信號s◦處於一低準位狀態 (low level)。而針對在第2 c圖中的該第一 2對1多工 器20之運作狀態，以表一的真值表(tnjth丨讣丨匀為本實 © 施說明，其中符號A及B分別為該第一 2對！多工器 20。之一輸入端，且該輸入端a用於接收來自該時脈產 生器所生的該第一時脈信號CLK卜該輸入端B用於接 ^來自該時脈產生器所生的該第二時脈信號CLK2，符 號S為—選擇輸人端’勒於接收該二進制信號S。及符 S A B Z ---------- 0 CLK1 CLK2 CLK1 11 200938991 1 CLK1 CLK2 CLK2 表一 從上述真值表所述内谷清楚地可知，當該選擇輸入 端S所接收的該一進制彳§就為〇時，則該輸出端z 係輸出來自該時脈產生器所產生的該第一時脈信號 CLK1，當該選擇輸入端S所接收的二進制信號Sq為1 時，該輸出端Z係輸出來自該時脈產生器所產生的該第 二時脈信號CLK2。而由第2B圖之該等時脈信號之波 β 形圖可知，於T1時期，因該選擇輸入端s所接收的二 進制#说S〇為0 ’所以’從該第一 2對1多工器20之 該輸出端Z係輸出來自該時脈產生器所產生的該第一時 脈信號CLK1。 承上，於第2A圖中，該同步切換控制器21係耦接 該取樣頻率選擇器20,係接收來自該取樣頻率選擇器 20之該第一時脈信號CLK1及該第二時脈信號CLK2其 中之一’且該同步切換控制器21係根據該頻率選擇信 ❹ 號之狀態及及來自該取樣頻率選擇器之CLK1及 CLK2之一之一有效緣之同步信號而分別輸出一頻率選 擇控制信號CLKSEL及一頻率輸出控制信號 CONTROL。仍需講述地，該同步切換控制器係包含一 脈衝緣(edge)偵測器211及一第一運算邏輯單元212， 見於第2C圖中，熟知此技藝人士可知，該脈衝緣檢測 器211，可分為正緣(Positive對edge)觸發邊緣檢測器 及負緣(Negative對edge)觸發邊緣檢測器。其中，正緣 12 200938991 檢測是檢測由0轉！，負緣檢測是檢測由〗轉 於 本電路中，此脈衝緣檢測器211為一 Rs型正 ρ 對㈣或一 D型正反器或——正反 器之其中之―，於第2C圖中所顯示的脈衝緣檢測器 211以D型正反器211為例，該〇型正反器211具有一 個輸入端D、-個輸出端q和—個時脈輸人端ck。One of CLK2, and the sampling frequency selector 20 is in the 2Cth diagram (wherein the 2C is the implementation circuit of each circuit block of FIG. 2B, please refer to FIG. 2A, FIG. 2B and the following A first two-to-one multiplexer 20 (multiplexer, mux) shown in FIG. 2C is representative, and as is well known, the first two-to-one multiplexer 20 is a logic circuit. It consists of 2 AND gates, 2 OR gates and a NOT gate. The frequency selection signal S() is a binary signal 'in the digital circuit, the first two pairs of 1. The multiplexer 20 selects one according to the logical value of 0 or 1 of the binary signal S0. The desired clock signal. The waveform of the binary signal s〇 is also shown in the second diagram. During the T1 period, the binary signal s is at a low level. For the operation state of the first two-to-one multiplexer 20 in the second c-picture, the true value table of Table 1 (tnjth is the actual implementation, wherein the symbols A and B are respectively One input end of the first two pairs! multiplexer 20, and the input end a is for receiving the first clock signal CLK generated by the clock generator, and the input terminal B is used for receiving The second clock signal CLK2 generated by the clock generator, the symbol S is - selects the input terminal to receive the binary signal S. And the character SABZ ---------- 0 CLK1 CLK2 CLK1 11 200938991 1 CLK1 CLK2 CLK2 Table 1 is clearly known from the inner valley of the above truth table, when the binary input § received by the selection input S is 〇, then the output z output is from the The first clock signal CLK1 generated by the clock generator, when the binary signal Sq received by the selection input terminal S is 1, the output terminal Z outputs the second time generated by the clock generator The pulse signal CLK2, and the waveform of the clock signals of the clock signals of FIG. 2B, is known to be received by the selection input terminal s during the T1 period. The hexadecimal # says S 〇 is 0 'so 'the output of the first two-to-one multiplexer 20 Z outputs the first clock signal CLK1 generated by the clock generator. In FIG. 2A, the synchronous switching controller 21 is coupled to the sampling frequency selector 20 to receive one of the first clock signal CLK1 and the second clock signal CLK2 from the sampling frequency selector 20. And the synchronous switching controller 21 outputs a frequency selection control signal CLKSEL and a frequency respectively according to the state of the frequency selection signal and the synchronization signal from one of the effective edges of the sampling frequency selectors CLK1 and CLK2. The output control signal CONTROL is still described. The synchronous switching controller includes an edge detector 211 and a first operational logic unit 212, as seen in FIG. 2C, which is well known to those skilled in the art. The edge detector 211 can be divided into a positive edge (Positive to edge) trigger edge detector and a negative edge (edge to edge) edge detector. Among them, the positive edge 12 200938991 detection is detected by 0 turn!, the negative edge detection is Detected by In the circuit, the pulse edge detector 211 is an Rs-type positive ρ pair (four) or a D-type flip-flop or a positive-and-reverse device, and the pulse edge detector 211 shown in FIG. 2C is For example, the D-type flip-flop 211 has an input terminal D, an output terminal q, and a clock input terminal ck.
熟知此技藝人士可知，D敎反Μ區分為正緣觸 發D型正反器及負緣觸發〇型正反器，前者為輸入的資 料會在時脈信號由〇 — 1時(上升緣)被偵測到，後者則 為輸入的資料會在時脈錢下_侧_，而經由時 脈信號的有效緣進一步觸發該正反器動作並將資料傳送 至輸出端。如表二亦表示為一正緣7觸發D型正反器依 據該時脈輸入端CK所接收的時脈信號之有效緣(上升緣） 及非有效緣(非上升緣)及該輸入端D接收該二進制信號 S〇之數值而輸出情形（以本電路之實施說明）。As is well known to those skilled in the art, the D敎 敎 is divided into a positive-edge triggered D-type flip-flop and a negative-edge triggered 〇-type flip-flop. The former is the input data when the clock signal is 〇-1 (rising edge) Detected, the latter is the input data will be in the clock__ side, and the active edge of the clock signal further triggers the flip-flop action and transmits the data to the output. As shown in Table 2, the positive edge (rising edge) and the inactive edge (non-rising edge) of the clock signal received by the positive-edge 7-triggered D-type flip-flop according to the clock input terminal CK and the input terminal D are also shown. The output is received by the value of the binary signal S (described in the implementation of the circuit).
Clock D Q iQprev 土升緣 0 . ·. . ： 0 ： ::f _减::::丨 1 X .. · . . . .-Non 對 Rising X . .·：：； constant .........:.-V -: Ο 表二 依上述所言，於第2C圖中，於時段T1期間，該正 緣觸發D型正反器211之該輸入端D係接收該二進制信 號S〇(低準位狀態，亦是0)，該時脈輸入端CK係接收 13 200938991 來自該第一 2對1多工器20之該第一時脈信號CL1U， 此時’若來自該第—2對1多卫器2G之該第-時脈信 ^ CLK1處於上升緣（自第1條虛線算起)且該輸入端D • 為G時，則根據表二所述，該輸出端Q則輸出-頻率選 擇控制信號CLKSEL (低準位狀態，亦是為〇)。 而與該正緣觸發D型正反器211_的該第一運算 邏輯單元212係用於檢測該二進制錢以刀換模式，理 解的事’躲所接㈣二_錄SQ之〇或〗的數位模 式，該第-運算邏輯單元212為一種係為一 x〇r間、 一 XNOR 閘、一 0R 閘、—AND 閘、—nand 閘、一 NOR閘、-膽閘、—M0S其中之—的具布林運算 功能(Boolean operation)之數位邏輯電路。以第2c圖中 的X0R閘212為例，於時段T1 _，該x〇R閉212 係接收該二進制信號S〇(低準位狀態，亦是〇)及由該正 緣觸發D型正反器如之該輸出端Q所輸出的該頻率選 擇控制信號CLKSEL (低準位狀態，亦是為G)，經一次 〇 X〇R運算後而得出一頻率輸出控制信號CONTROL (低 準位狀態，亦是為〇)。 而為旎決疋是否輸出該第一時脈信號CLK1及該第 -時脈信號CLK2之其巾之―，於本㈣之時脈切換電 路中係提㈣可控儀卿ϋ。於第2A _的該可^ 制頻率輸出選擇器22係接收來自該時脈產生器所產^ 的該第-時脈信號CLK1及該第二時脈信號CLK2及來 自該同步減控制器21所產生的該頻率選擇控制信號 200938991 CLKSEL與該頻率輸出控制信號CONTROL。其中，該 可控制頻率輸出選擇器22所決定的該時脈信號過程及 較詳細的電路揭示如下。Clock DQ iQprev 升升缘 0 . ·. . : 0 : ::f _ minus::::丨1 X .. · . . . .-Non on Rising X . ..::; constant ..... ....:.-V -: Ο Table 2 According to the above, in the 2C figure, during the period T1, the positive edge triggers the input terminal D of the D-type flip-flop 211 to receive the binary signal S. 〇 (low level state, also 0), the clock input terminal CK receives 13 200938991 from the first 2 to 1 multiplexer 20 of the first clock signal CL1U, at this time 'if from the first When the first-clock signal CLK1 of the 2-to-1 multi-guard 2G is at the rising edge (from the first dash line) and the input terminal D is G, the output terminal Q is as described in Table 2. Output-frequency selection control signal CLKSEL (low level state, also 〇). And the first operation logic unit 212 that triggers the D-type flip-flop 211_ with the positive edge is used to detect the binary money in a knife-changing mode, and the understanding of the thing is to hide the (four) two-record SQ or the In the digital mode, the first-operation logic unit 212 is a type of x〇r, an XNOR gate, an OR gate, an AND gate, a nand gate, a NOR gate, a -bile gate, and a M0S. A digital logic circuit with Boolean operation. Taking the X0R gate 212 in Fig. 2c as an example, in the period T1_, the x〇R closed 212 receives the binary signal S〇 (low level state, also 〇) and triggers the D type positive and negative by the positive edge The frequency selection control signal CLKSEL (low level state, also being G) outputted by the output terminal Q is obtained by a 〇X〇R operation to obtain a frequency output control signal CONTROL (low level state). It is also awkward). In order to determine whether to output the first clock signal CLK1 and the first-to-clock signal CLK2, the controller can be controlled in the clock switching circuit of (4). The programmable frequency output selector 22 of the 2A_ receives the first-to-clock signal CLK1 and the second clock signal CLK2 generated by the clock generator and from the synchronous controller 21 The generated frequency selection control signal 200938991 CLKSEL and the frequency output control signal CONTROL. The process of the clock signal determined by the controllable frequency output selector 22 and the more detailed circuit are disclosed below.
於第2C圖中可知，該可控制頻率輸出選擇器22包 含一第二2對1多工器221及一第二運算邏輯單元 222。該第二2對1多工器21與前述第一 2對1多工器 20之組成元件相同的，亦是，該第二2對1多工器221 係由2個AND閘、2個OR閘及1個NOT閘所組成。 且該第二2對1多工器221所依據的真值表相同於表 一，揭示於表三。如表三所示，其中符號A，及B，分別 為該第二2對1多工器之221 —輸入端’及該輸入端a， 用於接收來自該時脈產生器所產生的該第一時脈信號 CLK1，及該輸入端B’用於接收來自該時脈產生器所產 生的該第二時脈信號CLK2且符號S，為一選擇輪入端， S’ A， B， > ^ mm Z， 0 CLK1 CLK2 CLK1 1 CLK1 CLK2 CLK2 表三 ❹ 從表三的真值表的所述内容清楚地可知，當該選擇 輸入端S’所接收的該二進制信號So為0時，該輸出端 z’係輸出來自該時脈產生器所產生的該第一時脈信號 ’同樣地’當該選擇輸入端s’所接收的該二進制 ^號S〇為1時，則該輸出端z’係輸出來自該時脈產生 15 200938991 器所產生的該第二時脈信號CLK2。由第2B圖之該等時 脈信號之波形圖可知，於T1時期，該二進制信號心為 • 0時’自該第二2對1多工器221之該輸出端Z，係輸出 該第一時脈信號CLK1。 而與該第二2對1多工器221耦接的該第二運算邏 輯早元222係為一 XOR閘、一 XNOR間、一 間、 一 AND 閘、一 NAND 閘、一 NOR 閘、一 not 閘、一 MOS其中之一。於該可控制頻率輸出選擇器22内該第 ❹ 二運算邏輯單元222係為一種具布林運算功能之數^邏 輯電路。其中，該第二運算邏輯單元222以第2C圖中 的一 OR閘222為例，於時段T1期間，於該可控制頻 率輸出選擇器22内的該〇R閘222係接收來自該第一 運算邏輯單元212(X〇R閘）之該頻率輸出控制信號 CONTROL(低準位狀態，亦是為〇)及由該第一 2對1多 工器20所選擇出的該第一時脈信號CLK1經一次〇r 運算後，因該鮮輸ά控制錢為G狀態，故來自該第 © 二2對1多工器221之該第—時脈信_uClki經該〇r 閘222導通(pass)而在該〇R閘222之一輸出端 out輸出來自該第二多卫器22ι之該第一時脈信 號 CLK1。 而在第2C圖的時段丁2期間，該二進制信號§〇從一 低^準狀祕為-高位準«_»1)，至此，該二進 制信號S〇為1輸入至該第一卻多工器2〇之該選擇輸入 端S ’該第一2m多工器20係根據真值表（表一）而輸出 16 200938991 來自該時脈產生器所產生的該第二時脈信號CLK2，並 輸至該正緣觸發D型正反器211之該時脈輸入端〇反，此 .時，處於時段T2期間的來自該第一2對1多工器2〇之該第 一時脈#號(：1^2為下降緣狀態，此下降緣狀態對於該 同步切換控制器21内的該正緣觸發〇型正反器211係為一 非有效緣’及依據該輸人端D所接收該二進制信號^為】 ，則如表二所不，該正緣觸發D型正反器211之該輸出端 ❹ ⑽出值將不會改變’因而該輸出端Q所輸出該頻率選 擇控制信號CLKSEL仍為低位準狀態（亦是為〇)。 而當該第二2對1多工器221之該輸入端a，及該輸 入端B’係分別接收來自時脈產生器所產生該第一時脈信 ，CLK1及該第二時脈信號CLK2且該第二2對丨多工 器221依據該頻率選擇控制信號clksel(低位準狀 態，亦是為0)而在該輸出端z’輸出該第一時脈信號 CLK1至該〇R閘之一輸入端。 ❹ 同時，於第2C圖的時段T2期間，在該同步切換控 制器21内的該x〇R閘212係分別接收該二進制信號 S〇(咼位準狀態，亦是為1)及由該正緣觸發D型正反器 21所輸出的該頻率選擇控制信號CLKSEL(低位準狀 態，亦是為0)經該XOR212閘進行一次x〇R運算而得 出一頻率輸出控制信號CONTR〇L(高位準狀態，亦是 為並將該頻率輸出控制信號CONTROL(高位準狀 態’亦是為1)輸入至該〇R 222閘之另一輸入端。 而在該可控制頻率輸出選擇器22内的該〇R閘222 17 200938991 分別接收來自該XOR閘212之該頻率輸出控制信號 CONTROL (高位準狀態，亦是為〇及來自該第二2對i . 多工器221之該第一時脈信號CLK1，而該〇R閘222 因接收該頻率輸出控制信號C〇NTROL(高位準狀態， 亦是為1)而在該OR閘222之一輸出端CLOCK OUT輸 出一高準位信號（高位準狀態，亦是為，此高準位信 號亦是在於時段T2期間一小段時間r (自第i條虛線至 第2條虛線之間），稱之為一等待時間(h〇ld time)。持續 ❹ 地，來自該第一 2對1多工器20之該第二時脈信號 CLK2從下降緣狀態轉換至上升緣時，來自該第一 2對 1多工器2G之該第二時脈信號CLK2之上升緣狀態輸入 至該正緣觸發D型正反器211之該時脈輸入端CK，至 此，該正緣觸發D型正反器211依據表二所述，依據該 輸入端D所接收該二進制信號s〇(高位準狀態，亦是為 1)及該時脈輸入端CK所接收的上升緣(有效緣）進一步 觸發該正緣觸發D型正反器211動作並將資料傳送至輸 ❹ ㈣正賴發D型正反mi之該輸出端Q，致使該輸 出端Q輸出一頻率選擇控制信號CLKSEL(高位準狀 態，亦是為1)。 同時’來自時脈產生器所產线第—時脈信號 CLK1及該第二時脈錢CLK2分機至該第二2對} 多工器221之該輸入端A’及該輸入端B，。該第二2對1 多工器221依據來自該正緣觸發D型正反器之該頻率選 擇控制信號CLKSEL(高位準狀態，亦是為明輸出該 200938991 第'一時脈信號CLK2至該OR閘222之一輸入端。 而於時段T2期間，在該同步切換控制器内21的該 XOR閘212係分別接收該二進制信號s〇(高位準狀熊， 亦是為1)及由該正緣觸發D型正反器211所輸出的該頻 率選擇控制信號CLKSEL(高位準狀態，亦是為丨）^則 該等兩信號S〇、CLKSEL經該XOR閘212進行一次 XOR運算，輸出一頻率輸出控制信號CONTROL(低位 準狀態’亦是為0)至該OR閘222之另一輸入端。 至此，在經τ時間後，於該可控制頻率輸出選擇器 22内的該OR閘222係接收來自該X〇R閘212之該頻率輸 出控制信號CONTROL(低位準狀態，亦是為0)及由該第 二2對1多工器221所選擇出的該第二時脈信號CLK2經一 次OR運算後，因該頻率輸出控制信號c〇NTR〇L為低位 準狀態（亦是為0) ’故來自該第二2對1多工器22之該第二 時脈信號CLK2經該OR閘222導通而在該OR閘222之一 輸出端CLOCK OUT輸出來自該第二2對1多工器221之 該第二時脈信號CLK2。明顯地，從第2C圖的輸出波形 可知’該OR閘222所輸出的時脈信號已從該第一時脈信 號CLK1切換至該第二時脈信號CLK2。 而在第2C圖的時段的T2期間，該二進制信號S〇仍在 高位準狀態（亦是為1)，至一T3期間，該二進制信號S〇從 高位準狀態轉換至低位準狀態（1 —〇)，該二進制信號S〇 為〇輸入至該第一2對1多工器20之該選擇輸入端S，該第 一2對1多工器20係根據真值表(表一），自該第一2對1多 19 200938991 工器20之該輸出端z係輸出來自該時脈產生器所產生的 該第一時脈信號CLK1，並輸至該正緣觸發D型正 - 之該時脈輸入端CK，此時，來自該第一即多工器20 . 线帛―時脈錢CLK1正處於上升緣狀態（自第3條虛 算起）此正處於上升緣狀態對於該同步切換控制器 21内的該正緣觸發D型正反器211係為一非效緣，故該正 緣觸發D型正反器211的輸出將不會改變，所以，該正緣 ❻ 觸，〇型正反器211之該輸出端Q所輸出的頻率選擇控制 信號CLKSEL仍保持前一次於丁2期間輸出狀態，亦是所 輸出的該頻率選擇控制信號CLKSEL(仍是為1)，且依據 輸入該輸入端D之二進制信號S。為0，則如表二所示，依 據該輸入端D所接收該二進制信號§〇為〇及該時脈輸入端 CK所接收的正纽上升緣(非有錄)*會麟該正緣觸 發D型正反器211動作以使得該正緣觸發〇型正反器 之該輸出端Q輸出一頻率選擇控制信號CLKSEL(高位準 ❹ 狀態’亦是為1)。 而當該第二2對1多卫器221之該輸人端A，及該輸 入端B’係分別接收來自時脈產生器所產生該第一時脈信 號CLK1及該第二時脈信號CLK2且如表三所示，該第 二2對1多工器221依據該頻率選擇控制信號 CLKSEL(低位準狀態，亦是為〇)而自該第二2對1多工 器221之該輸出端z’輸出該第一時脈信號CLK1至該 OR閘222之一輸入端。 同時，於該第2C圖之時段T3期間，在該同步切換 20 200938991 控制器21内的該X〇R閘212係分別接收該二進制信號 S〇(低位準狀態’亦是為〇)及由該正緣觸發d型正反器 211所輸出的該頻率選擇控制信號CLKSEL(高位準狀 態’亦是為1)經該XOR閘212進行一次X〇R運算而得 出一頻率輸出控制信號CONTROL(高位準狀態，亦是 為1)，並將該頻率輸出控制信號CONTROL(高位準狀 態，亦是為1)輸入至該OR閘222之另一輸入端。As can be seen from Figure 2C, the controllable frequency output selector 22 includes a second 2-to-1 multiplexer 221 and a second operational logic unit 222. The second two-to-one multiplexer 21 is identical to the components of the first two-to-one multiplexer 20, that is, the second two-to-one multiplexer 221 is composed of two AND gates and two ORs. The gate and a NOT gate are formed. The truth table according to the second two-to-one multiplexer 221 is the same as in Table 1, and is disclosed in Table 3. As shown in Table 3, wherein the symbols A and B are respectively the 221 - input terminal ' of the second 2-to-1 multiplexer and the input terminal a for receiving the first generated by the clock generator a clock signal CLK1, and the input terminal B' is configured to receive the second clock signal CLK2 generated by the clock generator and the symbol S is a selection wheel, S' A, B, > ^ mm Z, 0 CLK1 CLK2 CLK1 1 CLK1 CLK2 CLK2 Table 3 ❹ From the contents of the truth table of Table 3, it is clear that when the binary signal So received by the selection input S' is 0, the output The end z' is outputting the first clock signal generated by the clock generator 'samely'. When the binary number S〇 received by the selection input terminal s' is 1, the output terminal z' The second clock signal CLK2 generated by the clock generation 15 200938991 is output. It can be seen from the waveform diagrams of the clock signals of FIG. 2B that, in the T1 period, when the binary signal center is “0”, the output Z from the second 2-to-1 multiplexer 221 outputs the first Clock signal CLK1. The second operational logic 222 coupled to the second two-to-one multiplexer 221 is an XOR gate, an XNOR, an AND, an AND gate, a NAND gate, a NOR gate, and a not One of the gates, one MOS. The second arithmetic logic unit 222 is a digital logic circuit having a Boolean operation function in the controllable frequency output selector 22. The second operation logic unit 222 takes an OR gate 222 in FIG. 2C as an example. During the time period T1, the 〇R gate 222 in the controllable frequency output selector 22 receives the first operation. The frequency output control signal CONTROL of the logic unit 212 (X〇R gate) (low level state, also 〇) and the first clock signal CLK1 selected by the first two-to-one multiplexer 20 After a 〇r operation, since the fresh control 钱 control money is in the G state, the first-time clock _uClki from the first two-to-one multiplexer 221 is turned on via the 〇r gate 222. And outputting the first clock signal CLK1 from the second multi-guard 22 from the output end out of the 〇R gate 222. In the period of time 2C of the 2C picture, the binary signal § 〇 is from a low level to a high level «_»1), and thus the binary signal S 〇 is 1 input to the first but multiplex The selection input terminal S' of the first 2m multiplexer 20 outputs 16 the second clock signal CLK2 generated by the clock generator according to the truth table (Table 1), and loses Up to the positive edge triggering the clock input end of the D-type flip-flop 211 is reversed. In this case, the first clock ## from the first 2-to-1 multiplexer 2〇 during the period T2 ( :1^2 is a falling edge state, the falling edge state is an inactive edge of the positive edge triggering type flip-flop 211 in the synchronous switching controller 21, and the binary is received according to the input terminal D If the signal ^ is ], then as shown in Table 2, the positive edge triggers the output terminal D (10) of the D-type flip-flop 211 will not change the value. Therefore, the frequency selection control signal CLKSEL output by the output terminal Q is still a low level state (also 〇). When the input end a of the second 2-to-1 multiplexer 221 and the input end B' are respectively received from The generator generates the first clock signal, CLK1 and the second clock signal CLK2, and the second two-pair multiplexer 221 selects the control signal clksel according to the frequency (low level state, also is 0) The output terminal z' outputs the first clock signal CLK1 to one of the input terminals of the 〇R gate. ❹ At the same time, during the period T2 of the 2Cth diagram, the x〇R gate 212 in the synchronous switching controller 21 Receiving the binary signal S〇 (咼 level state, also being 1) and the frequency selection control signal CLKSEL output by the positive edge trigger D-type flip-flop 21 (low level state, also being 0) Performing an x〇R operation through the XOR212 gate to obtain a frequency output control signal CONTR〇L (a high level state, and also inputting the frequency output control signal CONTROL (the high level state 'is also 1) to the The other input terminal of the 〇R 222 gate, and the 〇R gate 222 17 200938991 in the controllable frequency output selector 22 receives the frequency output control signal CONTROL from the XOR gate 212 (high level state, also For the second clock pair from the second pair of i. multiplexer 221 CLK1, and the 〇R gate 222 outputs a high level signal (high level state) at an output terminal CLOCK OUT of the OR gate 222 by receiving the frequency output control signal C〇NTROL (high level state, also being 1) Therefore, the high-level signal is also a period of time r (between the d-th line and the second dash line) during the period T2, which is called a waiting time (h〇ld time). The second clock signal CLK2 from the first two-to-one multiplexer 2G is switched from the falling edge state to the rising edge from the first two-to-one multiplexer 20 The rising edge state is input to the clock edge input terminal CK of the positive edge triggering D-type flip-flop 211. At this point, the positive edge triggering D-type flip-flop 211 receives the signal according to the input terminal D according to Table 2. The binary signal s〇 (high level state, also being 1) and the rising edge (effective edge) received by the clock input terminal CK further trigger the positive edge trigger D-type flip-flop 211 to operate and transmit data to the input port. (4) Depending on the output terminal Q of the D-type positive and negative mi, the output terminal Q outputs a frequency selection control signal CLKSEL (High level status is also 1). At the same time, the line-clock signal CLK1 and the second clock money CLK2 from the clock generator are connected to the input terminal A' of the second pair of multiplexers 221 and the input terminal B. The second 2-to-1 multiplexer 221 selects the control signal CLKSEL according to the frequency from the positive-edge triggered D-type flip-flop (the high level state is also to output the 200938991 first clock signal CLK2 to the OR gate) One input end of the 222. During the time period T2, the XOR gate 212 in the synchronous switching controller 21 receives the binary signal s〇 (high level, also being 1) and is triggered by the positive edge. The frequency selection control signal CLKSEL outputted by the D-type flip-flop 211 (the high level state is also 丨), the two signals S 〇, CLKSEL are subjected to an XOR operation via the XOR gate 212, and a frequency output control is output. The signal CONTROL (low level state 'is also 0) to the other input of the OR gate 222. Up to this point, after the τ time, the OR gate 222 in the controllable frequency output selector 22 receives from the The frequency output control signal CONTROL of the X〇R gate 212 (the low level state is also 0) and the second clock signal CLK2 selected by the second 2-to-1 multiplexer 221 are ORed. Because the frequency output control signal c〇NTR〇L is in a low level state (also 0) Therefore, the second clock signal CLK2 from the second 2-to-1 multiplexer 22 is turned on via the OR gate 222 and is output from the output terminal CLOCK OUT of the OR gate 222 from the second 2-to-1 multiplexer. The second clock signal CLK2 of 221. Obviously, from the output waveform of the 2C diagram, it can be seen that the clock signal output by the OR gate 222 has been switched from the first clock signal CLK1 to the second clock signal CLK2. During the period T2 of the period of FIG. 2C, the binary signal S〇 is still in the high level state (also 1), and during a period T3, the binary signal S〇 transitions from the high level state to the low level state (1). - 〇), the binary signal S〇 is input to the selection input S of the first 2-to-1 multiplexer 20, the first 2-to-1 multiplexer 20 is based on a truth table (Table 1), The output end z of the first two-to-one 19, 2009, 299, 2009, 29, 20 outputs the first clock signal CLK1 generated by the clock generator, and is input to the positive-edge trigger D-type positive- Clock input terminal CK, at this time, from the first multiplexer 20. Line 帛 - clock money CLK1 is in the rising edge state (from the third virtual calculation) The positive edge triggering D-type flip-flop 211 in the synchronous switching controller 21 is a non-effect, so the output of the positive-edge triggered D-type flip-flop 211 will not change, so The positive edge is touched, and the frequency selection control signal CLKSEL outputted by the output terminal Q of the 正-type flip-flop 211 remains in the output state of the previous time during D2, and is also the output frequency selection control signal CLKSEL (still It is 1) and is based on the binary signal S input to the input terminal D. If it is 0, as shown in Table 2, the binary signal received according to the input terminal D is 〇 and the positive rising edge (not recorded) received by the clock input terminal CK * will be triggered by the positive edge The D-type flip-flop 211 operates such that the output terminal Q of the positive-edge triggered 正-type flip-flop outputs a frequency selection control signal CLKSEL (the high-level state ‘ is also 1). When the input end A of the second two-to-one multi-guard 221 and the input end B' receive the first clock signal CLK1 and the second clock signal CLK2 generated by the clock generator, respectively. And as shown in Table 3, the second 2-to-1 multiplexer 221 selects the control signal CLKSEL (low level state, also 〇) according to the frequency from the output end of the second 2-to-1 multiplexer 221. z' outputs the first clock signal CLK1 to one of the input terminals of the OR gate 222. Meanwhile, during the period T3 of the 2Cth diagram, the X〇R gate 212 in the synchronous switch 20 200938991 controller 21 receives the binary signal S〇 (the low level state 'is also 〇) and The frequency selection control signal CLKSEL (the high level state 'is also 1) output by the positive edge trigger d-type flip-flop 211 is subjected to an X〇R operation via the XOR gate 212 to obtain a frequency output control signal CONTROL (high position) The quasi-state is also 1), and the frequency output control signal CONTROL (high level state, also being 1) is input to the other input terminal of the OR gate 222.
而在該可控制頻率輸出選擇器22内的該〇R閘222 分別接收來自該XOR閘212之該頻率輸出控制信號 ^ONTROL(高位準狀態’亦是為υ及來自該第二2對1 多工器22之該第一時脈信號CLK1，而該OR閘222因 接收該頻率輸出控制信號CLKSEL(高位準狀態，亦是 ，1)而在該OR閘222之一輸出端CL〇CK 〇υτ輸出一 局準位信號(亦是為1)，此高準位信號亦是在於時段τ3 期間内的一小段時間以稱之為另-等待時間_d tlme))。持續地，來自該第一 2對1多工器20之該第一 時脈信號CLK1從下降、雜態賴至上升料（自第4條 虛線起）’該脈輪入端CK所接收的上升緣(有效緣)進 一步觸發該正緣觸發D型正反器211動 至輸出該正緣觸發D型正反請之該輸出端= ，該正緣觸發D型正反器211依據該輸入端D所 一:=:S°(低位準狀態，亦是為〇)及該有效 = 發D型正反器211之該輪出端Q輸出 一頻率選擇㈣錢CLKSEL(低位準狀態，亦是為 200938991 〇)。 同時，來自時脈產生器所產生該第一時脈信號 CLK1及該第二時脈信號CLK2分別輸入至該第二2對 1多工器221之該輸入端A，及該輸入端B，。該第二2對 1多工器221依據來自該正緣觸發！）型正反器211之該 頻率選擇控制信號CLKSEL(低位準狀態，亦是為〇)= 輸出來自該第二2對1多工器221之該第一時脈信號 CLK1至該OR閘222之一輸入端。The 〇R gate 222 in the controllable frequency output selector 22 receives the frequency output control signal ^ONTROL from the XOR gate 212 (the high level state is also υ and from the second 2 to 1 The first clock signal CLK1 of the device 22, and the OR gate 222 receives the frequency output control signal CLKSEL (high level state, also, 1) at an output terminal of the OR gate 222, CL〇CK 〇υτ A level of level signal (also 1) is output, which is also a short period of time during the period τ3 to be called another-wait time _d tlme)). Continuously, the first clock signal CLK1 from the first two-to-one multiplexer 20 rises from a falling state, a hybrid state to a rising material (from the fourth dotted line), and the rise received by the chakra input terminal CK The edge (effective edge) further triggers the positive edge trigger D-type flip-flop 211 to output the positive edge trigger D-type positive and negative please the output terminal =, the positive edge trigger D-type flip-flop 211 according to the input terminal D One: =: S° (low level state, also 〇) and the valid = the D-type flip-flop 211 of the round-end Q output a frequency selection (four) money CLKSEL (low level state, also for 200938991 〇). At the same time, the first clock signal CLK1 and the second clock signal CLK2 generated by the clock generator are input to the input terminal A of the second 2-to-1 multiplexer 221, and the input terminal B, respectively. The second 2-to-1 multiplexer 221 is triggered based on the positive edge! The frequency selection control signal CLKSEL of the type flip-flop 211 (low level state, also 〇) = outputting the first clock signal CLK1 from the second two-to-one multiplexer 221 to the OR gate 222 An input.
而於時段T3期間（經時間^後），在該同步切換控 制器21内的該X0R閘212係分別接收該二進制信號 S〇(低位準狀態，亦是為〇)及由該正緣觸發D型正反器 221所輸出的該頻率選擇控制信號CLKSEL (低位準狀 態，亦是為0)，則該等兩信號So及CLKSEL·經該XOR 閘212進行一次x〇R運算，輸出一頻率輸出控制信號 CONTROL(低位準狀態，亦是為〇)至該〇反閘222之另 一端。 至此，在經r 1時間後，於該可控制頻率輸出選擇 器22内的該〇R閘222係接收來自該x〇r閘212之該頻率 輸出控制信號CONTROL(低位準狀態，亦是為〇)及由該 第一2對1多工器221所選擇出的該第一時脈信號CLK1經 一次OR運算後，因該OR閘222所接收的該頻率輸出控 制信號CONTROL為低位準狀態（亦是為〇)，故來自該第 一2對1多工器221之該第一時脈信號CLK1經該OR閘222 導通而在該OR閘之一輸出端CLOCK OUT輸出來自該第 22 200938991 一2對1多工器221之該第一時脈信號clki。 從上述内容可知，本發明時脈信號切換電路之與習知 技術的差異為，將由該石英振盪器此類型的時脈產生器 所產生的一第一時脈信號及一第二時脈信號一併輸入至 如取樣頻率選擇器此類型的—第—多玉器及—可控 率輸出選擇器，其中該第—多工器依據—具二進制之頻 率選擇信號的G或1賴式，相應地，輸出0或1的模式所 ❹ 對應的該第—時脈信號及該第二時脈信號之—而輸出至 一同步切換控制器（其中，同步切換控制器包含-脈衝緣 (edge)偵測器，該脈衝緣偵測器係為一正緣觸發或一負 緣觸發RS型正反器、一正緣觸發或一負緣觸發D型正反 器、一正緣觸發或一負緣觸發JK型正反器、一正緣觸發 ，一負緣觸發T型正反器之其中之一及一具布林運算功 能之第-運算邏輯單元，該第一運算邏輯單元係為一 又⑽閘、一XN〇R閘、一OR閘、一AND閘、一NAND 〇 閘、一N〇R閘、—NOT閘、一M0S其中之一），而該脈 ，，侦測器依據來自該第—多所輸出的該第-時脈 =及該第二時脈錢H有效緣之同步信號而輸 出具一進制之頻率選擇控制信號且該第一運算邏輯單 元依該頻率選擇信號的〇或1的數值進行一次布林運算以 輸出一具二進制之頻率輸出控制信號。 再者，已接收來自該時脈產生器之該第一時脈信號 及第二時脈信號之該可控制頻率輸出選擇器所包含的一 工器依據來自該脈衝緣偵測器之該頻率選擇控制 23 200938991 信號(〇或1模式）而相應地輸出該第一時脈信號及該第二 時脈信號之其中之—至該可控制頻率輪出選擇器所包含 的-具布林運算功能之第二運算邏輯單元(射，該 運算邏輯單元係為一X0R閘、一财⑽閘、一⑽閘、 一 ANDf甲1、一 NAND 閘、—N〇R 閉、—ν〇 一 MOS之其中之一）。 而具布林運算功能的該第二運算邏輯單元之二輸入 ❹端分難收來自該第—運算邏輯單元之_率^控制 信號與來自該第二多工器所選擇出該第—時脈信號及該 第二時脈信號之-，並依據該頻率輸出控制信號 數值)而決定是否輸出該第—時脈信號及第二時脈信號之 一，而在此該可控制頻率輸出選擇器内的第二運算邏輯 單元因進行_布林運算可決㈣料脈錢切換的時段 點，避免閃動(glitch)雜訊發生達到可控制該等時脈俨 之一的輸出。 ❹ 於本實施例中，該第二運算邏輯單元使用的〇尺閘 ’於進行-:欠OR布林運*如輸&_高辦錢(亦是為^ 為一等待時間，另一方面，該0R閘進行一次〇反布林運 算如輸出一低位準信號（亦是為0)則該〇R閘導通來自該 第二多工器所選出的該第一時脈信號及該第二時脈信號 之其中一，在第2C圖之波形說明圖式中具良好的驗證。〜 雖然在本實施例中’以石英振盪器所產生一第一時 脈<§號及一第二時脈信號為代表說明。但對於多個不同 頻率的時脈信號（以η個不同頻率的時脈信號為例，其 24 200938991 中，η係為大於1之正整數)欲輸入該時脈信號切換電路 時’則該第-多工器及該第二多工器則設計為具有、η個 輸入端用以分別接收η個不同頻率的時脈信號，相應 =第：多工器及該第二多工器皆設計為具有「—1個 選擇輸入鳊，如第3圖所示。 ❹ ❹ 最後’還須講述’於在第2C圖中所使用的任一之 換=觸;;用負=正反器’在本電路時腺信號切 之一輪出端回牛；從該正反盜之一輸入端到該正反器 時脈信號及該第該時脈產生器所產生的之該第一 步信號。且為所熟c其中之-之-有效緣之同 籌。在取樣㈣間不同，料影響本發明的範 限制本發明的用較佳實施例詳細說明本發明，而非 思而為諸般修飾，’、本案得由熟習此技術之人士任施匠 者。 然皆不脫本案申請專利範圍所欲保護 【圖式簡單說明】 第1B圖板:::知的時脈信號切換電路。 號之波形圖。 D的時脈信號切換電路而繪式該等信 第2a圖係續厂 。 不本發明之時脈信號切換電路之電路圖 25 200938991 第2Β圖係根據第2Α圖而繪示本發明之時脈信號切 、、，路之第—時脈信號CLK1、一第二時脈信號CLK2 一頻率選擇信號sQ、一頻率選擇控制信號CLKSEL& 頻率輸出控制信號CONTROL之波形圖。 第2C圖係根據第2；8圖之時脈信號切換電路而繪示 該時脈切換之—實現電路。 Ο 路圖2圖係’林發明之另—時脈信號切換電路之電 备輸入η個不同頻率的時脈信號至該第一多工器及 項第二多工器時）。 【主要元件符號說明】 10:2對1多工器； 12:第一時脈信號； 14:第二時脈信號； 16:控制信號； Q 18:信號線； 2.時脈彳§號切換電路； 20:取樣頻率選擇器； 21:同步切換控制器； 21 h脈衝緣(edge)偵測器； 212:第一運算邏輯單元； 22.可控制頻率輸出選擇器； 221:第二2對1多工器；以及 222:第二運算邏輯單元。 26During the period T3 (after the time ^), the XOR gate 212 in the synchronous switching controller 21 receives the binary signal S〇 (low level state, also 〇) and triggers D from the positive edge. The frequency selection control signal CLKSEL outputted by the type flip-flop 221 (the low level state is also 0), the two signals So and CLKSEL are subjected to an x 〇 R operation via the XOR gate 212, and output a frequency output. The control signal CONTROL (low level state, also 〇) is to the other end of the 〇 reverse gate 222. So far, after the r 1 time, the 〇R gate 222 in the controllable frequency output selector 22 receives the frequency output control signal CONTROL from the x〇r gate 212 (low level state, also 〇 And after the first clock signal CLK1 selected by the first two-to-one multiplexer 221 is ORed, the frequency output control signal CONTROL received by the OR gate 222 is in a low level state (also Therefore, the first clock signal CLK1 from the first two-to-one multiplexer 221 is turned on by the OR gate 222 and is outputted from the output terminal CLOCK OUT of the OR gate from the 22nd 200938991-2 The first clock signal clki to the 1 multiplexer 221. It can be seen from the above that the difference between the clock signal switching circuit of the present invention and the prior art is that a first clock signal and a second clock signal generated by the clock generator of the type of the crystal oscillator are And inputting to the first-type multi-jade and the controllable rate output selector of the type such as the sampling frequency selector, wherein the first-multiplexer is based on the G or the one of the binary frequency selection signals, correspondingly, Outputting the 0 or 1 mode corresponding to the first clock signal and the second clock signal - and outputting to a synchronous switching controller (where the synchronous switching controller includes - an edge detector) The pulse edge detector is a positive edge trigger or a negative edge triggered RS type flip-flop, a positive edge trigger or a negative edge triggered D-type flip-flop, a positive edge trigger or a negative edge trigger JK type a positive and negative device, a positive edge trigger, a negative edge triggering one of the T-type flip-flops and a first-operation logic unit having a Boolean operation function, the first operational logic unit being a (10) gate, a XN〇R gate, one OR gate, one AND gate, one NAND gate, one N R gate, - NOT gate, one of the M0S, and the pulse, the detector is based on the synchronization signal from the first-to-multiple output of the first-multiple output and the effective edge of the second clock And outputting a frequency selection control signal having a binary value, and the first operation logic unit performs a Boolean operation according to the value of 〇 or 1 of the frequency selection signal to output a binary frequency output control signal. Furthermore, the controllable frequency output selector that has received the first clock signal and the second clock signal from the clock generator selects a processor according to the frequency from the pulse edge detector. Controlling 23 200938991 signals (〇 or 1 mode) and correspondingly outputting the first clock signal and the second clock signal - to the controllable frequency wheel selector comprising - Boolean operation function The second arithmetic logic unit (the operation logic unit is an X0R gate, a finance (10) gate, a (10) gate, an ANDf A1, a NAND gate, -N〇R-close, - ν〇-MOS One). And the second input logic unit of the second arithmetic logic unit having the Boolean operation function is difficult to receive the _ rate control signal from the first operation logic unit and the first time clock selected from the second multiplexer Determining whether to output one of the first clock signal and the second clock signal according to the signal and the second clock signal, and outputting the control signal value according to the frequency, where the controllable frequency output selector is The second arithmetic logic unit can determine the time point of the (4) material pulse switching because the _Blining operation is performed, and the glitch noise is prevented from reaching the output that can control one of the clocks.本 In this embodiment, the second operation logic unit uses the 〇 闸 于 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行The 0R gate performs a 〇-relining operation, such as outputting a low level signal (also 0), the 〇R gate conducting the first clock signal selected from the second multiplexer and the second time One of the pulse signals has a good verification in the waveform description pattern of FIG. 2C. ~ Although in the present embodiment, a first clock generated by the quartz oscillator < § and a second clock The signal is a representative description. However, for a plurality of clock signals of different frequencies (for example, a clock signal of n different frequencies, in the case of 24 200938991, η is a positive integer greater than 1), the clock signal switching circuit is to be input. When the 'multiple multiplexer and the second multiplexer are designed to have η inputs for respectively receiving n different frequency clock signals, corresponding = first: multiplexer and the second more The tools are designed to have "-1 selection input" as shown in Figure 3. ❹ ❹ Last' must also tell 'In any of the switches used in Figure 2C = touch;; with negative = flip-flop 'in this circuit, the gland signal cuts one round out of the cow; from one of the positive and negative stolen inputs to the The positive and negative clock signals and the first step signal generated by the first clock generator, and are the same as the effective edge of the cooked c. The difference between the sampling (four), the material affects the invention The invention is described in detail with reference to the preferred embodiments of the present invention, and is not intended to be construed as being modified. The present invention may be employed by those skilled in the art. [Simple diagram of the diagram] 1B board::: Known clock signal switching circuit. Waveform of number. D clock signal switching circuit and drawing of the letter 2a is a continuation of the factory. Circuit diagram of clock signal switching circuit 25 200938991 The second diagram shows the clock signal cutting, the first-clock signal CLK1, the second clock signal CLK2, a frequency selection signal of the present invention according to the second drawing. sQ, a frequency selection control signal CLKSEL & frequency output control signal CONTROL wave Fig. 2C is a circuit diagram showing the clock switching according to the clock signal switching circuit of Fig. 2; Fig. 2 is a circuit diagram of the other circuit of the invention. Input n different frequency clock signals to the first multiplexer and the second multiplexer.) [Main component symbol description] 10: 2 to 1 multiplexer; 12: First clock signal; : second clock signal; 16: control signal; Q 18: signal line; 2. clock 彳 § number switching circuit; 20: sampling frequency selector; 21: synchronous switching controller; 21 h pulse edge detection Detector; 212: first operational logic unit; 22. controllable frequency output selector; 221: second 2-to-1 multiplexer; and 222: second operational logic unit. 26