TW200935303A - Strand-based computing hardware and dynamically optimizing strandware for a high performance microprocessor system - Google Patents

Abstract

Strand-based computing hardware and dynamically optimizing strandware are included in a high performance microprocessor system. The system operates on real time automatically and unobservably to parallelize single-threaded software into a plurality of parallel strands for execution by cores implemented in a multi-core and/or multi-threaded microprocessor of the system. The microprocessor executes a native instruction set tailored for speculative multithreading. The strandware directs hardware of the microprocessor to collect dynamic profiling information while executing the single-threaded software. The strandware analyzes the profiling information for the parallelization, and uses binary translation and dynamic optimization to produce native instructions to store in a translation cache later accessed to execute the produced native instructions of some of the single-threaded software. The system is capable of parallelizing a plurality of single-threaded software applications (e. g. application software, device drivers, operating system routines or kernels, and hypervisors).

Description

200935303 IX. Invention Description: [Technical field of invention] Improvement of efficiency and use efficiency Improvements in computer processing are required to provide good performance. [Prior Art] Unless explicitly identified as public or well-understood, (including the context of the context, definitions, or comparisons, the techniques and concepts are previously publicly known, '', interpreted as A Or otherwise the previous section. All references cited in this document, including the patents, patent applications, and publications, are hereby incorporated by reference in their entirety in their entirety. SUMMARY OF THE INVENTION The present invention can be implemented in a number of ways, including as a program, a device, a device, a system, and a computer readable medium (eg, an optical and/or magnetic mass storage device (eg, a disc) Medium in the medium or integrated circuit with a social storage (such as flash memory). In this specification, this embodiment (or any other form that the invention may take) may be practiced. MODE FOR CARRYING OUT THE INVENTION The present invention is embodied in a more detailed discussion of the technical efficiency and utility of the invention as identified above in the technical field identified above. All possible modifications and variations within the scope of the scope. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following detailed description of selected embodiments of the invention, together with The invention is described with respect to such specific 136, 758.doc 200935303. The specific embodiments herein are obviously not limited to the specific embodiments herein; for example, the present disclosure is limited thereto, m aa & ^ {what or all or the invention includes many substitutes to avoid Thousands of laws - can apply a variety of words ^ and so on ^ are not limited to): first -, last ..., various, two including (but fixed, selected Gan - grain, other, other, special use = special) to distinguish the specific embodiment set - this article

Prejudice, and: Obviously it does not mean to convey quality or any form of preference or to see and distinguish only the different sets. The order of a certain soap operation of the disclosed procedures can be varied within the scope of the invention. Where a plurality of embodiments are used to illustrate changes in the characteristics of the program, method, and/or program instructions, it is contemplated that other embodiments are directed to a plurality of the specific embodiments, respectively, in accordance with a predetermined or dynamically determined criteria. Static and/or dynamic selection of one of a plurality of modes of operation. In order to fully understand the present invention, numerous specific details are set forth in the description below. The details are provided for the purposes of example and the invention may be practiced without departing from the scope of the invention. The technical material related to the present invention in the technical field, and the head is not described in detail in order to avoid obscuring the present invention in vain. Overview Terminology The terminology used in this article uses various terms. The following are examples of at least some of the terms. The example of a thread is the software abstraction of the processor, such as the dynamic sequence that is shared and executed immediately after being in the same architectural machine state (such as the software visible state). Some (so-called single-thread) processors are enabled to execute a sequence of instructions on an architectural machine state. Some (so-so-so-executive) processors are enabled to execute N instruction sequences on N architectural machine states. In some systems, the operating system is equipped with hardware, destruction, and scheduling threads. An example of a string is an abstraction of the processor hardware', such as a dynamic micro-opcode that is shared and executed immediately after being in the same machine state (e.g., by a processor)

The hardware can be directly executed by the micro-operation) sequence. For some strings, the machine state is the state of the machine (such as the architectural scratchpad state) and is not visible to some of the stringer states (for example, the scratchpad state or the performance analysis register). In some embodiments, if the machine state of the string includes all architectural machine states of the thread (eg, the general-purpose scratchpad 'software accessible machine state register and memory state'), the string operating system is visible of. In some embodiments, even if a string of machine states includes all of the architectural machine states of the thread, the string is not visible to the operating system. (4) The example of the string is visible to the operating system and corresponds to the thread of the thread. An example of a push string (e.g., a successor string) is an invisible string of operating systems. Some strings contain only hidden machine states (e.g., pre-fetch or line-by-line analysis)> in some embodiments, string and/or processor hardware builds, destroys, and schedules. In some embodiments _ 'Make a string again. Some points:: For the specified target address (for the string created by the branch) and optionally specify other information (such as 'data to be inherited as machine state') (upper generation string) The micro-opcode responds. When executing the (pre-generation) string of micro-ops, I36758.doc 200935303 optionally constructs a speculative successor string. In various embodiments and/or usage scenarios, the micro-ops are eliminated. Reversing the string by one or more of the unrecoverable errors and the completion of the string (eg, via federation). In some embodiments and/or usage scenarios, the joint micro-computing code is responsive to the combined string. In an embodiment and/or or usage scheme, a set of hardware detection conditions (e.g., a current execution address that matches the start address of a successor string) is echoed. In various embodiments, 'by string And/or any combination of hardware (such as responding to processing (4) calculations or responding to the conditions specified by the program or the program itself). Destroy the string. In some usage scenarios, by placing a string of a previous generation The machine state merges with the machine state of one of the previous generations; then the previous generation is destroyed and the next generation string becomes a string of architectures. The virtual central processing unit (v CPU) example is enabled for the operating system. A software-readable execution context on which a thread is scheduled at any given time. In some implementations, the computer system will see ❹ or multiple VCPMs 5 see the operating system and system. Scheduling the state of the machine - the scratchpad portion, and in some embodiments, sharing the architectural memory state between _ or multiple VCPUs. Conceptually each includes one of dynamically built by the string and/or hardware or Multiple strings. For each VCPU, the strings are configured in a first-in, first-out (FIF0) queue, where the next string of architectures to be submitted to the VCPU and all other strings are speculative. Multi-core, multi-threaded and Microprocessors, multicores, and multi-threading have been growing since the introduction of the first microprocessor in the 1960s. 136758.doc 200935303 has grown. Some microprocessors have deep pipelines and/or more The GHz clock frequency operates to extract performance from a sequential program using a single processor. The software coin is written as a sequence of instructions and operations that are executed sequentially and/or sequentially by the processor. Increasing the performance of the program by operating at increased clock frequency, out-of-order (〇◦〇) execution of instructions, speculative execution of instructions, or various combinations thereof. Some instructions are independent of other private orders and thus provide instruction levels. Parallelism (ILP), and therefore can be parallel or

〇〇〇 Execution. Some microprocessors attempt to use ILP to improve performance and/or increase the utilization of functional units of the microprocessor. Some microprocessors (sometimes referred to as multi-core microprocessors) have one (e.g., processing unit). Some single-chip implementations have a full multi-core microprocessor that has shared cache memory and/or other hardware shared by the cores in certain execution entities. In some environments, an agent (e.g., a string) divides computing tasks into threads, and some multi-core microprocessors are more efficient by executing the threads in parallel on the core of the microprocessor. Some microprocessors, such as some multi-core microprocessors, have a core that is enabled with simultaneous multi-threading (SMT). Some microprocessors that are compatible with the X86 instruction set (such as some microprocessors from and from) have a phased-to-core copy. Some microprocessors (such as some microprocessors from Sun and coffee) have relatively many replicas of (relatively simple) ordered cores. Some word processors and multi-media applications are multi-threaded, and some microprocessors with relatively many cores are relatively well implemented on multi-threaded software. Some multi-core microprocessors are relatively well implemented on software with relatively high level of parallelism, I36758.doc 200935303 (TLP). However, in some environments, certain resources of some multi-core microprocessors are not used even when executing software with relatively high TLPs. Efforts to improve TLP software engineers using mechanisms to coordinate access to shared data to avoid collisions and/or incorrect behavior 'by reducing or avoiding linkages between threads to ensure a smooth and efficient parallel chain mechanism and assist in multiple executions The mechanism for debugging errors in the implementation scheme.

Relative to some problem areas, some compilers automatically recognize a seemingly sequential operation of a thread as a parallel thread that can be divided into operations. Some operational sequences are indeterminate relative to independence and may be used for parallel execution (e. g., portions of code generated from some common stylized languages (eg #c, c+MJava)). Software engineers sometimes use some special-purpose programming languages (or parallel extensions of general-purpose programming languages) to express parallelism and/or multi-core and/or multi-threaded microprocessors or parts thereof (such as graphics processing). Saponin or GPU). Software engineers sometimes express parallelism for certain scientific, floating point, and media processing applications. Predicting the basic principles of multi-threading In some usage scenarios and/or specific embodiments, it is speculated that multi-execution 4, thread-level speculation, or both achieve more efficient auto-parallelization. In the multi-threaded microprocessor system, the compiler software, string body, tough side microcode or microprocessor hardware single open basin stomach early 7" or its (four) combination will be a plurality of class 3 knife One or more of the selected ones of the instructions are inserted into various locations of the formula. Conceptually, the system - the system begins executing one of the (new) successor strings at the target address of the program, and the value of the scratchpad value (and the storage of the I) is from the (previous generation) string. (Subsequent stringing from the (previous generation) stringing again), 'string propagation. The propagation is based on stopping the successor string until the equivalent or by predicting the value and comparing the predicted value with the value generated by the previous generation string. The system acts as a subset of the thread to establish a successor string that receives a subset of the architectural state and/or subsequent threads from the thread. The fork instruction specifies the target address: 日 "RIP". The 35 system is implemented in various embodiments by various hardware components (eg, logic unit, finite state machine, microcode engine 3 circuit), various Software components (such as kernel-executable instructions, firmware two-exhaustion, serials, and other software agents) or various combinations thereof implement string functions (such as splits and unions). People speculate multi-thread micro-processing The system uses the (original) program order to process the "stay." Consider the succession of the string and the string of the destination address. Co-occurs when the previous generation executes directly to the target address (sometimes called the intersection). In some environments, the successor string has been completed (parallel to the previous generation string) and the subsequent string is erected/prepared. At the ear burial point, the system performs various consistency checks, for example. = The (possibly predicted) external register value of the succession string is transmitted to the successor string at the joint point. These checks ensure that the results of the execution of the series and the string are the same as those of the undivided and string. If any of these checks fail, the system takes the appropriate action (for example, by discarding the separate string 2). After the combination of the previous generation and the successor _, the previous generation string is terminated. The system then makes the context of the = previous generation string available for reuse. The successor string becomes the system establishment. The architecture of the thread to which the δ 串 string is directed can be seen as an execution entity. The system makes the current architectural state of the successor string (such as the scratchpad and the memory) the other bindings of the I36758.doc -13- 200935303 in the microprocessor (for example, the executor of the microprocessor on the other core) Other agents (such as DMA) and devices external to the microprocessor can be observed. Some speculative multi-threaded systems implement nested string models. For example, the previous generation • _P points are mainly post-materials, and are separated by phase. The string π, like... system nests the substrings in the upper generation string. The substrings are independent of 8 and are executed independently of each other. After all the substrings are completed, they are conditionally combined with s immediately. Implement a non-I-type speculative multi-threaded model with strict program ordering. For example, 'the upper generation string ρ has at most one point and the subsequent string Sel^s intersection (causing joint) or S at any time. The ρ is no longer divided before the execution. In some environments, the “= nested model uses less and/or more single hardware than the non-nested model. The unmodified sequential program is used. Some usage scenarios are suitable for combining non- The use of a nested model implementation. Some speculative multi-threaded systems use memory version management. For example, (presumably) a successor string stored to a specific memory location is used as a program to "speak more than a successor string." Observe but the other strings (which are in the order of the program. : The system is earlier than the successor string). The private version of this position is unobservable. In the joint 7 and the previous generation, the constellation makes the speculative storage available to other agents. Atomic mode. Other agents include different strings (or DMA) from subsequent (and later) strings, microprocessors, devices and systems external to the microprocessor to access any component of the memory. In some environments, the system accumulates thousands of bytes of data before the joint. Consider one of the upper strings (later in terms of program order) to write to the memory location and the upper generation string A subsequent string is to read the memory bit 136758.doc 200935303. If the successor string reads the position of the beta memory before the previous string is written to the memory location, the system stops the successor string. Uncovering the content sometimes refers to the above-mentioned f-state as confusing across string memory. In some scenarios, the system reduces (or avoids) the occurrence of cross-string memory confusion by selecting to reduce (or avoid) the occurrence of cross-string memory confusion. Crossing the string memory. =Up, the system configures the string belonging to the specific thread to the individual order of the reordering buffer (R0B) similar to the out-of-order processing 11. The system processes the sequence according to the program sequence. And the union. The string at the head of the queue is a skeleton string, and is enabled to perform a unique string of joint operations, and the subsequent string is a speculative string. In some schemes, the string contains complex control flows independent of other strings (eg Branches, Calls, and Loops. In some circumstances, the string performs thousands of sums between establishment (at the point and point) and termination (at the joint point). In some cases, even if there are relatively few unprocessed strings, the string parallelism is relatively large. It can be used by thousands of instructions. Some (4) use speculation based on a variety of purposes (such as pre-fetching). Multi-lighting, while some systems use speculative multi-threading only for pre-fetching. For example, a particular string encounters a cache miss when executing a load instruction that results in a relatively slow access to the cache or the master. The system self-loading instruction divides the t-string ' and stops the specific string. The system continues to stop the specific contention while waiting for the returned data to be (missing) loaded. Unlike some other types of strings, missing loads are not blocked. It is compensated for the provision of predictions or dummy values. In various usage scenarios, pre-fetching string b is pre-fetched for 136758.doc 200935303 with a location independent of the initial miss loading; for pre-fetching, tuning or pre-processing with the processed linked list Correct the branch predictor; or any combination thereof. Spring loading makes compensation (for example, due to pre-fetching the use of predictions or virtual ^ and is not suitable for union to another string), the suspension of the missed loading in response to the pre-fetching _ ^ people (in some environments) via Speculative improvement in performance achieved by multi-threading

Depends on the specific choice of points and joint points. In some embodiments, the system places points and points at the point where the 丨M path finally arrives: (where all possible paths are executed.). For example, the current repetitive process relative to the loop, lteratlon)' system, starts with a string that follows the repetitive process of the current repetitive process, thus implementing the two strings in whole or in part. (4) Another example (for example, when the repetitive processes of the loops are mutually dependent), the knives are _ to execute the code following the end of the loop, and the repetitive process of the loop is executed in a string and the loop is followed by The code is executed in another string. For another example, the system is divided into another string to start executing the code following the return of a self-operating function. (If necessary, predict the called function, til a TM The called function and the following return code are executed in parallel by two parts or parts. In various embodiments, the following points are inserted by: or by the compiler and/or the string automatically (as needed, based at least in part on line-by-line analysis execution, analysis of dynamic program behavior or both) by hardware automation; and by programmers manually. Various embodiments of the implementation of the system are automatic and/or not 2 $ some automatic and / or unobservable speculation multi-threaded implementation 1 ', σ applied to all types of target software (such as application software, 136758.doc -16- 200935303 device driver, operating system routine Core and hypervisor) without any programmer intervention. (Note that sometimes the target software is called the target code and the target code contains the target instructions.) Some automatic and/or unobservable speculation multi-threading Specific embodiments are industry standard instruction sets • r (eg x86 instruction set), industry standard programming tools or languages (eg c, C++ and other languages) and industry standard general purpose computer systems (eg server, workbench, table) Compatible with computer and notebook computer. System architecture φ System with computer capable of string capability Figure 1A illustrates a system with a string capable computer. Each computer with string capability has one or more microprocessors with string capability. A serial-capable microprocessor can access serial images, memory, non-volatile memory, input/output devices, and networks. Conceptually, the system performs a string to observe (via hardware assistance) and analyze target software. (eg application, driver, operating system and hypervisor software) (eg χ86) dynamic execution of instructions. It is determined how to split the χ86 instruction into a plurality of strings on the VLIW core resource of the microprocessor that is executed in parallel for the .. string-sequencing capability. The string translates the segmented instruction into an operation (eg, micro-operation or micro-operation code). And then 'configure the operations in the bundle for efficient execution on the VLIW core resource. The string is stored in the translation cache for later use (eg as - or township (4) Translating the translation needs to include additional operations that do not directly correspond to the X86 instructions (eg, to improve performance or to implement parallel execution of the string). The system then targets the stored bundle (eg, a string image rather than a portion of the X86 instruction). Performing the configuration and executing the stored bundle to try 136758.doc 200935303 to improve performance. In some embodiments, observing, analyzing, segmenting, and executing one or more of the stored bundle configurations and the stored bundles Relative to the trace of the instruction. The figure illustrates a string capable computer 2000.1 to 2000.2 that is enabled for communication with each other via couplings 2063, 2064 and network 2009. The string capable computer 2000.1 is coupled to the memory 2010 via the coupling 2050, to the keyboard/display 2005 via the coupling 2055 and to the peripheral device 2006 via the coupling 205 6 . This network is any communication infrastructure that enables communication between computers with serial capabilities, such as any combination of regional network (LAN), metropolitan area network (MAN), wide area network (WAN), and the Internet. The coupling 2063 is associated with, for example, an Ethernet network (eg, l〇Base-T, 100Base-T, and 1 or 10 billion bits), an optical network (eg, a synchronous optical network or SONET), or a node for clusters. Connection mechanisms such as Infiniband, MyriNet, QsNET, or blade server backplane networks are compatible. The storage component is any non-volatile mass storage component, array or network thereof (such as flash memory, disk or CD, and via network attached storage or NAS and / or storage array network or SAN technology) The coupled component). The coupling 2050 is compatible with, for example, Ethernet or optical networking, Fibre Channel, advanced technology attachment or port, serial port or SATA, external SATA or eSATA, and small computer system interface or SCSI. The keyboard/display component concept represents any type of one or more of alphanumeric, graphic or other human input/output devices (eg, a combination of a QWERTY keyboard, an optical mouse, and a flat panel display). The Coupled 2055 Conceptual Generation 136758.doc -18- 200935303 table implements one or more aspects of communication between a string capable computer and a keyboard/display. In the example, one of the components of the face 2055 is compatible with the universal serial bus (USB) and the other component is compatible with the video graphics adapter (VGA) connector. The Peripheral Component Symbol concept represents any type (eg, scanner or printer) that can be used with one or more I/O devices in conjunction with a computer with a string of forces. The 2056 Series concept represents one or more couplings that enable communication between a computer capable of string capabilities and peripheral devices. In various embodiments (not illustrated), various components (eg, memory 2 Q i Q, keyboard/display 2 〇〇$, and peripheral device 2006) that are external to the brain having string capabilities are included in the string. The ability of the computer. In some embodiments, one or more of the serial-capable microprocessors 2〇〇1丨 to (9)(1)2 are included to enable coupling to elements functionally and functionally external to the computer having string capabilities. Any hardware of the same or similar components. In various embodiments, the hard system included is compatible with one or more specific protocols, such as peripheral component interconnect (pci) bus, pci extension (PCI_X) bus, PCI Express (PCI-E)® One or more of the bus, hypertransport (Ητ) bus, and fast path interconnect (QP1) bus. In various embodiments, the hard system included is compatible with a proprietary protocol for communicating with the (intermediate) chipset, enabling the (intermediate) chipset to communicate via any one or more of the specific protocols. . In some embodiments, the computer with string capabilities is identical to each other, and in other embodiments the computer with string capabilities varies depending on market and/or consumer needs. In some embodiments, a computer with a string of powers is used as a server, a workbench, a desktop computer, a pen, and a personal or portable computer.乂1^1\¥核2013.1 and transaction memory 2〇14 As illustrated in the figure, the computer with string capability 2〇〇〇1 includes two microprocessors with string capability to let ^(1) view.2, _ to the dynamic random access memory (DRAM) component fine 2. i to 2 surgery. 2. The microprocessor capable of communicating with each other communicates with the flash memory 2003 via the facets 205 i. i to 2 and communicates with each other via the coupling 2Q53. The microprocessor (200) having the capability of (4) includes a progressive analysis unit 2〇111, a string management unit 2〇121, and in some embodiments, a microprocessor having a string capability, and in other specific embodiments, has a contention The microprocessor of capabilities varies depending on the market and/or consumer needs. In various embodiments, a microprocessor capable of string capability is implemented in any of a single integrated circuit crystal, a plurality of integrated circuit dies, a multi-die module, and a plurality of packaged circuits. For the sake of brevity, the following description is in relation to the illustrated microprocessor capable of string capability. Other microprocessors with string capability and string capability are similar. The serial-capable microprocessor 2〇〇ΐι exits the reset state (for example, when a cold boot is performed) and begins to extract and execute the string from the code portion of the serial image 2004 included in the flash memory 2003. instruction. The execution of the instructions initializes various string data structures (e.g., the string data 2〇〇21A and the translation memory 2〇02.1B, which are part of the DRAM 2002.1). Initialization includes copying all or any subset of the code portion of the string image to a portion of the string data and setting the side regions of the string data for the stacked 'stack and private data storage. 136758.doc -20- 200935303 The microprocessor with string capability then begins processing the χ86 instructions (such as the χ86 boot firmware included in the flash memory in some embodiments), which is observed by the party (at least in part) Through the line-by-line analysis unit 2〇111) and points•#. The processing is further subjected to the above-described splitting into strings for parallel execution, translation into operations, and configuration in bundles corresponding to various string images and storage in a cached cache (eg, translation of cache memory 2〇〇) 2,1Β)). The processing is further performed by the party in response to the subsequent configuration of the stored bundle and the execution of the stored bundle (at least in part via the string management unit 2012.1, VLIW core 2013.1 and the variant memory 2014). The division of elements illustrated in the drawings is merely illustrative as there are other specific embodiments that employ other divisions. For example, various embodiments include all or any portion of flash memory and/or DRAm in a microprocessor capable of string capability. For another example, various embodiments are included in a string capable microprocessor (eg, in one or more static random access memories or SRAMs on an integrated circuit die) for use in string data and/or Or translating φ to cache all or any part of the memory of the S. For another example, in some embodiments, the string data 2〇〇21 8 and the translation cache memory 2102.1B are included in different DRAMts (eg, one in the first double inline. The memory module or The DIMM and the other are in the second DIMM). For another example, various embodiments store all or any portion of the string image on storage 2010. Large-capacity multi-threaded hardware and serial diagrams Figure 1B and 1C illustrate the 136758.doc 21 200935303 related to a microprocessor with string capability (such as any of the microprocessors with string capability). Body, string body (soft body) and target software layer (for example, the sub-wire type is conceptual in nature, and (4): such as: system). The figure controls and some (four)_he. 4_See' This figure omits various 1 2::'9. Including one or more independent cores (eg, vliw cores (9) to _τ) and /: singular entities), each core implements one or more hardware threads according to a multi-threaded two-dimensional context switch The context of the content (for example, stored in the register slot case .... (4) and, or in the execution entity of the string contents π 194Β.1 to ι94Β.4). The microprocessor is enabled to execute instructions in accordance with the 6-set architecture. The microprocessor includes speculative multi-thread extensions and enhancements, such as hardware, inter-thread, and inter-bank register propagation logic and/or circuitry for implementing separate and joint instructions and/or operations (multi-core internet) Road 195), the implementation of memory version management and conflict detection capabilities, δ mnemonic 183, progressive analysis hardware 181 and other hardware components to achieve speculative multi-threading processing. In the illustrated embodiment, the microprocessor also includes a multi-layer cache memory hierarchy (eg, L1 D cache memory 193.1 to 193.4 and L2/L3 cache memory 196 execution entities), to One or more interfaces of a large-capacity memory and/or a hardware device external to the processor (a DRAM controller coupled to an external system/serial DRAm 184A and a north bridge 197), for example, having a plurality of microprocessors ( Each of the microprocessors optionally includes a plurality of cores in a computer-to-socket system interconnect (multi-socket system interconnect 198) and interface/coupling to external hardware devices (for external PCI Express, QPI) , Super Transmission 199 coupled chipset / PCIe bus interface 186). The string layers 110A and 110B (sometimes collectively referred to as string layer no) and (χ86) target 136758.doc -22- 200935303 software layer 101 are at least partially included in the microprocessor and/or coupled to one of the microprocessors All or any portion of a plurality of cores (e.g., any of the execution entities of Figures 1 CiVLIW core 191 > 1 to 191 4) is executed. The string layer is not visible to the components of the target software layer, conceptually "under the target software layer" and/or "at the same level as the target software layer"" transparent operation. The target software layer includes the operating system core 102 and the narration system "execution system core" top "execution program (illustrated as the execution entities of the applications 103.1 to 103.4 in various specific embodiments and/or usage scenarios, The target software layer includes - managing a plurality of operating system execution individual hypervisor programs (eg, similar to VMware or Xen). In various embodiments, the stratum layer implements one or more of the following capabilities: to virtualize one or more The CPU (e.g., vcpu 1〇41 to 〇46 execution entities) and associated virtual device 174 present virtualization of the microprocessor hardware to the target software. The VCPU appears to execute - where the target instruction set of the target soft layer is encoded. Dynamic mapping of the VCPU to the native core of the microprocessor (eg, enabling execution of the native instruction set _191" to the execution entity of 191.4) and the string context (which holds (10) as in the case of the temporary register .4 and/or string content 194 Β ι ^ 94 Β β one or more executing individuals). In the case of Ding/Software, the tool and equipment of the target software, the line-by-line analysis and the branching line are used to identify the individual sequence of dividing the (sequential) instruction stream into more speculations: for example, the system will be executed by ― or more The sequence instruction stream is divided into a plurality of speculative multi-thread strings. 136758.doc -23- 200935303 • Inserting instructions and/or code sequences into the target software based on the analysis to invoke the various speculative multi-thread hardware units of the microprocessor to divide and combine strings, predict and/or The live in value is propagated to the string to manage the memory version and the conflict between the strings and to pre-fetch the string. • Optimization of target software to speed up speculative multi-threading performance acceleration, * for example, rescheduling instructions to generate key string resident values, delays, and/or reordering to suppress parallelism earlier in time to destroy Or eliminate cross-string dependencies and remove memory obfuscation, and remove redundant ❹ operations within the pre-fetched string. • Maintain a repository of modified, tooled, and/or optimized code (eg, via Translate Cache Management) so that the code in the repository is invisible to the target code and is Can be used to replace the original target code (such as modifying, tooling, or part of the target code before optimization) by the string call. • Handling any intrinsic anomalies or mistakes's repairs, tools, equipment, and most The result of any of Jiayi (such as speculative multi-threading) will not occur when executing the target software. In some environments, internal exceptions or errors are handled including re-optimization and/or deactivation. Optimize performance • Provide an optional mechanism to the target code to provide hints for the string, such as possible points, synchronization points, possible cross-string confusion points, and other optimization information. Dynamic Optimization In some embodiments, the microprocessor hardware is enabled to execute - internal instructions that are different from the instruction set of the target software [in various embodiments 136758.doc -24- 20093 5303, 'Require to cooperate with any combination of multiple hardware acceleration mechanisms: Implement dynamic binary translation (for example, via χ86 binary translation 1丨$) to:: or multiple target instruction sets (eg χ86 compatible) The set of instructions, such as χ86_. 64♦"sets, is translated into native micro-ops (micro-ops). The software acceleration mechanism includes line-by-line analysis of hardware 1 8 1 , hardware acceleration unit i 82, transaction. ^ Recalling the body 183 and the hardware 386 device - or a plurality of all or any of the # knife microprocessor hardware (such as the VLIW core 191.1 to 191.4 execution individual) is enabled to directly execute the micro-opcode (and in various In a specific embodiment, the microprocessor hardware is not enabled to directly execute one or more of the target instruction sets. At least in some circumstances, the translation is then stored in a repository (eg, via a translation cache) Memory management 111) is used for fast re-calling and reuse (eg, as an image) to eliminate re-translation. In various embodiments, the microprocessor is enabled for access (eg, by coupling or attaching) Relatively large The system is via a dedicated DRAM module (which is included in the microprocessor or external to the microprocessor in various embodiments) or alternatively as an external system/invisible to the target code. The memory area is implemented by a portion of one of the reserved areas of the serial DRAM 184A. The memory area provides a memory for various components of the string (eg, one or more of program, code, stack, stack, and data) and In some embodiments, one or more portions of the cache memory (e.g., by the manager of the translation cache) are provided, and one or more buffers are optionally provided (e.g., speculation) Threading the temporary status buffer.) When the microprocessor is initially powered on (for example, by performing a cold boot), copy the serial code from the flash ROM to the memory area (eg to the dedicated DRAM module 136758.doc) -25- 200935303 or the external system/serial DRAM said in the reserved portion), the microprocessor then extracts the native micro-ops from the memory region. After the string initialization micro-processing W, for example, via hardware control 172) and the internal data structure of the string, the string body begins to perform a 'boot boot and' or operating system core boot program using binary translation (eg, via χ86 binary translation 115). The code (encoded in - or more of the target instruction set) is similar to a conventional hardware-based microprocessor without a binary translation layer. In some cases, the use of a string to perform binary translation and/or dynamic optimization provides advantages over the addition of speculative multi-threaded instructions to the target instruction set. In some environments, binary translation and/or dynamic optimization (for example) by removing and/or reducing hardware used to decode the target instruction set (eg, hardware secret decoder 187) and for out-of-order execution The hardware implementation simplifies the hard work. In some embodiments, 'conceptually employed' or multiple VLIW (ultra-long instruction word) microprocessor cores (eg, execution individuals of vli 191" to (9)*) Replace the removed and/or reduced hardware. The vuw core φ (for example) performs a bundle of pre-scheduled micro-ops, where all the micro-operations of the bundle are coded (eg in a plurality of functional units (eg ALU 192 to 192 especially 4 and FPU 192B. 1 to 192B.4) The execution of the individual) is performed in parallel (or starting to execute.). In various embodiments, the VLIW core lacks one or more of relatively complex decoding, hardware-based dependency analysis, and dynamic out-of-order scheduling. The VLIW core needs to include native memory (eg #li d cache memory 193) to 193.4 and the executable file of the temporary file 194Α.β194Α.4) and other per-core hardware structures for efficient processing. instruction. In some usage scenarios and/or specific embodiments, the VLIW core system is small enough to 136758.doc -26 - 200935303 to achieve the following - or the guest to go. Gland seedlings eve ^ 夕 夕. Counting cores in a given grain region, for more cores within a given power budget, and for frequencies that are higher than would otherwise be possible for a complex disordered core. In some implementations and/or specific embodiments, the VLIW core is semantically isolated from the target instruction set via binary translation to implement the micro*$code format, the scratchpad, and the VLIW core associated with efficient speculative multi-threading. Efficient coding of various details without modifying the target instruction set. The role of the string dynamic optimization software The tracking construction subsystem of the string layer (eg, tracking progressive analysis and capture 120) collects and/or translates the translated microcode (eg, has passed through) when executed by the microprocessor. The micro-ops of the sequence of the translated basic blocks of the common control flow path of the object code are organized into traces. The string is relatively extensively optimized using a wide variety of techniques (e.g., via optimization 丨 63). Some techniques are similar in scope to techniques that are implemented by optimized compilers that have access to the source code, but are used in line-by-line analysis (eg, line-by-line analysis by physical page 121, branch-by-line analysis 124, At least some optimizations are guided by the program behavior of the dynamic measurements collected during predictive optimization 125 and one or more of memory progressive analysis 127. For example, selective reordering (e.g., based on information obtained via memory obfuscation analysis 162) to the load and storage of the memory initiates a cache miss as early as possible. In some embodiments, 'selective reordering is based, at least in part, on loading and storage measurements with reference to the same address (e.g., via memory progressive analysis 127). In some usage scenarios and/or embodiments, selective reordering achieves relatively aggressive optimization across hundreds of instructions. Then, depending on the input, when the operand will be available and various hardware resources (such as functional units) will freely schedule the micro-ops (for example, by interpolating each micro-code 165)

To schedule). In some embodiments (e.g., with some specific embodiments having functionality illustrated by encoding a VLIW beam 167), scheduling attempts to encapsulate up to four micro-ops in each bundle. Having a plurality of microcodes in a bundle causes a particular VLIW core (e.g., any of the VLIW cores 191.1 through 191.4) to be able to perform the micro-operations when the scheduled tracking is performed later.

Weight. Finally, the optimized tracking (with VLIW bundles each having one or more micro-ops) is inserted into the repository as all or part of the string image (e.g., via translation cache memory management U1). In some embodiments, the hardware only performs native micro-ops from the traces stored in the translation cache, thereby enabling continuous reuse of the optimization performed by the string. In some usage scenarios and/or embodiments, depending on, for example, how often to perform a tracking, continuously re-optimizing tracking through a series of increasingly high performance optimization levels, the levels are relatively more expensive. Implementation (eg via promotion 13〇). In some embodiments, the dynamic optimization software achieves some relatively aggressive optimization via the use of atomic execution. In some environments, a relatively actively optimized execution entity will, in the absence of atomic execution, "unsafe", ::: will result in incorrect modification of the state of the architecture. One example of atomic execution changes the state of the architecture. Groups of micro-computing codes (referred to as submitting cross-groups?) '?_divisible units...tracking as needed—or multiple mentions often = submit group All micro-ops are correctly completed (for example, no "often or wrong)', according to the conclusion of all micro-computing codes of the submitted group I36758.doc -28- 200935303. For the architectural state, who is the cup_a few micro-operations two: ΓΛ In other contexts, the structure state of the drop-off group is changed relative to the result of submitting the group. For example, in one of the submitted groups

In the event that one of the micro-codes is abnormal (for example, a page misses or a branch that follows a path different from the path along which the initial trace was followed), a turn occurs and discards all micro-opcodes generated by the commit group. All the results. In some embodiments and/or usage scenarios, after the slewing, the microprocessor and the 'or string are re-executed in the original program order (and optionally without one or more optimizations) corresponding to Submit the group's microcode instructions to find out the source of the anomaly. Titled "Method and

The copending U.S. Patent Application Serial No. 1/994,774, the entire disclosure of which is incorporated herein by reference. In some embodiments and/or usage scenarios, the hardware and software of the combined operation are similar to none, for example, by tracking the scheduling through a relatively aggressive VLIW and optimizing the fine parallelism within a single string. The benefits of sequencing dynamic scheduling microprocessors. In various embodiments, fine parallelism is performed similar to the unordered microprocessor' hardware and software, while reordering relatively efficiently and interleaving the independent strings to cover memory latency stalls. In some environments, hardware and software implement relatively efficient scaling across many cores and/or threads, enabling an effective emission width of hundreds of micro-ops per clock. Multi-Thread Dynamic Optimization In some specific embodiments with large-capacity multi-core and/or multi-threaded microprocessors, dynamic optimization software is implemented to use a plurality of relatively efficient 136758.doc -29- 200935303

Nuclear and / or thread. For example, tracking line-by-line analysis and capture! 20, string construction 14 〇, scheduling and optimization 16 〇 and χ 86 binary translation I} $ one or ^ system at more than 1 level of ubiquitous multi-threading, resulting in reduced eve / Xiao consumption or effective Hide some or all of the additional burden associated with binary translation and/or dynamic optimization. The microprocessor executes the dynamic optimization software in a background manner so as not to interfere with the positive progression in the execution of the object code (e.g., through the optimized code from the translation cache). Various embodiments implement one or more of the "1" microprocessors and/or string portions of the resources used to implement the background of the dynamic optimization software (eg, in a multi-core microprocessor embodiment) One or more cores are explicitly dedicated to performing dynamic optimization software. The dedicated system is permanent, or #代地为 transient and / or dynamic 'for example, when part of the resource is available (for example, when the target code obviously puts the unused VCPU in an idle state), for another example, Or multiple core priority control mechanisms that implement the string thread (which maps (10), for example) to the target visible VCPU) to share the core and associated cache memory with little or no observable performance degradation ( For example, by using a slack loop established by a stopped target thread executed in accordance with a target instruction set architecture or ISA; hardware and constellation implementations In various embodiments, the elements illustrated in FIG. 1A correspond to maps All or part of the functionality explained with 1C. For example, in some embodiments, the DRAM 2002.1 of Figure 1A corresponds to the external system DRAM 1 84A of Figure 1C, and the translation cache memory management i camp s * Translating the cache memory 2002.1B. For another example, in some cases, I36758.doc -30- 200935303 The VLIW core 2013.1 of Figure 1A corresponds to the VLIW cores 191.1 to 191.4 of Figure 1C. One or more of the changes in Figure 1 The memory 2014.1 corresponds to the transaction memory 183 of FIG. 1C, and the progressive analysis unit 2011.1 of FIG. 1 corresponds to the line-by-line analysis hardware 181 of FIG. 1C. For another example, in some embodiments, FIG. The management unit 2012.1 corresponds to control logic coupled to one or more of the scratchpad files 194A.1 to 194A.4 and/or the string contexts 194B.1 to 194B.4 of Figure ic. For Figures 1, 1B and 1C As another example of the correspondence between the components, in some embodiments, the string image 2〇〇4 of FIG. 1A has an initial image of all or any portion of the string layers 110A and 110B of FIGS. 1B and 1C. As another example, in some embodiments, the string capable microprocessor 2001.1 of FIG. 1A implements the functions illustrated by the hardware layer 19 of FIG. 1C. In various embodiments, the chip set of FIG. 1C /pcie bus interface 186, multi-socket system interconnect 198 and/or ?. All or any part of express, Qpi, super-transmission ^ is implemented with coupling 2050, 2〇55, 2〇56, 2063, 205 of FIG. 1A 1.1 or 2053 all or any part of the associated interface. In various embodiments The chipset/PCIe bus interface 186 and/or the pci express, Qpi, and ultra-transmission 199 operating in conjunction with the interrupt of the ic, the SMP and the timer 175, and the keyboard/display 2〇〇5 of FIG. 1A are implemented. And/or all or any portion of the peripheral device 2006. In various embodiments, all or any portion of the interface associated with the coupling 2052.1 of Figure 1CiDRAM controller and Northbridge 197 is speculated to be more The threaded model of the various embodiments of the speculative multi-threading system is used to use the unmodified object code program in which the 136758.doc 200935303 Π:: deterministic programmed order execution is performed. Has been strict ^" there are at most successor strings. If the previous generation string p is first and then, before and after the association with S1 and/or before the termination of S1, the division of 82 is invalid (for example, by, for example) It will be considered as no operation or as a distinction between (4) and again. If the previous generation ❹ 10 knives and there are no Μ resources (for example, there is no free actor 2 network) to complete the points again, then depending on the points and why the class and the points are suppressed or alternatively blocked and executed again Until the payment is available. In some embodiments, the 'microprocessor is enabled to execute the native microcode instruction set according to the native microcode instruction set, including the available to divide and string, control the interaction between strings, union strings, and abort (eg, kill In addition to the various types of micro-codes, features and internal registers. In some embodiments, the various microcodes include: nype target, which instructs the microprocessor to create a new successor string S of the previous generation string ρ. The microprocessor (via any combination of hardware and software components) maps the successor string to a particular core and thread of the microprocessor in accordance with one or more string and/or hardware defined policies. Execute the previous generation string ^. (10) The specific VCPU of the opcode has a successor string (along with the previous generation string). The execution of the successor string begins at the target address specified by the target parameter (based on one of the native micro-opic code addresses in the body address space or as the target code RIp). The inhe parameter is used to perform the fork operation and will be modified by the previous generation application I36758.doc •32· 200935303 to determine which temporary storage n (4) to copy (10) to one of the successor strings (see positioning in this article). The section elsewhere skips the string. The parameter specifies one of several different string types for the successor string (such as fine. Pre-jump string, fully speculative multi-thread string, pre-fetch string, or other semantics or use) String). The fGrk micro-opcode provides the output value of the string 1. The string 1D is an identifier associated with the successor string (which is globally unique at least within the same vcpu), which specifies the successor string relative to The sequence of all other strings associated with a particular VCPU that has both the previous and succeeding strings. • kill.cmptype· ce ra, rb, τ directs the microprocessor to eliminate one or more strings. More specifically, when When executed in the upper generation string p, k(1) suspends P in a recursive manner and then contends 8 (if any) and all subsequent successors (if any) of 8. The execution of the kiU micro-opcode operates the cmptype via the specified ALU. (eg kU1·sub or kiu and Comparing the register operand with the tree - the result, then checking the specified condition code cc of the result (for example, j is equal to or equal to). If the specified condition is true, the string category identifier τ and the associated score The cross-country operation code string category identification item matches and the nested type is divided into depth. Zero' then kills the previous generation string p subsequent string. See elsewhere in this article - the section "string category identification" and, nesting Strings " to understand the additional disclosure. • waiuype [object] boots the microprocessor to stop suspending. More specifically, when executed in " causes the execution of string S to wait for a specified condition (and optionally wait - specify an object 'e.g., a memory address) before proceeding. For example, in some embodiments 136758.doc -33-200935303, the microprocessor is enabled to wait until the string is architected (eg, non-speculative), waiting for a particular memory location to be written, waiting until The successor string is completed and waits until the previous generation string reaches a certain state. • The join bootstrap microprocessor blocks the execution of the speculative successor string associated with the previous generation string until the previous generation string is merged with the successor string. A joint micro-op is executed by a string when a particular string is not speculative while being able to progress forward. • The micro-opcode optionally includes a -propagation bit that instructs the hardware to send the result of the micro-algorithm (in the previous generation string) to the successor string of the previous generation string. See the section "Before Jumping Strings" located elsewhere in this article for additional disclosure of the propagation and modification of the bits. In some embodiments, 'by performing a plurality of other micro-ops, performing a write to an internal machine state register, and automatically calling different hardware mechanisms based on non-micro-opcodes as needed. Any or all of the functionality of the above described micro-codes may be implemented. In the various usage scenarios in which the upper generation is divided and the post-sequence string is speculated

There are several reasons for waiting for y, y, squatting (such as pausing or temporarily aborting) and waiting for the second. For example, if an exception occurs in the speculative string, the anomaly indication-false speculation or the case where the upper generation fII is a successor string. For the other-example, one push is only used in the non-push = operation, because the specific operation is restricted to include the access 〇, the string. Restricted operation is performed by a supertransfer (9)), read or written to the device, 1 via PCI Express, QPI, Remembrance), access is restricted to non-push::: body area (eg not fast cached eight) The execution of a bunch of parts or taste 136758.doc -34- 200935303 Try to use the delayed operation result. When a previous generation string and a waiting succession string cross and if the previous generation string verifies all the foreigners and subsequent successors of the previous generation string If the resident matches, then the exception of the successor string is "true." The exception is true in the sense that the exception is not a side effect of the incorrect speculation and thus the microprocessor handles the exception in an architecturally visible manner. Next, when the execution of the subsequent string is resumed, the successor_ is immediately based on the exception (for example, into the operating system core) to handle the exception (eg, page miss). In some cases, when the execution of the subsequent string is resumed, execution is performed. Continue without error, because the successor string is now architectural (non-speculative microprocessor-based sequential synchronizing strings, and each VCPU owns one or more of these strings. The most recent architecture string indicates that the string is owned. The architectural state of the VCPU. The microprocessor allows the architectural state to be used for external observation of the VCPU (eg, via storage that has been committed to memory). The microprocessor is enabled to freely move the latest between cores within the microprocessor. The architecture string, and at the same time, the VCPU appears to continue execution (for example, by observing the operating system core with respect to the VCPU). Predictive multi-threading strategy microprocessor hardware and microprocessor string (software) Implementing speculative multi-threading on a number of levels that are increasingly broad: • When the string is stopped on a relatively long delay cache operation (such as a cache miss that the self-memory can compensate) Automatically pre-fetching strings (see the section "Pre-fetching strings" located elsewhere in this article.) Before using the data (for example, before pre-fetching the strings from the previous generation) The pre-extraction string attempts to extract the expected data into one or more cache memories and/or try to prepare one or more of the materials with the field In some environments, pre-fetching is in effect for hundreds of cycles. In some embodiments, as long as the strings are not separated and another string is provided, the system provides a pre-fetching string. Any type of string (thus preventing it - a particular slaughter has more than one successor string). In some embodiments, even when the substrings are split and another string, the system provides Extracting any type of string of strings (resulting in a scheme in which one particular string has more than one successor string). In some embodiments, the 'hardware has controllable pre-following based on one or more software and/or constellations. The policy selectively initiates or suppresses the logic of the establishment of the prefetch string. When the string determines that the previous generation string is relatively likely to stop on a particular instruction (eg, a cache that frequently encounters a cache miss), the previous generation is again Then skip the string (see the section located elsewhere in this article " before jumping over the string. . Alternatively, the preceding skipped string is therefore executed after the previous skipped string is branched at a relatively highly predictable last branch (e.g., a branch having a correct prediction rate greater than a predetermined and/or programmable threshold). The jump before the string is blocked until the previous generation string provides the previous jump depends on the resident. For example, when the previous generation generates the resident, the value of the foreigner is sent to the forward jump string (where the upper generation string is stationed outside) The subset of the person who jumped in front of the string is the one who stayed in the string). Sentees are included as needed to include the scratchpad and/or memory location. Inferring the string structure of the control flow structure and the idiom based on dynamics (and optionally statically) and speculating the string execution (SST) string (see the section located elsewhere in this article). Predictive string implementation (SST)": ^These structures and idioms include anti-I36758.doc -36- 200935303

Overlays (such as loops), calls and returns (such as secondary routines, functions, calls and returns to programs and libraries), and control flow unions (for example, in a conditional block by "if" and "Else" the common point of arrival of both paths). The SST string contains one or more sequences of instructions (e.g., basic blocks, traces, commit groups, or other instruction quantities). In some scenarios dynamic control flow changes occur at the end of each sequence of instructions to determine the sequence of instructions for the string to be executed. The control flow variation within an SST string (as opposed to some other string types) occurs independently of the control flow within the subsequent string of the SST string. Control flow changes within the SST string are relatively rare to make successors

D (j). In some cases, system selectivity changes an SST string to a pre-fetch string. In some environments, an SST string is in effect for tens of thousands or hundreds of thousands of cycles. • In some embodiments, the progressive analysis string I is used during the construction of the SST string, see the section located elsewhere herein, and the tooling for the line-by-line analysis ") to aggregate the data across the string. Relative to other strings, the line-by-line analysis is performed in tandem (for example, in program order) rather than in line with the line-by-line analysis: the previous generation string. Pre-extraction string = In some environments where the string is executed, the execution encounters a stop that does not block the progress of the process. In response, the micro-location, the benefit of the fork-forward pre-extraction string while stopping the encounter with the stop.

The microprocessor allocates (new) pre-fetched strings (in some cases I ^ ± . / /, body embodiment 10, on the same core as the previous generation string) but the architecture of the string above the string in different string contexts Status (scratchpad and hidden) begins. Prefetch 136758.doc •37- 200935303 The string continues to execute until the message is delivered to the stopped (upper generation) string causing the stopped string to resume processing (eg, for cache misses) Data is delivered to the stopped string. Subsequent microprocessors (e.g., elements of the hardware layer 190) automatically destroy the pref f string and unblock the stopped string. In some embodiments, the microprocessor has a Multiple software and/or serials can control the logic of the pre-fetch policy to selectively initiate or suppress the establishment of the pre-fetch string. For example, the 'string configuration microprocessor is used to encounter one of the strings in a string to cause the main memory. The access time is further divided into pre-fetched strings, and is used to stop the string when a _ leak causes an L2 or L3 hit. In some environments of the shackle-carrying, the pre-fetched string encounters a relatively long delay=cache Missing (for example, causing pre-fetching strings (4) Leakage. If this (4) person delivers (in the context of the pre-fetched string) - the difference (for example, all other data values sent by the right 1 via the cached hit (eg blocking. Pre-fetching string use) For the "ambiguous" placeholder value of the material value, instead of the heterocode, the result of a ambiguous input algorithm propagates the 胄-containing arithmetic code as the micro-transport value|,). The microprocessor is called the same 曰^ "Micro-opcode output is ambiguously matched to the actual destination of the branch:: When the destination string is executed-stored, the pre-fetched string::::two-pre-fetch see (for example, observable and Controlling) pre-fetching the string to prevent the previous generation string observation, 歹'J or temporary memory buffer element if the storage is written to a vague value. In some embodiments, J36758.doc 3 (eg, to the cache), the destination of the storage •38-200935303 receives the vague value (eg, the affected byte in one or more cache columns of the cache memory is marked as vague) Subsequent loading of the destination receives the vague value' Broadcasting the vague value. The propagation of vague values in various usage scenarios enables avoidance of pre-fetching of unwanted data (eg, when loading indicators) and/or avoiding those who would otherwise update the branch predictor incorrectly or inefficiently ( For example, when loading a branch condition).

In some embodiments, the microprocessor has logic to return configuration results and thresholds for cache misses to return ambiguous results (instead of stopping the pre-fetch string). For example, a serial configuration microprocessor is used to generate ambiguous values only for cache misses that result in primary memory access, and to stop for other cache misses. In various usage scenarios (such as integer and/or floating-point code), the pre-fetch string allows the data to be available before the previous generation (reducing or eliminating cache misses) and/or preparing the branch predictor (reducing or eliminating errors) prediction). Various embodiments use pre-extraction strings instead of hardware pre-fetching (or in addition to) hardware pre-extraction (except). In some environments where the previous generation is pre-fetched and pre-fetched, the pre-fetched string is executed for hundreds of cycles while the previous-generation string is waiting - the cache misses (for example, the main memory of the DRAM is implemented, for example) When the omission is made, the compensation is). In some usage scenarios and/or embodiments, a system enables one to progress toward a relatively long period of time that the previous generation string is waiting. For example, the string constructs one or more traces for use in the pre-fetched string, and the micro-recovery and the traces optionally exclude certain attributes, for example, the string optionally excludes the memory address Produced no 136758.doc -39- 200935303 = used in the micro-transport. For example, the string body optionally excludes the micro-ops that are only used to check the branch of the __. For example, the string is optionally excluded from storing the value of the unread (or relatively impossible to read) in the prefetched string to the memory relative to the "snap" in a 2" prefetched string: Code Pair: In another example, the string optionally excludes the micro-ops that are already stored (or relatively likely to exist) in the cache memory before the execution of the code. For example, the string optionally excludes micro-ops having attributes that make the micro-ops independent of pre-fetching. In some specific implementations and/or timepieces, the micro-processing = far ahead of (waiting) the previous generation _ (assuming there is time available) to perform the pre-fetch string. For example, the string tries to minimize (by eliminating or reducing) the micro-ops in the tracking, leaving only the micro-carriers specific to the one or more = critical paths to the specific manned execution. (usually resulting in a cache of missing carry-overs, resulting in a relatively long-lasting missed loader or a traitor combination. In some embodiments, the string and hardware (eg, fast) The missing performance counter is combined with, for example, borrowing information about the expired manned to collect and store the data structure used to determine the ad hoc line-by-line analysis. When optimizing the pre-fetching tracking, the string body = operation to reduce the generation The data of the target address of the specific manned person jumps over the string ^ The more jumps the thread is analyzed by the thread-by-line analysis of the threaded layer of the model layer (for example, the catching capture of Figure 13 will be chased when executed by the microprocessor = Jump over the speculation of multi-threading candidates. In some concrete 136758.doc •40- 200935303

❿ In the usage scenario, the system skips the pre-flight string for tracking with a relatively highly predictable terminal branch (for example, an unconditional branch, a loop instruction branch, or a branch that has been relatively successfully predicted by the system). The system selects candidates based on one or more characteristics as needed. An exemplary characteristic is, for example, relatively low static instruction level parallelism (ILP) due to relatively large N〇p. Another exemplary characteristic is a relatively low dynamic ILP (e.g., having a relatively frequent stop loading, resulting in a relatively difficult static observation of the dynamic scheduling gap. Another exemplary characteristic is greater than the parallel issuance possibility of a single core capable provider. It is effective to prejudge the multi-threading system in some cases that have relatively little dependency when tracking with all loop repetitive processes and/or loop repetitive processes. In some schemes where the in-line extension is extended to the call and return of the candidate in the single tracking, the pre-jump multi-threading system is effective. In some usage scenarios and/or specific embodiments, the pre-jumping speculation Multi-threading produces a lion-based: probabilistic performance level (but with relatively little hardware complexity). In some pre-jumping speculative multi-threading environments, a successor string skip Hundreds of instructions before the start of the chase = in some cases, by the pre-jumping speculation multi-implementation (for example, by a relatively high or maximum overlap) Successor The relatively accurate prediction of the starting address and the picture 2 illustrate an example of the hardware of the jump before execution (for example, by synthesizing the string), which is directed to looping < listening Drawing the core or interconnect. In this description, the term "pre-jumping string is the execution of the private object code (or its binary translated version) (as a string), 'where the clip is skipped in the upper string Terminal 136758.doc 41 200935303

Execution begins after an instruction (or binary translation equivalent) that is executed (in some circumstances) after tracing. For each pre-jumping string, the spear-level puppet horse generator (such as the scheduling and optimization of Figure (7) and/or one or more components of the figure id string construction 140) will be _fork.skip micro-operation The code is inserted into the terminal tracking of the previous generation string. —String "Terminal Tracking" refers to the last trace performed by the string before it reaches its joint point. When the system executes the kip micro-transport weight, the system divides the new (for example, subsequent or next generation) string as the pre-jump string. The pre-jump string begins execution at the τ-instruction (or its binary translated version) executed by the program sequence after the end of the trace containing the fork.skip micro-opcode. In some embodiments, Terminal tracking at the end of a conditional or indirect branch, the front jump string is opened at the target of the dynamic decision of the branch. In some use cases and, or in particular embodiments, the system dynamically selects the target by means of a tracking predictor and/or a branch predictor. In the scheme in which the terminal tracking ends with an unconditional branch and/or the string ends the tracking in the middle of the basic block, the start point of the previous skip is determined when the terminal tracking is generated. In Fig. 2, the f〇rk.skip micro-opcode 2 ι in the upper-generation string 200 has established a successor string 201, which is illustrated in the right-hand row as a string m 22 on the core 2. The successor string begins after a delay (illustrated as three cycles) due to the inter-core communication delay. The successor string then begins to perform the tracking corresponding to the bifurcation target address. The fork.skip micro-opcode encodes a propagation set that specifies the bitmap of the architecture register to be written (the trace does not modify other architectural registers) (illustrated as the propagated_archreg_set field dashed box component 212). Except 136758.doc -42- 200935303 The non-subsequent string of the schema register that was previously written to the member of the scratchpad set will then read its unspread version of the scratchpad). 'Otherwise the execution of the successor string is stopped for the propagation-sub-read, so the private version of the successor (instead of the previous generation's terminal tracking with respect to the previous generation string, the micro-opcode format includes a result indicating the micro-opcode) The mechanism that will propagate to the successor string. In some embodiments, the VLW beam includes _ or more "propagation" bits, each of which is associated with the beam

- or multiple micro-ops associated. For the forward skip scheduling and optimization - terminal tracking, and only in the micro-matrix to write the last micro-computing code of the specific architecture register A (relative to the original program of the tracking micro-computing code) Under the condition of the sequence), the string is set to propagate the bit of each micro-opcode, thereby generating an external value. In some cases (4), the original program order is different from the order in which the scheduled VLIW tracks, and in other embodiments, the order is the same.

When the micro-opcode targeting the architecture register A is executed and the propagation bit of the micro-code is set, the micro-code output value V is sent to the (current string) subsequent string S. (4) Up, and then the value is sent to the register 2 of the string s so that the micro-opcode in the string S is overwritten with the new (region-generated) value before the architecture register A is Stlt takes the attempted reception value of the architecture register A. V. If the attempt to read the resident architecture register has stopped the successor string S, then since the value 乂 has arrived, the string S is then unblocked to continue execution. In some environments, the string_specific resident architecture register is passed before the successor string reads the scratchpad 11. The specific register is written in the scene of the scene to the successor string of the subsequent stream, such as the register slot 194 phantom to 194A.4) and does not stop 136758.doc •43· 200935303 source. The value of the register is not traced by the terminal, and the register is not the member of the propagation set, and the successor string is followed by the value of the register at the beginning of the terminal tracking. The value is hidden in the background and propagated to the scratchpad file associated with the successor string. If the subsequent serial access register is not propagated, the successor architecture is stopped, and the successor string is stopped. Figure 2 illustrates an example of this propagation. After the micro-calculation code, the successor string is followed by the first-tracking of the first three-string, but the addition is performed (in cycles 3, 4, and 5, respectively, m * because the bundle does not depend on any resident a scratchpad (e.g., an external register from the previous generation string terminal). However, when the bundle 283 attempts to execute during loop 6, the bundle stops because the bundle depends on the last generation string and the terminal has not yet been generated. The resident architecture register % is added with the % mail. In loop 9, the bundle 269 of the previous generation string is calculated by the micro-computing codes 215 and 216, respectively, and the external value of the % coffee is propagated and the value is propagated. To the successor string. The value arrives at the core of the execution successor string 2〇1 after several cycles (eg, corresponding to the inter-core communication delay) and in loop 12, the (subsequent string) trace 201 wakes up and executes beams 284 and 285. The value is not available when a bunch of subsequent strings attempts to read %rdi. The previous generation string is generated in the loop 13 via the micro-opcode 217 and propagated in loop 16 to the successor string. 201 is used to arrive in loop 16. Then in the loop "middle bundle 286 wakes up and executes This diagram illustrates the background propagation of some of the external architecture registers (e.g., %rsp and %xmmh0 propagated by the micro-ops 213 and 2 分别, respectively) by the subsequent string read register. In some environments, a value has been attempted to be overwritten by a previous generation string before a successor string is sent to a subsequent string. In some I36758.doc • 44 - 200935303 In the middle, the old value of a register is before the way to the successor, the chain hardware prevents the previous generation from overwriting the old value. In some environments, the previous generation string has propagated the corresponding resident value to the successor string before the successor string. Overwriting the resident architecture register without reading the scratchpad. In some embodiments, the successor string notification of the previous generation string does not wait for the propagated scratchpad value because the subsequent string has Update (region generation) values. Various mechanisms are used in various embodiments to propagate the scratchpad values from the previous generation string to the successor string. Some embodiments are directed to the temporary propagation of the temporary propagation, the inheritance of the temporary storage. Use different propagation mechanisms and/or priorities In some embodiments, the scratchpad value is not replicated. Instead, the successor string uses the two=time copy scratchpad cache mechanism to retrieve the inherited and resident values from the on-demand string. The mechanism uses writes. The copy function prevents the inherited value from being overwritten by the previous generation before being passed to the successor string, and the subsequent string is no longer dependent on a value to suppress propagation. In some embodiments, a scratchpad renaming mechanism is used to avoid duplication. The actual value. The split operation copies the rename table of the previous generation string to the subsequent φ successor string (instead of the duplicate value), and the two strings share one or more physical registers until one of the physical registers is overwritten. Or multiple. * Predictive string manipulation (SST). The SST overview string splits the target software into a plurality of independent executable strings to achieve parallelism, performance, or both. The combination of the string and the hardware to dynamically analyze the target software is a measure of the relative security of the target software and the relatively large area of the data stream. The string is transformed into a string by inserting a point and a point at the beginning and inserting a joint point/minute at the end. 136758.doc -45- 200935303 The strings are programmed relative to each other' and executed independently. In various embodiments, 'hardware and string continue to be based on real-time feedback monitoring and fine-grained from the observation and line-by-line analysis of dynamic control flow and data dependencies, and the selection of joint points is implemented in some usage scenarios. Improved performance, improved adaptability and improved robustness. String Category Identification In some speculative multi-threading implementations, two parallel strings are generated in one point and one point: a new successor string that begins execution at the target software and at the target address and continues after the points and points. Execute the existing upper generation string (in the target software). The tracking predictor and/or the branch predictor dynamically select points and targets. After a fork, the category of the previous generation string (e.g., lifetime) includes all code that was executed after the execution of the previous generation string reached the initial start address of the successor string or before reaching some other limit. The string string progressive analysis subsystem derives the scope of each string. ❿ If the string recognition is for the parallelized loop, then the point is again (executing a fork operation at the point and point) and the target is again (the successor string is executed at the point and the target) The branch at the top of the loop and ending the loop limits the scope of the previous generation string. In the scenario where one of the conditional branches at the end of the loop (which jumps to the top of the loop for the next iteration), the branch abort direction is not used. The string uses heuristics based on various compilers (eg Gcc,

The output of Microsoft Visual Studio, Sun Studio, PathScale Compiler Suite, and PGI) recognizes the termination branch and direction. The compiler generates a rough equivalent control flow idiom for a given set of 136758.doc -46- 200935303 command sets (eg x86). For example, the boundary of the loop is identified by finding any branch that jumps to the base block immediately after the basic block that jumps back to the top of the loop for the next iteration. Other termination branches include return instructions and unconditional branches to the address after the last • basic block in the loop body.彳 其中 其中 其中 、 、 、 、 原 原 原 原 原 原 原 原 原 原 原 原 + + + + + + + + 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且also. The material of the previous generation is only terminated by the main body of the function, and is terminated by the intersection of the previous generation string and the return address, unless the program executes the error code or the exception handling routine. Otherwise the function call returns to the call location relatively frequently. For example, when the target is at the beginning of a relatively large code block and the target is after the community of the block, there are other relatively more general types. The internal branch within the block (e. g., the material of the previous generation) optionally exits the block and branches into the successor. The string will be internal branches • The tool will be equipped to terminate the branch. In various embodiments, various structured stylizations (e.g., for loops, calls, and returns) are handled as part of a more generalized control flow analysis technique. In a ..., physical example, 'by using the basic block containing the origin and the origin" " and recursively following each branch with and without the exit to perform a control flow graph The depth of the basic block is first traversed to find the terminating branch. In the usage scheme, the location termination branch is caused by various types of η: (for example, not mapped to a branch in the address space, invalid or no branch, and other conditions that make it difficult to determine the control flow change) 136758.doc -47· 200935303 Complexity = However, even if the string does not detect the correctness of all target software. In the case of any of the knowledge of the original structure, such as the original code, the unrecognized implementation of the string operation is accepted. The "end branch" is also identified by the tracking of the conditional kill microinjection code injection and the tooling and the like termination branch refers to all subsequent strings evaluated as true_=micro:::3 ==. If the implementation of === estimative, then an alternative type of conditional killing of the micro-computing code in addition to the micro-computing code string and all its successor strings (see positioning, elsewhere in this article) bridge tracking and resident temporary storage Prediction "). If the termination of the basic block is to branch microcode (for example, " ah which compares the register _2 and only knows when the comparison condition is true), the end of the 'bean' body injection a match kill micro Opcodes, such as "kUUc R1, R2, T". The kill code specifies that the branch matches cc, R1, and R2. The nested string is maintained in a specific deterministic manner to maintain the target software, in some embodiments The body uses a strictly programmed non-nested speculative multi-threaded demographic dust in which the upper-generation string P has at most one successor string 81 (81 optionally recursively to the successor string S2', etc.). Some embodiments result in a string It is possible to have a plurality of subsequent pre-fetch strings (except as needed for a single non-pre-fetch subsequent string) because the pre-fetched strings do not modify the architectural state. In some programs, P encounters another point before the joint S1. In order to protect I36758.doc •48· 200935303 Temple and sexual behavior, when the successor string exists (4) (4) in ^: to point. In order to ensure that ρ eventually combined with S1, Ning = with hardware implementation functions (such as timeout) to detect and Suspension of control Analyze the target software for the terminal branch to reduce or prevent future generations and currents. Each killing micro-code is marked with a string (four) identification item, so if the point-to-string is suppressed, then any of the data is suppressed. Kill the micro-opcode.

In order to implement the recursive function, each string is saved—the private branch that is incremented in the suppression time and the nested counter (initialized to zero when the string is created). When hardware processing - when the micro-opcode is removed, the nested counter of one string is zero, then the micro-operating code is killed, only the string is aborted, otherwise the nest counter is decremented and the string is not aborted. Candidate String Selection In some usage scenarios, some loops are good candidates for speculative multi-threading (each string has one or more iterations). In some embodiments, the hardware includes a progressive analysis logic unit and a body synthesis tooling code (which interacts with the progressive analysis logic unit) for determining which loops are suitable for splitting into parallel strings. Each of the reverse (loop) branches in the target software has a unique target entity address p used by the string for identification and lamp-by-light analysis. The hardware loops through the tracking of the total cycle and the repetitive process and uses the tunable threshold for the total cycle and the repeated use to determine the loop that is too small to be optimized for prolific production (eg, hardware filtering out each repetitive process) A loop hardware with less than 256 cycles allocates a loop index counter (LPC) indexed by p to the relatively large loop. The LPC saves the total loop, the repeat process, the confidence estimator, and the I36758 .doc •49- 200935303 Other information related to determining whether the loop is a good candidate for optimization. The string periodically reviews the LPC to identify the string candidates. The string manages the LPC. In various embodiments, the LPC One or more of the caches are cached in hardware and/or stored in memory. In some embodiments, similar techniques are used for other types of candidate strings (eg, called functions). Need to use a set of call-by-book analysis counters (CPC) to record various statistical content, such as called

The number of cycles consumed in the function, which registers are modified, the most likely to return values, and other information that may be useful in determining whether a string is a good candidate for optimization. Nested Set Chart Construction In some embodiments, the string body is dynamically constructed as a string or candidate string that is well known to the string body or a plurality of data structures representing the relationship between the regions of the object code. The string makes the structure of (4) and so on to track the nests of the strings in each other (4). For a plurality of nested loops (such as internal loops and external loops), the 3 = 1 body string optionally includes a nested function call (in the letter, string two strings) or one or more Circles. In some embodiments, in some embodiments, the string is expected to have a translation cache memory (for example, a security code, a code) to perform the code operation in the executed embodiment. _ more (four) nest (four) material structure. In a specific embodiment, the hardware includes the use of coordination, body logic. Lai (four) hair (four) nested relationship based on the nested nest data structure The string uses the 136758.doc -50- 200935303 heuristic to select the relatively more efficient region of the code to convert to a string, and the string tool equips each selected string for further line-by-line analysis as explained below. In a specific embodiment, the heuristic includes one or more techniques for selecting an appropriate string from the nested internal and external loops. • Tooling for line-by-line analysis • Based on the origin, the sub-target, and the termination The branch and the individual direction set, the string device injects the tool equipment into the target software, and the micro-code-based translation Y is stored in the translation cache memory, for example, to form a complete and correctly defined string. In some embodiments, the stringer injects the progressive analysis into the tracking of the basic blocks contained at the origin and origin. Line-by-line analysis = non-hardware establishment - line-by-line analysis string 'for example, located in the section elsewhere," on the line-by-line analysis of line-by-line analysis "and "subsequent string line-by-line analysis" The tracking of each terminating branch is described in the section "Chasition Category Identification" located elsewhere in this article. The previous generation string analysis is performed ❷ After the dozens of tools are equipped with line-by-line analysis, the execution includes points and points. The next time, the body expands a line-by-line analysis string as a successor string. The line-by-line analysis of the string is blocked until the previous generation string intersects with the start address of the line-by-line analysis string 'X° and then the line-by-line analysis string begins execution' The upper generation string is blocked. When the line-by-line analysis string is completed (for example, via the intersection, the end branch, or the other branch), the upper generation string is unblocked and the line is analyzed line by line. As described below, the hardware calls the string to complete the string. Construction. Perform a line-by-line analysis and then 'hardly enter the special progressive analysis mode to execute the rest of the previous generation string. 136758.doc •51 · 200935303 For each occurrence of certain events in the previous generation string, The string configuration performs a series of progressive analysis records (SEPR), which are to be written into a memory buffer allocated by the string to protect the SEPR generated by the previous generation string. In an example, the SEPR is written when certain types of memory addresses (loaded storage) are implemented. In some embodiments, for example, by recording basic blocks, tracking, controlling flow changes, or the like Execution writes additional SEPR to enable the string to be re-constructed later by the string = correct code sequence. 'Subsequent string progressive analysis of the previous generation string is blocked at completion, while subsequent (progressive analysis) _ execution and identification Memory and memory dependencies. Relative to the dependency of the scratchpad, with the succession of the string, the hard disk is hard to read the schema register before the scratchpad is written in the successor string. Each bit of the bit mask is updated. The bit 2 mask indicates that the resident string from the previous generation is used as a resident for the successor string ^ relative to the memory dependency 'in some embodiments, the transaction memory version management System implementation data cache memory告b±田甲战入入', the hardware uses the cache column (or byte level) granularity to reserve in the memory location. The hardware by loading the speculative string has loaded which bytes (or more The bitmap of the $bit block tracks the stock. The hardware tracks the material as needed, for example, which specific future strings have been loaded - the memory stone f is in the "7 Μ衣0 more body using the cache column And/or storing bitmaps in separate structures. The bits are loaded from the string earlier than the load string (in the order of the program) (eg the last of all strings. In some environments) The earliest string architecture A (for example, when the column is clean, in some environments, the earliest string is 136758.doc -52- 200935303, the string of speculations (for example, when the column is paid). Column: = When taking the column, the hardware checks if any future strings are in the cache, food: Hardware! In this case, the hardware has been found to cross the string span = future string and any later, or hardware notification string confusion, so that the string can implement a software definition policy. The flexibility of the D-stop string is based on the line-by-line analysis of the string of hard words. After the previous generation string has been completed, the Ding "crossing string confusion does not occur; the hardware depends on the program order (relative to the string order, the husband must A, the order (the order of the micro-opcodes of the relative input and the storage) performs all the loads... J' so the hard-wired system is free for other uses. Hard-spot::: when the second type is in some implementations In the example system (such as string memory transfer), using the memory reserve hardware to analyze the analysis of the traversing of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ At the end of the call, the end of the analysis. Other types of points (such as call or generalization) have possible unrestricted categories, and therefore the system uses heuristics to limit the progressive line-by-line analysis of the string has been completed, ±^= It is detected that the upper generation string is unblocked and the string body is heard: the line-construction is completely speculated _ the joint of the tools and equipment required = the data flow chart constructed by SEPR is used to construct the system. Data, string body Beginning to build a data flow table for the external nodes of the root node 136758.doc -53- 200935303 It is also explained in (4), when performing the previous generation string, what hardware and hardware are used as the hardware to perform tracking and/or recording of one of the basic blocks Save the program (4) heart list, and also save the cache memory tag and the related load and store index - data. Use the record 'string body to decode each basic block in each executed track to be programmed. The stream of micro-computing code. For the construction of the Qing, use the = device to rename the table 'convert the micro-operating code operand to the index of the earlier micro-computing code. ❹ In order to trace the memory dependence, the string saves a memory weight naming The table 'maps the cache location to the latest storage operation for writing to the address. 1 The load and storage selectively specify the previous storage as the original operand. The string combined memory weight naming table usage record Please sigh in order to include memory dependencies in the DFG. At the end of the program, all the micro-ops executed in the previous generation string have been incorporated into the data flow chart, in which Just register The name table and memory weight naming table point to the root node of the chart (residents). · Bridge tracking and resident register prediction - guess the successor string of the inner set (such as the last survivor of the previous generation string) from: Predictor value predictions that existed in the previous generation string. The string body searches for dynamics from each of the external (scratchpad and memory) depths to generate a subset of the 7 operational code. All subsets of the program order are The collection system is set up outside the county. County I= establishes the structure of the above-mentioned generation string and the structure of the scratchpad and the beginning of the memory value of the bridge, and only includes the set of foreign resident generations for predicting the last resident. (For example, by the inferred string of the in-situ bit mask, the indicated bridge is 136758.doc -54- 200935303 and any external register register is copied to the memory buffer. The system later uses these replicas to detect false predictions. When a trace is repeated to - speculation (4), the string sets up a new string to begin execution at the bridge-snap-and-predictive string---the micro-code. In addition to handling the dependency of the scratchpad, the bridge (4) converts any terminating branch (and the associated micro-computing code that computes the branching condition) into a discontinuous speculative micro-computing code. Finally, the bridge pursuit sets up various (four) temporary storages for the string, for example, to the (four) memory value column 、 table, the deferred list and the unconditional branch, and the indicator to the beginning of the speculative string. The bridge is optimized to reduce or minimize the length using a variety of dynamic optimization techniques. Some idioms (such as overflow 盥 padding registers or in-string t-feeding multiple calls and returns) sometimes result in unremoved self-stacking of the person and storage-storage. Similarly, sometimes the stacking index or other temporary n is repeatedly incremented or decremented, and the dependency chain 4 is added to add a constant. The string recognizes at least some of the f words and patterns and optimizes the dependency keys to relatively few or fewer operations. For example, the string uses his (10)e seven ad-use shorts, where the manned read data from the stock is speculatively replaced by the value of the previous stock (with the register and the memory prediction at the joint point) Verify speculation). If the string is not able to reduce the bridge tracking to a predetermined or programmable length, the string will abandon the string optimization. Abandonment occurs in a variety of environments, such as when there is a true cross-string register dependency, or when the "outsider" is calculated relatively late in the last two strings and consumed relatively early in the successor string Use 136758.doc -55- 200935303 (thus resulting in a relatively long dependency chain). °Recalling the body value prediction for some string 'bridge tracking prediction memory value line addition: _, φ body is used in the subsequent step-by-step analysis (for example, as explained elsewhere in this article) The string-by-line analysis " enables Daigan to load the reserve data to determine which memory locations are taken by (4) (4). In some embodiments, access to the hardware data cache is performed. 1 Sign and 70 data to construct a list of cache locations that are forwarded across the string.叮 Find the body in the memory weight naming table for DFG

The position of each wire affected. The table M H tabs to the most recently stored micro-op (in program order) for writing to the location. The string is then constructed to produce a sub-graph of the micro-ops necessary to store the value of the micro-ops (e. g., using depth-first search). The string includes the micro-ops that enter the bridge tracking along with any other micro-ops used to generate the scratchpad value prediction. The stored micro-op in the bridge trace decouples the storage in the previous generation string from the subsequent successor string (subsequent contention is self-bridge tracking loading prediction). Finally, the string copies the information about each of the predicted stocks to a list of stock prediction confirmations that are later than the actual stored value to confirm the guess. In various embodiments, the information includes a physical address of the stored item, a stored value, and a mask of the byte written by the stored item (or alternatively, the stored item is in a byte group) Size and offset). Joint processing routine tracking Each of the speculative strings constructed by the string has a matching bridge tracking and association. 136758.doc • 56- 200935303 Regular tracking. The joint processing routine traces the exact road used... The flyback is actually predicted by the bridge tracking). 1 or the memory value _ (for example, ignoring the unused two - the end of the previous generation string (for example, via the intersection with the successor string, the level to the other event), the hardware re-follows the successor string to start the execution of the needle f The joint processing routine. For the S register value prediction used, the joint processing routine reads the predicted value from the memory 2 buffer (for example, U is in the section elsewhere herein, bridge tracking = resident temporary storage) (predicted in the "predicted"), and compares the predicted value with the resident value from the previous generation: the hardware includes "through" register read and memory input function, which enables comparison of joints The status of the trace read joint trace (eg, scratchpad and memory) and the previous generation string is compared for comparison. Some embodiments compare only the scratchpad read by the successor string. Memory value prediction, a list of predicted stores used by the joint tracking cloth (in various embodiments, including physical addresses, values, and - or more of the byte masks for each item), And each predicted stored value and the previous generation The area at the same physical address is compared with the external value. If the system detects any mismatch, the system aborts the successor string and the previous generation string continues over the joint point as if the system was not divided and the successor string. If the joint system succeeds, Then the system discards the previous generation string and the subsequent string becomes a new architecture string for the corresponding VCPU. Conclusion In the description, some choices have been made for the convenience of preparing text and schema and unless there is an indication of the opposite, the selection should not be essential. The above is explained as 136, 758.doc • 57- 200935303 for additional information on the structure and operation of the specific embodiments described. Examples of such choices include: the specific organization used for the identification of the schema number or = Recognizing and referring to the specific organization or assignment of the features and the elements of the elements (e.g., annotated or numerical identifiers). The word "including" or "comprising" is expressly intended to be interpreted as a logical set of the opening category. Abstract words do not mean to convey the inclusion of an entity unless it is clearly followed by the word within." 'Although it is based on clarity of explanation and understanding The present invention is not limited to the details of the present invention. The specific embodiments disclosed herein are illustrative and not restrictive. Many variations of the construction, configuration, and use of this description are possible and are within the scope of the patent application scope of the issued patent: for example, 'interconnect and functional unit bit width, clock speed and The type of technology used is variable in various component blocks in accordance with various specific embodiments. The names provided to the interconnects and logic are merely exemplary and should not be construed as limiting the illustrated concepts. The sequence and configuration of the procedures, acts, and functional elements can be varied in accordance with various embodiments. In addition, unless:: the contrary statement is made, otherwise the range of values specified, the maximum=minimum used, or other specific rules such as ISA , the binoculars of the cycle = the number of items or grades in the device) is only the specified range of values, maximum and minimum values, and specific regulations, which are expected to be pursued. Improvement and change in the operation, and should not be construed as limiting. Various components, subsystems, functions, operations, in-line routines, sub-normals, routines, procedures may be implemented using functionally equivalent techniques well known in the art, rather than the described 136758.doc -58.200935303 , macro instructions or parts thereof. It should also be appreciated that many of the functional aspects of the specific embodiments can be designed and constrained in accordance with the specific embodiments and facilitate processing (to facilitate the transfer of previously used hardware functions into the software) and higher integration flexibility (to facilitate the use of previously used software) The technique of transferring functionality to hardware) tends to be functionally selective using hardware (ie, general purpose circuitry) or software (ie, via a programmed controller or processor).

Specific variations in various embodiments include (but are not limited to): segmentation differences; different form factors and configurations; use of different operating systems and other system software; use different interface standards, network protocols, or communication keys And other changes expected in the implementation of the concepts described herein based on the specific application-specific engineering and industry constraints. Specific embodiments have been described in terms of details and environmental contexts that are required to be far from the minimum implementations of many aspects of the specific embodiments described. Those skilled in the art will recognize that certain embodiments omit the disclosed components or features without altering the basic cooperation between the remaining components. It is understood that many of the details disclosed are not required to implement the various embodiments of the specific embodiments described. The components and features that are omitted in the remaining elements are distinguished from the prior art and do not limit the concepts described herein. «All such variations of the juice are based on insubstantial changes in the principles conveyed by the specific embodiments illustrated. It should also be understood that the embodiments described herein can be widely applied to other applications and are not limited to the particular application or industry in which the described I body = example. Therefore, the present invention should not be construed as including all modifications of the scope of the patent application scope of the patent issued. [Simple description of the diagram] Figure 〗 A explains the computer and the ancient with the injury. Each has the ability to string. There are - or more of the right to use the serial image, memory storage, input / output devices and transmitters. 微 Neiqi and Xing 壻 string of micro-processing = and 〗. Joint interpretation and A microprocessor-based hardware, string (software), and target software layer (such as a subsystem) with string capabilities. 2. A common explanation of the jump before execution (for example, by string and hard - the example, which is drawn for the time when the loop is used for the loop. Sometimes the description is shown in Fig. 2, and the coffee is shown in Fig. 2. [Major component symbol description] Reference 101 102 103.1 to 103.4 104.1 to 104.6 110, 110A, 110B 111 115 120 121 124 125 127 (x86) target software layer operating system core application VCPU serial layer translation cache memory management X 8 6 binary translation tracking progressive analysis and capture entity page line-by-line analysis branch line by line analysis Predictively Optimized Memory Progressive Analysis 136758.doc -60- 200935303 130 Promotion 140 String Construction 160 Scheduling and Optimization 162 Memory Confusion Analysis '163 Optimization, 165 Scheduling Microcode 167 Encoding VLIW Bundle 172 Hardware Control 174 Virtual Device 175 Interrupt, SMP and Timer 181 Progressive Analysis Hardware 182 Hardware Acceleration Unit 183 Transaction Memory 184A External System / Serial DRAM 186 Chipset / PCIe Bus Interface 187 Hardware X86 Decoder 190 Hard Layer • 191.1 to 191.4 VLIW Core. 192A.1 to 192A.4 ALU 192B.1 to 192B.4 FPU 193.1 to 193.4 LI D Cache Memory 194A.1 to 194A.4 Register File 194B .1 to 194B.4 Serial context 195 Multicore internet 136758.doc -61 - 200935303 211 212 © 213, 214, 215, 216, 217 269, 280, 281, 282, 284, 285 196 197 198 199 200 201 2000.1 , 2000.2 2001.1 ' 2001.2

2002.1 ' 2002.2 2002.ΙΑ 2002.IB ❹ 2003 * 2004 - 2005 2006 2009 2010 2011.1 2012.1 L2/L3 cache memory DRAM controller and Northbridge multi-socket system interconnection PCI Express, QPI, super transmission last string successor string fork. Skip micro-opcode spread set micro-computing code bundle with string capability computer with string capability microprocessor dynamic random access memory component string data translation cache memory flash memory string image keyboard / display peripheral device network Road storage line-by-line analysis unit string management unit 136758.doc -62- 200935303 2013.1 VLIW core 2014.1 transaction memory 2050 face 2051.1, 2051.2 coupling 2052.1 face 2053 coupling 2055 coupling 2056 coupling 2063 coupling 2064 coupling 136758.doc -63 -

Claims (1)

200935303 X. Patent application scope: 1 A system, which comprises: a string construction component, which is used for dynamic construction - one of them - (four) progressive analysis orientation - at least a string of construction components is at least partially (four) a part, wherein the person performs at least one test of the plurality of threads of the day h, and the segmentation execution part of each string includes a plurality of individual string images; δχ is a cut execution thread, and the execution component is used for the one Or a plurality of processing; and ''string-based t for the processed string 铱 Platinum F7 β This / Ding Xu § hai execution component enables I to simultaneously perform corresponding to the string f ^ ^ . The knife "executes the multiple strings of two or more threads of the individual multiple images of the application. 2. The system of claim 1, wherein for -, _. y is divided for each processed string Thread The thread in the thread contains at least the thread of the batch/cutting thread and a string of the string of 5 successors. The architecture string 3 is the architecture state of the thread cutting thread. - Architecture string content, \ 'The successor string is younger than the string of the string splitting thread, and the money string is updated with a sequence of contexts of the speculative version of the one of the architectural states of the string splitting thread. The system of the long term 1' Wherein the execution component is further enabled to simultaneously perform: a plurality of strings comprising one of the architectures associated with the processed strings of the processed strings, each of the architectural strings updating an individual architecture string context containing the individual architectural states. For example, the system of claim 3, 136758, doc 200935303, wherein the divided strings of the processed strings include the string splitting execution thread, the plurality of threads in the thread, and at least one or more successors of the string splitting thread The string of the framework string, each of the worms or the worms 4-way than the string splitting thread 芊 = each subsequent string update contains one of the staggered threads of the staggered thread state of the speculative version of the armored A (7) successor string context; and a dedicated network is stored in one or more dedicated content caches in the microprocessor. A ❹ ❹ ❹ 5 a system in which the concurrent performers are executed on a single core of a microprocessor. A plurality of strings 6_ Π::Γ: 统' where the plurality of threads within the execution thread are simultaneously executed. 7.:=~ The second component of the construction component is the executable code and the microcode - or more of the actual 8' item 7 ''where the executable code and the exhaustion of the - or medium. At least partially stored in one or more non-volatile storage devices, such as the system of claim 1, further comprising: a hidden body that includes - or a plurality of DRAM devices; The constructing component of the thread part allocates the portion of the memory. The system of claim 1 is constructed to the string, further comprising: a build that is enabled to decode at least a type of upsell and at least one type of deconstructed microcode. 136758.doc 200935303 "• The system of claim 2, further comprising: a context store, dedicated serial logic, coupled to the content context; and at least for the one or more threads And it is enabled to perform a plurality of hardware assisted merges by the & string cutter. The system of claim 2, further comprising: a content network storage device a string of contextual links, such as string and singularity; and a contextual context corresponding to at least one of the processed strings of at least one processed string splitting thread to the (4) context store The system of claim 2, further comprising: a transaction memory comprising a dedicated transaction memory and dedicated transaction memory control logic, the transaction memory system being enabled to target the body: At least one processed string splitting thread of the thread implements memory asset=hardware assisted version management, wherein each of the plurality of memory locations holds a plurality of data versions, wherein for each of the plurality of memory locations In one case, the first version of one of the versions corresponds to the architecture string and the at least one second version of the versions individually corresponds to at least one of the successor strings. 14. The system of claim 1, further comprising · an analysis component for identifying an individual span that corresponds to the occurrence of one or more individual memory locations between the plurality of simultaneous execution threads and confusing one or more individual memory locations One or more latency dependencies; I36758.doc 200935303 component that removes the one or more latency dependencies by employing one or more individual deferred operations instead of S spanning string operations; Evaluating each of the deferred operations performed by the plurality of concurrent execution threads within the thread; wherein the identifying and the replacing are enabled to dynamically operate during the processing of the processed string split threads, And ° ^ relative to the execution of the processed string split threads, the result system 15 achieved by executing the processing of the thread within the thread simultaneously, the target 5; the result specified for the strict sequential processing architecture. The method includes: constructing at least one of the one or more threads to segment the thread segmentation thread, ^ via 兮一$ each shed#, wherein the dynamic construction system is at least partially at least part of the plurality of threads - Implemented, in which the string splitting the thread of the string is divided into "Hung Bo", each string image; ° 仃 邛 包含 包含 包含 个别 包含 包含 包含 包含 包含 包含 包含 个别 个别 个别 个别 个别 个别 个别 个别 个别 个别 个别 个别Lines; and for each of the processed strings, eight 丨 丨 / - - - - - - , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , string. Two or two of I are 16. According to the method of claim 15, the further step includes ·· wherein the processed string of each of the eight/strings includes the string splitting thread 2 _ the plurality of threads within the thread The successor string-architecture string, each of which "reads at least - or the architecture string is younger; /, than the string splitting thread 136758.doc 200935303 where the processed string is updated for the processed string split threads a framework string context containing the architectural state of the string splitting thread; and a partitioning thread for each of the processed strings, each subsequent string updating packet 3 is a speculative version of one of the architectural states of the cutting thread Individual 'subsequent string content context. 17. The method of claim 15, further comprising simultaneously executing a plurality of strings comprising threads of one of the architectural strings associated with each of the strings being executed, each architectural string updating an individual architecture comprising individual architectural states String content 脉 context. 18. The method of claim 15, wherein the one or more threads comprise all or any portion of an application executed in a user mode and/or an operating system core executed in a privileged mode. The method of claim 15, wherein the one or more threads comprise all or any portion of a virtual machine hacking and/or one or more operating system cores managed by the virtual machine monitor. The method of claim 15, wherein the one or more threads are based on at least a heartbeat architecture and the plurality of string images are based on a second * instruction set architecture. The method of claim 15, wherein the dynamic construction is automatic and the one or more threads are unobservable. 22. A method of graying out: £5 Ί r, further comprising performing each of the plurality of strings within the execution thread simultaneously on a core of a microprocessor. The method of claim 2, further comprising performing each of the plurality of strings within the execution thread simultaneously on an individual power of the microprocessor. 136758.doc