TW200933895A - Display device and cu alloy film for use in the display device - Google Patents

Display device and cu alloy film for use in the display device

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Publication number
TW200933895A
TW200933895A TW97140922A TW97140922A TW200933895A TW 200933895 A TW200933895 A TW 200933895A TW 97140922 A TW97140922 A TW 97140922A TW 97140922 A TW97140922 A TW 97140922A TW 200933895 A TW200933895 A TW 200933895A
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Taiwan
Prior art keywords
film
alloy
alloy film
display device
atom
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TW97140922A
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Chinese (zh)
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TWI484637B (en
Inventor
Takashi Onishi
Aya Miki
Hiroshi Goto
Masao Mizuno
Hirotaka Ito
Katsufumi Tomihisa
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Kobe Steel Ltd
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Priority claimed from JP2008038981A external-priority patent/JP5368717B2/en
Application filed by Kobe Steel Ltd filed Critical Kobe Steel Ltd
Publication of TW200933895A publication Critical patent/TW200933895A/en
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Publication of TWI484637B publication Critical patent/TWI484637B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • C23C14/3414—Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention provides a Cu alloy film for a display device, which has a lower electric resistance than the conventional Cu alloy film, can realize direct connection of low contact resistance to a transparent electroconductive film without forming any barrier metal, and, when applied to liquid crystal displays and the like, can provide a high display quality. The Cu alloy film for a display device is connected directly to a transparent electroconductive film on a substrate and is characterized by comprising 0.1 to 0.5 atomic% of Ge and 0.1 to 0.5 atomic% in total of at least one metal selected from the group consisting of Ni, Zn, Fe and Co.

Description

200933895 九、發明說明 【發明所屬之技術領域】 本發明係關於顯示裝置及其所使用之Cu合金膜。特 別’係關於顯不裝置之薄膜電晶體（Thin Film Transistor ’以下’稱爲TFT )中，直接接續至透明導電膜的顯示裝 置用Cu合金膜，及該Cu合金膜使用於上述薄膜電晶體之 例如液晶顯示器，有機EL顯示器等之平面面板顯示器（ φ 顯示裝置）、及形成上述Cu合金膜所用之濺鍍靶。又， 關於如上述顯示裝置中之薄膜電晶體之 •源極及/或汲極以及信號線、及/或、 •閘極及掃描線 所用之Cu合金膜、及該Cu合金膜爲使用於上述源極及/ 或汲極以及信號線、及/或、閘極及掃描線所用之上述液 晶顯示器、有機EL顯示器等之顯示裝置、及形成上述Cu 合金膜所用之濺鍍靶。另外，以下，顯示裝置中，以液晶 〇 顯示器爲例說明，但並非意圖限定於此。 【先前技術】 例如液晶顯示器被使用於小型之行動電話至30吋、 及超過100吋之大型電視的各式各樣領域。此液晶顯示器 爲根據畫素的驅動方法，被分成單純矩陣型液晶顯示器和 主動矩陣型液晶顯示器。其中，組裝TFT作爲開關元件的 主動矩陣型液晶顯示器，因畫質爲高品質且亦可應付高速 的動畫，故成爲液晶顯示器的主流。 -5- 200933895 圖1爲示出應用於主動矩陣型液晶顯示器之代表性的 液晶顯示器之構造。一邊參照圖1 一邊說明此液晶顯示器 的構造及動作原理。 首先，液晶顯示器100爲具備TFT基板1、和對向 TFT基板1配置之對向基板2、和配置於TFT基板1與對 向基板2之間之作用爲光變調層機能的液晶層3。 TFT基板1爲具有於絕緣性之玻璃基板la上配置的 TFT4、畫素電極（透明導電膜）5、包含掃描線和信號線 的配線部6。 又，對向基板2爲具有於玻璃板全面所形成的共通電 極7、於對向TFT基板1側之畫素電極（透明導電膜）5 位置所配置之彩色濾光片8、和於對向TFT基板1上之 TFT4及配線部6位置所配置之遮光膜9。對向基板2爲進 一步具有令液晶層所含之液晶分子於指定方向上配向的配 向膜1 1。 於TFT基板1及對向基板2之外側（液晶層之反側） ，分別配置偏光板l〇a、10b。 液晶顯示器100中，於各畫素中，對向基板2與畫素 電極（透明導電膜）5之間的電場被TFT4所控制，並且 經由此電場令液晶層3中的液晶分子配向變化，且通過液 晶層3的光線被變調（遮光和透光）。如此，令穿透對向 基板2的光穿透量被控制，並且以影像型式顯示。 於液晶顯示器100的下方設置背光22，此光爲由圖1 的下方往上方通過。 -6- 200933895 又，TFT基板1爲經由透過TAB帶12所連結的驅動 電路1 3及控制電路1 4所驅動。 圖2爲圖1中，A的主要部分放大圖之一例。圖2中 ，於玻璃基板1 a上形成掃描線（閘極電線）25，掃描線 25的一部分作爲控制TFT之開-關的閘極26之機能。以 覆蓋閘極26般形成閘極絕緣膜（SiN ) 27。透過閘極絕緣 膜27與掃描線25交叉般形成信號線（源-汲極配線）34 ❹ ，且信號線34的一部分作爲TFT之源極29之機能。於閘 極絕緣膜27上，依序形成非晶質矽通道層（活性半導體 膜）33、信號線（源-汲極配線）34、層間絕緣膜（SiN ) 3 0。此型式一般被稱爲底部閘型。 於閘極絕緣膜27上之畫素區域，例如配置（Ιη203 ) 中含有1〇質量％左右氧化錫（SnO )之氧化銦錫（ITO ) 膜、和（Ιη203 )中含有氧化鋅之IZO膜所形成的畫素電 極（透明導電膜）5，於圖2中，TFT之汲極28爲直接畫 φ 素電極（透明導電膜）5並且以電性連接的構造。 若對此TFT基板，經由掃描線對閘極26外加閘極電 壓，則TFT4呈現打開的狀態，預先外加至信號線的驅動 電壓爲由源極29，經由汲極28外加至畫素電極（透明導 電膜）5。如此若對畫素電極（透明導電膜）5外加指定程 度的驅動電壓，則在與對向基板2之間發生充分的電位差 ，且液晶層3所含之液晶分子爲配向並且發生光變調。 又，於TFT構造的上方，爲了提高亮度有時設置反射 電極（未予圖示）。 200933895 圖8爲圖1中，A的主要部分放大圖之另一例。圖8 中，於玻璃基板la上形成掃描線（閘極電線）25，掃描 線25的一部分作爲控制TFT之開-關的閘極26之機能。 以覆蓋閘極26般形成閘極絕緣膜（SiN) 27。透過閘極絕 緣膜27與掃描線25交叉般形成信號線（源-汲極配線） 34，且信號線34的一部分作爲TFT之源極29之機能。於 閘極絕緣膜27上，依序形成非晶質矽通道層（活性半導 體層）、信號線（源-汲極配線）34、鈍化膜（保護膜、 SiN) 40。此型式一般被稱爲底部閘型。 於閘極絕緣膜27上之畫素區域，例如配置（In2〇3 ) 中含有10質量％左右氧化錫（SnO)之氧化銦錫（Indium Tin Oxide ; IT0 )膜、和（Ιη203 )中含有氧化鋅之氧化銦 鋅（Indium Zinc Oxide; IZO)膜所形成的畫素電極（透 明導電膜）5，於圖8中，TFT之汲極28爲直接接觸畫素 電極（透明導電膜）5並且以電性連接的構造。 若對此TFT基板，經由掃描線的閘極26外加閘極電 壓，則TFT4呈現打開的狀態，預先外加至信號線的驅動 電壓爲由源極29，經由汲極28外加至畫素電極（透明導 電膜）5。如此若對畫素電極（透明導電膜）5外加指定程 度的驅動電壓，則在與對向基板2之間發生充分電位差， 且液晶層3所含之液晶分子爲配向並且發生光變調。 又，於TFT之上方，爲了提高亮度有時設置反射電極 (未予圖示）。更且，畫素電極有時與反射電極接觸。 於圖8所示之TFT的源極29與汲極28之間外加電壓 -8-200933895 IX. Description of the Invention [Technical Field] The present invention relates to a display device and a Cu alloy film used therefor. In particular, in a thin film transistor (hereinafter referred to as a TFT) of a display device, a Cu alloy film for a display device directly connected to a transparent conductive film, and the Cu alloy film is used for the above-mentioned thin film transistor. For example, a flat panel display (φ display device) such as a liquid crystal display, an organic EL display, or a sputtering target for forming the above-described Cu alloy film. Further, the Cu alloy film used for the source and/or the drain of the thin film transistor and the signal line, and/or the gate and the scan line in the display device described above, and the Cu alloy film are used in the above A display device such as the liquid crystal display, the organic EL display, or the like used for the source and/or the drain and the signal line, and/or the gate and the scan line, and a sputtering target for forming the Cu alloy film. Further, in the display device, a liquid crystal display is described as an example, but it is not intended to be limited thereto. [Prior Art] For example, a liquid crystal display is used in a wide variety of fields, from small mobile phones to 30 吋 and large televisions over 100 。. This liquid crystal display is classified into a simple matrix type liquid crystal display and an active matrix type liquid crystal display according to the driving method of the pixel. Among them, an active matrix type liquid crystal display in which a TFT is used as a switching element has become a mainstream of liquid crystal displays because of its high image quality and high speed animation. -5- 200933895 Fig. 1 is a view showing the configuration of a representative liquid crystal display applied to an active matrix type liquid crystal display. The structure and operation principle of the liquid crystal display will be described with reference to Fig. 1 . First, the liquid crystal display 100 is a liquid crystal layer 3 including a TFT substrate 1 and a counter substrate 2 disposed opposite to the TFT substrate 1, and a function of an optical modulation layer disposed between the TFT substrate 1 and the counter substrate 2. The TFT substrate 1 is a TFT 4 having a insulating glass substrate 1a, a pixel electrode (transparent conductive film) 5, and a wiring portion 6 including scanning lines and signal lines. Further, the counter substrate 2 is a color filter 8 having a common electrode 7 formed on the entire glass plate and a pixel electrode (transparent conductive film) 5 on the opposite TFT substrate 1 side, and is opposed to each other. The TFT 4 on the TFT substrate 1 and the light shielding film 9 disposed at the position of the wiring portion 6. The counter substrate 2 further has an alignment film 11 which aligns liquid crystal molecules contained in the liquid crystal layer in a predetermined direction. Polarizing plates 10a and 10b are disposed on the outer sides of the TFT substrate 1 and the counter substrate 2 (on the opposite side of the liquid crystal layer). In the liquid crystal display 100, in each pixel, an electric field between the opposite substrate 2 and the pixel electrode (transparent conductive film) 5 is controlled by the TFT 4, and the alignment of the liquid crystal molecules in the liquid crystal layer 3 is caused by the electric field, and The light passing through the liquid crystal layer 3 is tuned (shading and light transmission). Thus, the amount of light transmitted through the opposite substrate 2 is controlled and displayed in an image type. A backlight 22 is disposed below the liquid crystal display 100, and the light passes upward from the lower side of FIG. -6- 200933895 Further, the TFT substrate 1 is driven by the drive circuit 13 and the control circuit 14 connected via the TAB tape 12. Fig. 2 is a view showing an enlarged view of a main portion of Fig. 1; In Fig. 2, a scanning line (gate wire) 25 is formed on the glass substrate 1a, and a part of the scanning line 25 functions as a gate 26 for controlling the on-off of the TFT. A gate insulating film (SiN) 27 is formed to cover the gate 26. A signal line (source-drain wiring) 34 ❹ is formed through the gate insulating film 27 and the scanning line 25, and a part of the signal line 34 functions as the source 29 of the TFT. On the gate insulating film 27, an amorphous germanium channel layer (active semiconductor film) 33, a signal line (source-drain wiring) 34, and an interlayer insulating film (SiN) 30 are sequentially formed. This type is generally referred to as the bottom gate type. In the pixel region on the gate insulating film 27, for example, an indium tin oxide (ITO) film containing about 1% by mass of tin oxide (SnO) and an IZO film containing zinc oxide in (Ιη203) are disposed (Ιη203). The formed pixel electrode (transparent conductive film) 5 is formed in Fig. 2, and the drain electrode 28 of the TFT is a structure in which a φ element electrode (transparent conductive film) 5 is directly drawn and electrically connected. When a gate voltage is applied to the gate electrode 26 via the scanning line, the TFT 4 is turned on, and the driving voltage applied to the signal line in advance is applied from the source 29 to the pixel electrode via the drain electrode 28 (transparent Conductive film) 5. When a driving voltage of a predetermined degree is applied to the pixel electrode (transparent conductive film) 5, a sufficient potential difference occurs between the counter electrode and the counter substrate 2, and liquid crystal molecules contained in the liquid crystal layer 3 are aligned and light is modulated. Further, a reflective electrode (not shown) may be provided above the TFT structure in order to increase the brightness. 200933895 FIG. 8 is another example of an enlarged view of a main portion of FIG. In Fig. 8, a scanning line (gate wire) 25 is formed on the glass substrate 1a, and a part of the scanning line 25 functions as a gate 26 for controlling the on-off of the TFT. A gate insulating film (SiN) 27 is formed to cover the gate 26. A signal line (source-drain wiring) 34 is formed through the gate insulating film 27 and the scanning line 25, and a part of the signal line 34 functions as the source 29 of the TFT. On the gate insulating film 27, an amorphous germanium channel layer (active semiconductor layer), a signal line (source-drain wiring) 34, and a passivation film (protective film, SiN) 40 are sequentially formed. This type is generally referred to as the bottom gate type. In the pixel region on the gate insulating film 27, for example, an indium tin oxide (ITO) film containing 10% by mass of tin oxide (SnO) is contained in (In2〇3), and (Ιη203) contains oxidation. a pixel electrode (transparent conductive film) 5 formed of a zinc indium zinc oxide (IZO) film. In FIG. 8, the drain electrode 28 of the TFT is a direct contact pixel electrode (transparent conductive film) 5 and The construction of the electrical connection. When a gate voltage is applied to the TFT substrate via the gate 26 of the scanning line, the TFT 4 is turned on, and the driving voltage applied to the signal line in advance is applied from the source 29 to the pixel electrode via the drain 28 (transparent Conductive film) 5. When a driving voltage of a predetermined degree is applied to the pixel electrode (transparent conductive film) 5, a sufficient potential difference occurs between the counter electrode and the counter substrate 2, and liquid crystal molecules contained in the liquid crystal layer 3 are aligned and light is modulated. Further, a reflective electrode (not shown) may be provided above the TFT in order to increase the brightness. Moreover, the pixel electrode is sometimes in contact with the reflective electrode. Applying a voltage -8- between the source 29 and the drain 28 of the TFT shown in FIG.

200933895 ’將閘極26之電壓進行ΟΝ/OFF控制，則可控 道層由源極29往汲極28的電流，並且經由畫素 制液晶層3的電場，其結果，令各畫素的光穿透 且亦可顯示動畫像。 上述源-汲極配線34和掃描線25、閘極26 | 易之理由，由Al-Nd等之A1合金（以下，將其稱 合金）薄膜所形成。 但是，近年來，由於液晶顯示器大型化和動 爲由60kHZ至120kHz變更等之情事，減低配線 成必須課題，具有更低電阻率之配線材料的需求 是’以電視用之大型面板爲中心，比純A1和A1 A1系材料更低電阻率，又，耐土堆（hillock) Cu系材料受到注目（金屬〔散裝材〕的電阻率， 2·7χ10_6Ω . cm，相對地純 Cu 爲 1·8χ10·6Ω · cm 但是，將Cu系材料應用於配線之情形，仍 化性低的技術課題。例如將Cu系材料應用於閘 源-汲極配線之情形，該閘極配線爲以閘極墊與 膜（ITO膜）連接’又，源-汲極配線爲以源極墊 電膜（ITO膜）連接。形成該構造之步驟，係於 配線和源-汲極配線形成後以約3 0 0 °C曝露於大氣 該步驟中’於構成閘極配線和源-汲極配線的Cu 面形成氧化皮膜。於形成此類氧化皮膜的（：11系 若形成透明導電膜（ITO膜），則該氧化皮膜變 鍵阻礙（shot key barrier)，故具有無法取得透 經由通 極5控 變調， 加工容 ! A1系 周波數 電阻變 高。於 金等之 優良的 ,A1爲 〇 留耐氧 配線和 明導電 透明導 述閘極 步驟， 配線表 線上， 射擊關 導電膜 200933895 與良好接觸性的課題。 又，將Cu系材料應用於配線時，亦具有與玻璃基板 (通常，以SiOz、ai2〇3、Ba0、b2〇3作爲主成分的玻璃 )和絕緣性之密黏性差的課題。液晶顯示器之閘極電線爲 於玻璃基板上形成’源-汲極配線爲於絕緣膜上形成。但 是’若於此些配線使用Cu系材料，則Cu系配線由玻璃基 板上剝離’故具有Cu系配線無法單獨應用於閘極配線的 課題。 爲了解決上述課題，以往，於源極29、汲極28、信 號線34、閘極26及掃描線25的上方和下方，分別進行形 成Mo、Cr、Ti、W等之高熔點金屬所構成的薄膜（以下 ，稱爲阻障金屬層）。 但是，於Cu系配線/阻障金屬層般之二層構造中，因 爲具有電阻率高的阻障金屬（Mo等），故以二層全體型 式的配線電阻（實效的配線電阻）具有變高的問題。更且 ，此類二層構造中，因爲將材質不同的薄膜層合，故具有 (1)步驟複雜、（2)在形成配線形狀圖型時的濕式蝕刻 (確保蝕刻速率、控制錐狀等之控制配線剖面形狀等）有 變難的問題，隨著液晶顯示器大量生產所伴隨的低費化， 而變成無法輕視形成阻障金屬層所伴隨的製造費用上升和 生產性降低。因此，急切期望可省略阻障金屬層的形成， 並可與透明導電膜直接接續的配線材料。 直到目前，已提案可省略形成阻障金屬層的Cu合金 膜’例如於專利文獻1中，示出ζη及/或M g以總量含有 -10- 200933895 0.1〜3.0原子％，或Ni及/或Μη以總量含有0.1〜0.5原子％ 的Cu合金膜，更且，Fe及/或Co以總量含有〇.〇2~1.〇原 子％和P爲含有0.005〜0_5原子％的Cu合金膜。 但是，於應付上述液晶顯示器之大型化等所伴隨之 Cu合金膜的電阻率進一步減低上，必須對於cu合金膜的 成分組成進一步檢討。 又，於專利文獻2中，提案大規模集成電路（LSI) 0 之配線所用的Cu-Ge合金，並且規定其組成。作爲LSI用 配線，期望其實效電阻率爲5μΩ · cm以下，於此情形中 ’以上述Cu-Ge合金亦可實現該電阻率。但是，使用於液 晶顯示器之配線的情形中，期望配線的實效電阻率比 2.5~3.0μ Ω · cm以下更低，但以上述Cu-Ge合金則難實現 該低電阻率。 更且’上述專利文獻1及2並未檢討令Cu合金膜與 玻璃基板的密黏性提高。 ❹ 又’將Cu系材料應用於配線時，具有與玻璃基板和 絕緣膜（例如閘極絕緣膜）之密黏性差的課題。特別，於 絕緣膜上形成時’具有如下之問題。即，通常以CVD所 形成的SiN膜作爲絕緣膜。先前所使用之A1系材料所構 成的電極•配線與絕緣膜的密黏性爲良好，但Cu系材料 所構成的電極•配線（Cu系電極•配線）與絕緣膜（特 別形成SiN膜作爲絕緣膜）的密黏性差，且Cu系電極. 配線爲由絕緣膜（SiN膜）剝離的問題。但是，關於與絕 緣膜（SiN膜）的密黏性提高，仍未被充分檢討。 -11 - 200933895 因此，先前採用Cu系電極•配線的液晶顯示器中， 採取SiN膜與Cu系電極•配線之間透過底膜（純Mo膜 、Mo-Ti合金層等之含Mo底層）的構造。即，具有於含 Mo底層中形成純Cu薄膜之二層構造的配線例。但是，此 類二層構造配線爲以電阻率高的含Mo底層作爲配線底層 ，故具有二層全體的配線阻抗（實效的配線阻抗）變高； 步驟變得複雜，耗費費用；由於層合材質不同的薄膜，故 於形成配線形狀圖型時，難以濕式蝕刻控制錐型；之課題 專利文獻1 :特開2007-017926號公報 專利文獻2:特開2005-191363號公報 【發明內容】 (發明所欲解決之課題） 本發明爲著眼於如上述之情事而完成者，本發明之第 1目的，係在於提供更加改善Cu合金膜特徵的低電阻率 ’並且可省略阻障金屬層的形成，並且與透明導電膜（ ITO膜，IZO膜等）直接接續時可取得良好接觸性的Cu 合金膜。 本發明之第2目的爲在於提供繼續維持Cu合金膜特 徵的低電阻率，並且與玻璃基板的密黏性優良，可省略與 玻璃基板間之阻障金屬層（即可以單層使用）的Cu合金 膜。 更且，本發明亦以提供（1)將上述Cu合金膜使用於 -12- 200933895 TFT’例如液晶顯示器所代表的平面面板顯示器（顯示裝 置）；及（2)形成具有如上述優良性能之Cu合金膜用的 濺鍍靶爲其目的。 又，本發明之第3目的爲在於提供繼續維持Cu系材 料特徵的低電阻率，並且與絕緣膜（例如SiN膜）之密黏 性優良的Cu合金膜，及其使用於TFT (特別，TFT之源 極及/或汲極以及信號線）未形成上述含Mo底層之例如液 晶顯示器所代表的平面面板顯示器（顯示裝置）。又，本 發明亦以提供形成具有如上述優良性能之Cu合金膜用的 濺鍍靶爲其目的。 (解決課題之手段） 所謂可達成第1目的之本發明的顯示裝置用Cu合金 膜，係於基板上，直接接續至透明導電膜之顯示裝置用 Cu合金膜，具有含有0.1~0.5原子％ ( at% ) Ge，且合計 含有0.1〜0.5原子％由Ni、Zn、Fe、及Co所組成群中選 出一種以上爲其特徵。 本發明亦包含具備含有前述Cu合金膜之薄膜電晶體 爲其特徵的顯示裝置，其態樣可列舉薄膜電晶體之閘極及 掃描線中含有前述Cu合金膜，且該Cu合金膜爲直接接續 至透明導電膜的顯示裝置，和薄膜電晶體之源極及汲極中 之至少一者及信號線中含有前述Cu合金膜，且該Cu合金 膜爲直接接續至透明導電膜的顯示裝置。 前述透明導電膜可列舉以氧化銦錫（ITO)或氧化銦 -13- 200933895 鋅（IZO )所形成者。 又，於本發明中，亦包含前述Cu合金膜之形成中所 用的濺鍍靶，含有 0.1〜〇·5原子％Ge，且，合計含有 0.1〜〇.5原子％由Ni、Zn、Fe、及Co所組成群中選出一種 以上之Cu合金所構成的濺鍍靶。 所謂可達成第2目的之本發明的顯示裝置用Cu合金 膜，係與玻璃基板直接接續的顯示裝置用Cu合金膜，具 有含有（1 )合計〇.2~1原子％Ge及Ni (即，不包含Ge 爲〇原子％或Ni爲0原子％之情形）：或（2 )合計0.2〜1 原子％Ge及Zn (即，不包含Ge爲0原子％或Zn爲0原 子％之情形）爲其特徵。 本發明亦包含具備含有前述Cu合金膜之薄膜電晶體 爲其特徵的顯示裝置，其態樣可列舉具備具有低部閘型構 造之薄膜電晶體的顯示裝置，於該薄膜電晶體之閘極及掃 描線中含有前述Cu合金膜，且該Cu合金膜爲直接接續至 玻璃基板的顯示裝置。 又，於本發明中，亦包含前述Cu合金膜之形成中所 用的濺鍍靶，（1)合計含有〇·2〜1原子％ Ge及Ni (即， 不包含Ge爲0原子％或Ni爲〇原子％之情形）之Cu合金 :或（2 )合計含有0.2~1原子％Ge及Zn (即，不包含Ge 爲〇原子％或Zn爲0原子％之情形）之Cu合金所構成的 濺鍍靶。 又，所謂可達成第3目的之本發明的顯示裝置用Cu 合金膜，係爲顯示裝置中薄膜電晶體之 -14- 200933895 源極及汲極中至少一者及信號線、 以及 閘極及掃描線 中之至少一者所含的顯示裝置用Cu合金膜，其具有含有 0.1〜0.5原子％ Ge爲其特徵。 又，本發明亦包含具有薄膜電晶體之 源極及汲極中之至少一者及信號線、 以及 閘極及掃描線 中之至少一者含有上述顯示裝置用Cu合金膜此點爲其特 徵的顯示裝置。 前述顯示裝置爲前述薄膜電晶體爲具有底部閘型構造 ，於絕緣膜（特別氮化矽膜）上具有前述源極及汲極中之 至少一者之一部分之形態者，因可充分發揮前述Cu合金 膜之效果，故爲佳。 又，於本發明中，亦包含前述Cu合金膜之形成中所 用的濺鍍靶，含有0.1~0.5原子°/❶Ge之Cu合金所構成的 濺鍍靶。 (發明之效果） 若根據本發明，則可實現具有可應付液晶顯示器之大 型化和動作周波數高區域化之低電阻率Cu合金膜的顯示 裝置。又，若根據可達成第1目的之本發明的態樣’（以 下’簡稱爲「第1態樣」），則可令Cu合金膜與ITO和 -15- 200933895 IZO等之透明導電膜’於低的接觸電阻下直接接觸。更且 ，若根據可達成第2目的之本發日月的態樣（以下’簡稱爲 「第2態樣」），則可令Cu合金膜與玻璃基板直接接續 。其結果，可提供能省略高熔點金屬薄膜（阻障金屬層） 之高性能的顯示裝置。又’若根據可達成第3目的之本發 明的態樣（以下’簡稱爲「第3態樣」），則本發明之 Cu合金膜爲與絕緣膜（特別SiN)膜的密黏性優良’故應 用於顯示裝置（例如液晶顯示器）用之源-汲極配線時’ 可未形成上述含Mo底層’作成單層’並且提供可省略上 述含Mo底層之高性能的顯示裝置。 【實施方式】 首先，由第1態樣開始說明。本發明者等人爲了實現 更加改善Cu合金膜特徵之低電阻率的同時，即使省略阻 障金靥層並與透明導電膜（ITO膜，IZO膜等）直接接續 之情形中，亦可取得良好接觸性的Cu合金膜，及將其使 用於TFT的顯示裝置，進行致力硏究。 首先，著眼於耐氧化性優良，且與透明導電膜（ITO 膜，IZO膜等）直接接續之情形中取得良好接觸性的Cu-Ge合金膜。Cu-Ge合金膜爲如專利文獻2記載，於As-deposited 狀態 係指剛 以濺鍍 形成後 之狀態 ，以下 相同） 中，Ge爲於Cu中均勻固溶，且Ge的濃度分佈於厚度方 向上爲均勻的。但是，若將此Cu-Ge合金膜，於氧分壓存 在之狀態下加熱，則Ge於Cu薄膜表面擴散、濃化，並於 -16- 200933895 表面形成強固的氧化皮膜（Ge02含有比率高的氧化皮膜 )。此氧化皮膜由於氧氣的擴散阻擋性極爲優良，故於高 溫（300 °C左右）大氣曝露後，不會於Cu合金膜表面形成 厚的氧化皮膜（結果未形成射擊關鍵阻礙），可確保與透 明導電膜良好之接觸性。於是，以如此可實現高溫耐氧化 性之同時，亦可實現某程度之低電阻率的Cu-Ge合金膜爲 基礎，進行可令電阻率進一步降低之第3元素種類和含量 的檢討。其結果，發現有效爲採用Ni、Zn、Fe、Co作爲 第3元素。 以下，詳述關於可確保低電阻率之同時，與透明導電 膜直接接續時可取得良好之歐姆接觸性之本發明之Cu合 金膜之成分•組成的規定理由。 首先，本發明之Cu合金膜爲以Ge作爲必須成分。經 由含有此Ge，則如上述，與純Cu之情形和含有Ge以外 之元素的2元系Cu合金相比較，可顯著提高耐氧化性， 例如即使經過300°C左右之大氣曝露步驟後，亦可確保與200933895 'When the voltage of the gate 26 is ΟΝ/OFF controlled, the current from the source 29 to the drain 28 can be controlled, and the electric field of the liquid crystal layer 3 is made via the pixel, and as a result, the light of each pixel is made. Penetrate and also display moving portraits. The reason why the source-drain wiring 34, the scanning line 25, and the gate 26 are easy is formed of a film of an A1 alloy (hereinafter referred to as an alloy) such as Al-Nd. However, in recent years, the size of the liquid crystal display has changed from 60 kHZ to 120 kHz, and the wiring has become a necessity. The demand for wiring materials having a lower resistivity is based on the large panel for television. Pure A1 and A1 A1 materials have lower resistivity, and the hillock-resistant Cu-based materials are attracting attention (the resistivity of metal [bulk], 2·7χ10_6Ω·cm, relatively pure Cu is 1. 8χ10·6Ω) · cm However, when a Cu-based material is applied to wiring, the technical problem is still low. For example, when a Cu-based material is applied to a gate-drain wiring, the gate wiring is a gate pad and a film ( ITO film) connection 'again, the source-drain wiring is connected by a source pad film (ITO film). The step of forming the structure is exposed at about 300 ° C after wiring and source-drain wiring are formed. In this step of the atmosphere, an oxide film is formed on the Cu surface constituting the gate wiring and the source-drain wiring. When the oxide film is formed (: 11 is formed into a transparent conductive film (ITO film), the oxide film becomes Key lock (shot key barrier), It is impossible to obtain the through-pass 5 control and the processing capacity! The A1 system has a high number of cycles, and the A1 is excellent for gold, etc., A1 is the residual oxygen-proof wiring and the conductive conductive transparent gate step, on the wiring line, When the Cu-based material is applied to wiring, it also has a glass substrate (generally, glass having SiOz, ai2〇3, Ba0, and b2〇3 as main components) and The problem of poor adhesion of the insulating property is that the gate wire of the liquid crystal display is formed on the glass substrate. The source-drain wiring is formed on the insulating film. However, if a Cu-based material is used for the wiring, the Cu-based wiring is used. Since the Cu-based wiring is peeled off, the problem that the Cu-based wiring cannot be applied to the gate wiring alone is solved. In order to solve the above problem, conventionally, the source electrode 29, the drain electrode 28, the signal line 34, the gate electrode 26, and the scanning line 25 are provided. A thin film (hereinafter referred to as a barrier metal layer) formed of a high melting point metal such as Mo, Cr, Ti, or W is formed under the film, and is formed in a two-layer structure like a Cu-based wiring/barrier metal layer. Since there is a barrier metal (Mo or the like) having a high specific resistance, the wiring resistance (effective wiring resistance) of the two-layer type has a problem of increasing height. Moreover, in such a two-layer structure, materials are different. Since the film is laminated, the step (1) is complicated, and (2) the wet etching (the etching rate, the shape of the control wiring such as the control tap, etc.) is difficult to form when forming the wiring pattern, and the like. The low cost associated with mass production of liquid crystal displays has become an inability to underestimate the increase in manufacturing costs and productivity with the formation of barrier metal layers. Therefore, it is eagerly desired to omit the formation of the barrier metal layer and to directly connect the wiring material to the transparent conductive film. Until now, it has been proposed to omit the Cu alloy film forming the barrier metal layer. For example, in Patent Document 1, it is shown that ζη and/or Mg are contained in a total amount of -10 200933895 0.1 to 3.0 atom%, or Ni and / Or Μη contains a Cu alloy film of 0.1 to 0.5 atom% in total, and further, Fe and/or Co contains 〇.〇2~1. 〇 atom% and P are Cu alloys containing 0.005 to 0_5 atom% in total. membrane. However, in order to further reduce the electrical resistivity of the Cu alloy film accompanying the increase in the size of the liquid crystal display, it is necessary to further examine the composition of the cu alloy film. Further, in Patent Document 2, a Cu-Ge alloy used for wiring of a large-scale integrated circuit (LSI) 0 is proposed, and its composition is defined. As the LSI wiring, the effective resistivity is desirably 5 μΩ · cm or less. In this case, the resistivity can also be achieved by the above Cu-Ge alloy. However, in the case of wiring for a liquid crystal display, it is desirable that the effective resistivity of the wiring is lower than 2.5 to 3.0 μΩ · cm or less, but it is difficult to achieve the low resistivity with the above Cu-Ge alloy. Further, the above Patent Documents 1 and 2 do not examine the improvement of the adhesion between the Cu alloy film and the glass substrate. Further, when a Cu-based material is applied to wiring, it has a problem of poor adhesion to a glass substrate and an insulating film (for example, a gate insulating film). In particular, when formed on an insulating film, the following problems occur. That is, an SiN film which is usually formed by CVD is used as an insulating film. The electrode/wiring formed by the A1 material used in the prior art is excellent in adhesion to the insulating film, but the electrode/wiring (Cu-based electrode and wiring) composed of a Cu-based material and the insulating film (in particular, the SiN film is formed as an insulating layer). The film has poor adhesion and a Cu-based electrode. The wiring is a problem of being peeled off by an insulating film (SiN film). However, the adhesion to the insulating film (SiN film) has not been sufficiently reviewed. -11 - 200933895 Therefore, in a liquid crystal display using a Cu-based electrode and a wiring, a structure in which a bottom film (a Mo-containing underlayer such as a pure Mo film or a Mo-Ti alloy layer) is passed between the SiN film and the Cu-based electrode and the wiring is used. . That is, a wiring example having a two-layer structure in which a pure Cu thin film is formed in the Mo-containing underlayer. However, since such a two-layer structure wiring has a Mo-containing underlayer having a high resistivity as a wiring underlayer, the wiring resistance (effective wiring resistance) of the entire two layers becomes high; the steps become complicated and costly; In the case of the formation of the wiring pattern, it is difficult to wet-etch the control of the taper type. Patent Document 1: JP-A-2007-017926 (Patent Document 2: JP-A-2005-191363) OBJECTS TO BE SOLVED BY THE INVENTION The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a low resistivity which further improves the characteristics of a Cu alloy film and to omit formation of a barrier metal layer. And a Cu alloy film which can obtain good contact property when directly connected to a transparent conductive film (ITO film, IZO film, etc.). A second object of the present invention is to provide a low resistivity which maintains the characteristics of a Cu alloy film, and which is excellent in adhesion to a glass substrate, and a Cu which can be omitted from the barrier metal layer (that is, can be used in a single layer) between the glass substrates can be omitted. Alloy film. Furthermore, the present invention also provides (1) the above-described Cu alloy film for use in a flat panel display (display device) represented by a liquid crystal display such as a -12-200933895 TFT'; and (2) forming a Cu having the above-described excellent properties. A sputtering target for an alloy film is intended for the purpose. Further, a third object of the present invention is to provide a Cu alloy film which is excellent in adhesion to a insulating film (for example, an SiN film) and which is excellent in adhesion to a Cu-based material, and is used for a TFT (particularly, TFT). The source and/or the drain and the signal line) do not form the above-described flat panel display (display device) represented by a liquid crystal display including the Mo underlayer. Further, the present invention has an object of providing a sputtering target for forming a Cu alloy film having the above-described excellent properties. (Means for Solving the Problem) The Cu alloy film for a display device of the present invention which achieves the first object is a Cu alloy film for a display device which is directly connected to a transparent conductive film, and has a content of 0.1 to 0.5% by atom. At%) Ge, and a total of 0.1 to 0.5 atom% is selected from the group consisting of Ni, Zn, Fe, and Co. The present invention also includes a display device including a thin film transistor including the Cu alloy film, and the aspect thereof includes the Cu alloy film in the gate and the scanning line of the thin film transistor, and the Cu alloy film is directly connected. The display device to the transparent conductive film and the at least one of the source and the drain of the thin film transistor and the signal line include the Cu alloy film, and the Cu alloy film is a display device directly connected to the transparent conductive film. The transparent conductive film may be formed by indium tin oxide (ITO) or indium oxide -13-200933895 zinc (IZO). Further, in the present invention, the sputtering target used for forming the Cu alloy film contains 0.1 to 〇·5 atom% of Ge, and the total amount of 0.1 to 原子.5 atom% is composed of Ni, Zn, Fe, A sputtering target composed of one or more Cu alloys selected from the group consisting of Co and Co. The Cu alloy film for a display device of the present invention which achieves the second object is a Cu alloy film for a display device which is directly connected to a glass substrate, and has a total of (1) ~2 to 1 atom% of Ge and Ni (that is, The case where Ge is not 〇 atom or Ni is 0 atom%): or (2) 0.2 to 1 atom% of Ge and Zn (that is, the case where Ge is 0 atom% or Zn is 0 atom%) Its characteristics. The present invention also includes a display device including a thin film transistor including the Cu alloy film, and a display device including a thin film transistor having a low gate structure, and a gate of the thin film transistor and The Cu alloy film is contained in the scanning line, and the Cu alloy film is a display device directly connected to the glass substrate. Further, in the present invention, the sputtering target used in the formation of the Cu alloy film is also contained, and (1) contains a total of 〜·2 to 1 atom% of Ge and Ni (that is, does not contain Ge of 0 atom% or Ni is Cu alloy in the case of 〇 atom%) or (2) a splash of Cu alloy containing 0.2 to 1 atom% of Ge and Zn (that is, a case where Ge is not contained or Zn is 0 atom%) Plating target. Further, the Cu alloy film for a display device of the present invention which achieves the third object is at least one of a source and a drain of a thin film transistor in a display device, a signal line, a gate, and a scan. A Cu alloy film for a display device included in at least one of the wires is characterized in that it contains 0.1 to 0.5 atom% of Ge. Furthermore, the present invention also includes the feature that at least one of the source and the drain of the thin film transistor and the signal line, and at least one of the gate and the scan line include the Cu alloy film for the display device. Display device. In the display device, the thin film transistor has a bottom gate structure and has at least one of the source and the drain on the insulating film (particularly a tantalum nitride film), so that the Cu can be sufficiently exhibited. The effect of the alloy film is good. Further, in the present invention, the sputtering target used for the formation of the Cu alloy film is further provided, and a sputtering target comprising a Cu alloy of 0.1 to 0.5 atomic %/Ge is contained. (Effects of the Invention) According to the present invention, it is possible to realize a display device having a low-resistivity Cu alloy film which can cope with the enlargement of the liquid crystal display and the high number of operation cycles. In addition, according to the aspect of the present invention which can achieve the first object (hereinafter, simply referred to as "the first aspect"), the Cu alloy film and the transparent conductive film of ITO and -15-200933895 IZO can be made. Direct contact under low contact resistance. Further, according to the aspect of the present day and the month in which the second object can be achieved (hereinafter referred to as "the second aspect"), the Cu alloy film can be directly connected to the glass substrate. As a result, it is possible to provide a display device capable of omitting a high-melting-point metal film (barrier metal layer). In addition, the Cu alloy film of the present invention has excellent adhesion to an insulating film (particularly SiN) film according to the aspect of the present invention in which the third object can be achieved (hereinafter, simply referred to as "the third aspect"). Therefore, when it is applied to a source-drain wiring for a display device (for example, a liquid crystal display), the above-described Mo-containing underlayer can be formed as a single layer, and a display device capable of omitting the high performance of the Mo-containing underlayer can be provided. [Embodiment] First, the first aspect will be described. In order to achieve a lower resistivity of the characteristics of the Cu alloy film, the inventors of the present invention can achieve good results even when the barrier metal layer is omitted and directly connected to the transparent conductive film (ITO film, IZO film, etc.). A contact Cu alloy film and a display device using the same for TFT are made to investigate. First, attention is paid to a Cu-Ge alloy film which is excellent in oxidation resistance and which is in direct contact with a transparent conductive film (ITO film, IZO film, etc.). The Cu-Ge alloy film is described in Patent Document 2, and in the As-deposited state, the state immediately after sputtering, the same applies hereinafter, Ge is uniformly dissolved in Cu, and the concentration of Ge is distributed in the thickness direction. The upper is even. However, when the Cu-Ge alloy film is heated in the presence of oxygen partial pressure, Ge diffuses and concentrates on the surface of the Cu film, and a strong oxide film is formed on the surface of -16-200933895 (the Ge02 content ratio is high). Oxidation film). Since the oxide film is extremely excellent in diffusion barrier property of oxygen, after exposure to the atmosphere at a high temperature (about 300 ° C), a thick oxide film is not formed on the surface of the Cu alloy film (the result is that no key impediment is formed), and transparency and transparency can be ensured. Good contact of the conductive film. Therefore, in consideration of the high-temperature oxidation resistance, it is possible to carry out a review of the third element type and content which can further reduce the electrical resistivity based on a Cu-Ge alloy film having a certain low resistivity. As a result, it was found to be effective to use Ni, Zn, Fe, and Co as the third element. In the following, the reason for the composition and composition of the Cu alloy film of the present invention which can achieve good ohmic contact when directly connected to the transparent conductive film while ensuring low resistivity is described in detail. First, the Cu alloy film of the present invention contains Ge as an essential component. By including the Ge, as described above, the oxidation resistance can be remarkably improved as compared with the case of pure Cu and the ternary Cu alloy containing an element other than Ge, for example, even after an atmospheric exposure step of about 300 ° C. Can ensure

Cu合金膜上方所形成之透明導電膜之良好的歐姆接觸性 〇 於充分發揮此類效果上，含有0.1原子％以上Ge。若 Ge相對於Cu薄膜的絕對量少，則上述氧化皮膜（Ge〇2) 難以均勻之連續膜型式形成，結果，無法有效作用爲氧氣 的擴散阻擋層，無法充分發揮高溫耐氧化性。較佳爲含有 0.2原子°/。以上Ge。Ge之含量愈多則Cu合金膜的高溫耐 氧化性愈提高，但由於C u合金膜的電阻率增加，故必須 -17- 200933895 將Ge的含量抑制於0.5原子％以下（較佳爲〇·3原子％以 下）。 但是，Cu-Ge的2元系Cu合金膜，具有Ge含量愈增 加則電阻率愈增加的傾向，與純Cu膜相比較則電阻率高 。並且，Cu-Ge合金膜於施以熱處理（較佳爲450 °C以下 ，更佳爲400 °C以下）之情形中，電阻率降低之傾向小， 無法期待經由熱履歷而造成低電阻率化。 於是，若令作爲第3元素之Ni、Zn、Fe、及Co所組 成群中選出一種以上（以下，稱爲 X) ’合計含有 0.1〜0·5原子％，作成Cu-Ge-X合金膜，則可知在熱處理 該合金膜時，促進Ge的析出，且電阻率爲比Cu-Ge合金 膜充分降低。 如此將Cu-Ge-X合金膜熱處理令電阻率降低者’係認 爲例如於Cu-Ge-Ni合金膜之情形中，Ni3Ge和NiGe爲析 出，於Cu-Ge-Zn合金膜之情形中，Cui5Ge4Zn爲析出’ 於Cu-Ge-FE合金膜之情形中，Fe2Ge、FeGe2爲析出，又 於Cu-Ge-Co合金膜之情形中，分別析出Co2Ge、CoGe、 Co2Ge3、CoGe2，且Ge及第3元素之固溶量減低。 組合複數 X 者’可列舉 Cu-Ge-Ni-Zn、Cu-Ge-Zn-Co 、Cu-Ge-Ni-Co，如此組合複數X之情形中，亦分別形成 上述X與Ge之析出物。因此，此情形亦不會令各元素的 添加效果相互抵銷，可發揮減低電阻率之效果。 於發揮上述效果上，令X含量總量爲0.1原子％以上 即可。較佳爲0.2原子％以上。但是，總量若超過0.5原 200933895 子％，則第3元素爲過剩存在超過Ge含量，未與Ge完成 反應之第3元素（與Ge反應未完成形成金屬間化合物的 第3元素）爲以剩餘元素（於Cu合金膜中的固溶元素） 型式殘留，反而令Cu合金膜的電阻率增加，故爲不佳。 由此類觀點而言，認爲Ce含量（原子％ ) /X含量（原子％ )之比率爲1〜2爲佳。 其次說明第2態樣。第2態樣之Cu合金膜亦與第1 φ 態樣之Cu合金膜同樣地，由Cu-Ge-X (第3元素）合金 所構成，但選擇Ni或Zn作爲X此點爲與第1態樣不同。 達成第2目的，即，繼續確保Cu合金膜特徵之低電 阻，並且提高Cu配線與玻璃基板之密黏性上，期望於Cu 配線與玻璃基板之間形成結合能量大的化學性鍵結。即， 相比於「以物理吸黏等所造成的物理性鍵結」，若形成結 合能量（鍵結力）大之「以化學吸黏和形成界面反應層等 所造成的化學性鍵結」，則可實現更強的密黏力。但是， ❹ 由於Cu配線與玻璃基板形成化學性鍵結，故Cu配線與玻 璃基板的密黏性差。 於是，本發明者等人著眼於Cu中添加指定的合金元 素’並於該合金元素與玻璃基板之構成元素間形成化學性 鍵結’以提高與玻璃基板的密黏性。於此化學性鍵結的形 成上’ Ge爲有效作用。Ge爲與氧的親和性強（易形成氧 化物）’且與玻璃基板之主成分Si02反應，於玻璃基板 界面透過氧形成鍵結（Si-0-Ge)。又，Ge於CU中的擴 散係數大’故即使於Cu膜中少量添加亦於玻璃基板界面 -19- 200933895 擴散濃化，並於界面透過氧形成鍵結，令密黏性大幅提高 〇 除了具有此類提高密黏性作用之Ge，加上複合添加 Ni或Zn，則可令Cu合金膜對於玻璃基板的密黏性進一步 提高。此（Ge，Ni )或（Ge，Zn )複合添加的作用雖未 明確，但認爲經由在Cu中添加Ni或Zn，則可促進Ge往 界面的擴散濃化。 又，通常若於Cu中添加合金元素則導致電阻率增加 ，但即使於Cu中添加Ni或Zn，亦幾乎完全不會增加Cu 合金的電阻率。Cu-Ni合金爲全率固溶系，Ni爲於Cu中 全率固溶，故認爲增加電阻率的幫助少。另一方面，Cu-Zn合金爲包晶系，但Zn於Cu中的固溶限制寬至約30% ，故認爲增加電阻率的幫助少。更且如上述，Cu-Ge-Ni合 金中經由熱處理令Ni3Ge、NiGe以金屬間化合物型式析出 ，於Cu-Ge-Zn合金配線中經由熱處理令Cu15Ge4Zn以金 屬間化合物型式析出，故Ni或Zn對於Cu-Ge合金中的添 加，亦有效作用於減低電阻率。 爲了令如上述與玻璃基板之良好密黏性及低電阻率兩 相成立，令（Ni，Ge)或（Zn，Ge)的合計量均爲0.2原 子％以上（較佳爲0.3原子％以上）' 1原子％以下（較佳 爲0.6原子％以下）。此合計量若過少，則合金元素朝向 玻璃基板界面的濃化程度亦少，於界面形成化學鍵結的程 度亦少，無法良好發揮高密黏性。又，此合計量若過剩， 雖可提高密黏性，但Cu合金膜本身的電阻率增加。又， -20- 200933895 第2態樣中之較佳的Ge含量（原子％ ) /X含量（原子％ )之比率爲〇·5〜2.〇。 於第2態樣中，於提高Cu合金膜之高溫耐氧化性且 實現與透明導電膜之良好接觸性，加上減低電阻率上’以 亦滿足第1態樣之元素量要件爲佳。即’第2態樣亦以 Ge量較佳爲0.1原子％以上（更佳爲0.2原子％以上）’ 較佳爲0.5原子％以下（更佳爲0.3原子％以下），Ni、Zn 之各量較佳爲0.1原子％以上（更佳爲〇·2原子％以上）、 較佳爲0.5原子％以下（更佳爲0.4原子％以下）。 上述（即第1態樣及第2態樣之）Cu-Ge-X合金膜爲 含有上述規定量之Ge及第3元素（X) ’且殘餘部分Cu 及不可避免之雜質。前述不可避免之雜質可列舉氧、氮、 碳、氬等，其合計爲0.1原子％以下。又，爲了提高其他 特性（例如耐蝕性等），於Cu-Ge-X合金膜中亦可進一步 含有其他元素。 於上述Cu-Ge-X合金膜之形成上，期望採用濺鍍法。 所謂濺鍍法，係於真空中導入Ar等之惰性氣體，於基板 與濺鍍靶（以後，有時稱爲靶）之間形成電漿放電，並將 經由該電漿放電所離子化的Ar衝撞至上述靶，敲出該靶 之原子並於基板上堆積製造薄膜的方法。因爲可比離子電 鍍法和電子束蒸鑛法、真空蒸鍍法所形成之薄膜更輕易形 成成分和膜厚之膜面內均勻性優良的薄膜，且以 As-deposited 狀態 可形成 合金元 素爲均 勻固溶 的薄膜 ，故可 有效表現高溫耐氧化性等。濺鍍法例如可採用DC濺鍍法 -21 - 200933895 、RF濺鍍法、磁控管濺鍍法、反應性濺鍍法等之任一種 濺鍍法，且其形成條件若適當設定即可。 又，以上述濺鍍法，形成上述Cu-Ge-X合金膜上，若 使用與所欲之Cu-Ge-X合金膜相同成分，組成的Cu-Ge-X 合金濺鍍靶，則無組成不勻，可形成所欲之成分、組成的 Cu-Ge-X合金膜。即，於形成第1態樣之Cu-Ge-X合金膜 上，若使用含有0.1〜0.5原子％之Ge、及0.1〜0.5原子％由 Ni、Zn、Fe、及Co所組成群中選出一種以上之Cu合金 所構成者，與所欲之Cu-Ge-X合金膜相同成分、組成的 Cu-Ge-X合金濺鍍靶即可。又，於形成第2態樣之Cu-Ge-X合金膜上，若使用（1)合計含有0.2〜1原子％〇6及Ni 之Cu合金：或（2)合計含有0.2〜1原子％Ge及Zn之Cu 合金所構成者，與所欲之Cu-Ge-X合金膜相同成分、組成 的Cu-Ge-X合金濺鍍靶即可。 靶之形狀爲包含根據濺鍍裝置之形狀和構造加工成任 意形狀（角型平板狀、圓形平板狀、環形平板狀等）者。 上述靶之製造方法可列舉以溶解鑄造法和粉末燒結法 、噴霧成形法，製造Cu基合金所構成之鑄塊而取得之方 法，和製造Cu基合金所構成之雛型（取得最終緻密體前 的中間體）後，以緻密化手段將該雛型予以緻密化而取得 之方法等。 以濺鍍法等形成上述Cu-Ge-X合金膜後，期望施以熱 處理。經由熱處理，於第1態樣之Cu合金膜令電阻率（ 配線電阻）減低，於第2態樣之Cu合金膜，與玻璃基板 -22- 200933895 的密黏性提高之同時，電阻率亦減低。於此些Cu合 中電阻率減低，認爲係因如上述Ni3Ge等析出，Ge及 元素（X)之固溶量減低。又，第2態樣之Cu合金膜 玻璃基板之密黏性提高，認爲係因經由熱處理（熱能 ’促進合金元素於Cu合金膜及玻璃基板界面的濃化 且亦促進界面形成化學性鍵結。 熱處理溫度愈高，且熱處理時間（保持時間）愈 認爲愈有效減低電阻率及提高密黏性。但是，若熱處 溫度及時間爲過剩，則對玻璃基板造成不良影響，生 降低。因此’熱處理溫度較佳爲35(TC以上，更佳爲 °C以下（再佳爲400°C以下），熱處理時間較佳爲30 以上，更佳爲120分鐘以下。 本發明之Cu-Ge-X合金膜爲特別使用顯示裝置的 。其中若將第1態樣之Cu-Ge-X合金膜，特別使用於 • TFT之閘極及掃描線、及/或 •源極及/或汲極、以及信號線， 則可充分發揮其特性。 又，第2態樣之Cu-Ge-X合金膜爲省略阻障金屬 特別於具有底部閘型構造之前述TFT的源極及掃描線 單層使用爲佳。 另外，本發明之Cu-Ge-X合金膜複數使用於上述 之閘極及掃描線、源極及/或汲極、以及信號線之情 ，構成彼等之Cu-Ge-X合金膜的成分，組成亦可爲一 且於規定範圍內令成分、組成不同亦可。Good ohmic contact property of the transparent conductive film formed over the Cu alloy film 含有 0.1% by atom or more of Ge in order to sufficiently exert such effects. When the absolute amount of Ge relative to the Cu thin film is small, the oxide film (Ge〇2) is difficult to form a uniform continuous film pattern, and as a result, it is not effective as a diffusion barrier layer of oxygen, and high-temperature oxidation resistance cannot be sufficiently exhibited. It is preferably contained at 0.2 atomic %. Above Ge. The higher the content of Ge, the higher the high temperature oxidation resistance of the Cu alloy film. However, since the resistivity of the Cu alloy film increases, it is necessary to suppress the content of Ge to 0.5 atomic % or less (preferably 〇····· 3 atom% or less). However, in the Cu-Ge ternary Cu alloy film, as the Ge content increases, the resistivity tends to increase, and the resistivity is higher than that of the pure Cu film. Further, in the case where the Cu-Ge alloy film is subjected to heat treatment (preferably 450 ° C or lower, more preferably 400 ° C or lower), the tendency of the resistivity to decrease is small, and it is impossible to expect a low resistivity due to the heat history. . Then, one or more selected from the group consisting of Ni, Zn, Fe, and Co as the third element (hereinafter, referred to as X)' is contained in an amount of 0.1 to 0.5 atomic % in total to form a Cu-Ge-X alloy film. It is understood that when the alloy film is heat-treated, precipitation of Ge is promoted, and the specific resistance is sufficiently lower than that of the Cu-Ge alloy film. Thus, the heat treatment of the Cu-Ge-X alloy film is such that the resistivity is lowered. In the case of, for example, a Cu-Ge-Ni alloy film, Ni3Ge and NiGe are precipitated, and in the case of the Cu-Ge-Zn alloy film, When Cui5Ge4Zn is precipitated in the case of Cu-Ge-FE alloy film, Fe2Ge and FeGe2 are precipitated, and in the case of Cu-Ge-Co alloy film, Co2Ge, CoGe, Co2Ge3, CoGe2, Ge and 3rd are precipitated, respectively. The amount of solid solution of the element is reduced. The combination of the plural X's can be exemplified by Cu-Ge-Ni-Zn, Cu-Ge-Zn-Co, and Cu-Ge-Ni-Co, and in the case where the complex number X is combined, the precipitates of the above X and Ge are also formed, respectively. Therefore, this situation does not offset the additive effect of each element, and the effect of reducing the resistivity can be exerted. In order to exert the above effects, the total amount of X may be 0.1 atom% or more. It is preferably 0.2 atom% or more. However, if the total amount exceeds 0.5% of the original 200933895%, the third element is an excess of the Ge content exceeding the Ge content, and the third element which does not complete the reaction with Ge (the third element which does not complete the formation of the intermetallic compound with the Ge reaction) is left. The element (solid solution element in the Cu alloy film) remains in the form, which in turn causes the resistivity of the Cu alloy film to increase, which is not preferable. From such a viewpoint, it is considered that the ratio of the Ce content (atomic %) / X content (atomic %) is preferably 1 to 2. Next, the second aspect will be described. The Cu alloy film of the second aspect is also composed of a Cu-Ge-X (third element) alloy similarly to the Cu alloy film of the first φ state, but the point of selecting Ni or Zn as X is the first The situation is different. In order to achieve the second object, in order to further ensure the low resistance of the Cu alloy film and to improve the adhesion between the Cu wiring and the glass substrate, it is desirable to form a chemical bond having a large bonding energy between the Cu wiring and the glass substrate. That is, compared with "physical bonding caused by physical adhesion, etc.", if a bonding energy (bonding force) is formed, "chemical bonding caused by chemical adsorption and formation of an interface reaction layer, etc." is formed. , can achieve stronger adhesion. However, since the Cu wiring forms a chemical bond with the glass substrate, the adhesion between the Cu wiring and the glass substrate is inferior. Then, the inventors of the present invention paid attention to the addition of a specified alloy element ' in Cu and formed a chemical bond between the alloy element and the constituent elements of the glass substrate to improve the adhesion to the glass substrate. The formation of this chemical bond is 'Ge' effective. Ge has a strong affinity with oxygen (it is easy to form an oxide) and reacts with the main component SiO 2 of the glass substrate to form a bond (Si-0-Ge) through the oxygen at the interface of the glass substrate. Moreover, the diffusion coefficient of Ge in CU is large, so even if it is added in a small amount in the Cu film, it is diffused and concentrated at the glass substrate interface -19-200933895, and the bond is transmitted through the interface at the interface, so that the adhesion is greatly improved. Such a Ge which enhances the adhesion and the addition of Ni or Zn in combination can further improve the adhesion of the Cu alloy film to the glass substrate. Although the effect of the (Ge, Ni) or (Ge, Zn) composite addition is not clear, it is considered that by adding Ni or Zn to Cu, diffusion of Ge to the interface can be promoted. Further, generally, when an alloying element is added to Cu, the electrical resistivity is increased. However, even if Ni or Zn is added to Cu, the electrical resistivity of the Cu alloy is hardly increased at all. The Cu-Ni alloy is a full-rate solid solution system, and Ni is a solid solution at a full rate in Cu, so that it is considered that the increase in resistivity is less. On the other hand, the Cu-Zn alloy is a peritectic system, but the solid solution limitation of Zn in Cu is as wide as about 30%, so that it is considered that the increase in resistivity is small. Further, as described above, in the Cu-Ge-Ni alloy, Ni3Ge and NiGe are precipitated as an intermetallic compound by heat treatment, and Cu15Ge4Zn is precipitated as an intermetallic compound by heat treatment in the Cu-Ge-Zn alloy wiring, so Ni or Zn is The addition in the Cu-Ge alloy is also effective in reducing the resistivity. In order to establish both the good adhesion and the low electrical resistivity of the glass substrate as described above, the total amount of (Ni, Ge) or (Zn, Ge) is 0.2 atom% or more (preferably 0.3 atom% or more). '1 atom% or less (preferably 0.6 atom% or less). If the total amount is too small, the degree of concentration of the alloying element toward the interface of the glass substrate is small, and the degree of chemical bonding at the interface is small, so that high-viscosity cannot be exhibited well. Further, if the total amount is excessive, the adhesion can be improved, but the electrical resistivity of the Cu alloy film itself increases. Further, -20-200933895 The ratio of the preferred Ge content (atomic %) / X content (atomic %) in the second aspect is 〇·5~2. In the second aspect, it is preferable to increase the high-temperature oxidation resistance of the Cu alloy film and achieve good contact with the transparent conductive film, and to reduce the resistivity to satisfy the elemental quantity of the first aspect. In other words, the second aspect also preferably has a Ge content of 0.1 atom% or more (more preferably 0.2 atom% or more), preferably 0.5 atom% or less (more preferably 0.3 atom% or less), and each of Ni and Zn. It is preferably 0.1 atom% or more (more preferably 〇2 atom% or more), preferably 0.5 atom% or less (more preferably 0.4 atom% or less). The above-mentioned (i.e., the first aspect and the second aspect) Cu-Ge-X alloy film contains the predetermined amount of Ge and the third element (X)', and the residual portion Cu and unavoidable impurities. Examples of the unavoidable impurities include oxygen, nitrogen, carbon, argon, and the like, and the total amount thereof is 0.1 atom% or less. Further, in order to improve other characteristics (e.g., corrosion resistance, etc.), other elements may be further contained in the Cu-Ge-X alloy film. In the formation of the above Cu-Ge-X alloy film, it is desirable to use a sputtering method. In the sputtering method, an inert gas such as Ar is introduced into a vacuum, and a plasma discharge is formed between a substrate and a sputtering target (hereinafter sometimes referred to as a target), and Ar ionized by the plasma discharge is introduced. A method of colliding with the target, knocking out atoms of the target, and depositing a film on the substrate. Because the film formed by the ion plating method, the electron beam evaporation method, or the vacuum evaporation method can form a film having excellent uniformity in the film surface of the component and the film thickness, and the alloy element can be uniformly formed in the As-deposited state. The film is dissolved, so it can effectively exhibit high temperature oxidation resistance. The sputtering method may be, for example, a sputtering method of DC sputtering method - 21 - 200933895, RF sputtering method, magnetron sputtering method, reactive sputtering method, or the like, and the formation conditions may be appropriately set. Further, when the Cu-Ge-X alloy sputtering film is formed on the Cu-Ge-X alloy film by the sputtering method, the composition of the Cu-Ge-X alloy sputtering target having the same composition as that of the desired Cu-Ge-X alloy film has no composition. The unevenness can form a Cu-Ge-X alloy film of a desired composition and composition. That is, in the Cu-Ge-X alloy film on which the first aspect is formed, one selected from the group consisting of 0.1 to 0.5 at% of Ge and 0.1 to 0.5 at% of Ni, Zn, Fe, and Co. The Cu-Ge-X alloy sputtering target having the same composition and composition as the Cu-Ge-X alloy film as described above may be used for the above-mentioned Cu alloy. Further, on the Cu-Ge-X alloy film in which the second aspect is formed, (1) a Cu alloy containing 0.2 to 1 atom% of ruthenium 6 and Ni in total is used: or (2) a total of 0.2 to 1 atom% of Ge is used. And a Cu-Ge-X alloy sputtering target having the same composition and composition as the Cu-Ge-X alloy film of the Zn alloy. The shape of the target is such that it is processed into any shape (angular plate shape, circular flat plate shape, annular flat plate shape, etc.) according to the shape and configuration of the sputtering apparatus. Examples of the method for producing the above-mentioned target include a method of producing an ingot made of a Cu-based alloy by a dissolution casting method, a powder sintering method, a spray molding method, and a prototype of a Cu-based alloy (before obtaining a final dense body). After the intermediate), the method of densifying the prototype is obtained by densification means. After the Cu-Ge-X alloy film is formed by sputtering or the like, it is desirable to apply heat treatment. Through the heat treatment, the Cu alloy film in the first aspect reduces the resistivity (wiring resistance), and the Cu alloy film in the second aspect has a higher adhesion to the glass substrate-22-200933895, and the resistivity is also lowered. . When the resistivity is lowered in the above-mentioned Cu combination, it is considered that the solid solution amount of Ge and the element (X) is lowered by precipitation of Ni3Ge or the like as described above. Further, the adhesion property of the Cu alloy film glass substrate of the second aspect is improved, and it is considered that the alloy element is promoted to form a chemical bond at the interface between the Cu alloy film and the glass substrate via heat treatment (heat energy). The higher the heat treatment temperature, the more effective the heat treatment time (holding time) is to reduce the resistivity and improve the adhesion. However, if the temperature and time of the heat are excessive, the glass substrate is adversely affected and the growth is lowered. The heat treatment temperature is preferably 35 (TC or more, more preferably ° C or less (more preferably 400 ° C or less), and the heat treatment time is preferably 30 or more, more preferably 120 minutes or less. Cu-Ge-X of the present invention The alloy film is particularly suitable for use in a display device, wherein the first aspect of the Cu-Ge-X alloy film is particularly used for the gate and scan lines of the TFT, and/or the source and/or the drain, and In addition, the second aspect of the Cu-Ge-X alloy film is preferably used for omitting the barrier metal, particularly for the source of the TFT having the bottom gate structure and the scanning line single layer. In addition, the Cu-Ge-X alloy of the present invention The plurality of components used in the above-mentioned gate and scan lines, source and/or drain electrodes, and signal lines constitute the composition of the Cu-Ge-X alloy film, and the composition may be one and within the specified range. Composition and composition are also different.

金膜 .第3 中與 量） ，並 長， 理的 產性 450 分鐘 TFT 層， ，以 TFT 形中 致， -23- 200933895 以下，一邊參照圖面，一邊說明本發明之顯示裝置的 較佳實施形態。以下，代表性列舉說明具備非晶矽TFT基 板的液晶顯示裝置，但本發明不被限定於此，在適合前、 後述主旨之範圍中加以適當變更進行實施亦可，其均被包 含於本發明的技術性範圍。 於前述圖2中，列舉將源極29和汲極28、信號線（ 於圖2中未顯示）、及/或掃描線（閘極配線）25和閘極 26，以本發明之Cu合金膜（例如Cu-0.3原子％Ge-0.3原 子％Ni合金）作成之一態樣。 若根據本實施形態（第1之態樣），不會如先前般， 於源-汲極的上方，不必中介存在Mo等所構成的阻障金屬 層，可令Cu合金膜與透明導電膜直接接續，且可實現與 先前之TFT基板同程度以上之良好的TFT特性（參照後 述之實施例）。又，若根據第2態樣，於掃描線（閘極配 線）和閘極之下方不必中介存在阻障金屬層，可令Cu合 金膜與玻璃基板直接接續。 其次，一邊參照圖3〜7，一邊說明圖2所示之本實施 形態之TFT基板的製造方法。圖3~7中加以與圖2相同的 參照符號。 首先，如圖3所示般，於玻璃基板（透明基板）ia, 使用濺鍍法形成厚度20〇nm左右的Cu合金膜（例如， Cu-0.3原子％Ge-0.3原子％Ni合金）。將此膜形成圖型， 則可形成閘極26及掃描線25。此時，於後述之圖4中， 以閘極絕緣膜27之覆蓋範圍爲良好般，將上述層合薄膜 -24- 200933895 之側面以傾斜角約30°〜60。之錐狀予以蝕刻爲佳。 其次’如圖4所示般，例如使用電漿CVD法等之方 法’形成約3 00nm左右的閘極絕緣膜（siN ) 27。電漿 CVD法之成膜溫度若爲約3 5 0。(：即可。 接著，如圖5所示般，例如使用電漿CVD法等之方 法’於閘極絕緣膜（SiN ) 27之上，形成厚度200nm左右 之無摻混氫化非晶矽膜（a-Si: H)、及厚度50nm左右之 φ 摻混磷的n+型氫化非晶矽膜（n + a_si : η )所構成的非晶 矽通道膜（活性半導體膜）33，並將此膜33形成圖型。 其次於其上，使用濺鍍法，形成厚度3 OOnm左右之Cu合 金膜（例如，Cu-0.3原子％Ge-0.3原子％Ni合金）後形成 圖型，則如圖6所示般，形成與信號線一體之源極29、和 直接接續至畫素電極（透明導電膜）5的汲極28。另外， 上述濺鍍之成膜溫度若爲約150°C即可。 其次，如圖7所示般，例如使用電漿CVD裝置等， φ 形成厚度300nm左右之層間絕緣膜30。其次，於層間絕 緣膜30上形成光阻（未予圖示）後，將層間絕緣膜30形 成圖型，例如以乾式蝕刻等在層間絕緣膜3 0上形成接觸 孔。同時，與面板端部之閘極上之TAB接續的部分上形 成接觸孔。 最後，例如於保管時間（8小時左右）之範圍內，如 前述圖2所示般，例如成膜出厚度4Onm左右的ITO膜， 並以濕式蝕刻進行形成圖型，則可形成畫素電極（透明導 電膜）5。同時，與面板端部之閘極之TAB的接續部分， -25- 200933895 右形成用以與TAB接黏之ιτο膜41圖型，則完成TFT陣 列基板1。 如此處理所製作的TFT基板，汲極28與畫素電極（ 透明導電膜）5爲直接接觸’且掃描線25與TAB接續用 之ITO膜亦直接接觸。 上述，雖使用ITO膜作爲畫素電極（透明導電膜）5 ’但亦可使用IZO膜（InOx-ZnOx系導電性氧化膜）。又 ’亦可使用多晶矽代替非晶矽作爲活性半導體膜。 使用如此處理所得的T F T基板，例如，根據下列記載 之方法’製作前述圖1所示的液晶顯示器。 首先’於如上述處理所製作之TFT基板1的表面，例 如塗佈聚醯亞胺，乾燥後進行摩擦處理以形成配向膜。 另一方面’對向基板2爲於玻璃基板上，例如將Cr 以矩陣狀形成圖型，則可形成遮光膜9。其次，於遮光膜 9之間隙，形成樹脂製之紅、綠、藍的彩色濾光片8。於 遮光膜9與彩色濾光片8上，配置ITO膜般之透明導電性 膜作爲共通電極7，則可形成對向電極。其後，於對向電 極之最上層例如塗佈聚醯亞胺，乾燥後，進行摩擦處理形 成配向膜1 1。 其次，將TFT基板1與對向基板2之形成配向膜11 的面彼此對向配置，並以樹脂製的密封材1 6，除去液晶的 封入口將TFT基板1與對向基板2貼合。此時，於TFT 基板1與對向基板2之間，中介存在間隔件15令2枚基 板間的間隙大約保持一定。 -26- 200933895 將如此處理所得之空元件放於真空中，以封入口浸於 液晶之狀態慢慢恢復至大氣壓，則可於空元件中注入含有 液晶分子的液晶材料，形成液晶層，並將封入口封合。最 後，於空元件之外側兩面貼上偏光板l〇a、1 〇b並完成液 晶面板。 其次’如前述圖1所示般，於液晶顯示器電性接續驅 動液晶顯示器的驅動電路13，並且配置於液晶顯示器的側 ❹ 部或裏面部。其後，經由含有成爲液晶顯示器之顯示面開 口的保持框23、和成爲面光源之背光22和導光板20和保 持框23’保持液晶顯示器，並且完成液晶顯示器。 本發明之顯示裝置爲以規定的Cu合金膜形成配線、 電極部，故可實規格外優良的性能和信賴性。 其次說明第3態樣。本發明者等人爲了實現繼續維持 Cu系材料特徵的低電阻率，並且與絕緣膜（例如氮化矽 膜）之密黏性優良的Cu合金膜、及將其使用於TFT之顯 〇 示裝置’進行致力硏究。其結果，以所謂若作成含有少量 Ge的Cu合金膜即可的思想爲基礎，發現其具體性方法。 以下’詳述關於第3 .態樣。 本發明之Cu合金膜爲含有0.1〜0.5原子％ ( at% ) Ge (以下，將此類本發明之Cu合金膜，特別稱爲「含Cu-G e合金膜」）。本發明中，發現經由含有0 · 1原子％以上 (較佳爲0.15原子％以上、更佳爲0·20原子％以上）Ge， 則可顯著提高與絕緣膜的密黏性。 如此經由含有Ge可表現高密黏性的理由並未充分闡 -27- 200933895 明，但於絕緣膜使用氮化矽（以下，以「SiN」表示）之 情形中，認爲如下。 即，以CVD所形成的SiN膜中含有少量氧。若於此 SiN膜上形成純Cu膜，則於上述純Cu膜與SiN膜的界面 (以下以「Cu/SiN界面」表示），構成純Cu膜的Cu與 上述氧反應並形成氧化物。經由形成此氧化物，於Cu/SiN 界面發生殘留應力，且純Cu膜與SiN膜的密黏性降低。 相對地，若於SiN膜上，形成含Cu-Ge合金膜，則 SiN膜中所含的氧爲與Ge優先反應，且氧由含Cu-Ge合 金膜與SiN膜的界面（以下以「Cu合金/SiN界面」表示 )，拉近至含Cu-Ge合金膜側，並且於含Cu-Ge合金膜側 (即，非上述界面，於含Cu-Ge合金膜中）比Cu合金 /SiN界面形成更多氧化物（Ge02 )。如此，因爲未於Cu 合金/ SiN界面形成氧化物，並於Cu合金/ SiN界面不會發 生殘留應力，故含Cu-Ge合金膜與SiN膜的密黏性提高。 又，於Cu合金/SiN界面，形成Ge02，透過其，認爲亦有 表現含Cu-Ge合金膜與SiN膜之高密黏性的可能性。更且 ，於絕緣膜爲氮化矽之情形中，Si與Ge爲周期表中之同 族元素，化學親和性強，故含Cu-Ge合金膜中的Ge與 SiN膜中的Si爲形成化學性鍵結，且界面的密黏性提高亦 被認爲係爲提高密黏性的原因。 另外，於上述說明中，雖然說明關於使用氮化矽膜作 爲絕緣膜的情況，但並非限定於此，亦包含絕緣膜爲含有 少量氧之其他絕緣膜；於氮化鋁膜、氮化鈦膜、氮化鉬膜 -28 - 200933895 等之上形成含（：11-(}6合金膜之情況。 上述效果爲於Ge含量爲〇.1原子％以上表現，Ge含 量愈多則密黏性愈高’但即使過多’此效果亦飽和。又’ 若增加Ge含量’則電阻率增加’故必須將Ge之含量抑制 於0.5原子％以下。由電阻率抑制至更低之觀點而言，Ge 爲0.2原子％以下爲佳。 上述含Cu-Ge合金膜即使以as-deposited狀態亦爲密 φ 黏性優良，進行後退火（成膜後至350 °C爲止的熱處理） ，亦可同樣發揮優良的密黏力。 上述含Cu-Ge合金膜爲含有上述規定量之Ge，且有 殘餘部分Cu及不可避免的雜質’上述不可避免的雜質可 列舉氧、氮、碳、氬等，其合計爲0.1原子％以下。 又，在不損害本發明作用之範圍下，以賦予其他特性 爲目的，亦可積極添加下述元素。即，將含Cu-Ge合金膜 ，例如應用於具有底部閘型構造之TFT的源極及/或汲極 φ 以及信號線之情形中，其特性要求有「與絕緣膜SiN膜之 密黏性」、「耐氧化性（與ITO膜之接觸安定性（低接觸 電阻））」、「對於構成半導體膜之α-Si的擴散抑制（ 確保TFT特性的安定性）」、「耐蝕性」等。其中，於添 力口 Ge下，可確保上述「與SiN膜之密黏性」、和「耐氧 化性（與ITO膜之接觸安定性（低接觸電阻））」。因此 ，更且，爲了提高上述「對於α-Si之擴散抑制」和「耐 蝕性」添加第3元素亦無妨。 又，於亦確保與使用作爲基板之玻璃的密黏性上，其 -29- 200933895 有效爲含有由 Ni、Pt、Au、Ce、Ru、W、Cr、Ir、Mo、Gold film. The third and the amount), and the length of the 450-minute TFT layer, the TFT-shaped layer, -23-200933895, and the preferred embodiment of the display device of the present invention will be described with reference to the drawings. Implementation form. In the following, a liquid crystal display device including an amorphous germanium TFT substrate will be described as a representative example. However, the present invention is not limited thereto, and may be appropriately modified and implemented in the scope of the present invention, which is included in the present invention. The technical scope. In the foregoing FIG. 2, the source electrode 29 and the drain electrode 28, the signal line (not shown in FIG. 2), and/or the scan line (gate line) 25 and the gate electrode 26 are illustrated as the Cu alloy film of the present invention. (For example, Cu-0.3 at% Ge-0.3 at% Ni alloy) is made into one aspect. According to the present embodiment (the first aspect), the barrier metal layer formed of Mo or the like is not necessarily interposed on the source-drain electrode as in the prior art, and the Cu alloy film and the transparent conductive film can be directly used. In the continuation, it is possible to achieve good TFT characteristics of the same level or more as the previous TFT substrate (refer to the embodiment described later). Further, according to the second aspect, it is not necessary to intervene the barrier metal layer under the scanning line (gate wiring) and the gate, so that the Cu alloy film and the glass substrate can be directly connected. Next, a method of manufacturing the TFT substrate of this embodiment shown in Fig. 2 will be described with reference to Figs. 3 to 7 . The same reference numerals as in Fig. 2 are given in Figs. 3 to 7. First, as shown in FIG. 3, a Cu alloy film (for example, Cu-0.3 at% Ge-0.3 at% Ni alloy) having a thickness of about 20 Å is formed on a glass substrate (transparent substrate) ia by sputtering. By forming the film into a pattern, the gate 26 and the scanning line 25 can be formed. At this time, in Fig. 4 which will be described later, the coverage of the gate insulating film 27 is good, and the side surface of the laminated film -24-200933895 is inclined at an angle of about 30 to 60. The taper is preferably etched. Then, as shown in Fig. 4, for example, a gate insulating film (siN) 27 of about 300 nm is formed by a method such as a plasma CVD method. The film formation temperature of the plasma CVD method is about 305. (The following is possible. Next, as shown in FIG. 5, a non-blended hydrogenated amorphous germanium film having a thickness of about 200 nm is formed on the gate insulating film (SiN) 27 by, for example, a plasma CVD method. a-Si: H), and an amorphous germanium channel film (active semiconductor film) 33 composed of an n+-type hydrogenated amorphous germanium film (n + a_si : η ) mixed with phosphorus having a thickness of about 50 nm, and the film 33. A pattern is formed. Next, a pattern of a Cu alloy film (for example, Cu-0.3 at% Ge-0.3 at% Ni alloy) having a thickness of about 300 nm is formed by sputtering, and then a pattern is formed, as shown in FIG. As shown, a source electrode 29 integrated with the signal line and a drain electrode 28 directly connected to the pixel electrode (transparent conductive film) 5 are formed. The film formation temperature of the sputtering may be about 150 ° C. As shown in Fig. 7, for example, an interlayer insulating film 30 having a thickness of about 300 nm is formed by using a plasma CVD apparatus or the like. Next, after forming a photoresist (not shown) on the interlayer insulating film 30, an interlayer insulating film is formed. 30 forms a pattern, for example, a contact hole is formed on the interlayer insulating film 30 by dry etching or the like. Meanwhile, with the end of the panel A contact hole is formed in a portion of the gate on the TAB. Finally, for example, in the range of storage time (about 8 hours), as shown in FIG. 2 above, for example, an ITO film having a thickness of about 4 nm is formed, and is wet. When etching is performed to form a pattern, a pixel electrode (transparent conductive film) 5 can be formed. At the same time, a contiguous portion of the TAB of the gate end portion of the panel, -25-200933895, is formed to form a film for bonding to the TAB. In the pattern of 41, the TFT array substrate 1 is completed. In this way, the TFT substrate is processed, the drain electrode 28 is in direct contact with the pixel electrode (transparent conductive film) 5, and the ITO film for the connection between the scanning line 25 and the TAB is also in direct contact. In the above, an ITO film is used as the pixel electrode (transparent conductive film) 5', but an IZO film (InOx-ZnOx-based conductive oxide film) may be used. Further, polycrystalline germanium may be used instead of the amorphous germanium as the active semiconductor film. Using the TFT substrate obtained in this manner, for example, the liquid crystal display shown in Fig. 1 is produced by the method described below. First, the surface of the TFT substrate 1 produced as described above is coated with, for example, polyimine. After drying, the rubbing treatment is performed to form an alignment film. On the other hand, when the counter substrate 2 is formed on a glass substrate, for example, Cr is formed in a matrix form, the light shielding film 9 can be formed. Secondly, in the gap of the light shielding film 9. A red, green, and blue color filter 8 made of resin is formed. On the light-shielding film 9 and the color filter 8, a transparent conductive film such as an ITO film is disposed as the common electrode 7, whereby a counter electrode can be formed. Thereafter, for example, polyimine is applied to the uppermost layer of the counter electrode, dried, and then subjected to rubbing treatment to form an alignment film 11. Next, the surfaces of the TFT substrate 1 and the counter substrate 2 on which the alignment film 11 is formed are opposed to each other. The TFT substrate 1 and the counter substrate 2 are bonded to each other by a sealing member for removing the liquid crystal, which is disposed in a resin. At this time, a spacer 15 is interposed between the TFT substrate 1 and the counter substrate 2 so that the gap between the two substrates is kept constant. -26- 200933895 The vacuum element thus obtained is placed in a vacuum to gradually return to the atmospheric pressure in a state where the inlet is immersed in the liquid crystal, and a liquid crystal material containing liquid crystal molecules can be injected into the empty element to form a liquid crystal layer, and Seal the entrance seal. Finally, polarizing plates l〇a, 1 〇b are attached to both sides of the outer side of the empty member and the liquid crystal panel is completed. Next, as shown in Fig. 1, the liquid crystal display is electrically connected to the driving circuit 13 of the liquid crystal display, and is disposed on the side portion or the inner portion of the liquid crystal display. Thereafter, the liquid crystal display is held by the holding frame 23 including the opening of the display surface of the liquid crystal display, the backlight 22 serving as the surface light source, and the light guide plate 20 and the holding frame 23', and the liquid crystal display is completed. In the display device of the present invention, since the wiring and the electrode portion are formed by a predetermined Cu alloy film, excellent performance and reliability can be achieved in addition to the specifications. Next, the third aspect will be described. The inventors of the present invention have realized a low resistivity which maintains the characteristics of a Cu-based material, and a Cu alloy film excellent in adhesion to an insulating film (for example, a tantalum nitride film), and a display device using the same for the TFT. 'Investigate the effort. As a result, a specific method was found based on the idea that a Cu alloy film containing a small amount of Ge was prepared. The following is a detailed description of the third aspect. The Cu alloy film of the present invention contains 0.1 to 0.5 atom% (at%) of Ge (hereinafter, such a Cu alloy film of the present invention, particularly referred to as "Cu-Ge-containing alloy film"). In the present invention, it has been found that the adhesion to the insulating film can be remarkably improved by containing 0.1 atom% or more (preferably 0.15 atom% or more, more preferably 0.20 atom% or more) of Ge. The reason why the high-viscosity is exhibited by the inclusion of Ge is not fully explained in the case of -27-200933895. However, in the case where the insulating film is made of tantalum nitride (hereinafter referred to as "SiN"), it is considered as follows. That is, the SiN film formed by CVD contains a small amount of oxygen. When a pure Cu film is formed on the SiN film, Cu which forms a pure Cu film reacts with the oxygen to form an oxide at the interface between the pure Cu film and the SiN film (hereinafter referred to as "Cu/SiN interface"). By forming this oxide, residual stress occurs at the Cu/SiN interface, and the adhesion between the pure Cu film and the SiN film is lowered. On the other hand, when a Cu-Ge-containing alloy film is formed on the SiN film, the oxygen contained in the SiN film preferentially reacts with Ge, and the interface between the Cu-Ge-containing alloy film and the SiN film is oxygen (hereinafter referred to as "Cu" Alloy/SiN interface"), drawn to the side of the Cu-Ge-containing alloy film, and on the side of the Cu-Ge-containing alloy film (ie, not in the above interface, in the Cu-Ge-containing alloy film) than the Cu alloy/SiN interface More oxide (Ge02) is formed. Thus, since no oxide is formed at the Cu alloy/SiN interface and no residual stress occurs at the Cu alloy/SiN interface, the adhesion between the Cu-Ge-containing alloy film and the SiN film is improved. Further, Ge02 is formed at the Cu alloy/SiN interface, and it is considered that there is a possibility that the Cu-Ge alloy film and the SiN film are highly dense. Further, in the case where the insulating film is tantalum nitride, Si and Ge are the same elements in the periodic table, and the chemical affinity is strong, so the Ge in the Cu-Ge alloy film and the Si in the SiN film form a chemical property. Bonding, and the adhesion of the interface is also considered to be the reason for improving the adhesion. Further, in the above description, the case where a tantalum nitride film is used as the insulating film is described, but the invention is not limited thereto, and the insulating film is also an insulating film containing a small amount of oxygen; in the aluminum nitride film or the titanium nitride film. On the other hand, a film containing (:11-(}6 alloy film) is formed on the molybdenum nitride film -28 - 200933895. The above effect is expressed in the case where the Ge content is 〇.1 atom% or more, and the more the Ge content is, the more dense the viscosity is. High 'but even too much' this effect is saturated. And 'If the Ge content is increased, the resistivity increases', so the content of Ge must be suppressed to 0.5 atomic % or less. From the viewpoint of resistivity suppression to a lower level, Ge is 0.2 atom% or less is preferable. The Cu-Ge-containing alloy film is excellent in adhesion in an as-deposited state, and is post-annealed (heat treatment up to 350 °C after film formation), and can also be excellent in the same manner. The Cu-Ge-containing alloy film contains a predetermined amount of Ge and has a residual portion of Cu and unavoidable impurities. The above-mentioned unavoidable impurities include oxygen, nitrogen, carbon, argon, etc., and the total is 0.1. Atomic % or less. Also, without damage For the purpose of imparting other characteristics, the following elements may be actively added. That is, a Cu-Ge-containing alloy film is applied, for example, to a source and/or a germanium of a TFT having a bottom gate structure. In the case of the pole φ and the signal line, the characteristics are required to be "adhesive to the SiN film of the insulating film", "oxidation resistance (contact stability with the ITO film (low contact resistance))", and "for the semiconductor film." The α-Si diffusion suppression (ensures the stability of the TFT characteristics), the "corrosion resistance", etc., in the case of the addition of Ge, the "adhesion to the SiN film" and the "oxidation resistance" are ensured. (The contact stability with the ITO film (low contact resistance)). Therefore, it is also possible to add the third element in order to improve the above-mentioned "inhibition of diffusion of α-Si" and "corrosion resistance". On the adhesion to the glass used as the substrate, -29-200933895 is effective to contain Ni, Pt, Au, Ce, Ru, W, Cr, Ir, Mo,

Fe、A1及Zr所組成群中選出一種或二種以上作爲第3元 素，含有此第3元素之多元系的含Cu-Ge合金膜，亦可使 用於上述閘極及掃描線、和源極和/或汲極以及信號線。 另外，將含Cu-Ge合金膜，使用於TFT之 •源極及/或汲極以及信號線、及/或、 •閘極及掃描線 之情形，有時要求更低的電阻率。若欲賦予低電阻率以外 之特性而提高Ge含量，則如上述電阻率爲增加，但爲了 繼續含有Ge並且更加降低電阻率，其有效爲含有由Ni、 Zn、Fe及Co所組成群中選出一種或二種以上作爲3元素 〇 於上述含Cu-Ge合金膜之形成上，期望採用濺鍍法。 所謂濺鍍法，係於真空中導入Ar等之惰性氣體，並於基 板與濺鍍靶（以後，有時稱爲靶）之間形成電漿放電，並 經由該電漿放電令離子化的Ar衝撞至上述靶，並敲出該 靶的原子且於基板上堆積製作薄膜的方法。比離子電鍍法 和電子束蒸鍍法、真空蒸鍍法所形成的薄膜，更容易形成 成分和膜厚之膜面內均句性優良的薄膜，且可以as-deposited 狀態 形成合 金元素 爲均勻 固溶的 薄膜， 故可有 效表現高溫耐氧化性。濺鍍法可採用例如DC濺鍍法、RF 濺鍍法、磁控管濺鍍法、反應性濺鍍法等任一種濺鍍法， 且形成條件若適當設定即可。 又，以上述濺鑛法，形成上述含Cu-Ge合金膜上，上 -30- 200933895 述靶爲由含有0.1-0.5原子％ Ge的Cu合金所構成，若使 用與所欲之含Cu-Ge合金膜相同組成之今Cu-Ge合金濺鍍 靶，則無組成不勻，可形成所欲成分、組成的含C u - G e合 金膜故佳。 靶之形狀爲包含根據濺鍍裝置之形狀和構造而加工成 任意形狀（角型平板狀、圓形平板狀、環形平板狀等）者 〇 0 上述靶之製造方法可列舉以溶解鑄造法和粉末燒結法 、噴霧成形法、製造Cu基合金所構成的鑄塊而取得的方 法、和製造Cu基合金所構成之雛型（取得最終緻密體前 的中間體）後，將該雛型經由緻密化手段予以緻密化而取 得的方法。 本發明之Cu合金膜（含Cu-Ge合金膜）被使用於顯 示裝置中之薄膜電晶體的 •源極及/或汲極以及信號線、及/或、 〇 •閘極及掃描線 應用於該處則可充分發揮含Cu-Ge合金膜的特性。 本發明中，前述TFT爲具有底部閘型構造者，前述源 極及/或汲極的一部分爲於絕緣膜（特別爲氮化矽膜）上 所形成之情形視爲較佳形態。 另外’將含Cu-Ge合金膜使用於源極及/或汲極以及 信號線、及/或、閘極及掃描線之多處時，彼此之含Cu-Ge 合金膜的組成可爲一致，且亦可於規定範圍內令組成不同 -31 - 200933895 以下，一邊參照圖面’一邊說明第3態樣之顯示裝置 的較佳實施形態。以下’代表性列舉說明具備非晶矽T F T 基板的液晶顯示器，但本發明不被限定於此，在適合前、 後述主旨之範圍下加以適當變更進行實施亦可，其均被包 含於本發明之技術性範圍。 於前述圖8中’列舉將源極29和汲極28、信號線（ 於圖8中未顯示）、及/或掃描線（閘極配線）25和閘極 26，以含Cu-Ge合金膜（例如Cu-0.3原子％Ge合金膜） 作成之一態樣。 若根據本實施形態’則可未如先前般中介存在含Mo 底層，於絕緣膜上直接層合含Cu-Ge合金膜，且可實現與 先前之TFT基板同程度以上的良好TFT特性（參照後述 之實施例）。 其次’一邊參照圖9〜15，一邊說明前述圖8所示之本 實施形態之TFT基板的製造方法。於圖5中加以與圖 8相同的參照符號。 首先，如圖9所示般，於玻璃基板（透明基板）la， 使用濺鍍法成膜出厚度20〇nm左右的含Cu-Ge合金膜（ 例如，Cu-0_3原子％Ge合金膜）。將此膜形成圖型，則形 成閘極26及掃描線25。此時，於後述之圖1〇中，以閘極 絕緣膜27之覆蓋範圍爲良好般，將上述合金膜的側面以 傾斜角約30° ~60°之錐狀進行蝕刻爲佳。 其次，如圖1 〇所示般，例如使用電漿CVD等之方法 ，形成約3 00nm左右的閘極絕緣膜（SiN膜）27。電漿 200933895 CVD法之成膜溫度若爲約3 50°C即可。接著，於閘極絕緣 膜27上，成膜出厚度5 0nm左右之氫化非晶矽膜（a-Si : H)及厚度3 00nm左右之氮化矽膜（SiNx)。 接著，以閘極26作爲光罩進行裏面曝光，如圖11所 示般將氮化矽膜（SiNx)形成圖型，形成通道保護膜。更 且於其上，如圖12所示般，將摻混磷之厚度5 Onm左右的 n +型氫化非晶矽膜（n + a-Si : H)成膜後，將氫化非晶矽膜 φ ( a-Si : Η )及n +型氫化非晶矽膜（n + a-Si : Η )形成圖型 〇 其後如圖13所示般，使用濺鍍法，形成厚度3 0 Onm 左右之含Cu-Ge合金膜（例如，Cu-0.3原子％Ge合金膜） 後形成圖型，則可形成與信號線一體之源極29 '與直接接 續至畫素電極（透明導電膜）5的汲極28。 其後如圖1 4所示般，例如使用電漿CVD裝置等，將 氮化矽膜40例如以膜厚300nm左右成膜則可形成保護膜 ❹ 。此時之成膜爲例如以250 °C左右進行。於此氮化矽膜40 上形成光阻層3 1後，將該氮化矽膜40形成圖型，例如經 由乾式蝕刻等在氮化矽膜40上形成接觸孔32。又’雖未 圖示，但同時與面板端部之閘極上之TAB接續部分形成 接觸孔。 更且如圖1 5所示般，例如經過以氧電漿拋光之步驟 後，例如使用胺系等之剝離液進行光阻層31的剝離處理 ’最後，如前述圖8所不般，例如成膜出厚度40nm左右 的ITO膜，並以濕式蝕刻進行形成圖型’則可形成畫素電 -33- 200933895 極（透明導電膜）5。 上述中，雖使用ITO膜作爲畫素電極（透明導電膜） 5，但亦可使用IZO膜（InOx-ZnOx系導電性氧化膜）。 又，亦可使用多晶矽代替非晶矽作爲活性半導體層。 使用如此處理所得之TFT基板，例如，根據下列記載 之方法，製造前述圖1所示之液晶顯示器。 首先，於如上述處理所製作之TFT基板1的表面，例 如塗佈聚醯亞胺，乾燥後進行摩擦處理以形成配向膜。 另一方面，對向基板2爲於玻璃基板上，例如將Cr 以矩陣狀形成圖型，則可形成遮光膜9。其次，於遮光膜 9之間隙，形成樹脂製之紅、綠、藍的彩色濾光片8。於 遮光膜9與彩色濾光片8上，將ITO膜般之透明導電膜以 共通電極7型式配置，則可形成對向電極。其後，於對向 電極之最上層例如塗佈聚醯亞胺，乾燥後，進行摩擦處理 以形成配向膜1 1。 其次，將TFT基板1與對向基板2之形成配向膜11 的面彼此對向配置，並以樹脂製的密封材1 6，除去液晶的 封入口將TFT基板1與對向基板2貼合。此時，於TFT 基板1與對向基板2之間，中介存在間隔件15令2枚基 板間的間隙大約保持一定。 將如此處理所得之空元件放於真空中，以封入口浸於 液晶之狀態慢慢恢復至大氣壓，則可於空元件中注入含有 液晶分子的液晶材料，形成液晶層，並將封入口封合。最 後，於空元件之外側兩面貼上偏光板1 0a、1 Ob並完成液 $ -34- 200933895 晶面板。 其次’如前述圖1所示般，於液晶顯示 動液晶顯示器的驅動電路13，並且配置於液 部或裏面部。其後，經由含有成爲液晶顯示 口的保持框23、和成爲面光源之背光22和君 持框23，保持液晶顯示器，並且完成液晶顯 另外，本發明之含Cu_Ge合金膜爲於具 Q 造之TFT中，亦可應用於絕緣膜上所形成的 實施例 以下，根據實施例更加詳細說明本發明 例並非限定本發明之性質者，於可適合前、 圍下亦可適當變更並實施，其均被包含於本 範圍。 〇 〈第1態樣&gt; 首先根據實施例1 -1及1 -2，說明第1態 (試料之製作） 根據DC磁控管濺鍍法（成膜條件爲如 溫，於玻璃基板（康寧公司製Eagle#2000、 度0.7mm)上，形成0.3μιη指定成分、組成 。此時，使用真空溶解法所製作之各種組成f 靶作爲濺鍍靶，形成Cu-Ge合金膜。又，於 器電性接續驅 晶顯兩器的側 器之顯示面開 寡光板20和保 示器。 有底部閘型構 閘極及掃描線 ，但下述實施 後述主旨之範 發明之技術性 樣。 下述），於室 直徑5 Ommx厚 的Cu合金膜 的Cu-Ge合金 前述Cu-Ge合 -35- 200933895 金靶上，設置含有第3元素：X之純金屬晶片或X以外之 第3元素（Nb、Hf、Zr或Sb)之晶片’進行組成調整’ 形成各種成分、組成的 Cu-Ge-X合金膜和Cu-Ge· ( X以 外之第3元素）合金膜。One or two or more of Fe, A1, and Zr are selected as the third element, and a Cu-Ge-containing alloy film containing the third element is used for the gate, the scan line, and the source. And / or bungee and signal lines. Further, when a Cu-Ge-containing alloy film is used for a source and/or a drain of a TFT, a signal line, and/or a gate and a scan line, a lower resistivity is sometimes required. If the Ge content is to be increased by imparting characteristics other than the low resistivity, the resistivity is increased as described above, but in order to continue to contain Ge and further reduce the resistivity, it is effective to be selected from the group consisting of Ni, Zn, Fe, and Co. One or two or more of the three elements are formed on the above-described Cu-Ge-containing alloy film, and sputtering is desirably employed. In the sputtering method, an inert gas such as Ar is introduced into a vacuum, and a plasma discharge is formed between a substrate and a sputtering target (hereinafter, sometimes referred to as a target), and an ionized Ar is ionized through the plasma discharge. A method of colliding with the target and knocking out the atoms of the target and depositing a thin film on the substrate. Compared with the film formed by the ion plating method, the electron beam evaporation method, or the vacuum vapor deposition method, it is easier to form a film having excellent uniformity in the film surface of the component and the film thickness, and the alloy element can be formed into an as-deposited state to be uniform. The film is dissolved, so it can effectively exhibit high temperature and oxidation resistance. The sputtering method may be any sputtering method such as a DC sputtering method, an RF sputtering method, a magnetron sputtering method, or a reactive sputtering method, and the formation conditions may be appropriately set. Further, the above-described Cu-Ge-containing alloy film is formed by the above-described sputtering method, and the above-mentioned target is composed of a Cu alloy containing 0.1-0.5 at% of Ge, if used and desired Cu-Ge. The Cu-Ge alloy sputtering target having the same composition of the alloy film has no composition unevenness, and it is preferable to form a Cu-G e alloy film having a desired composition and composition. The shape of the target is processed into an arbitrary shape (angular plate shape, circular flat plate shape, annular flat plate shape, etc.) according to the shape and structure of the sputtering apparatus. 制造0 The manufacturing method of the above target may be exemplified by dissolution casting method and powder. A method of sintering, a spray molding method, a method of producing an ingot composed of a Cu-based alloy, and a prototype of a Cu-based alloy (an intermediate before obtaining a final dense body), and then densifying the prototype The method by which the means are densified. The Cu alloy film (including a Cu-Ge alloy film) of the present invention is used for a source and/or a drain of a thin film transistor in a display device, and a signal line, and/or a gate, a gate, and a scan line. This place can fully utilize the characteristics of the Cu-Ge-containing alloy film. In the present invention, the TFT has a bottom gate structure, and a part of the source and/or the drain is formed on an insulating film (particularly a tantalum nitride film). In addition, when a Cu-Ge-containing alloy film is used for a source and/or a drain, and a signal line, and/or a gate and a scan line, the composition of the Cu-Ge-containing alloy film may be uniform. Further, in a predetermined range, a preferred embodiment of the display device of the third aspect will be described with reference to the drawings in a different configuration from -31 to 200933895. In the following, a liquid crystal display having an amorphous germanium TFT substrate will be described as a representative example. However, the present invention is not limited thereto, and may be appropriately modified and implemented in the scope of the present invention, which is included in the present invention. Technical scope. In the foregoing FIG. 8, 'the source 29 and the drain 28, the signal line (not shown in FIG. 8), and/or the scan line (gate wiring) 25 and the gate 26 are listed to include a Cu-Ge alloy film. (For example, a Cu-0.3 atom% Ge alloy film) is formed in one form. According to the present embodiment, the Mo-containing underlayer is not interposed as described above, and the Cu-Ge-containing alloy film is directly laminated on the insulating film, and good TFT characteristics of the same level or more as those of the conventional TFT substrate can be achieved (refer to the following description). Example). Next, a method of manufacturing the TFT substrate of the embodiment shown in Fig. 8 will be described with reference to Figs. 9 to 15 . The same reference numerals as in Fig. 8 are given in Fig. 5. First, as shown in Fig. 9, a Cu-Ge-containing alloy film (for example, a Cu-0_3 atom% Ge alloy film) having a thickness of about 20 Å is formed on a glass substrate (transparent substrate) la by sputtering. When the film is patterned, the gate 26 and the scanning line 25 are formed. In the case of Fig. 1 which will be described later, it is preferable that the side surface of the alloy film is etched in a tapered shape having an inclination angle of about 30 to 60 in order to provide a good coverage of the gate insulating film 27. Next, as shown in FIG. 1A, a gate insulating film (SiN film) 27 of about 300 nm is formed by a method such as plasma CVD. Plasma 200933895 The film formation temperature of the CVD method is about 3 50 ° C. Next, on the gate insulating film 27, a hydrogenated amorphous germanium film (a-Si: H) having a thickness of about 50 nm and a tantalum nitride film (SiNx) having a thickness of about 300 nm are formed. Next, the gate electrode 26 was used as a mask to expose the inside, and as shown in Fig. 11, a tantalum nitride film (SiNx) was patterned to form a channel protective film. Further, as shown in FIG. 12, a hydrogenated amorphous ruthenium film is formed by forming an n + -type hydrogenated amorphous ruthenium film (n + a-Si : H) having a thickness of about 5 Onm. φ ( a-Si : Η ) and n + -type hydrogenated amorphous ruthenium film (n + a-Si : Η ) form a pattern, then as shown in Fig. 13, using a sputtering method to form a thickness of about 3 0 Onm After forming a pattern by using a Cu-Ge alloy film (for example, a Cu-0.3 atom% Ge alloy film), a source 29' integral with the signal line and a source directly connected to the pixel electrode (transparent conductive film) 5 can be formed. Bungee jumping 28. Thereafter, as shown in Fig. 14, the protective film ❹ can be formed by, for example, forming a film of a tantalum nitride film 40 with a film thickness of about 300 nm by using a plasma CVD apparatus or the like. The film formation at this time is, for example, about 250 °C. After the photoresist layer 31 is formed on the tantalum nitride film 40, the tantalum nitride film 40 is patterned, and the contact hole 32 is formed on the tantalum nitride film 40 by, for example, dry etching. Further, although not shown, a contact hole is formed at the TAB joint portion on the gate of the end portion of the panel. Further, as shown in FIG. 15, for example, after the step of polishing by oxygen plasma, for example, the stripping treatment of the photoresist layer 31 is performed using a stripping solution such as an amine system. Finally, as shown in FIG. 8 above, for example, An ITO film having a thickness of about 40 nm is formed and formed into a pattern by wet etching to form a pixel (transparent conductive film) 5 . In the above, an ITO film is used as the pixel electrode (transparent conductive film) 5, but an IZO film (InOx-ZnOx-based conductive oxide film) can also be used. Further, polycrystalline germanium may be used instead of amorphous germanium as the active semiconductor layer. Using the TFT substrate obtained in this manner, for example, the liquid crystal display shown in Fig. 1 described above is manufactured according to the method described below. First, on the surface of the TFT substrate 1 produced as described above, for example, polyimine is applied, dried, and subjected to rubbing treatment to form an alignment film. On the other hand, when the counter substrate 2 is formed on a glass substrate, for example, Cr is formed in a matrix form, the light shielding film 9 can be formed. Next, a red, green, and blue color filter 8 made of resin is formed in the gap between the light-shielding films 9. On the light-shielding film 9 and the color filter 8, an ITO film-like transparent conductive film is disposed in the form of a common electrode 7, whereby a counter electrode can be formed. Thereafter, for example, polyimine is applied to the uppermost layer of the counter electrode, dried, and then subjected to a rubbing treatment to form an alignment film 11 . Then, the surfaces of the TFT substrate 1 and the counter substrate 2 on which the alignment film 11 is formed are arranged to face each other, and the TFT substrate 1 and the counter substrate 2 are bonded together by a sealing material for removing the liquid crystal by a resin sealing material 16. At this time, a spacer 15 is interposed between the TFT substrate 1 and the counter substrate 2 so that the gap between the two substrates is kept constant. The hollow element thus obtained is placed in a vacuum, and the liquid crystal material containing liquid crystal molecules is injected into the empty element to form a liquid crystal layer, and the sealing port is sealed, by slowly returning to the atmospheric pressure in a state where the inlet is immersed in the liquid crystal. . Finally, the polarizing plates 10a, 1 Ob are attached to the outer sides of the empty members and the liquid crystal panel is completed. Next, as shown in Fig. 1, the driving circuit 13 of the liquid crystal display is liquid crystal display, and is disposed in the liquid portion or the inner portion. Thereafter, the liquid crystal display is held by the holding frame 23 serving as the liquid crystal display port, and the backlight 22 and the medal frame 23 serving as the surface light source, and the liquid crystal display is completed. Further, the Cu-Ge-containing alloy film of the present invention is made of Q. The TFT can also be applied to an embodiment formed on an insulating film. Hereinafter, the present invention will be described in more detail with reference to the embodiments, and the present invention is not limited to the nature of the present invention, and may be appropriately modified and implemented before and after being suitable. It is included in this scope. 〇 <First aspect> First, according to Examples 1-1 and 1-2, the first state (production of the sample) is explained. According to the DC magnetron sputtering method (film formation conditions are as follows, on a glass substrate (Corning) In the company's Eagle #2000, degree 0.7 mm), a specified composition and composition of 0.3 μm were formed. At this time, various composition f targets prepared by a vacuum dissolution method were used as sputtering targets to form a Cu-Ge alloy film. The display surface of the side device of the electrically connected crystal display device is provided with the oligoplate 20 and the protector. There is a bottom gate type gate and a scanning line, but the following describes the technical aspects of the invention described below. Cu-Ge alloy of a Cu alloy film having a thickness of 5 Ommx and a thickness of 5 mm in the above-mentioned Cu-Ge-35-200933895 gold target is provided with a pure metal wafer containing a third element: X or a third element other than X (Nb) The wafer of Hf, Zr or Sb) is subjected to composition adjustment to form a Cu-Ge-X alloy film of various compositions and compositions, and a Cu-Ge (3rd element other than X) alloy film.

所得之Cu-Ge合金膜和Cu-Ge-X合金膜、Cu-Ge- ( XThe obtained Cu-Ge alloy film and Cu-Ge-X alloy film, Cu-Ge- (X

以外之第3元素）合金膜的組成爲使用ICP發光分光分析 裝置（島津製作所製之ICP發光分光分析裝置「ICP-8000 型」）予以定量分析。 (成膜條件） •背壓：1 .0xl(T6Torr 以下 • Ar 氣壓：2.0xl0-3Torr .Ar 氣流量：30sccm •濺鍍功率：3.2W/cm2 •極間距離：50mm •基板溫度：室溫 〔實施例1 -1〕 使用上述各種之Cu-Ge合金膜、Cu-Ge-X合金膜或 Cu-Ge- (X以外之第3元素）合金膜，測定如下述所示之 電阻率，並進行其評價。 (電阻率之測定） 對於Cu-Ge合金膜或Cu-Ge-X合金膜，施以微影及濕 -36- 200933895 式鈾刻，加工成寬ΙΟΟμηι、長度10mm之條紋狀圖型（電 阻率測定用圖型）後，以使用探測器之直流四探針法於室 溫中測定該圖型的電阻率。 另外，電阻率之測定爲對於As-deposited狀態之條紋 狀圖型、及、對於模擬Cu合金膜成膜後之熱處理，於真 空中（S lxl〇_6T〇rr )中以400 °C30分鐘之熱處理對上述 Cu合金膜施行後的條紋狀圖型進行。 ❹ (Cu-Ge合金膜之電阻率） 對於改變Ge含量之各種Cu-Ge合金膜，測定上述電 阻率之結果整理於圖16。 圖16爲分別示出As-deposited狀態與400°C真空熱處 理後之Cu-Ge合金膜的電阻率與Ge含量的關係。由此圖 16，Cu-Ge合金膜的電阻率，於As-deposited狀態下，隨 著Ge含量之增加而大約以直線性增加。施以上述熱處理 〇 的試料，與As-deposited狀態之試料相比較，電阻率之絕 對値有若干降低，關於施以上述熱處理的試料，可知電阻 率亦顯示出隨著Ge含量的增加而以直線性增加的傾向。 (Cu-0.1原子％Ge-X合金膜之電阻率） 對於改變X含量之各種Cu-0.1原子％Ge-X合金膜， 測定上述電阻率之結果整理於圖17。 圖17爲分別示出As-deposited狀態與400°C真空熱處 理後之Cu-0.1原子％Ge-X合金膜的電阻率與X含量的關 -37- 200933895 係。由此圖17可考察如下。即，Cu-0.1原子％Ge-X合金 膜之電阻率爲As-deposited狀態者，隨著第3元素：X含 量之增加而大約直線性增加，對於電阻率增加之影響爲根 據第3元素：X之種類（Co、Fe、Ni、Zn )而異’可知以 Co&gt;Fe&gt;Ni&gt;Zn之順序對電阻率增加所造成的影響變大。 另一方面，400 °C真空熱處理後之試料的電阻率’於 同一 X含量中比As-deposited狀態者更加顯著變小’隨著 上述第3元素：X的添加，察見比Cu-0.1原子％Ge合金 膜之電阻率更加降低或者維持的傾向。400 °C真空熱處理 後之電阻率的絕對値爲根據第3元素：X之種類（Co、Fe 、Ni、Zn)和含量而異，但於Cu-0.1原子％Ge 2元系成 分中添加直到〇·5原子％(〇：〇、？6、&gt;^、211)之任一者作 爲第3元素之情形中，可知顯示出比Cu-0.1原子％Ge合 金膜更低的電阻率。 (Cu-0.3原子％Ge-X合金膜之電阻率） 對於改變X含量之各種Cu-0.3原子％Ge_x合金膜’ 測定上述電阻率之結果整理於圖1 8。 圖1 8爲分別示出As-deposited狀態與400°C真空熱處 理後之Cu-0.3原子％Ge-X合金膜的電阻率與X含量的關 係。由此圖18可考察如下。即’ Cu-0.3原子WGe-X合金 膜之電阻率爲態者’隨著第3元素：X含 量之增加而大約直線性增加’對於電阻率增加之影響爲根 據第3元素：X之種類（Co、Fe、Ni、Zn)而異’可知以 -38- 200933895 C〇&gt;Fe&gt;Zn&gt;Ni之順序對電阻率增加所造成的影響（特別以 Co和Fe)變大。 另一方面，400 °C真空熱處理後之試料的電阻率，於 同一 X含量中比As-deposited狀態者更加顯著變小，隨著 上述第3元素：X的添加，察見比Cu-0.3原子％Ge合金 膜之電阻率更加降低或者維持的傾向。400 °C真空熱處理 後之電阻率的絕對値爲根據第3元素：X之種類（Co、Fe ❹ 、Ni、Zn)和含量而異，但於Cu-0.3原子％Ge 2元系成 分中添加直到 0.5原子％ ( Co、Fe、Ni、Zn )之任一者作 爲第3元素之情形中，可知顯示出比Cu-0.3原子％Ge合 金膜更低的電阻率。 (Cu-0.5原子％Ge-X合金膜之電阻率） 對於改變X含量之各種Cu-0.5原子％Ge-X合金膜， 測定上述電阻率之結果整理於圖19。 圖19爲分別示出As-deposited狀態與400°C真空熱處 理後之Cu-0.5原子％Ge-X合金膜的電阻率與X含量的關 係。由此圖19可考察如下。即’ Cu-0.5原子％Ge-X合金 膜之電阻率爲As-deposited狀態者，隨著第3元素：X含 量之增加而大約直線性增加，對於電阻率增加之影響爲根 據第3元素：X之種類（Co、Fe、Ni、Zn)而異’可知以 Co&gt;Fe&gt;Ni&gt;Zn之順序對電阻率增加所造成的影響（特別以 Co和Fe)變大。 另一方面，400 °C真空熱處理後之試料的電阻率，於 -39- 200933895 同一X含量中比As-deposited狀態者更加顯著變小，隨著 上述第3元素：X的添加，察見比Cu-0.5原子％〇6合金 膜之電阻率更加降低或者維持的傾向。400 °C真空熱處理 後之電阻率的絕對値爲根據第3元素：X之種類（Co、Fe 、Ni、Zn)和含量而異，但於Cu-0.5原子％〇6 2元系成 分中添加直到〇.5原子％(0〇、[6、1^、211)之任一者作 爲第3元素之情形中，可知顯示出比Cu-0.5原子％Ge合 金膜更低的電阻率。 ^ 亦調整關於第3元素使用X以外之元素（Nb、Hf、The composition of the alloy film other than the third element was quantitatively analyzed by an ICP emission spectroscopic analyzer (ICP-8000 type ICP emission spectrometer manufactured by Shimadzu Corporation). (film formation conditions) • Back pressure: 1.0xl (less than T6Torr • Ar gas pressure: 2.0xl0-3Torr. Ar gas flow rate: 30sccm • Sputter power: 3.2W/cm2 • Distance between poles: 50mm • Substrate temperature: room temperature [Example 1-1] Using the various Cu-Ge alloy films, Cu-Ge-X alloy films, or Cu-Ge- (the third element other than X) alloy film described above, the resistivity as shown below was measured, and The evaluation was carried out. (Measurement of resistivity) For Cu-Ge alloy film or Cu-Ge-X alloy film, lithography and wet-36-200933895 uranium engraving were applied to form a stripe pattern of width ΙΟΟμηι and length 10 mm. After the type (resistance measurement pattern), the resistivity of the pattern was measured at room temperature using a DC four-probe method using a detector. In addition, the resistivity was measured as a striped pattern for the As-deposited state. And, for the heat treatment after the film formation of the simulated Cu alloy film, the stripe pattern after the Cu alloy film is applied by heat treatment at 400 ° C for 30 minutes in a vacuum (S lxl 〇 6T 〇 rr ). Resistivity of Cu-Ge alloy film) For various Cu-Ge alloy films which change the Ge content, the above resistivity is measured The results are summarized in Fig. 16. Fig. 16 is a graph showing the relationship between the resistivity and the Ge content of the Cu-Ge alloy film after the As-deposited state and the vacuum heat treatment at 400 ° C. Thus, Fig. 16 shows the Cu-Ge alloy film. The resistivity, in the As-deposited state, increases linearly with increasing Ge content. The sample subjected to the above heat treatment has a certain decrease in the absolute value of the resistivity compared with the sample in the As-deposited state. Regarding the sample subjected to the above heat treatment, it was found that the resistivity also showed a tendency to increase linearly as the Ge content increased. (Resistance of Cu-0.1 atom% Ge-X alloy film) Various Cus for changing the X content -0.1 atom% Ge-X alloy film, the results of measuring the above resistivity are summarized in Fig. 17. Fig. 17 is a Cu-0.1 atom% Ge-X alloy film after the vacuum heat treatment at 400 ° C, respectively, showing the As-deposited state The resistivity is related to the X content -37-200933895. From Fig. 17, the following can be considered. That is, the resistivity of the Cu-0.1 atom% Ge-X alloy film is As-deposited, with the third element: X Increase in content and increase in linearity, increase in resistivity The influence of the third element: X (Co, Fe, Ni, Zn) varies, and it is known that the influence of the increase in the resistivity in the order of Co &gt; Fe &gt; Ni &gt; Zn becomes large. The resistivity of the sample after vacuum heat treatment at °C is more significantly smaller than that of the As-deposited state in the same X content. With the addition of the third element: X, it is found that the ratio of the Cu-0.1 atom% Ge alloy film is The tendency of the resistivity to be further reduced or maintained. The absolute enthalpy of the resistivity after vacuum heat treatment at 400 °C varies depending on the third element: X type (Co, Fe, Ni, Zn) and content, but is added to the Cu-0.1 atom% Ge 2 element component until In the case where any of 5 atom% (〇: 〇, ?6, &gt;^, 211) is the third element, it is understood that the resistivity is lower than that of the Cu-0.1 atom% Ge alloy film. (Resistivity of Cu-0.3 at% Ge-X alloy film) For various Cu-0.3 at% Ge_x alloy films in which the X content was changed, the results of the above resistivity were measured and are shown in Fig. 18. Fig. 18 is a graph showing the relationship between the resistivity and the X content of the Cu-0.3 atomic % Ge-X alloy film after the As-deposited state and the vacuum heat treatment at 400 °C, respectively. From Fig. 18, the following can be considered. That is, the resistivity of the 'Cu-0.3 atomic WGe-X alloy film' is approximately linearly increased as the third element: the X content increases. The effect on the increase in resistivity is based on the third element: the type of X ( Co, Fe, Ni, and Zn) are different, and it is understood that the influence of the increase in resistivity (especially Co and Fe) in the order of -38-200933895 C〇&gt;Fe&gt;Zn&gt;Ni becomes large. On the other hand, the resistivity of the sample after vacuum heat treatment at 400 °C is significantly smaller than that of the As-deposited state in the same X content, and the Cu-0.3 atom is observed with the addition of the third element: X described above. The resistivity of the %Ge alloy film is more likely to decrease or maintain. The absolute enthalpy of the resistivity after vacuum heat treatment at 400 °C varies depending on the third element: X type (Co, Fe 、, Ni, Zn) and content, but is added to the Cu-0.3 atom% Ge 2 element component. In the case where any of 0.5 atom% (Co, Fe, Ni, Zn) was used as the third element, it was found that the resistivity was lower than that of the Cu-0.3 atom% Ge alloy film. (Resistivity of Cu-0.5 Atom% Ge-X Alloy Film) The results of measuring the above specific resistivity for various Cu-0.5 atom% Ge-X alloy films in which the X content was changed are shown in Fig. 19 . Fig. 19 is a graph showing the relationship between the resistivity and the X content of the Cu-0.5 atom% Ge-X alloy film after the As-deposited state and the vacuum heat treatment at 400 °C, respectively. From Fig. 19, the following can be considered. That is, the resistivity of the Cu-0.5 atom% Ge-X alloy film is As-deposited, and the linearity increases as the third element: X content increases, and the influence on the increase in resistivity is based on the third element: The type of X (Co, Fe, Ni, Zn) varies, and it is understood that the influence of the increase in the resistivity (especially Co and Fe) in the order of Co&gt;Fe&gt;Ni&gt;Zn becomes large. On the other hand, the resistivity of the sample after vacuum heat treatment at 400 °C is significantly smaller than that of the As-deposited state in the same X content of -39-200933895. With the addition of the above third element: X, the ratio is observed. The resistivity of the Cu-0.5 atomic % 6 alloy film is more likely to decrease or maintain. The absolute enthalpy of resistivity after vacuum heat treatment at 400 °C varies according to the third element: X type (Co, Fe, Ni, Zn) and content, but is added to the Cu-0.5 atomic % 〇6 2 element component. In the case where any of 原子.5 at% (0 〇, [6, 1^, 211) was used as the third element, it was found that the resistivity was lower than that of the Cu-0.5 at% Ge alloy film. ^ Also adjust the elements of the third element using X (Nb, Hf,

Zr、Sb )作爲比較例之情況。圖 20爲分別示出 As-deposited 狀態與 400°C 真空熱處理後之 Cu-0.5 原子％0卜 (X以外之第3元素）合金膜的電阻率與X以外之第3元 素含量的關係。由此圖20，可知進行400 °C下之真空熱處 理則令電阻率下降，但與前述圖16所示之Cu-0.5原子 %Ge合金膜之電阻率同程度或更大，即使添加X以外之元 素作爲第3元素，亦不會因第3元素的添加而取得減低電 ◎ 阻率的效果。 〔實施例1-2〕 使用上述各種之Cu-Ge合金膜或Cu-Ge-X合金膜’如 下述所示測定接觸電阻，並以直接接續透明導電膜（IT0 膜）評價歐姆接觸性。 (接觸電阻之測定） -40- 200933895 首先，如下製作圖21所示之開耳芬圖型。詳言之， 對於各種Cu-Ge合金膜或Cu-Ge-X合金膜施以微影及濕式 蝕刻，並加工成圖21所示形狀之圖型（開耳芬圖型的下 方配線圖型）。其次，根據CVD法，形成SiN薄膜（膜 厚：0.3μηι之絕緣膜），並以微影及乾式蝕刻於該圖型上 形成大小：ΙΟμιη正方的接觸孔（接續孔）。其次，於其 上方將透明導電膜（ΙΤΟ膜），根據DC磁控管濺鎪法於 ❹ 室溫下形成〇.2μηι，並且以微影及濕式蝕刻，加工成圖21 所示形狀的圖型（開耳芬圖型的上方配線圖型）。 使用如此處理所製作之開耳芬圖型（評價元件），測 定Cu合金膜與ΙΤΟ膜之界面的電阻（接觸電阻）。 於接觸電阻的測定上，使用四端子之手動探測器和半 半導體參數分析器「HP4156A」 （Hewlet Packard公司製 )。於此測定中，如圖21所示般，於Cu合金膜之1端子 (II )與ITO之1端子（12 )之間流過電流I，並偵測 〇 V1-V2間的電壓V，將接續部C之接觸電阻R以「R = V/I 」型式求出。 另外，接觸電阻之測定爲對於As-deposited狀態之開 耳芬圖型、及、對於模擬Cu合金膜成膜後之熱處理製作 開耳芬圖型（評價元件）中，於接觸孔（接續孔）之形成 後且於透明導電膜（ITO膜）形成前，進行大氣氧化處理 (250°C X5分鐘）之開耳芬圖型進行。 (Cu-Ge合金膜與ITO膜之界面的接觸電阻） -41 - 200933895 對於改變Ge含量之各種Cu-Ge合金膜，測定與上述 ITO膜之界面的接觸電阻的結果整理於圖22。 圖22爲分別示出無大氣氧化熱處理之情形與大氣氧 化熱處理後之Cu-Ge合金膜與ITO膜界面中的接觸電阻、 與Ge含量之關係。 由圖22,於未進行大氣氧化處理之情形中，即使Ge 含量爲零亦令接觸電阻爲小至約20Ω。未進行大氣氧化處 理之情形，隨著Ge含量增加令接觸電阻進一步降低，於 Cu-0.5原子％Ge合金膜中接觸電阻爲降低至約6Ω爲止。 另一方面，施以大氣氧化處理之情形，Ge含量爲零的Cu 膜（純Cu膜）中接觸電阻爲大至約138Ω。但是，經由 添加Ge則可顯著降低接觸電阻。且於Cu-0.5原子％Ge合 金膜中接觸電阻爲降低至約76 Ω。 由此情事可知，即使模擬Cu合金膜成膜後之熱處理 進行大氣氧化處理之情形，亦經由在Cu膜中少量添加Ge 並且予以合金化，則可提高高溫耐氧化性，且可確保與透 明導電膜之良好的接觸性。 (Cu-Ge-X合金膜與ITO膜之界面的接觸電阻） 本發明之Cu合金膜爲經由含有規定量之Ge，而確保 優良的歐姆接觸性，進行確認即使於含有第3元素之情形 中，亦可確保與Cu-Ge同等或更高之優良的接觸電阻性之 實驗。 對於改變Ge含量及X之種類和含量之各種的Cu-Ge- -42- 200933895 X合金膜，測定如上述與上述ITO膜之界面的接觸電阻。 另外，於此實驗中，於任一種情形中，均在開耳芬圖型（ 評價元件）的製作中，於接觸孔（接續孔）的形成後且於 透明導電膜（ΙΤΟ膜）形成前，進行大氣氧化處理（250 t x5分鐘）。 圖23爲分別示出X之種類、含量於Cu-Ge-X合金膜 與ITO膜之界面中的接觸電阻、與Ge含量的關係。 〇 由此圖23可考察如下。即，於Cu-Ge合金膜中分別 添加〇· 1原子％、0.2原子°/〇、0.3原子％Fe、Co、Zn作爲 第3元素X時之接觸電阻，係與Ge量爲相同之情形，未 添加上述第3元素之情形（Cu-Ge合金膜）之接觸電阻同 等或者稍低。相對地，於Cu-Ge合金膜中添加0.5原子 %Ni作爲第3元素之情形中，接觸電阻値爲顯著降低，相 比於Cu-Ge合金膜，可知顯示出良好的歐姆接觸性。 〇 〈第2態樣〉 其次根據實施例1-3〜實施例1-6，說明第2態樣。 (試料之製作） 根據DC磁控管濺鍍法（成膜條件爲如上述（實施例 1-1及1-2))，於室溫下，於玻璃基板（康寧公司製 Eagle#2000)上，形成〇·3μηι指定成分，組成的Cu合金 配線薄膜。此時，使用純Cu中將添加元素組裝上晶片（ chip on )的濺鍍靶作爲靶，並將Cu合金膜成膜。成膜後 -43- 200933895 於真空氛圍氣中進行350°Cx30分鐘的熱處理，製作試料 。所得之Cu合金膜的組成爲使用ICP發光分光分析裝置 (島津製作所製之ICP發光分光分析裝置「ICP-8 000型」 )予以定量分析。 〔實施例1-3〕 以膠帶剝離試驗，評價Cu-Ge-Ni合金膜與玻璃基板 的密黏性。詳言之，首先於Cu合金膜表面，使用刀片以 1mm間隔加入棋盤格狀的切口。其次，於上述成膜表面上 緊密貼附3M公司製黑色聚酯膠帶（製品編碼8422B)， 並將上述膠帶的拉剝角度保持於60° ，將上述膠帶一舉性 拉剝。其後計數未經上述膠帶剝離之棋盤格的區格數，取 得與全部區格的比率（密黏率=膜殘存率）。另外，爲了 比較，亦評價純Cu膜、Cu-Ge合金膜及Cu-Ni合金膜的 密黏性。Zr, Sb) is the case of the comparative example. Fig. 20 is a graph showing the relationship between the resistivity of the As-deposited state and the Cu-0.5 atomic % 0 (the third element other than X) alloy film after vacuum heat treatment at 400 ° C and the third element content other than X. 20, it can be seen that the vacuum heat treatment at 400 ° C lowers the electrical resistivity, but is equal to or greater than the resistivity of the Cu-0.5 atomic % alloy alloy film shown in FIG. 16 described above, even if X is added. As the third element, the element does not have the effect of reducing the electric resistance due to the addition of the third element. [Example 1-2] The contact resistance was measured by using the various Cu-Ge alloy films or Cu-Ge-X alloy films described above, and the ohmic contact property was evaluated by directly connecting the transparent conductive film (IT0 film). (Measurement of Contact Resistance) -40- 200933895 First, the open ear phenotype shown in Fig. 21 was produced as follows. In detail, various Cu-Ge alloy films or Cu-Ge-X alloy films are subjected to lithography and wet etching, and processed into a pattern of the shape shown in Fig. 21 (the lower wiring pattern of the open ear phenotype) ). Next, according to the CVD method, a SiN film (film thickness: 0.3 μm of an insulating film) was formed, and a contact hole (joining hole) having a size of ΙΟμιη was formed by lithography and dry etching on the pattern. Next, a transparent conductive film (ruthenium film) is formed thereon in accordance with a DC magnetron sputtering method to form 〇.2μηι at room temperature, and is processed into a shape shown in Fig. 21 by lithography and wet etching. Type (the upper wiring pattern of the open ear phenotype). Using the open ear phenotype (evaluation element) produced in this manner, the electric resistance (contact resistance) at the interface between the Cu alloy film and the ruthenium film was measured. For the measurement of the contact resistance, a four-terminal manual detector and a semi-semiconductor parameter analyzer "HP4156A" (manufactured by Hewlet Packard Co., Ltd.) were used. In this measurement, as shown in FIG. 21, a current I flows between the one terminal (II) of the Cu alloy film and the one terminal (12) of the ITO, and the voltage V between the 〇V1 - V2 is detected, and The contact resistance R of the connection portion C is obtained by the "R = V/I" type. In addition, the contact resistance was measured in the As-deposited state of the open ear phenotype, and in the heat treatment after the film formation of the simulated Cu alloy film, the open ear phenotype (evaluation element) was used in the contact hole (the splicing hole). After the formation of the transparent conductive film (ITO film), it was carried out by atmospheric oxidation treatment (250 ° C for 5 minutes). (Contact Resistance at Interface Between Cu-Ge Alloy Film and ITO Film) -41 - 200933895 The results of measuring the contact resistance at the interface with the above ITO film for various Cu-Ge alloy films which change the Ge content are shown in Fig. 22. Fig. 22 is a graph showing the relationship between the contact resistance and the Ge content in the interface between the Cu-Ge alloy film and the ITO film after the atmospheric oxidation heat treatment, respectively, in the case of no atmospheric oxidation heat treatment. From Fig. 22, in the case where the atmospheric oxidation treatment is not performed, the contact resistance is as small as about 20 Ω even if the Ge content is zero. In the case where the atmospheric oxidation treatment was not performed, the contact resistance was further lowered as the Ge content was increased, and the contact resistance was lowered to about 6 Ω in the Cu-0.5 atom% Ge alloy film. On the other hand, in the case of atmospheric oxidation treatment, the contact resistance in the Cu film (pure Cu film) having a zero Ge content is as large as about 138 Ω. However, the contact resistance can be significantly reduced by adding Ge. The contact resistance was reduced to about 76 Ω in the Cu-0.5 atom% Ge alloy film. From this, it can be seen that even if the heat treatment after the film formation of the Cu alloy film is performed to perform atmospheric oxidation treatment, by adding a small amount of Ge to the Cu film and alloying it, the high-temperature oxidation resistance can be improved, and the transparent conductive can be ensured. Good contact of the film. (Contact resistance at the interface between the Cu-Ge-X alloy film and the ITO film) The Cu alloy film of the present invention ensures excellent ohmic contact property by containing a predetermined amount of Ge, and is confirmed even in the case where the third element is contained. It also ensures an excellent contact resistance test equivalent to or higher than Cu-Ge. The contact resistance at the interface with the above-mentioned ITO film was measured for various Cu-Ge-42-200933895 X alloy films in which the Ge content and the type and content of X were changed. Further, in this experiment, in either case, in the production of the open ear phenotype (evaluation element), after the formation of the contact hole (the connection hole) and before the formation of the transparent conductive film (the ruthenium film), Perform atmospheric oxidation treatment (250 t x 5 minutes). Fig. 23 is a graph showing the relationship between the contact resistance and the Ge content in the interface between the Cu-Ge-X alloy film and the ITO film, respectively, of the type of X. 〇 From Figure 23, the following can be considered. In other words, when the Cu-Ge alloy film is added with 〇·1 atom%, 0.2 atom%/〇, 0.3 atom% Fe, Co, and Zn as the third element X, the contact resistance is the same as the amount of Ge. When the third element is not added (Cu-Ge alloy film), the contact resistance is equal or slightly lower. On the other hand, in the case where 0.5 atom% of Ni was added as the third element to the Cu-Ge alloy film, the contact resistance 値 was remarkably lowered, and it was found that good ohmic contact property was exhibited as compared with the Cu-Ge alloy film. 〈 <Second Aspect> Next, the second aspect will be described based on Examples 1-3 to 1-6. (Production of sample) According to DC magnetron sputtering method (film formation conditions are as described above (Examples 1-1 and 1-2)), at room temperature, on a glass substrate (Eagle #2000 manufactured by Corning Incorporated) A Cu alloy wiring film having a composition of 〇·3μηι specified composition. At this time, a sputtering target in which an additive element was assembled on a chip in pure Cu was used as a target, and a Cu alloy film was formed into a film. After film formation -43- 200933895 Heat treatment at 350 ° C for 30 minutes in a vacuum atmosphere to prepare a sample. The composition of the obtained Cu alloy film was quantitatively analyzed by using an ICP emission spectroscopic analyzer (ICP-Glowing Spectrometer "ICP-8 000" manufactured by Shimadzu Corporation). [Example 1-3] The adhesion of the Cu-Ge-Ni alloy film to the glass substrate was evaluated by a tape peeling test. In detail, first, on the surface of the Cu alloy film, a checkerboard-shaped slit was added at intervals of 1 mm using a blade. Next, a black polyester tape (product code 8422B) made by 3M Company was closely attached to the film-forming surface, and the tape was stretched at 60°, and the tape was peeled off at one turn. Thereafter, the number of cells of the checkerboard which was not peeled off by the above tape was counted, and the ratio to the entire cell (viscosity = film residual ratio) was obtained. Further, for comparison, the adhesion of the pure Cu film, the Cu-Ge alloy film, and the Cu-Ni alloy film was also evaluated.

As-deposited狀態及成膜後熱處理（3 50 °C X30分鐘） 之純Cu膜及上述Cu合金膜的密黏率，分別整理於圖24 及圖25。另外，於此實施例中，令Ge添加量及Ni添加 量，分別以〇〜1.0原子％之範圍變化。由此圖24及圖25 可知，滿足本發明要件之Cu-Ge-Ni合金膜，經由施行熱 處理，比As-deposited狀態者，顯示20%以上格外優良的 密黏性。 〔實施例1-4〕 -44- 200933895 根據實施例1 -3同樣之方法，以膠帶剝離試驗，評價 Cu-Ge-Zn合金膜與玻璃基板的密黏性。As-deposited狀態 及成膜後熱處理（350 °Cx30分鐘）之上述Cu合金膜的密 黏率，分別整理於圖26及圖27。另外，於此實施例中， 令Ge添加量及Zn添加量，分別以0~1.0原子％之範圍變 化。由此圖26及圖27可知，滿足本發明要件之Cu-Ge-Zn合金膜，經由施行熱處理，比As-deposited狀態者， 〇 顯示20%以上格外優良的密黏性。 〔實施例1-5〕 根據實施例1-1同樣之方法，測定Cu-Ge-Ni合金膜 的電阻率。另外，爲了比較，亦測定純Cu膜、Cu-Ge合 金膜及Cu-Ni合金膜的電阻率。As-deposited狀態及成膜 後熱處理（350 °Cx30分鐘）之上述Cu合金膜的電阻率， 分別整理於圖28及29。察見電阻率有比例於合金元素之 ❹ 添加總量而增加的傾向。又，相比於As-deposited狀態， 熱處理後之狀態中，電阻率爲減低，可知滿足本發明要件 的Cu-Ge-Ni合金膜於熱處理後，顯示出4.5μΩ cm以下的 低電阻率（圖29)。 〔實施例1-6〕 根據實施例1-1同樣之方法，測定Cu-Ge-Zn合金膜 的電阻率。As-deposited狀態及成膜後熱處理（350 °C X30 分鐘）之上述Cu合金膜的電阻率，分別整理於圖30及圖 -45- 200933895 3 1。察見電阻率有比例於合金元素之添加總量而增加的傾 向。又，相比於As-dePosited狀態，熱處理後之狀態中， 電阻率爲減低，可知滿足本發明要件的Cu-Ge-Zn合金膜 於熱處理後，顯示出4.5μΩ cm以下的低電阻率（圖31) &lt;第3態樣&gt; 其次根據實施例2-1〜實施例2-3，說明第3態樣。 〔實施例2-1〕 爲了評價Cu合金膜與SiN膜的密黏性，乃以如下之 膠帶進行剝離試驗。 (試料之製作） 首先，於玻璃基板（康寧公司製 Eagle2000、直徑 50mmx厚度0.7mm)上，根據CVD形成2〇〇nm SiN膜， 再於SiN膜上，根據DC磁控管濺鍍法（成膜條件爲如下 述），於室溫中，形成300nm純Cu膜、純Mo膜、或表 1所示成分、組成的Cu合金膜，作成試料。另外，於純 Cu膜、純Mo膜的形成上，分別於濺鍍靶使用純Cu、純 Mo，且於各種成分之Cu合金膜的形成上，於純Cu濺鍍 靶上使用設置含有Cu以外元素之晶片的靶。 (成膜條件） -46 - 200933895 •背壓：1.0xl(T6T〇rr 以下 • Ar 氣壓：2.0xl0_3Torr • Ar 氣流：30sccm •濺鍍功率：3.2W/cm2 •極間距離：50nm •基板溫度：室溫 另外，所形成之Cu合金膜的組成爲使用ICP發光分 光分析裝置（島津製作所製之ICP發光分光分析裝置「 ICP-8000型」），予以定量分析並確認。 (與SiN膜之密黏性的評價） 於如此處理所製作試料之成膜表面（純Cu膜、純Mo 膜、或上述Cu合金膜之表面），使用刀片以1mm間隔加 入棋盤格狀的切口。其次，於試料上緊密貼附Scotch (註 冊商標）Mending Tape，並將上述膠帶的拉剝角度保持於 60° ，將上述膠帶一舉性拉剝，計數未經上述膠帶剝離之 棋盤格的區格數，求出與全部區格的比率（膜殘存率）。 其結果示於表1之「as-deposited」欄。又，對於上述各 試料，於真空氛圍氣中施以150°Cx30min，熱處理者，亦 進行上述膜殘存率的測定。其結果倂記於表1。 -47- 200933895 〔表1〕The adhesion ratio of the pure Cu film and the Cu alloy film in the As-deposited state and the post-film heat treatment (3 50 ° C X 30 minutes) are shown in Fig. 24 and Fig. 25, respectively. Further, in this embodiment, the amount of Ge added and the amount of Ni added were changed in the range of 〇 to 1.0 at%, respectively. As can be seen from Fig. 24 and Fig. 25, the Cu-Ge-Ni alloy film which satisfies the requirements of the present invention exhibits an excellent adhesion of 20% or more to the As-deposited state by heat treatment. [Example 1-4] -44-200933895 The adhesion of the Cu-Ge-Zn alloy film to the glass substrate was evaluated by a tape peeling test in the same manner as in Example 1-3. The adhesion ratio of the above-mentioned Cu alloy film in the As-deposited state and the post-film heat treatment (350 °C x 30 minutes) is shown in Fig. 26 and Fig. 27, respectively. Further, in this embodiment, the amount of addition of Ge and the amount of addition of Zn are changed in the range of 0 to 1.0 atom%, respectively. As can be seen from Fig. 26 and Fig. 27, the Cu-Ge-Zn alloy film which satisfies the requirements of the present invention exhibits an excellent adhesion of 20% or more to the As-deposited state by heat treatment. [Example 1-5] The resistivity of the Cu-Ge-Ni alloy film was measured in the same manner as in Example 1-1. Further, for comparison, the resistivities of the pure Cu film, the Cu-Ge alloy film, and the Cu-Ni alloy film were also measured. The resistivity of the above-mentioned Cu alloy film in the As-deposited state and the post-film heat treatment (350 ° C x 30 minutes) are shown in Figs. 28 and 29, respectively. It is observed that the resistivity tends to increase in proportion to the total amount of lanthanum added to the alloying elements. Further, in the state after the heat treatment, the resistivity is lowered as compared with the As-deposited state, and it is understood that the Cu-Ge-Ni alloy film satisfying the requirements of the present invention exhibits a low resistivity of 4.5 μΩ cm or less after heat treatment (Fig. 29). [Example 1-6] The resistivity of the Cu-Ge-Zn alloy film was measured in the same manner as in Example 1-1. The resistivity of the above-mentioned Cu alloy film in the As-deposited state and the post-film heat treatment (350 ° C X 30 minutes) is shown in Fig. 30 and Fig. 45-2009-200933895 31, respectively. It is observed that the resistivity increases in proportion to the total amount of addition of the alloying elements. Further, compared with the As-dePosited state, the resistivity was lowered in the state after the heat treatment, and it was found that the Cu-Ge-Zn alloy film satisfying the requirements of the present invention exhibited a low resistivity of 4.5 μΩ cm or less after heat treatment (Fig. 31) &lt;Third aspect&gt; Next, the third aspect will be described based on the embodiment 2-1 to the embodiment 2-3. [Example 2-1] In order to evaluate the adhesion between the Cu alloy film and the SiN film, a peeling test was carried out using the following tape. (Preparation of sample) First, a 2 〇〇 nm SiN film was formed by CVD on a glass substrate (Eagle 2000 manufactured by Corning Co., Ltd., diameter: 50 mm x 0.7 mm), and then on a SiN film, according to a DC magnetron sputtering method. The film conditions were as follows. A 300 nm pure Cu film, a pure Mo film, or a Cu alloy film having the composition and composition shown in Table 1 was formed at room temperature to prepare a sample. Further, in the formation of a pure Cu film or a pure Mo film, pure Cu or pure Mo is used for the sputtering target, and the Cu alloy film of various components is formed on the pure Cu sputtering target, and the Cu plating target is used. The target of the wafer of elements. (Film formation conditions) -46 - 200933895 • Back pressure: 1.0xl (T6T〇rr or less • Ar Pressure: 2.0xl0_3Torr • Ar flow: 30sccm • Sputter power: 3.2W/cm2 • Distance between poles: 50nm • Substrate temperature: In addition, the composition of the formed Cu alloy film was quantitatively analyzed and confirmed by an ICP emission spectroscopic analyzer (ICP-8000 type ICP emission spectrometer manufactured by Shimadzu Corporation). Evaluation of the film formation surface (pure Cu film, pure Mo film, or the surface of the above-mentioned Cu alloy film) of the sample prepared in this manner, using a blade to join a checkerboard-shaped slit at intervals of 1 mm. Secondly, the sample was tightly closed. Attach Scotch (registered trademark) Mending Tape, and maintain the stripping angle of the above tape at 60°, peel the above tape in one fell swoop, count the number of squares of the checkerboard that has not been stripped by the above tape, and find the whole area. The ratio of the lattice (residence of the film). The results are shown in the column "as-deposited" in Table 1. Further, for each of the above samples, 150 ° C for 30 min was applied in a vacuum atmosphere, and the film was also subjected to heat treatment. Measured. The results are shown in Table 1. Merger -47-200933895 [Table 1]

No. 試料 膜殘存率(％) as-deposited 150°C x30min.熱處理後 1 純Cu 0 0 2 純Mo 100 100 3 Cu-0.5at%Ag 2.7 0 4 Cu-0.5at%Al 0 0 5 Cu-0.5at%Au 0 0 6 Cu-0.5at%Co 0 4 7 Cu-0.5at%Fe 0 0 8 Cu-0.5at%Ge 100 100 9 Cu-0.5at%Hf 0 0 10 Cu-0.5at%In 0 0 11 Cu-0.5at%Mn 0 4 12 Cu-0.5at%Mo 0 8 13 Cu-0.5at%Si 1.3 16 14 Cu_0.5at%Sm 0 2.7 15 Cu-0.5at%V 0 0 16 Cu-0.5at°/〇W 0 0 17 Cu-0.5at%Zr 0 0 18 Cu-0.5at%B 30.7 0 19 Cu-0.5at%Cd 0 0 20 Cu-0.5at%Ce 0 0 21 Cu-0.5at%Dy 0 0 22 Cu-0.5at%Re 0 0 23 Cu-0.5at%Ru 0 0 24 Cu-0.5at%Sb 0 0 25 Cu-0.5at%Sc 0 0 26 Cu-0.5at%Sn 0 0 27 Cu-0.5at%Te 0 0 28 Cu-0.5at%Y 0 0 29 Cu-0.5at%Yb 0 0No. Sample film residual rate (%) as-deposited 150 ° C x 30 min. After heat treatment 1 pure Cu 0 0 2 pure Mo 100 100 3 Cu-0.5 at% Ag 2.7 0 4 Cu-0.5 at% Al 0 0 5 Cu- 0.5at%Au0 0 6 Cu-0.5at%Co 0 4 7 Cu-0.5at%Fe 0 0 8 Cu-0.5at%Ge 100 100 9 Cu-0.5at%Hf 0 0 10 Cu-0.5at%In 0 0 11 Cu-0.5at%Mn 0 4 12 Cu-0.5at%Mo 0 8 13 Cu-0.5at%Si 1.3 16 14 Cu_0.5at%Sm 0 2.7 15 Cu-0.5at%V 0 0 16 Cu-0.5at °/〇W 0 0 17 Cu-0.5at%Zr 0 0 18 Cu-0.5at%B 30.7 0 19 Cu-0.5at%Cd 0 0 20 Cu-0.5at%Ce 0 0 21 Cu-0.5at%Dy 0 0 22 Cu-0.5at%Re 0 0 23 Cu-0.5at%Ru 0 0 24 Cu-0.5at%Sb 0 0 25 Cu-0.5at%Sc 0 0 26 Cu-0.5at%Sn 0 0 27 Cu-0.5 At%Te 0 0 28 Cu-0.5at%Y 0 0 29 Cu-0.5at%Yb 0 0

-48- 200933895 由表1，可考察如下。純Cu膜之膜殘存率爲零，未 顯示與SiN膜的密黏性，相對地，純Mo膜之膜殘存率爲 10 0%，對於SiN膜顯示良好的密黏性。但，純Mo於室溫 下的電阻率，具有更高於純Cu的優點。 又，Cu合金膜中’除了含Cu-Ge合金膜以外，膜殘 存率大約爲零或未滿50%，相對地，Cu-0.5at°/〇Ge合金膜 之膜殘存率爲100%，可知對於SiN膜顯示良好的密黏性 ❹ 〔實施例2-2〕 調整Cu合金膜中之Ge含量與熱處理條件，對於與 SiN膜之密黏性（上述膜殘存率）所造成的影響。 (試料之製作） 於玻璃基板（康寧公司製Eagle2000 )上，同上述實 φ 施例2-1，根據CVD形成2 0Onm SiN膜，再於SiN膜上以 DC磁控管濺鍍法，形成3 00nm純Cu膜或Ge含量不同之 Cu合金膜，作成試料。另外，於純Cu膜的形成上，於濺 鍍靶使用純Cu，且於上述Ge含量不同之Cu合金膜的形 成上’將真空溶解法所製作之各種組成物的Cu-Ge2元系 合金靶，使用作爲濺鍍靶。 (與SiN膜之密黏性的評價） 準備（a)如上述處理所製作的試料（as-deposited狀 -49- 200933895 態之試料）' (b) 於真空氛圍氣中施以l5〇°Cx30min之熱處理的 試料、 (c) 於真空氛圍氣中施以35(TC&gt;&lt;3〇min之熱處理的 試料、 以實施例2-1同樣之方法進行與SiN膜之密黏性（上述膜 殘存率）的評價。 對於改變Ge含量及熱處理條件之各種Cu合金膜，測 定上述膜殘存率之結果整理於圖32。圖32爲分別示出上 述（a) as-deposited狀態、（b)以上述150 °C熱處理後、 (c)以上述350°C熱處理後之Cu合金膜中的Ge含量與 上述膜殘存的關係。 由此圖32可知，純Cu膜之膜殘存率爲零，含有 0.1 at%Ge，則令膜殘存率急劇增加，並且對於SiN膜顯示 良好的密黏性。若再增加Ge含量，則密黏性（膜殘存率 )爲提高，Ge含量爲〇.lat°/〇以上且膜殘存率爲90%以上 ，Ge含量爲0.5 at%以上且膜殘存率爲100%。此類傾向可 知，有無熱處理和熱處理條件並無關係。 〔實施例2-3〕 使用純Cu膜、Ge含量不同之各種Cu合金膜，測定 如下述之電阻率，並進行其評價。 (試料之製作） -50- 200933895 於玻璃基板（康寧公司製Eagle2000 )上，同上述實 施例2-1，以DC磁控管濺鍍法，形成300nm純Cu膜或 Ge含量不同的Cu合金膜。於上述Ge含量不同之Cu合金 膜的形成上，將真空溶解法所製作之各種組成的Cu-Ge2 元系合金靶，使用作爲濺鍍靶。 (電阻率之測定） 對於上述形成之純Cu膜或各種Ge含量的Cu合金膜 ，施以微影及濕式蝕刻，加工成寬1〇〇μηι、長度10mm之 條紋狀圖型（電阻率測定用圖型）後，以使用探測器之直 流四探針法於室溫中測定該圖型的電阻率。 另外，電阻率之測定爲對於as-deposited狀態之條紋 狀圖型、及、對於模擬Cu合金膜成膜後之熱處理，於真 空中（S lxlO_6Torr )中以400°C30分鐘之熱處理對上述 Cu合金膜施行後的條紋狀圖型進行。 對於改變Ge含量之各種Cu合金膜，測定上述電阻率 之結果整理於圖33。圖33爲分別示出as-deposited狀態 與400°C真空熱處理後之Cu合金膜中的Ge含量與電阻率 的關係。 由此圖33，Cu合金膜的電阻率，於as-deposited狀 態下，隨著Ge含量之增加而大約以直線性增加。施以上 述熱處理的試料，與as-deposited狀態之試料相比較，電 阻率之絕對値有若干降低，關於施以上述熱處理的試料， 可知電阻率亦顯示出隨著Ge含量的增加而以直線性增加 -51 - 200933895 的傾向。又，得知Cu合金中之Ge含量爲0.5at%以下之 情形中，可達成電阻率：5 μ Ω cm以下的低電阻率。 雖然參照詳細或特定的實施態樣說明本發明，但業者 自當知曉在不超脫本發明之精神和範圍下可加以各式各樣 的變更和修正。 本申請爲根據2007年10月24日申請之日本專利申 請（特願2007-276717) 、2008年2月20日申請之日本 專利申請（特願2008-03 898 1 )，且其內容於此處以參照 型式倂入。 (產業上之可利用性） 若根據本發明，則可實現具有能應付液晶顯示器大型 化和動作周波數高區域化之低電阻率Cu合金膜的顯示裝 置。若根據本發明之第1態樣，則可令Cu合金膜與ITO 和IZO等之透明導電膜，以低接觸電阻直接接觸。更且， 若根據本發明之第2態樣，則可令Cu合金膜與玻璃基板 直接接續。其結果，可廉價提供能省略高熔點金屬薄膜（ 阻障金屬層）之高性能的顯示裝置。又，若根據本發明之 第3態樣，因爲本發明之Cu合金膜爲與絕緣膜（特別 SiN膜）的密黏性優良，故應用於顯示裝置（例如液晶顯 示器）用之源-汲極時，可未形成上述含Mo底層並且作成 單層，可提供能省略上述含Mo底層的高性能顯示裝置。 【圖式簡單說明】 -52- 200933895 圖1爲示出應用非晶質的TFT基板之代表性的液晶顯 示器構造的槪略剖面放大說明圖。 圖2爲示出本發明之實施形態之TFT基板構造的槪略 剖面說明圖之一例，圖1中之A的主要部分放六圖。 圖3爲依序示出圖2所示之TFT基板之製造步驟之一 例的說明圖。 圖4爲依序示出圖2所示之TFT基板之製造步驟之一 0 例的說明圖。 圖5爲依序示出圖2所示之TFT基板之製造步驟之一 例的說明圖。 圖6爲依序示出圖2所示之TFT基板之製造步驟之一 例的說明圖。 圖7爲依序示出圖2所示之TFT基板之製造步驟之一 例的說明圖。 圖8爲示出本發明之實施形態之TFT基板構造之槪略 〇 剖面說明圖的另一例，圖1中之A的主要部分放大圖。 圖9爲依序示出圖8所示之TFT基板之製造步驟之一 例的說明圖。 圖10爲依序示出圖8所示之TFT基板之製造步驟之 一例的說明圖。 圖11爲依序示出圖8所示之TFT基板之製造步驟之 —例的說明圖。 圖12爲依序示出圖8所示之TFT基板之製造步驟之 —例的說明圖。 -53- 200933895 圖13爲依序示出圖8所示之TFT基板之製造步驟之 —例的說明圖。 圖14爲依序示出圖8所示之TFT基板之製造步驟之 —例的說明圖。 圖15爲依序示出圖8所示之TFT基板之製造步驟之 一例的說明圖。 圖16爲分別示出As-deposited狀態和400°C真空熱處 理後之Cu-Ge合金膜之電阻率與Ge含量的關係圖。 圖17爲分別示出As-deposited狀態和400°C真空熱處 理後之Cu-0.1原子％Ge-X合金膜之電阻率與X含量的關 係圖。 圖1 8爲分別示出As-deposited狀態和400°C真空熱處 理後之Cu-0.3原子％Ge-X合金膜之電阻率與X含量的關 係圖。 圖19爲分別示出As-deposited狀態和400 °C真空熱處 理後之Cu-0.5原子°/。〇6-又合金膜之電阻率與X含量的關 係圖。 圖20爲分別示出As-deposited狀態和400°C真空熱處 理後之Cu-0.5原子％Ge-(X以外之第3元素）合金膜之 電阻率與X以外之第3元素含量的關係圖。 圖21爲示出測定Cu-Ge合金膜或Cu-Ge-X合金膜與 透明導電膜間之接觸電阻所用之開耳芬（kelvin )圖型圖 圖22爲以有無大氣氧化熱處理區別示出Cu-Ge合金 200933895 膜之ITO膜界面之接觸電阻、與Ge含量的關係圖。 圖23爲以X之種類•含量區別示出Cu-Ge-X合金膜 之ITO膜界面之接觸電阻、與Ge含量的關係圖。 圖24爲對於As-deposited狀態之Cu-Ge-Ni合金膜， 示出組成與密黏率之關係圖。 圖25爲對於35(TC真空熱處理後之Cu-Ge-Ni合金膜 ，示出組成與密黏率之關係圖。 圖26爲對於As-deposited狀態之Cu-Ge-Zn合金膜， 示出組成與密黏率之關係圖。 圖27爲對於350 °C真空熱處理後之Cu-Ge-Zn合金膜 ，示出組成與密黏率之關係圖。 圖28爲對於As-deposited狀態之Cu-Ge-Ni合金膜， 示出組成與電阻率之關係圖。 圖29爲對於350 °C真空熱處理後之Cu-Ge-Ni合金膜 ，示出組成與電阻率之關係圖。 圖30爲對於As-deposited狀態之Cu-Ge-Zn合金膜’ 示出組成與電阻率之關係圖。 圖31爲對於350 °C真空熱處理後之Cu-Ge-Zn合金膜 ，示出組成與電阻率之關係圖。 圖32爲分別示出as-deposited狀態、150 °C熱處理後 、35(TC熱處理後之Cu合金膜中之Ge含量與膜殘存率的 關係圖。 圖33爲分別示出as-deposited狀態和400°C真空熱處 理後之Cu合金膜中之Ge含量與電阻率的關係圖。 -55- 200933895 【主要元件符號說明】 1 : TFT基板 1 a :玻璃基板 2 :對向基板（對向電極） 3 :液晶層 4 :薄膜電晶體（TFT)-48- 200933895 From Table 1, the following can be considered. The film residual ratio of the pure Cu film was zero, and the adhesion to the SiN film was not exhibited. On the other hand, the film residual ratio of the pure Mo film was 100%, and the adhesion to the SiN film was excellent. However, the resistivity of pure Mo at room temperature has the advantage of being higher than pure Cu. Further, in the Cu alloy film, the film residual ratio is about zero or less than 50% except for the Cu-Ge alloy-containing film, and the film residual ratio of the Cu-0.5 at/〇Ge alloy film is relatively 100%. The SiN film showed good adhesion ❹ [Example 2-2] The influence of the Ge content in the Cu alloy film and the heat treatment conditions on the adhesion to the SiN film (the film residual ratio) was adjusted. (Production of sample) On a glass substrate (Eagle 2000 manufactured by Corning Co., Ltd.), a 20 nm SiN film was formed according to CVD, and a DC magnetron sputtering method was formed on the SiN film. A 00 nm pure Cu film or a Cu alloy film having a different Ge content was prepared as a sample. Further, in the formation of a pure Cu film, pure Cu is used for the sputtering target, and Cu-Ge2 elemental alloy target of various compositions prepared by vacuum dissolution method is formed on the formation of the Cu alloy film having different Ge contents. Used as a sputtering target. (Evaluation of adhesion to SiN film) Preparation (a) Sample prepared as described above (as-deposited sample -49-200933895 sample)' (b) Applying 5 〇 ° C x 30 min in a vacuum atmosphere (c) a sample subjected to heat treatment of 35 (TC) &lt; 3 〇min in a vacuum atmosphere, and the adhesion to the SiN film was carried out in the same manner as in Example 2-1 (residual film remaining) The evaluation of the film residual ratio for various Cu alloy films which change the Ge content and the heat treatment conditions is shown in Fig. 32. Fig. 32 shows the above (a) as-deposited state and (b) After heat treatment at 150 °C, (c) the relationship between the Ge content in the Cu alloy film heat-treated at 350 ° C and the film remaining. As can be seen from Fig. 32, the film residual ratio of the pure Cu film is zero, and 0.1 at %Ge makes the film residual rate increase sharply and shows good adhesion to the SiN film. If the Ge content is further increased, the adhesion (film residual ratio) is improved, and the Ge content is 〇.lat°/〇 or more. Further, the film residual ratio is 90% or more, the Ge content is 0.5 at% or more, and the film residual ratio is 100%. It is understood that there is no relationship between the heat treatment and the heat treatment conditions. [Example 2-3] Using a pure Cu film and various Cu alloy films having different Ge contents, the resistivity as described below was measured and evaluated. (Production of sample) - 50- 200933895 On a glass substrate (Eagle 2000 manufactured by Corning Incorporated), a 300 nm pure Cu film or a Cu alloy film having a different Ge content was formed by DC magnetron sputtering as in the above Example 2-1. In the formation of the Cu alloy film, a Cu-Ge2 element alloy target of various compositions prepared by a vacuum dissolution method was used as a sputtering target. (Measurement of resistivity) For the above-formed pure Cu film or various Ge contents The Cu alloy film was subjected to lithography and wet etching, and processed into a stripe pattern of a width of 1 μm and a length of 10 mm (a pattern for resistivity measurement), and then a DC four-probe method using a detector was used. The resistivity of the pattern was measured at a temperature. Further, the resistivity was measured as a stripe pattern for the as-deposited state, and for the heat treatment after the film formation of the simulated Cu alloy film, in a vacuum (S lxlO_6 Torr ) 400 ° C for 30 minutes The heat treatment is performed on the stripe pattern after the Cu alloy film is applied. The results of measuring the resistivity for various Cu alloy films which change the Ge content are summarized in Fig. 33. Fig. 33 shows the as-deposited state and 400 ° C, respectively. The relationship between the Ge content and the specific resistance in the Cu alloy film after vacuum heat treatment. From Fig. 33, the resistivity of the Cu alloy film increases linearly with the increase of the Ge content in the as-deposited state. The sample subjected to the above heat treatment showed a certain decrease in the absolute enthalpy of the resistivity as compared with the sample in the as-deposited state. With respect to the sample subjected to the above heat treatment, it was found that the resistivity also showed linearity with an increase in the Ge content. Increase the tendency of -51 - 200933895. Further, in the case where the Ge content in the Cu alloy is 0.5 at% or less, the resistivity: a low resistivity of 5 μ Ω cm or less can be achieved. While the invention has been described with respect to the embodiments of the embodiments of the present invention, it is understood that various changes and modifications can be made without departing from the spirit and scope of the invention. The present application is Japanese Patent Application (Japanese Patent Application No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. Refer to the pattern type. (Industrial Applicability) According to the present invention, it is possible to realize a display device having a low-resistivity Cu alloy film which can cope with an increase in size of a liquid crystal display and a high range of operation cycles. According to the first aspect of the present invention, the Cu alloy film can be directly contacted with a transparent conductive film such as ITO or IZO with a low contact resistance. Further, according to the second aspect of the present invention, the Cu alloy film can be directly bonded to the glass substrate. As a result, a high-performance display device capable of omitting a high-melting-point metal film (barrier metal layer) can be provided at low cost. Further, according to the third aspect of the present invention, since the Cu alloy film of the present invention is excellent in adhesion to an insulating film (particularly a SiN film), it is applied to a source-drainage for a display device (for example, a liquid crystal display). In this case, the Mo-containing underlayer may not be formed and formed as a single layer, and a high-performance display device capable of omitting the Mo-containing underlayer may be provided. [Brief Description of the Drawings] - 52- 200933895 Fig. 1 is an enlarged schematic cross-sectional view showing a structure of a representative liquid crystal display to which an amorphous TFT substrate is applied. Fig. 2 is a schematic cross-sectional explanatory view showing a structure of a TFT substrate according to an embodiment of the present invention, and a main portion of Fig. 1 is a six-figure diagram. Fig. 3 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in Fig. 2 in order. Fig. 4 is an explanatory view showing an example of manufacturing steps of the TFT substrate shown in Fig. 2 in order. Fig. 5 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in Fig. 2 in order. Fig. 6 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in Fig. 2 in order. Fig. 7 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in Fig. 2 in order. Fig. 8 is a schematic cross-sectional view showing a schematic configuration of a TFT substrate structure according to an embodiment of the present invention, and an enlarged view of a main portion of A in Fig. 1. Fig. 9 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in Fig. 8 in order. Fig. 10 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in Fig. 8 in order. FIG. 11 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in FIG. 8 in order. FIG. 12 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in FIG. 8 in order. -53- 200933895 FIG. 13 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in FIG. 8 in order. Fig. 14 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in Fig. 8 in order. Fig. 15 is an explanatory view showing an example of a manufacturing procedure of the TFT substrate shown in Fig. 8 in order. Fig. 16 is a graph showing the relationship between the resistivity and the Ge content of the Cu-Ge alloy film after the As-deposited state and the 400 °C vacuum heat treatment, respectively. Fig. 17 is a graph showing the relationship between the resistivity and the X content of the Cu-0.1 atom% Ge-X alloy film after the As-deposited state and the 400 °C vacuum heat treatment, respectively. Fig. 18 is a graph showing the relationship between the resistivity and the X content of the Cu-0.3 atom% Ge-X alloy film after the As-deposited state and the 400 °C vacuum heat treatment, respectively. Fig. 19 is a view showing the As-deposited state and Cu-0.5 atom °/ after vacuum heat treatment at 400 °C, respectively. 〇6-The relationship between the resistivity and the X content of the alloy film. Fig. 20 is a graph showing the relationship between the resistivity of the As-deposited state and the Cu-0.5 atomic % Ge-(the third element other than X) alloy film after vacuum heat treatment at 400 °C and the content of the third element other than X. Figure 21 is a kelvin diagram showing the contact resistance between a Cu-Ge alloy film or a Cu-Ge-X alloy film and a transparent conductive film. Figure 22 shows Cu in the presence or absence of atmospheric oxidation heat treatment. -Ge alloy 200933895 The relationship between the contact resistance and the Ge content of the ITO film interface of the film. Fig. 23 is a graph showing the relationship between the contact resistance at the interface of the ITO film of the Cu-Ge-X alloy film and the Ge content in terms of the type and content of X. Fig. 24 is a graph showing the relationship between the composition and the adhesion rate for the Cu-Ge-Ni alloy film in the As-deposited state. Fig. 25 is a graph showing the relationship between composition and adhesion rate for a Cu-Ge-Ni alloy film after vacuum heat treatment of 35. Fig. 26 shows a composition for a Cu-Ge-Zn alloy film in an As-deposited state. Fig. 27 is a graph showing the relationship between composition and adhesion rate for a Cu-Ge-Zn alloy film after vacuum heat treatment at 350 ° C. Fig. 28 is Cu-Ge for As-deposited state. -Ni alloy film, showing the relationship between composition and electrical resistivity. Fig. 29 is a graph showing the relationship between composition and electrical resistivity for a Cu-Ge-Ni alloy film after vacuum heat treatment at 350 ° C. Fig. 30 is for As- The deposited state Cu-Ge-Zn alloy film 'shows a graph of composition versus resistivity. Fig. 31 is a graph showing the relationship between composition and resistivity for a Cu-Ge-Zn alloy film after vacuum heat treatment at 350 °C. Fig. 32 is a graph showing the relationship between the as-deposited state, the heat treatment at 150 °C, and 35 (the Ge content in the Cu alloy film after the TC heat treatment and the film residual ratio). Fig. 33 shows the as-deposited state and 400, respectively. Graph of Ge content and resistivity in Cu alloy film after vacuum heat treatment at °C. -55- 200933895 [Main component symbol 1] TFT substrate 1 a : Glass substrate 2 : Counter substrate (opposite electrode) 3 : Liquid crystal layer 4 : Thin film transistor (TFT)

5:畫素電極（透明導電膜） 6 :配線部 7 :共通電極 8 :彩色濾光片 9 :遮光膜5: pixel electrode (transparent conductive film) 6 : wiring portion 7 : common electrode 8 : color filter 9 : light shielding film

10a、10b :偏光板 1 1 :配向膜 12 : TAB 帶 1 3 :驅動電路 1 4 :控制電路 1 5 :間隔件 1 6 :密封材 17 :保護膜 1 8 :擴散板 19 :稜鏡片 20 :導光板 2 1 :反射板 -56- 200933895 22 :背光 23 :保持框 24 :印刷基板 線） 25 :掃描線（閘極j 2 6、2 7 :閘極 2 8 :汲極 29 :源極10a, 10b: polarizing plate 1 1 : alignment film 12 : TAB tape 1 3 : drive circuit 1 4 : control circuit 1 5 : spacer 1 6 : sealing material 17 : protective film 1 8 : diffusion plate 19 : cymbal 20 : Light guide plate 2 1 : reflector -56- 200933895 22 : backlight 23 : holding frame 24 : printed substrate line) 25 : scan line (gate j 2 6 , 2 7 : gate 2 8 : drain 29 : source

3 0 :層間絕緣膜 3 1 :光阻層 I (活性半導體膜） 極配線） I、SiN ) 32 :接觸孔 3 3 :非晶質矽通道丨 34 :信號線（源-汲3 0 : interlayer insulating film 3 1 : photoresist layer I (active semiconductor film) pole wiring) I, SiN) 32 : contact hole 3 3 : amorphous germanium channel 丨 34 : signal line (source - 汲

40 :鈍化膜（保護JI 41 :接續用ITO膜 100:液晶顯不器40: Passivation film (protection JI 41: continuous use of ITO film 100: liquid crystal display

-57--57-

Claims (1)

200933895 十、申請專利範圍 ^ 一種顯示裝置用Cu合金膜’其爲於基板上，直接 接續至透明導電膜之顯示裝置用Cu合金膜，其特徵爲含 有0.1〜〇·5原子％ Ge，且合計含有0.1〜0.5原子％由Ni、Zn 、Fe、及Co所組成群中選出1種以上。 2. —種顯示裝置用Cu合金膜，其爲與玻璃基板直接 接續的顯示裝置用Cu合金膜，其特徵爲合計含有〇.2~1 ❿ 原子％Ge及Ni。 3. —種顯示裝置用Cu合金膜，其爲與玻璃基板直接 接續的顯示裝置用Cu合金膜，其特徵爲合計含有0.2〜1 原子％ G e及Ζ η。 4. 一種顯示裝置，其特徵爲具備含有如申請專利範 圍第1項〜第3項中任一項之顯示裝置用Cu合金膜的薄膜 電晶體。 5. —種顯示裝置，其特徵爲於薄膜電晶體之閘極及 G 掃描線含有如申請專利範圍第1項~第3項中任一項之顯 示裝置用Cu合金膜’且該Cu合金膜爲直接接續至透明導 電膜。 6· —種顯示裝置，其特徵爲於薄膜電晶體之源極及 汲極中之至少一者以及信號線含有如申請專利範圍第1項 〜第3項中任一項之顯示裝置用Cu合金膜，且該Cu合金 膜爲直接接續至透明導電膜。 7· —種顯示裝置’其爲具備具有底部閘極型構造之 薄膜電晶體的顯示裝置’其特徵爲於該薄膜電晶體之閘極 -58- 200933895 及掃描線含有如申請專利範圍第2項或第3項之顯示裝置 用Cu合金膜，且該Cu合金膜爲直接接續至玻璃基板。 8. —種顯示裝置用Cu合金膜，其爲於顯示裝置中之 薄膜電晶體之 源極及汲極中之至少一者以及信號線、 及、 閘極及掃描線 中之至少一者所含之顯示裝置用Cu合金膜，其特徵爲含 有0.1〜0.5原子％Ge。 9. 一種顯示裝置，其特徵爲於薄膜電晶體之 源極及汲極中之至少一者以及信號線、 及、 閘極及掃描線 中之至少一者含有如申請專利範圍第8項之顯示裝置用 Cu合金膜。 10. 如申請專利範圍第9項之顯示裝置，其中前述薄 膜電晶體爲具有底部閘極型構造，且於絕緣膜上具有前述 源極及汲極中之至少一者的一部分。 11. 如申請專利範圍第10項之顯示裝置，其中前述 絕緣膜爲含有氮化矽。 12. —種濺鍍靶，其爲形成Cu合金膜所用之濺鍍靶 ，其特徵爲由含有 0.1〜〇·5原子％ Ge，且，合計含有 0.1-0.5原子％由Ni、Zn、Fe、及Co所組成群中選出一種 以上之Cu合金所構成。 -59- 200933895 13. —種濺鍍靶，其爲形成cu合金 ，其特徵爲由合計含有0.2-1原子％ Ge及 構成。 14. 一種濺鍍靶，其爲形成Cu合金 ，其特徵爲由合計含有0.2~1原子％Ge及 構成。 15. —種濺鍍靶，其爲形成Cu合金 ，其特徵爲由含有0.1〜0.5原子％ Ge之Cu ❹ 膜所用之濺鍍靶 Ni之Cu合金所 膜所用之濺鍍靶 Zn之Cu合金所 膜所用之濺鍍靶 合金所構成。 -60-200933895 X. Patent application scope ^ A Cu alloy film for a display device is a Cu alloy film for a display device directly connected to a transparent conductive film on a substrate, which is characterized by containing 0.1 to 〇·5 atom% of Ge, and the total One or more selected from the group consisting of Ni, Zn, Fe, and Co are contained in an amount of 0.1 to 0.5% by atom. 2. A Cu alloy film for a display device, which is a Cu alloy film for a display device directly connected to a glass substrate, and is characterized by containing a total of 2.2 to 1 原子 atom% of Ge and Ni. 3. A Cu alloy film for a display device which is a Cu alloy film for a display device which is directly connected to a glass substrate and which is characterized by containing 0.2 to 1 atom% of G e and η η in total. A display device comprising a thin film transistor comprising a Cu alloy film for a display device according to any one of the first to third aspects of the invention. 5. A display device characterized in that the gate of the thin film transistor and the G scan line contain a Cu alloy film for a display device according to any one of claims 1 to 3, and the Cu alloy film It is directly connected to the transparent conductive film. A display device characterized in that at least one of a source and a drain of a thin film transistor and a signal line contain a Cu alloy for a display device according to any one of claims 1 to 3. A film, and the Cu alloy film is directly connected to the transparent conductive film. A display device having a thin film transistor having a bottom gate structure is characterized in that the gate of the thin film transistor is -58-200933895 and the scanning line contains the second item as claimed in the patent application. Or the display device of the third aspect uses a Cu alloy film, and the Cu alloy film is directly connected to the glass substrate. 8. A Cu alloy film for a display device, comprising at least one of a source and a drain of a thin film transistor in a display device, and at least one of a signal line, a gate, and a scan line A Cu alloy film for a display device is characterized by containing 0.1 to 0.5 atom% of Ge. 9. A display device, characterized in that at least one of a source and a drain of a thin film transistor and at least one of a signal line, and a gate and a scan line have a display as shown in item 8 of the patent application scope The device uses a Cu alloy film. 10. The display device of claim 9, wherein the thin film transistor has a bottom gate type structure and has a portion of at least one of the source and the drain on the insulating film. 11. The display device of claim 10, wherein the insulating film comprises tantalum nitride. 12. A sputtering target which is a sputtering target for forming a Cu alloy film, which is characterized by containing 0.1 to 〇·5 atom% of Ge, and a total of 0.1 to 0.5 atom% of Ni, Zn, Fe, And one or more of the Cu alloys are selected from the group consisting of Co. -59- 200933895 13. A sputtering target which is formed by forming a cu alloy and is characterized by containing 0.2-1 atom% of Ge in total. A sputtering target which is formed by forming a Cu alloy and comprising 0.2 to 1 atom% of Ge in total. 15. A sputtering target which is a Cu alloy formed by a sputtering target Zn used for a film of a Cu alloy of a sputtering target Ni for a Cu ❹ film containing 0.1 to 0.5 atom% Ge. It is composed of a sputtering target alloy used for the film. -60-
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