TW200931248A - Electronic systems having non-volatile memories and related data processing methods - Google Patents

Abstract

A data processing method for use in an electronic system having at least one non-volatile memory, a flash memory bus and a peripheral bus is disclosed. The non-volatile memory has at least one attribute data and a bootable code. The method comprises following steps. An auto reading procedure is performed to acquire the at least one attribute data and an address for the bootable code from the non-volatile memory in response of that a reset signal of the flash memory bus has been deasserted. Then, the attribute data and the address for the bootable code is utilized to set and execute the bootable code in response of that the reset signal of the peripheral bus has been deasserted.

Description

200931248 - IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for processing volatility of a boot-related code stored in a non-physical method for storing information on a usable (10) body component. Stored in memory components [Prior Art] ❹ Ο In general, all in the system? Small one into the output system, _ Qing _ simple paste as the basic loss of the relevant procedures. For systems with non-volatile memory, -r will m#m^ flash memory)) (2), and will also rely on strong code _ volatile memory components to avoid the early non-volatile Sex memory storage boot 4 机 machine know code. The biggest difference between non-volatile memory components (such as flash memory) and general dynamic random access memory (DR) is that when there is no power supply ^ volatile memory (four) pieces The secret data is new, and the power saving function and shock resistance, so the non-volatile memory (four) components become the embedded pure memory solution. The memory components usually include a memory controller and a memory. Memory control Before the system's peripheral bus (such as PCI bus) is reset, you must know some attributes about the flash memory, such as bus width of 8 or 16 bits and page size. For information such as 512-bit, 2048-bit, or 4096-bit, the memory controller can correctly read the boot code stored in the memory after the peripheral bus is reset.

Client's Docket No.: VIC07-0041 TT^ Docket No: 〇6〇8-A41328-lW/Final/Jasonkung 200931248 Body pin ir, such attribute data is detected by the memory controller strappmg pin) The voltage level is obtained. However, each such table corresponds to at least one of the hardware pins'. For example, at least one is required to indicate the width of the bus bar and two pins are used to indicate the page size. Feet, if the =^= shouting limited, these hardware are connected to the original connection [invention content Γ hardware pin, will make the system not work properly. In view of the above, one of the objects of the present invention is to provide a data processing method for a non-volatile memory of a program code to describe a sufficient number of (four) special hardware pins. m seeks for the purpose of the description, and the present invention provides a data processing method suitable for electronic systems. /, medium, the electronic system includes at least one non-volatile memory - the non-volatile record of the corpus corpus ‘ has the attribute dragon and the boot code. The data processing method package first, after the reset of the memory bus-reset signal, the t-self-following program obtains at least the attribute data of the non-volatile memory from the non-volatile memory and the booting After the address of the program is located in Tian Erwei, (4) after the signal is aborted (10), the address of the boot code and the address of the boot code are used to read the boot code to the peripheral sink. The invention further provides an electronic The system, including - has at least -> 1 data and - boot handle. - Hair memory. Memory bus is used for tons of non-volatile memory ==

Client's Docket No.: VIC07-0041 TT>s Docket NorOeOS^lSlg-TW/Finayjasonkung 6 200931248 Two connected to the controller. Wherein, the controller pays to the peripheral bus after the address of the memory code |= sink = at least - threat (four) and at least the attribute dragon and the reset (four) of the boot. Address, read the machine code e

The method of processing the material is applied to the electronic system. (4) The memory, the controller, and the coupling are: 兮: 2:: The memory bus between the non-volatile memories and - Coupling material ^ Zhao Wei peripheral busbar. The non-volatile memory has at least one attribute 2 = the method of checking includes the step of τ column. First, after the northern t-telephone of the memory clutter is stopped, the at least attribute data is taken from the it body by the preset attribute data and the preset address. Then, in the peripheral sink 〇〇 reset money stop just using the attribute data obtained to configure the control benefit. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the preferred embodiments illustrated herein A data processing method suitable for non-volatile memory components (for example, flash memory), using the junction and characteristics of non-volatile memory components, enabling the recording of the memory device components in the face memory device The specific format data in the special location to obtain the attribute data related to the non-volatile memory component and the relevant index of the code stored therein, which can be used to

Client's Docket No.:VIC07-0041 rr.DocketNo:0608-A41328-TW/Fina]/Jas〇11lcun1 7 200931248 - The hardware pin of the familiar device solves the problem of insufficient system hardware pins, and it is convenient for further Expansion. In addition, according to the method of the present invention, the boot S code (ie, BIOS code) stored in the non-volatile memory component can be divided into different blocks and placed continuously or discontinuously, and the comparison provided by the present invention can be utilized. The table reads each block in sequence' to make the design more flexible and more efficient. Figure 1 shows an electronic system 1 in accordance with an embodiment of the present invention. The electronic system 0000 includes at least a processor 102, a wafer 'group 101, a front side bus bar 18 一面 between the processor 160 and the chip set 101, and a non-volatile, m. The chipset 101 includes a controller 11A, a ρα busbar controller 160, a busbar 170 coupled to the controller and the pCI busbar controller, and a power management unit 19A. Although in the present embodiment, the controller 1H) is connected to the electronic system and other modules through the PCI S stream, as is known to those skilled in the art, the electronic system can also use the external HE of the specification. Read and implement the communication between the UG and other modules. The multiplexer 110 is coupled to the non-volatile memory 12 through a memory bus (e.g., NAND Flash bus) 130. The power management unit wo includes at least a --staff register 140 and a --second register 15A. In this embodiment, the temporary storage thief 140 and the second temporary storage device 15 are battery-powered (four) well) temporary registers, which can be used to reserve data 142 and m, respectively, for use at boot time, but not Limited to this. The non-volatile memory 120 includes a boot code (eg, BI〇s code) 122' that stores various programs required for the electronic system to boot up, and is used to execute the system after the electronic system 1 is powered on. Boot program (b〇〇t sequence),

Clienfs Docket N〇.:VIC07-0041 TT's Docket No:〇6〇8-A41328-TW/Finayjasonkung 200931248 • To make it work properly. The non-volatile memory m further includes an attribute data 124' to store the basic attribute data of the non-volatile memory 12〇, for example, the confluence F is 8 bits or 16 bits and the page is divided (the size of the (4) is 512 bits. Information such as a tuple, a 2048 byte, or a 4096 byte. The controller 110 is transparent, and is coupled to the forward memory 13 by the bus 13G, and thereby accesses the non-volatile memory 120. Therefore, the control The device 11 can access the boot code 122 in the non-volatile memory m through the delta memory bus 13 ❹ 、 you, a; in the following examples, the non-volatile memory 12 is fast with NAND Flash memory is described as an example, but the present invention is not limited thereto. The NAND flash memory is composed of a series of blocks, each of which contains a series of pages. Figure 2 shows the third page. The timing sequence of one of the electronic systems shown in Figure 1. Please refer to Figure 1 and Figure 2, the four signal lines are used to indicate the system timing operation at boot time, where the signal line CPURST# , PCIRST#, H NFRST#, and PWRGD are used to indicate that the processor resets the signal line, PCI bus reset signal line, flash memory reset signal line and system power signal line. When the processor resets the signal line CPURST#, PCI bus reset signal line PCIRST# and flash memory reset signal line NFRst# When asserted, a low level will appear on the signal line. When it is deasserted, a high level will appear on the signal line. When a high level appears on the system power signal line PWRGD, the electronic system 100 is normal. Figure 3A shows a schematic diagram of a flash memory content configuration in accordance with an embodiment of the present invention. As shown, the starting position in the flash memory 300 (i.e., the first

Client's Docket No. :VIC07-0041 TT^ Docket No:0608-A41328-TW/Final/Jasonkung 9 200931248 • The paging of each block includes a first-data block 31〇' and also includes a boot The code 340, the boot code 34() is stored by the position of the flash memory 300 as shown in FIG. 3, that is, the label 3u indicates the start position. The first data block 310 stores the relevant attribute data of the flash memory 3〇〇 to indicate the format used by the flash memory. An index of the index of the associated memory address indicating the boot code 34 起始 at the start position of the flash memory 300 is also stored in the first data block 310. In order to ensure that the transfer of important data is not caused by an access error or other error, the result of the error is executed, so the first data block 310 may further include a related backup of the material. And the original resources due to the NAND flash memory process can not guarantee the reliability of the NAND column to maintain its performance in the life cycle, therefore, in the production and use of the nand flash flash hidden body will produce bad blocks. However, the producer of the να·flash memory will ensure that the first data block 31 of the flash memory is good, therefore, the boot code is generally stored continuously in the first data block; To ensure that the boot code is corrupted. In this embodiment, in order to increase the elasticity of 6 and 50, the boot code 34〇 can be stored in any position of the flash memory and can be stored in the first data block 31〇. The address index index data 36G locates the initial address of the boot code. As shown in Fig. 3a, the program code 340 is divided into several blocks, as shown in the block #ι至块块#4. The boot code 34〇 also has a lookup table (τ) 33〇, and the comparison table τ may include a block number and a flash memory address corresponding to the block, wherein the corresponding flash memory address may be flashed. An absolute address in memory

Client’s Docket No.: VIC07-0041 TT»s Docket No: 0608-A41328-TW/Fmal/Jasonkung 200931248 or the relative address expressed by the distance from block #1. The block #1 in the boot code 34〇 stores the address of the face comparison table τ (4) according to the table address 32〇, that is, the reference table address 32〇 can be found and referenced to the comparison table τ. As shown, the comparison table T is stored in the address 314. Therefore, the content in the comparison table address 32 is set to the address 314. The 'reference table' can be placed anywhere in the boot code 34〇. It should be noted that although the blocks of the boot code in this embodiment are continuously configured, in other implementations, the blocks of the boot code may be randomly distributed, such as block #1 followed by block # 3, the next block is #2. As shown in FIG. 3A, the first data block 31 is sequentially stored with the data B0 and B1 representing the attribute data 350, and the data P of the related index index 360 representing the starting position of the boot code 34〇, Pi, P2, and p3, where B1 is a backup of B0 'P1 is a backup of P0' P3 is a backup of p2, and P2 is used to indicate the address of the boot code stored for backup. Please note that the first data block 310 also includes a number of reserved data portions for subsequent expansion. The attribute data 350 shown in Fig. 3A and the address index index data 3 60 of the boot code are each a single byte. Those skilled in the art will appreciate that this arrangement is only one of many embodiments. The implementation of the system can be varied in accordance with various engineering or other considerations without departing from the true meaning of the invention. Figure 3B shows a schematic diagram of an attribute data 35〇 in accordance with an embodiment of the present invention. The attribute profile 350 can include data 354 to indicate the busbar width 351, the page size 352, the current mode of operation 353, and the support mode. For example, the bus width 351 can be 8 or 16 bits. The page size is 352.

Client's Docket N〇.:VIC07-0041 TT5s Docket No:0608-A41328-TW/Final/Jasonkung 200931248 is 512-bit byte, 2〇48 byte or 354 can be single channel mode or dual channel mode, De. Support mode Single channel mode means that the data is based on 8-bit data. Dual-channel mode means that data is accessed in 8-bit mode per channel, while in dual-channel mode, 16-bit is performed in shot-by-pass mode ^ For the storage, the player includes a single film (also 咏ch (6) mode and the visual work style. This is a two-part (her ehip) wedge, and the copy is the original boot code. - When the memory is in the single-chip mode, the original code is displayed. When the fast code is placed in the same flash memory === boot mode, such as the dual-chip mode, Pu boot ^ ^ flashing body is in the multi-code system division in the memory of / / towel and backup boot as light as the example of the 'per-properties are expressed by the number of Trang bits, such as ^ bit represents its The bus width and two bits indicate that the basin is large = then the attribute data 35〇(B〇/B1) is an 8-bit 枓, where the bit b〇(351) represents the bus width, the bit it B2 as (352) indicates the paging size 'bit b3 (353) indicates the support mode, and the bit Μ (353) indicates the current work. Mode, bit b6_b5 (355) is a reserved bit, and bit b7 (356) represents an error check bit 7L. The error check bit is used to check whether the data has occurred during the transfer process. Please note that although In this embodiment, a Cyclic Redundancy Check (CRC) is used to generate an error check bit. In other embodiments, any conventional error check code may be used, such as a Parity Check. ), Hamming code check (HammingC〇deCheckM error correction code (ECC)) to generate error check bits to determine whether the data is

Client's Docket No.: VIC07-0041 TT's Docket No:0608-A41328-TW/Fmayjasonkung 12 200931248 - Right. The CRC checksum is generated according to the column according to the rule, and the checksum is generated by a certain rule. The k-bit-matrix sequence is appended to the message to form a (ie CRC code) r bit, which is finally sent out. At the receiving end, Xixun checks the rules followed by the number of 1 code sequences (k+r) to determine the value of _^= between the horses and horses when the value of the bit b of the attribute data 350 is 〇. The table is shown as 8-bit 兀, and when the value of bit b0 is 纟-width. Similarly, the value of the bit must be bl ^ ^ width is 16 bits 〇 m 4 von 0 Bu 10 and 11 respectively 矣 π page size is 512 bytes, 2 仟 byte, 4 表 table epitope The value of b3 is 〇 and 13 占 respectively indicates support for millet and = retention. And dual channel mode. When the value of the bit Μ is 〇, the table;:=Mo is in the monolithic mode, and when the value of the bit b4 is i, the expression is modulo: the attribute (4) 3” is known as the flashing tree (4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (361) indicates the starting position of the boot program (ie, area 70). Bit b7 (263) indicates an error check bit. Similarly, the error: the element uses a CRC code or an odd parity code, which can be used. Judging whether the data is correct or not, those skilled in the art can understand that Figures 3A to 3C are only two: Several examples in the examples. For the convenience of description, the data of the first eve V 0 eight figure to the stem Qp chart The structure will be used in the following embodiments. Fig. 4 shows a data processing method at the time of power-on according to an embodiment of the present invention.

Client's Docket N〇.: VIC07-0041 TT^s Docket No: 0608-A41328-TW/Fmal/Jasonkung 13 200931248 Flowchart 400. Please refer to the i, 2, and 4 drawings at the same time. When the system power is turned on and the system's power supply reaches the range where the system can operate stably, the system power signal line PWRGD will be triggered (high level) to indicate that the power supply is in the steady state. At this time, in step S410, after the flash memory reset signal line NFRst# is suspended, that is, after the flash memory system completes the reset operation, the controller 11 is based on ❹

A set of preset attribute data performs an automatic reading process to obtain the attribute data of the flash memory 12G and the address (start address) of the block #1 of the boot code 122 from the flash memory 12〇. . In this embodiment, the preset attribute data refers to reading the data in the flash memory 12G in a manner that the bit width of the flash memory 12 is S bit and the small size is the toilet group. In particular, in some embodiments, the controller 1GQ completes the auto-play program (as shown in Figure 2) before the PCIRST# reset signal is aborted. The _from_take program and attribute data will be described in detail below. After the automatic reading process is executed, the attribute data of the flash memory 12 and the address of the block #1 of the boot code 122 can be flashed. Then, in step S420, the controller 11 configures the flash memory system based on the attribute data so that the memory is accessed in an optimized manner. In step S430, after the PCIRST# reset signal of the PCI bus is suspended, the control thief 110 uses the configured access mode to read the system configuration according to the address of the block #1 obtained by the automatic reading program. Information to make the system into the configuration of the slice group 1G1 and system memory (as shown in Figure 2, 220 and cycle T2). Usually, the system configuration information is the first to be executed by the boot code.

Client's Docket Ν〇·γΤΓΛ7 ΛΛ/Ι, TPs Secret 200931248 '一^刀' thus controls 11 110 after the pci bus reset is completed (ie after the claw row resets the k line PCIRST# abort), according to the chipset (1) The issued command (not shown) reads the system in block #1 of the boot code 340 and sets the information. In one embodiment, the aforementioned chip set (1) may include a north bridge crystal, and the command issued is a ROMSIP command. / After, after step S440, after the processor resets the signal line cpURST# to stop, that is, the processing 11 completes the reset button, and reads and executes the remaining portion of the block #1 through the PCI implicit program (such as The address of the block #1 shown in Fig. 2 and the period T3 of the boot code is equal to the start or base position of the boot code 122 in the flash memory 120. Next, block # 2 may be continuously disposed after the block #1, or may be placed discontinuously in any position of the flash memory 12. Therefore, as in step S450', a reference table address is obtained from the block #1. Finally, in step S460', a comparison table τ is obtained by using the comparison table address, and then the remaining blocks of the booting program 122 are found and executed by referring to the table τ to perform the startup of the entire system. It can include the block number and the flash memory and address corresponding to the Wei block. Therefore, refer to the relative position of the __ block in the wire T in the boot code 122, and find each remaining block in order and sequentially. Read to read the boot code from the fast memory. Referring to FIG. 3a, the remaining blocks of the code 122 are from block #2 to block #4, so these remaining blocks can be sequentially found in the second table τ and sequentially read out. ..... 5 shows a self-illustration 500 according to an embodiment of the present invention. In this embodiment, it is assumed that there are two booting programs "= If the memory is in a single-chip mode, then two boot codes are stored in the same hole." ]5 recalled crystal

Clienfs Docket N〇.:VIC07-0041 TT s Docket No:0608-A41328-TW/Final/Jasonkung 15 200931248 - On-chip 'If multi-chip mode, such as dual-chip mode, then two boot codes are placed in one The first flash memory chip and a second flash memory chip. As shown in Fig. 4, in step S510, based on the data 152 stored in the second register 15, the one of the booting codes to be read is determined to be stored. In the two-chip mode-embodiment, if the data is 152, Μ indicates that the inspection device is a first-flash memory chip, otherwise the inspection device is a second flash chip.曰曰 Next, in step S520, the data of the first unit length of the inspection device (flash memory) is read with the preset attribute data. In this embodiment, since each piece of data has one backup material and its data is 8 bits, the unit length data is defined as 32-bit data. In other words, the attribute data Β0 and Β1 in the first data block 31〇 and the related index indexes ρ and ρι will be read simultaneously. In the beginning, I can't know the true attribute data of the flash memory. Therefore, the default attribute data such as the bus width is 8 bits, the page size is 2 bytes, and the error correction is performed with one bit. Code (ECC), etc., to read the data of the first 16 bits of the φth data block. A bit error correction code (ECC) can be used to detect and automatically correct (fix) the wrong material with only one bit' to restore it to the original data of the positive_. Next, in step S530, the data of the first unit length is checked to obtain a valid data. Since the attribute data B0 and B1 have been read, it is checked whether the attribute data B0 (350) is valid. The CRC check is performed through the error check bit of the attribute b7 in the attribute data B, to determine whether the attribute data is correct. If the CRC check result of the attribute data B0 is correct, the attribute data

Client’s Docket N〇.:VIC07-0041 TT's Docket No:0608-A41328-TW/Final/Jas〇n3cung 200931248 is an effective material. Otherwise 'and then check the CRC check of the attribute. If the secret version is correct, the attribute data B1 is valid. For this purchase, then: ί people know that if a one-bit error correction code tr-sleeve unit design (single level eel1, SLc) flash flashes two dips and two right-only one bit error, then The backup data should be correct if the CRC check result of the BG is the parent material, and the attribute poor material B1 can be used as the valid data. ❹ ❹ Step S54G ’ According to the valid data, the second memory 3B I of the flash memory can be obtained according to the bit 2 of the valid data, the flash reading, and the current working mode of the body are in the monolithic mode or the multi-chip mode.存 ΓΓ 50, according to the current working mode and the first register 140 to get the F shell 4 to check it - remember his index index, and thus the address of the block #1 of the boot code. The flowchart (10)' of the automatic reading program according to the embodiment of the present invention is used to indicate the detailed operation of the step S550. For example, if the current security model in step s (four) is shown, the first-temporary execution step S620 is checked. In step = whether the data 142 is,. ,. If yes, if step _4, check whether the CRC of the index and the index index is a spider (step s6M - f body = step S616, determine the memory address index index 〇 (p 〇疋) as determined by the memory index 1 (P1) ) is valid data (step S6, :: factory, otherwise 'body index 1 read the code area _., 卩 can be based on memory if the data H2 is, Γ (step _2 no), then the steps are executed, Take

Chent's Docket N〇.:VIC07-0041 TT's Docket ^:0608^41328^«13^〇^ 17 200931248 The same preset attribute data is read from the second unit length of the flash memory in the inspection device. Similarly, the next 32-bit data in the first data block will be read, that is, the memory address index index 2 (p2) and the record address index index 3 (P3) will be read. ° ❹ ❹ Next, in step S615, it is checked whether the crc of the memory address index index 2 (ρ2) is correct. If yes (YES in step S615), in step S617, the memory 2 index index 2CP2 is determined to be valid data; otherwise, the memory address "index 3 (P3) is valid data" is determined, that is, read according to the memory index 3. Block #1. If the current working mode is multi-chip mode, execute step _, check if the CRC of the memory address index index is correct. If yes, such as one °, determine the memory health compensation "丨 is effective Wei, (4) The target index 1 (P1) is valid data (step S624). After the above steps, you can get the valid data recorded with the flash memory and the =η ' of the block where the boot code is recorded, so that you can use the material to set the spear control. King code. When reading, because the device is powered on, if the sigh is stored in the early channel mode, the first temporary storage H stores 14G, (10) >), and the S610 starts executing, that is, according to the sigh, Go back to the step machine code. If in the single-channel mode, the '=^Bee backup backup is started and the private method ends.

Client’s Docket N〇.:VIC〇7-〇〇41 ir, sDw8.A4132^w/FinaWas_ , corrected error _, indicating that the backup (four) material also occurred wrong

Ulg 18 200931248 Error 'So the boot failed. The index f reads the boot code and encounters the data 152 that cannot be repaired by the register address register. If the data 152 ^,,,, then the second is checked, T, and the first temporary is 0' in the OT u section, ' then it will be changed to set the test to start execution, the data set to π 1 back Go to the step if the data 152^, 2 is the 苐-data block in the other memory slice. failure. The county (four) copies (four) are also sent to the wrong, so the start ❹ 怜 pity H Γ according to the above automatic reading process, at the boot, return and boot =: 2::=:=:=: comparison table, then refer to The comparison table finds and reads the boot code. The above description of the flash memory pure code reading _ should be _ _ single city object uw ^ : machine = ? fast = memory. Only because each memory cell of the MLC flash memory can store 2 bits' _ when it is judged that the memory address index index is valid data, error correction cannot be performed by CRC. In this case, if the multi-level cell design is used in the fast memory, the controller 110 can automatically read the private sequence and take a sector (sect〇r) data and pass the 4-bit element. The ECC correction is used to determine whether the content of the memory address index is correct. The above description provides several different embodiments or different methods of applying the invention. The specific devices and methods in the examples are intended to help explain the main spirit and purpose of the invention, and the invention is not limited thereto.

Client's Docket N〇.:VIC07-0〇41 TPs Docket No:〇6〇8-A41328-TW/Final/Jasonkung 19 200931248, but it is not the scope of protection of the spirit of the present invention. Therefore, although the present invention has been shouted The invention is not limited to the scope of the invention, and the invention is intended to be modified and modified. [Simple description of the map]

1 shows an illustration of an electronic system connection in accordance with an embodiment of the present invention. FIG. 2 shows a timing sequence of a system according to an embodiment of the present invention. FIG. 3A shows a schematic diagram of FIG. '_(4) Persuasion configuration according to an embodiment of the present invention

FIG. 3B shows a schematic diagram of an attribute data block according to an embodiment of the present invention. FIG. 3C shows another embodiment of an attribute data block according to an embodiment of the present invention. FIG. 4 shows an example of booting according to an embodiment of the present invention. A flow chart of the data processing method. 5 is a flow chart showing an automatic reading program according to an embodiment of the present invention. FIG. 6 is a view showing another flow of an automatic reading program according to an embodiment of the present invention. 101~ chipset;

Client's Docket No.: VIC〇7-〇〇41 TT's Docket No:0608-A41328-TW/Fmal/Jasonlamg 20 200931248 . 102~ processor 110~ controller; 120~ non-volatile memory; 122~ boot code 124~ attribute data; 130~memory bus; 14〇~first register; 150~second register; 142142,152~ data; 160~PCI controller; 170~PCI bus; 180 ~ front-end bus; 190 ~ power management unit; CPURST#, PCIRST#, NFRST#, PWRGD~ signal line; 3 00~ flash memory; 310~ first data block; 312, 314~ address; Comparison table address; 330~ comparison table T; 340~ boot code; 350, BO, B1, 351, 352, 353, 354~ attribute data; 360, P0, PI, P2, P3~ address index index data; S410-S460-step; S510-S550~step~;

Client's Docket No. : VIC07-0041 TT's Docket No: 0608-A41328-TW/Final/Jasonkung 21 200931248 . S610 , S612 , S613 , S614 , S615 , S616 , S617 , S618 , S620 , S622 , S624 , S630 ~ steps .

Client's Docket No. :VIC07-0041 TT5s Docket No:0608-A41328-TW/Final/Jasonkung 22

Claims (1)

200931248 X. Patent Application Range: 1. A data processing method for an electronic system, wherein the electronic system includes at least one non-volatile memory, a memory bus connected to the non-volatile memory, and a peripheral sink. The non-volatile memory has at least one attribute data and a boot code, and the data processing method comprises the following steps: after one of the memory bus stops resetting the signal, performing an automatic read according to a preset attribute data Taking the program to obtain the at least one attribute data of the non-volatile memory from the non-volatile memory and the address of the boot code; and after the reset signal of the peripheral bus is suspended, the use is obtained. The at least one attribute data and the address of the boot code are read from the boot code to the peripheral bus. 2. For the data processing method described in claim 1, the method further includes: reading, by using the address of the boot code, the first block of the boot code, and obtaining the first block from the first block a lookup table address; and using the lookup table address to obtain a lookup table to execute at least one remaining block of the boot code. 3. The data processing method of claim 1, further comprising: reading a starting position of the non-volatile memory to obtain a first data block; and obtaining the first data block At least one attribute data and the open Client's Docket N〇.: VIC07-0041 TT5s Docket No: 0608-A41328-TW/Final/Jasonkung 23 200931248 - The address of the program code. 4. The data processing method of claim 1, wherein the step of executing the automatic reading program further comprises: determining an inspection device according to a data stored in a first temporary storage; The attribute data reads one of the first unit length data of one of the starting positions of the inspection device; and checks the first unit length data to obtain a valid data. 5. The data processing method of claim 4, wherein the first unit length data has at least one error check bit, and the step of checking the first unit length data further comprises: checking the bit according to the error Yuan' determines the valid information. 6. The data processing method of claim 4, wherein the first unit length data has a source data and a backup data, the original data and the backup data having an error check bit, the check The step of one unit length of data further includes: determining whether the original data is correct according to the error check bit of the original data; and if so, determining that the original data is the valid data, wherein the original data is the same as the backup data . 7. If the data processing method described in item 6 of the patent application scope is further included, if the original data is incorrect, the backup data is determined to be the valid data. 8. The data processing method as described in claim 6, wherein Client's Docket No.: VIC07-0041 TT's Docket No: 0608-A41328-TW/Final/Jasonkung 24 200931248 = capital: one includes the at least one Index data of the address of the attribute data. The test column type stone horse, as in the information section mentioned in item 4 of the patent application scope, the step of executing the automatic reading procedure further includes: -t (four) t according to the financial effect data 'obtaining the non-volatile record «the current working mode' The current mode, the and the second mode, and the second mode j, the current working mode and the second temporary storage device, are determined to check the address of one of the memory address indicator code. *W Μ 到 该 . . 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如a φ HI , ν «唆一" 屺 屺 memory address index index and a first address memory address index index; and ❹ mode is the single mode, the second temporary state is checked Whether the material is equal to a preset value. 11·If the data processing method described in the patent application 帛H) is more S* dry· If the data of the second register is equal to the preset value, check the first Whether the index of the δ mnemonic address index is correct; when the index of the first-memory address index is correct, it is determined that the index of the replied address index to be checked is the index of the first-memory address index; and when the first-memory If the index of the body address index is incorrect, it is decided that Client's Docket N〇.:VIC07-0041 TT s Socket No:〇6〇8-A41328-TW/Final/Jasonkung 25 200931248 The second memory address indicator checks the memory Body address index The index is the index. The data processing method described in 10 items is further 12. If the scope of the patent application includes: if the (four) value of the second temporary storage is not equal to (4), the reading is performed by using the preset attribute data. Detecting a second unit length data of the device, wherein the second unit length data is after the first unit length data; Obtaining, by the second unit length data, a third memory address index index and a fourth memory address index index; and determining, according to the first: memory address index (4) and the fourth memory address index The error check bit determines the index of the memory address indicator to be checked. 13. If the data processing method described in item (4) i of the patent application is applied, the attribute data includes at least information indicating the width of the bus bar and the size of the page.资料. The method for processing data according to the application of the patent _ _, further comprising configuring a controller by using the obtained at least one attribute data. 15. An electronic system comprising: an attribute data and an open non-volatile memory having at least a computer code; a controller for controlling the non-volatile memory; and a memory bus The non-volatile memory and the peripheral bus bar are coupled to the controller; CHenfs Docket N〇.: VIC07-0041 AT s DocketNo: 0608-A4132S-TW/FinayJasonkung 26 200931248 wherein the controller After the reset signal of the memory bus is suspended, an automatic reading process is performed to obtain the at least one attribute data of the non-volatile memory and the address of the boot code from the non-volatile memory, and After the reset signal of the peripheral bus is suspended, the at least one attribute data and the address of the boot code are used to read the boot code to the peripheral bus. * 16. The electronic system of claim 15, further comprising a - the first register and a second register for storing the at least one attribute data and the address of the boot code Check the information. 17. The electronic system as claimed in claim 15 , wherein the program code has a -th block and at least a "remaining block", and the control thief reads the address according to the address of the boot code. The first block, from which the control block address is received in the first block, and the comparison table (4) obtains a lookup table, thereby reading the at least one remaining block. 18·Electronics as claimed in Article 15 of the patent application The material is at least included to indicate a bus bar width; one point 19. The electric non-volatile memory system as described in claim 15 is -NAND_(4)^-中中20. A data processing method for one electron a system, wherein the electronic system comprises a non-volatile memory, a memory for the non-volatile memory, and a memory bus with a === controller peripheral busbar, the non-volatile memory having Γΐ: Poor material, the data processing method includes the following steps: · Client's Docket N〇.: VIC07-0041 TTJs Docket No: 0608-A41328-TW/Fina3/Jasonkung 27 200931248 . Reset in one of the memory busbars After the signal is suspended, the at least one attribute data is read from the non-volatile memory according to a preset attribute data and a preset address; and the attribute is obtained before the one of the peripheral bus lines resets the signal suspension. The data is configured with the controller. 21. The data processing method of claim 20, wherein the non-volatile memory further has a boot code and an address of the boot code. ❹ 22. The data processing method of claim 21, further comprising: after the reset signal of the memory bus is suspended, the non-volatile according to the preset attribute data and the preset address The address of the boot code is read in the memory; and after the reset signal of the peripheral bus is suspended, the boot code is used to obtain the boot code. ❹ Client’s Docket N〇.:VIC07-0041 TT^ Docket No:0608-A41328-TW/Final/Jasonkung 28