TW200926615A - Multi-code LDPC (low density parity check) decoder - Google Patents

Abstract

Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null submatrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Description

200926615 IX. INSTRUCTIONS: [Technical field to which the invention pertains] This month relates to communication systems, and more particularly to decoding techniques for low density • Low Density Parity Check (LDPC) coded signals in communication systems. [Prior Art] • The data transmission system has been continuously developed for many years. In recent years, the communication system using the iterative error correction code is the focus of researchers. The most interesting of these is the communication secret using LDPC codes. In the case of the same SNR, the communication system using the stacked code has a lower bit error rate than the communication system using other codes. A continuing and major development in this area is to reduce the ratio in the communication system to achieve a specific rate of miscalculation. The ideal goal is to try to study the Shannon's limit of the communication channel. The Shannon limit can be regarded as a channel towel with a specific signal-to-noise ratio to make (4) data fresh, through which the error-free transmission can be realized. In other words, mountain greenness is the theoretical limit of the capacity of the channel under the given complement and preparation. The LDPC code has been proven to provide very good decoding performance close to the Shannon limit under certain altitudes. In theory, some LDPC decoders have been proven to reach the G.3 score of Chenneng. The length is - the material LDpc obstructed the performance, it confirmed that the LDpc code in the 驴 驴 有 有 有 有 有 有 有 有 有 有 有 有 有 有 有 有 LD LD LD LD The LDPC coded signal has been turned over in many new fields. Examples of several possible communication systems that can employ 5 200926615 LDP C coded signals include communication systems using 4-pair twisted pair cables for high speed Ethernet applications (eg lOGbps (gigabits per second) based on ffiEE 802.3an) Ethernet operation (1〇GBASE_T) and communication systems operating within the wireless environment (eg, within the IEEE 802.11 environmental space including the emerging EE emerging standards). ❹ For these special communication system applications, it is highly desirable to have an error correction code that enables near capacity. The latency constraints introduced by the use of traditional link codes prevent their use in high data rate communication system applications.

Generally speaking, in the communication system environment using the LDPC code, in the communication channel, there is a first communication device having the capability of encoding H, and at the other end of the communication channel, there is a second capable of decoding H. communication device. In the case of recording, the two communication devices have the ability to encode H and decoder (for example, in a two-way communication system) LDPC codes can also be used in various applications, including those in some form. The application of data storage (for example, hard disk drive coffee applications and other storage devices) in which the material is compiled before being written to the storage medium, and then the data is decoded after being read/removed from the data medium. Among the existing communication devices, one of the biggest difficulties in designing effective devices and/or communication devices for decommissioning LDpc coded signals is the error-storing and the process of decoding in the county (for example, 'restore and save between check 5|engine and _ engine All the bit edge messages (check edge messages) that are updated and used when the library and the check edge message are sent and used are large area sums (4). The LDPC code is processed in a relatively small block size ^ 6 200926615 Processing & some check edge messages and bits (four) information required memory management = very difficult to handle. Therefore, the technical field needs and will: ::= = good means to decode ·: coder signal to extract Editing and drinking: In addition, when the size of the LDPC coded and healthy phase check matrix reaches a predetermined size, the first processing module and the second processing module (example)

The interconnectivity between the 'check engine and the bit engine' will increase significantly. SUMMARY OF THE INVENTION The apparatus and method of the present invention are further described in the following drawings, frequency embodiments, and claims. According to an aspect of the present invention, there is provided a decoding unit for decoding an LDPC (Low Density Parity Check) encoded signal, the decoder comprising: a plurality of memories; a plurality of bit engines 'and the plurality of bits Each bit engine in the engine is configured to connect to at least one of the plurality of memories; a plurality of check engines 'each of the plurality of check engines are used to connect to At least one of the plurality of memories; and a plurality of multiplexers (MUXs) configured to: selectively: the plurality of bit engines and devices during a decoding process of the first LDPC coded signal Connecting a plurality of check engines to the first selected one of the plurality of memories; 200926615 selectively selecting the plurality of bit engines and the plurality of bits during a decoding process of the second LDPC coded signal a verification engine coupled to the second selected one of the plurality of memories; and wherein: the plurality of memories includes a predetermined number of memories, the predetermined number of memories being used to complement a plurality of LDPCs Encoded multiple LDP a plurality of non-zero sub-matrices of the C-type towel; the masher is configured to decode the _ LDpc coded signal, where the first LDPC coded signal corresponds to a first-c-c matrix of the plurality of LDpc matrices, thereby generating Preferably, the decoder is used to decode the second LDpc coded signal in the first LDPC code record, and the second job code signal corresponds to the second matrix of the multiple hung Dpc turn The generation of the county LDPC coded letter m is encoded by the Saki's New Zealand estimate. Preferably, the memory is determined by superimposing a plurality of non-zero sub-matrices corresponding to a plurality of LDpc codes of the plurality of LDpcs, and determining a plurality of (four) other (four) matrices in the plurality of memories. The first greedy (soft from the office), depth (depth) search is indeed the peach _ _ lose. = 地地, by the four-plus-synchronized-in-memory-partial memory, deep search corresponding to a plurality of singular, non-zero _, and the greedy The depth search at least partially considers a column affine metric (eg, _ affinity matric), the column affine metric representing 'in the first LDpc matrix', at least the other - nDPC moment* The connectedness of the columns in the array. Preferably 'the layout of the plurality of memories within the communication device is based on a merge mode. 'mergepattem' generates the merge by at least partially considering a column affine metric representing the first LDPC The connectivity of the columns in the matrix to at least one other column of the first 'O LDPC matrix and the columns of the second LDPC matrix. Preferably, the plurality of memories comprise a plurality of merged memories, and the one of the plurality of merged memories corresponds to the first LDpc matrix; the non-zero submatrix also corresponds to the A second non-zero submatrix in the second LDPC matrix. Preferably, the first LDpc matrix of the plurality of LDPC matrices includes a plurality of non-zero sub-matrices; the second LDpc matrix of the plurality of LDPC matrices includes a second plurality of non-zero sub-matrices; And in the decoding process of the first LDPC coded signal, when processing the first-non-zero sub-matrix of the first plurality of non-zero sub-matrices, using one of the plurality of memories; In the decoding process of the second LDPC coded money, when the second multi-zero sub-scale (4)-non-snake matrix is processed, the one of the memories is also manufactured. 3 200926615 Preferably, The first LDpc matrix of the plurality of LDPC matrices includes a subset of the plurality of non-zero sub-matrices; and the first: LDpc matrix of the plurality of (10) vehicles includes the plurality of non-zero sub-matrices The subset and at least one additional non-zero submatrix. Preferably, in the decoding process of the first LDPC, the encoded signal, when the first non-zero submatrix of the LDPC matrix is used, and in the solution rhyme of the second C coded signal, when used The second LD?c matrix (four) two non-zero sub-matrices, using one of the plurality of memories; and the positions of the rows and columns of the first non-zero sub-matrix in the LDPC matrix ^ The positions of the rows and columns of the second non-zero submatrix in the first LDPC matrix are preferably, when the first LDpc coded signal is used to solve the first LDpc coded signal, using the first matrix towel (four) - the rotor And when decoding the second LDP.

When: using the second LDK: the second non-zero submatrix in the matrix, one of the memories in the LDPC matrix, the first non-zero submatrix in the LDPC matrix is included The first row and the first column; and the second non-zero submatrix include a row and a second column at the second moment. Selectively, in the processing of bit_, the -= of the plurality of multiplexers, one bit engine of the plurality of bit engines is connected to the memory of the plurality of ^; and the 200926615 is in the check node The one multiplexer of the plurality of multiplexers connects the check engines of the plurality of check engines to the one of the plurality of memories. Preferably said decoder is implemented in an integrated circuit. Preferably, the decoder is implemented in a communication setup for the communication channel to be unrecognized from the communication channel - LDPC encoding the money (4) uDpc coded signal; and the communication device is implemented at least in the following Satellite communication system, wireless communication green, Wei communication, and domain Cong system. According to an aspect of the present invention, there is provided a decoder for decoding an LDpc (Low Level Parity) encoded signal, the decoder comprising: a plurality of memories; a plurality of bit engines, and said Each of the plurality of bit engines is connected to at least one of the plurality of memories; the check engine 'each of the plurality of check engines is connected to the At least one memory of the plurality of memories; and a plurality of multiplexers (MUXs) for: ???When decoding the first LDPC coded signal, 'in the process of bit node processing', the plurality of bit engines are a first selected bit engine coupled to the first selected one of the plurality of memories; when the first LDPC encoded signal is decoded, 'the plurality of check engines are 'in the process of verifying node processing The first selected check engine is connected to the first selected memory of the plurality of memory bodies of the 2009 20091515; when the first LDPC coded signal is decoded, the plurality of said LDPC coded signals are in the process of bit node processing In a bit-bit engine a second selected bit engine connected to the second selected one of the plurality of memories; and - when the field decodes the second LDPC encoded signal, the plurality of check engines are 'in the process of check node processing A second selected check engine of the A is connected to the second selected one of the plurality of memories; wherein: the plurality of § memories comprise a predetermined number of memories, the predetermined number of The memory is used to represent a plurality of non-zero sub-matrices in a plurality of LDPC matrices corresponding to a plurality of LDPCs; the decoding H is used to decode the first-LDPC encoded signal, and the first LDPC encoding letter Generating a best estimate of the bits encoded within the first LDPC encoded signal at a first LDpc matrix, k of the plurality of LDpc matrices; the decoder is configured to decode the second LDpc encoded signal, The second LDPC encodes the LDPC matrix (four) two LDpc matrices, thereby generating a best estimate of the bits encoded in the second LDPC coded signal. Preferably, the plurality of bit engines A selected bit engine is more than said The second selected bit engine of the bit engine; and the first selected check engine of the plurality of check engines is the second selected check engine of the plurality of check engines. The first selected bit engine of the plurality of bit engines is all bit engines of the 12 200926615 plurality of bit engines; and the first selected check engine of the plurality of check engines is the plurality of check engines • all check engines of the engine - preferably 'in the decoding process of the first LDpc coded signal, the first LDPC coded signal from all bit engines of the plurality of bit engines and the check engine All of the check engines are disconnected. Preferably - during the decoding of the first LDPC coded signal, one of the plurality of multiplexers is used in the plurality of memories a memory body connected to at least one bit engine; in the decoding process of the first LDPC coded signal, the multiplexer of the plurality of multiplexers is used to The memory is connected to at least a check engine; and in the decoding process of the first LDPC coded signal, the multiplexing 15 of the plurality of multiplexer wipers is used to remove the memory of the plurality of memory wipes All the check engines of the financial converter engine and the job check engine of the township spleen are disconnected. Preferably, a part of the memory in the plurality of memories is determined by superimposing the plurality of non-zero sub-offices corresponding to the plurality of LDPC-encoded plurality of LDPC matrix towels. Preferably, a part of the memory in the plurality of memories is determined by performing a first-pass, depth search on the superposition of the correction rotor matrix in the plurality of LDpc matrices corresponding to the plurality of LDpc codes. 13 200926615 Preferably, determining a part of the plurality of memories by performing a first-greedy, deep search on a superposition of the plurality of non-zero sub-matrices in the plurality of ldpc matrices corresponding to the plurality of LDPCs Memory; and, the greedy, depth search at least partially considers a column affine metric, the column affine metric indicating at least another of the first LDPC matrix of the first LDPC matrix • Touch connectivity of the second LDpc scale towel. Preferably 'the layout of said plurality of memories within said communication device is based on a merge. mode' generating said merge mode by at least partially considering a column affine metric representing said LDPC moment The connectivity of at least the other columns in the first LDpc matrix and the columns in the second LDpc matrix. Preferably, the plurality of memories include a plurality of merged memories, and the one of the plurality of merged memories corresponds to the first non-zero submatrix in the first LDpc matrix, and corresponds to a second non-zero sub-moment in the second LDpc matrix

Advantageously, said first array of said plurality of LDPC matrices comprises a first plurality of non-zero sub-matrices; said first: LDpc matrix of said plurality of LDPC matrices comprising a second plurality of zero sub-matrices; In the decoding process of the first LDPC, the encoded signal, when processing the first plurality of non-zero sub-moments_first-non-zero sub-matrices, causing the plurality of memories to be a memory; The decoding process towel of the two LDPC coded money, when processing the first-non-zero sub-matrix of the second plurality of non-zero sub-matrices, also manufactures the one memory in the memory of the 14 200926615 memory. Advantageously, said first LDpc matrix of said plurality of LDPC matrices comprises a subset of said plurality of non-zero sub-matrices; and said kLDpc matrix of said plurality of LDPC matrices comprises said plurality of non-zero sub-matrices The subset of and at least one additional non-zero submatrix. Preferably, in the decoding process of the first LDPC coded signal, when the first non-zero submatrix of the first LDPC matrix is used, and in the decoding process of the second LDPC coded signal, # When the second non-zero submatrix of the second LDpc matrix is used, 'the memory cell 中 of the plurality of memories and the first rotor moment _ row and column of the LDPC turn are the same. The positions of the rows and columns of the second rotor turn in the phase two LDPC matrix are preferably, when decoding the first - τ battle matrix (four) - Mei _ saki, the first said

The scales & sighs the second LDPC (four) two - make the two derivatives = turn the coffee ^ touch the province e matrix t preferred 'in the process of the bit node with the device will be the multi-domain One of the plurality of multiplexers is connected to one of the plurality of memories 15 200926615; and during the processing of the check node, among the plurality of multiplexers The one multiplexer connects the check engines of the plurality of check engines to the one of the plurality of memories. Preferably, the decoder is implemented in an integrated circuit. Preferably, the decoding thief is implemented in a communication device, the communication device is configured to receive the first LDPC coded signal or the third LDpc coded signal by using a channel, and the ❹ At least the implementation of the following towels: age communication systems, wireless communication systems, wired communication systems, and fiber-optic communication systems. According to an aspect of the present invention, there is provided a decoder for decoding an ld?c (low-parent, parity check) encoded signal, the decoder comprising: a plurality of memories; a plurality of bit engines, and Each of the plurality of bit engines is coupled to at least one of the plurality of memories; 多个 a plurality of check engines 'per _ check engine of the plurality of check engines Connected to at least one of the plurality of memories; and a plurality of multiplexers (MUX) for: when decoding the first LDK: encoded signal, in the process of processing the bit node, The Petch engine is connected to the first selected memory; when decoding the first LDPC coded signal, the plurality of check engines are connected to the check node processing 16 200926615 The first selected memory in the plurality of memories; when decoding the second LDPC coded signal, connecting the plurality of bit engines to the first of the plurality of memories during bit node processing Two selected memories; when decoding When the LDPC encodes the signal, the plurality of check engines are connected to the second selected one of the plurality of memories during the processing of the check node; when the third LDPC and the coded letter are decoded Connecting the plurality of bit engines to a third selected one of the plurality of memories during bit node processing; and processing the check node by the field when decoding the second LDPC coded signal Connecting the plurality of verification engines to the third selected one of the plurality of memories; wherein: the plurality of memories comprise a predetermined number of memories, the predetermined number of memories The body is used to represent a plurality of non-zero sub-matrices in a plurality of LDpc matrices corresponding to the plurality of LDpcs; the decoding frame is used to decode a job-LDpc codec signal, and the first LDPC code domain corresponds to the a first LDpc matrix of the plurality of LDpc matrices, thereby generating a best estimate of the ratio encoded in the LDPC coded signal; the decoding n is used to decode the second LDpc coded signal, the second LDPC coded domain corresponding to At the plurality of LDpc moments The second lc matrix of the array, 17 200926615, thereby generating a best estimate of the bits encoded in the second LDPr forced & , ' 5 ;; with = decoding _ foot touch three thieves, the first = code The signal corresponds to a third matrix of the plurality of Congma matrices as a best estimate of the bits encoded within the second LDPC encoded signal. A plurality of memories _ a part of the memory are described in detail by arranging each of the plurality of non-zero sub-matrices of the μ 八 八 编码 编码 编码 编码 编码 编码 编码 编码.

Preferably, the touch pair corresponds to the plurality of job codes of the plurality of LDPC codes, and the township material is turned into a greedy deep shot, and the part memory of the body is determined. A also determines the _ partial memory in the memory by using a plurality of (10) C matrices corresponding to the plurality of LDPC 'codes = _ _ _ super _ _ greedy, _ cable;

The user is greedy, and the depth is at least partially nuclear volatility metric, and the column affine degree indicates that the column in the _LDpc matrix and at least another column in the first-level matrix, the first The column LDPC in the two LDPC matrix (4) is sturdy. Preferably, the 'sense of the Weixin device _ is based on the merge nucleus' 2 to generate the merge mode at least partially considering the column affine metric, the column affine metric representing the first LDPC matrix The column is connected to at least another column in the -10th c matrix, a column in the second LDpc matrix, and a column in the third 18 200926615 LDPC matrix. The plurality of memories include a plurality of merged memories, the plurality: the merged memory in the memory corresponds to the first LDPC matrix; the non-zero submatrix also corresponds to The second non-array in the second dirty matrix also corresponds to the third non-zero sub-matrix in the first: LDpc matrix. Preferably, the first LDp of the plurality of LDPC matrices describes a subset of the plurality of non-zero sub-matrices; and the second LDPC matrix rotated by the vehicle includes the plurality of _ 卞 卞Subsets and at least one additional non-zero submatrix. ^Worry, when decoding the first - Congbian Yu, making the first-non-zero sub-matrix in the first matrix, and when deciphering the second c-coded signal, using the second The LDPC extension slams the λα 哲 to use one of the plurality of ticks; and the affine-line includes the second row in the matrix of the fourth (the fourth) Preferably, in the matrix, the decanter is implemented in an integrated circuit. =Selectively, said decoder is implemented in a communication device, said pass receiving said first signal from a communication channel; and C, a flat code field or said second LDPC coded W pass in the following At least one implementation - satellite communication system, 19 200926615 wireless communication secret, wired secret, and first letter system. The various advantages, aspects, and details of the embodiments of the present invention will be described in detail in the description below. [Embodiment] The LDPC (Healthy and Parity) code is a capacity riding front (5) c), and is being used by a large number of communication fresh (for example, female purchase, ΐ ΐ 、, mobile 2 〇, DVB-S 2). Related application areas include magnetic recording, wireless, high-speed data transmission over fiber optic cables and fiber optics. An implementation that enables the LDpc gamma processing of the light-coded green record line, where the check node processing (sometimes referred to as check engine processing) and the bit node processing (sometimes referred to as bit engine processing) are performed in the future. The message is passed back (for example, a check edge message and a bit edge message (sometimes called a variable edge message)). In some cases, this is called message passing decoding processing, on the graphical label of the encoding (for example, LDPC bipartite graphs) is sometimes referred to as "t_d operation". In most communication applications that use LDPC encoded signals, it is necessary and / or expect to support multiple encodings. There are various reasons for this. On the one hand, different encodings can be used for different noise environments and / or data characteristics. For example, when the operating environment of the communication system changes (such as dirty changes), The encoding may also be adaptively changed to accommodate changes in the environment, maintaining an acceptable performance level (eg, acceptable high throughput at low bit error rates of $). The transceiver can be designed to support multiple multi-protocol transceivers of different communication protocols. Many applications also operate using LDPC coding, which is based on sub-matrix and is based on sub-matrix. The LDpc matrix uses a submatrix whose order is changed. For example, the IEEE 802.11n standard specifies 12 different _pc encodings. The Q2 i6a standard regulates 24 different LDpcs, which are also based on sub-matrix structures. The Φ-supplement of the present invention can be used in these application examples of the liver. Ο 〇 The green-enhanced LDpc code of the Korean-end domain provided by the present invention The sub-matrix structure of the family is an effective way to reduce the implementation complexity of the decoder. In general, at any time, the bribe only needs to support the coding scheme in the coding family (for example, when the bribe is transferred to the LDPC coded core) When the number is edited, the decoder structure of the present invention enables the memory and the computing unit to be efficiently shared. This can greatly reduce the decoder's need for storage space and computing units to reduce the size of the decoder. The present invention also provides a method for obtaining sigma and decoding a benefit construct from all PDPC coded 4-pin (supe ring siti〇n) mosquitoes in the LDpc code family using a variety of related techniques. This merge technique is in an individual coding structure. The zero submatrix is used and is based on metrics based on proximity in the graphical representation of the LDPC encoding. It should be noted that the method provided by the present invention can also be applied. Other LDpc decoding configurations include the aforementioned US Provisional Patent Application No. 6/958, 〇 14 and U.S. Utility Model 1 Patent Application No. 11/828,532, the entire disclosure of which is the LDPC decoding of "Distributed Processing LEPC (Low Density Parity Check) decoder" The novel method provided by the present invention uses a single communication device and/or hardware to perform decoding operations of various LDPC code domains. Each of these coded signals has a corresponding available for performing decoding processing. matrix. In some embodiments, each LDpc matrix corresponding to each LDpc code may have a submatrix of the same number. In other embodiments, the number of sub-matrices in each LDpc coding matrix may be f. The goal of this method is to minimize the area of the communication device _ 'with the same scale as the path congestion. # This method can also be used to design a communication 解码 5 for decoding a plurality of LDpc coded signals. Example b' may use an embodiment to obtain a communication device for decoding a curry coded signal generated according to any of the 12 coding schemes that are used in the first sign. In addition, the present invention can be combined Note that the core (10) is optimized for use in decoding interoperability of different LDPC matrices. There are various ways to minimize the number of code signals used in a communication device to decode multiple code signals. For example, The single method includes superimposing each LDpc matrix encoded. Whenever the sub-matrix bits are set, the _matrix _matrix includes non-zero elements (remuneration 1 e qing), and then memory _ in the sub-position The additional coding environment provides a sufficient hardware environment. In addition, the additional savings of the hardware portion obtained from this direct abundance method will be described in the following embodiments. The goal is to send digital data to another location or subsystem from a location or subsystem without error or at a low (4) low error rate. As shown in Figure 22, 200926615, the data can pass through various communication channels in various communication systems. Come Transmission: magnetic media, wired, wireless, optical, copper, and other types of media. Figures 1 and 2 are schematic views of 1 and 200, respectively, of a communication system in accordance with various embodiments of the present invention. The communication system 1A includes a communication channel 199, and a communication device 11A (including a transmitter 112 with an encoder ι4 and a receiver 116 with a decoder (4) 8) located at the 199-end of the communication channel is located in the communication channel 199. Another-side communication device 12A (including a transmitter 126 with an encoder 128 and a receiver 122 with a decoder m) is in communication connection. In some embodiments, "devices 110 and 120 are both It can include only one transmitter or one receiver. The communication channel can be implemented by a variety of different types of media (e.g., using satellite communication channels 13Q of the mosquito antennas 132 and 134, the pylons 142 and 144, and/or the local antennas 152 and I54 (4) (10), The wired communication channel 15A and/or the fiber-optic communication channel using the electro-optical (E/O) interface 162 and the optical-electrical (〇(6) interface 164. In addition, the communication channel 199 can be formed by more than one medium. In order to reduce undesired transmission errors in the communication system, error correction and channel coding are usually used. Generally, the error and the _ include the use of the transmitter-side encoder and the use of the receiver-side decoder. 2 shown in the communication money channel, the sender's face bit 2G1 is provided to the transmitter to tear, and the transmission (4) 7 enables the codec and the payee mapper (which can be regarded as different function blocks η2 and similar) respectively 23 200926615 Encoding these information bits 201, thereby generating a discrete value modulation symbol sequence 203' and then providing it to the transmit driver 230. The transmit driver 230 is generated using a DAC (digital to analog converter) 232. The signal is transmitted 2 〇 4 for a continuous time, and then transmitted. The waver says 'generates the chopped continuous time that is sufficiently suitable for the communication channel 299 to transmit. The signal 205. At the receiving end of the communication channel 299, the continuous time receives the signal 2〇6 Provided to the AFE (Analog Front End) 260, the APE 26A includes a Receive Filter 262 (Generating Filtered Continuous Time Receive Signal 2〇7) and an adC (Analog to Digital Converter) 264 (Generation. Discrete Time Receive Signal 2〇8) Metric generator metrics 27 27 sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym sym , , , , , , , , , , , , , , , , , , , , , , , , , , , , The best estimate of information bits 210 The decoders of the previous embodiments have various features of the present invention. In addition, the following figures and related descriptions will describe devices, systems, functionality, and/or that support the present invention. Or other and specific embodiments of the method (some of which are more detailed). One particular type of signal processed in accordance with the present invention is the LDpc coded signal number. Prior to giving a more detailed introduction, the LDpc code is first performed. General To be described, Fig. 3 shows an embodiment of a device 3 that performs an LDPC decoding process. The device 300 includes a processing pull group 32 and a memory. The memory body is connected to the board, and the 320 and 5 memories are included. 31 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于At 24 200926615, processing core group 320 can be implemented using a shared processing artifact, a single processing device, or multiple processing. Such processing is to grasp hard microprocessors, microcontrollers, microprocessors, microcomputers, central processing materials, field programmable arrays, process logic devices, state machines, logic circuits, analog circuits, digital circuits, and/or The operating instructions process any device of money (analog and/or number (four)). A physical device can be a single storage device or multiple storage devices. Such a depository setting Ο 以 ^ is only a quilt, random note (four) 1 lost city, non-volatile record static memory, dynamic memory, _ memory and / or storage digital 2, any equipment. Note that when the processing device 320 passes the state machine, the analog circuit, and the semaphore, the storage device is embedded in a circuit including a state machine, an analog circuit, and a digital circuit logic circuit. In some embodiments, if so, the manner in which the LDPC decoding process is performed (for example, from the ΓΓ__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . For example, information corresponding to the used LDPC code (for example, (4): parity check matrix) may also be provided from the processing module to the communication system. In addition, any pass within the communication system smoke = in which way the executed Cong Ma will be executed, or from the processing module, the processing module 320 can be expected to generate a variety of executions. Some of the implementations 25 200926615 320 optionally provide different information (e.g., sfl corresponding to different LDPC codes, etc.) to different communication devices and/or communication systems. Thus, different communication links between different communication devices may employ different LDPC codes and/or perform LDPC decoding. It will be apparent that the processing module 320 can provide the same information to each of the different overnight devices and/or communication systems without departing from the scope and spirit of the invention. FIG. 4 shows an apparatus 4 (8) for performing LDpC decoding processing of another embodiment. The device 400 includes a processing module 420 and a memory 41. The memory 41 is coupled to the processing module 420, and the memory 410 is used to store operational instructions that enable the processing module 42 to perform various functions. The processing of the 42G (the (four) service) can be implemented as a device capable of performing the (four) functions of the various modules and/or functional blocks described herein. For example, a 'processing module (served by memory 41) may be implemented as a means for performing and/or controlling LDPC decoding processing performed in accordance with any of the embodiments described herein or its equivalent embodiments. device. The processing module 42G can be implemented using a flipping processing device, a single processing device, or a plurality of processing devices. Such a processor can be used in micro-management, microcontroller, digital health processing H, micro (four) brain, central processing unit, field programmable gate _, programmable logic secret, shape, logic, analog circuit, digital circuit And / or based on the age of the treatment record (classical than the silk (four)) _ what memory _ can be a separate copy of the preparation for the preparation of maternity. The storage device can be read-only (4), age-old memory, Qi Keelong, non-volatile; memory, static, _ _, fast 和, and / or any device that stores digital 200926615 . Note that when the processing device 42 performs one or more functions thereof through a state machine, an analog circuit, a digital circuit, and/or a logic circuit, the corresponding operation is stored; the county person in the order includes a state machine, an analog circuit, a circuit, and Within the circuit of the domain logic circuit.

某些 Some embodiments, if so, the device can be any of a variety of communication devices 430' or a communication device 43A. A communication device 430 including a processing module 420 and an e-memory 410 can be implemented in any communication system 44A. It is to be noted that the LDPC decoding process in the present application and/or each of the four (four) (four) parameters modified according to the coffee c decoding process and its various equivalent embodiments can be applied to various types of communication systems and/or communication devices. FIG. 5 is a schematic diagram of an LDPC^I: sub-graph 500. In the industry, the LDpc bipartite graph is also known as the Tanner graph (tanner graph). LDpc parity checks the code for the moment _ almost financial elements are scaled into the parity check matrix is a sparse matrix. For example, good, 3 ("'s research is considered to be the LDpc code parity check matrix whose block length is 。. The LDPC code is a linear block code, so the set of all codewords is called the parity check matrix. In the ugly zero space. ΠΧ For the LDPC code, it is the sparse binary matrix of _, dimension. Each row of the hit corresponds to the binocular parity '-group green & 'face f material Wei 7 · participation in parity Each column of the ugly corresponds to the code character number. For each codeword x, there are, and each of them is a parity symbol. Therefore, 27 200926615 The coding rate ^ is given as · r ~(nm)/n ( 2) The weights of rows and columns are defined as the number of sets of elements of a given row or column, respectively. The ugly set elements are selected to meet the performance requirements of the encoding. The number of 1s in the column of the parity check matrix For 忒(7), the number j of j in the 7th line of the parity check matrix is expressed as E. For example, 所有 for all / '式句=式, for all), Equation (7) = 4 'The LDPC Ma It is called (preemptive) rule 蹲, otherwise it is called irregular LDPC code. For an introduction to LDPC codes, please refer to the following reference documents: [1] R. Gallager » Low-Dentisy Parity>Check Codes » Cambridge 5 MA: MIT Press 5 1963.

[2] R. G. Gallager Low dentisy parity check codes,, > IRE Trans. Info. Theory. Vol. IT-8, Jan. 1962, pp. 21-28.

[3] M. G. Luby, M. Mitzenmacher, M. A_ Shokrollahi, D. A.

Spielman^andV. Stemann, "Practical Loss-Resilient Codes">pr〇c. 29th Symp. On Theory of Computing, 1997, pp. 150-159. The regular LDPC code can be expressed as a bipartite graph 500' its parity The left node of the matrix is a code bit variable (or "variable node" (or "bit node") 51) in the bit decoding method for decoding the LDPC coded signal, and the right node is a check equation (or "check node" 520) ). The binary graph 5 〇〇 (or called the Tanner graph 500) of the LDPC code defined by 7/ can be defined by a tamper variable node (for example, iV bit nodes) and one check node. Each of the v variable nodes 51 变 28 28 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 266 Within the node). Edges 530, b 512 and check nodes c; 522 are shown. The four edges (as shown in Equation 514), "" are called variables (the degree of the point is similarly, the parent check nodes in the machine node 520 have exact edges (as shown in Equation 524). Connect the (4) with one or more variable nodes (or bit nodes) 51. The number of edges is called the degree y of the check node. The complex number is the point (or bit node 512) 512 The edge 0 between the nodes q 522 can be determined as U. However, on the other side, the edge of the edge can be represented as (10) hand (or butterfly). Alternatively, the edge in the two-blade map corresponds to & a collection element, where the collection element ~ represents an edge-joining bit (eg, a variable) node ζ• and a parity section sentence. ^ External false 疋 gives the variable node Vf (or bit node ~), the slave node A set of edges emitted by or as a point 6) is defined as a nab (four) (or Ο Π (/) these edges are called bit edges, and messages corresponding to these bit edges are called bit edge messages. Assuming that check node 9 is given, the pure-group edge emitted from node 9 can be defined as a post, ringing 4. These edges are called checksums. The message corresponding to these check edges is called the check edge m, and the result of the export is just = (or m==4) and 丨瓦必|=4. Generally speaking, any available bipartite graph The represented demema is characterized by a graphic code. It should be noted that the 'irregular LDPC code can also be represented by a bipartite graph. However, the degree of each group of nodes in the LDPC code can be selected according to some distributions. Therefore, 'two different variable nodes for irregular LDPC codes' and v, 2, | 丨 may not be equal to I ν ΓΘ 对于 For both check nodes, this relationship is also the same. The concept of irregular LDPC codes is at the earliest The introduction is given in the reference document [3]. In summary, by the illustration of the LDPC code, the parameters of the LDpc code can be defined by the degree of distribution, as described in M. Luby et al. in the above referenced file, the following reference documents. There are also related descriptions: [4] TJ Richardson and RL Urbanke, “The capacity 〇f Q low-density parity-check code under message-passing decoding, » IEEE Trans· Inform. Theory ' Vol. 47, No. 2, Feb. 2001, pp· 599_618 This distribution The description is as follows: Λ denotes the fraction of the edge emitted from the variable node whose degree is /, and the outer representation denotes the fraction of the edge emitted from the check node of degree z, then the degree distribution defines the heart 如下 as follows: 々σ 1-2 , The _ and 7^ are divided into the maximum degree of the Wei node and the check node. The weight is also applicable to the irregularity. Although the various embodiments described herein adopt the rule LDPC, it is noted that the features of the present invention are Applicable to regular LDPC ~ LDPC codes. Note that (4), most of the embodiments described in this application employ "bit nodes and edge-to-edge messages" or equivalent expressions of such prior art naming LDPC decoding, "bit nodes - 疋 in bit-side messages, , is also referred to by 30 200926615 as "variable nodes," and "variable side messages," and, therefore, bit values (or variable values) are those values that are estimated to be different. Both of these names can be used in this application. Figure 6 illustrates one embodiment of an LDPC decoding function 600. To perform decoding of an LDPC encoded signal having a sequence of bit signals, the functional blocks shown in Figure 6 are employed. In general, continuous reception is received from the communication channel. Time signal (continu〇uS-time s_al), as shown by reference numeral 601. The communication channel can be any type of channel, including but not limited to wired communication channel, wireless communication wanted, optical fiber communication channel, 1100 Read channel or other type of communication channel capable of transmitting a continuous time signal encoded using an LDPC code. The analog front end (AFE) 610 performs any initial processing on the continuous time signal ( For example, a discrete time signal 611 is generated by performing filtering (analog and/or digital filtering), one or more processes of gain adjustment, etc., and performing digital sampling. The discrete time signal 611 is also referred to as a digital signal, a baseband signal, or an existing Other nomenclature known in the art. Typically the 'discrete time signal 611 is divided into signal's, 卩 (in-phase, quadrature) values.

The metric generator 620 receives the discrete time signal 611 (eg, which includes I, Q values) 'and the corresponding bit metric and/or log likelihood ratio (LLR) 621 corresponding to the reception within the discrete time signal 611 value. In some embodiments, the calculation of these bit metrics/LLR symbol metrics 621 is a two-step process in which metric generator 620 first calculates the symbology of the symbol corresponding to discrete time signal 611, and then the metric generator The symbol metric is used to decompose these symbol metrics into bit metrics / LLR 621. These bit metrics MR 31 200926615 " are then used by the bit engine 63 to initialize the ratio of pending messages (e.g., as indicated by the reference numeral milk), and the iterative decoding process of the DPC handle number is performed 5 (eg, When the Spur Engine (4) and the Execution Engine 64 are executed, the message will be used. The value of the main log likelihood ratio (L£R) is ', and the value of the corresponding received symbol is the value of =. The initialization of the bit edge message of the pin variable node can be defined as Λ - In

❹ Similarly, the 'biter node' bit engine uses the most recently updated bit 3) message to calculate the corresponding soft information for that bit (e.g., as shown by soft message 632). Wonderfully, 'usually iterative, _initialized feeding message is sent to the check engine 640'. During its first decoding iteration, the check 640 uses the initialized Qibian County Jingbian side message.在. At each check node, the 'LDPC decoding process forms a parity result on the positive (Slgn) of the inbound message (x〇R>; this is obtained by having the sign of the outbound station as the parity The result is the XOR of the corresponding person 阙1. The Bay number is then calculated from the check node (four) bits according to the following formula (for example, the reliability of the outbound message of the change point f: ie Λ.. = 2tanh' f ΓΙ tanli \kfhjk^Mi U JJ In some desirable embodiments, this calculation is performed in the logarithmic domain (4) to convert the multiplication 200926615 into addition, as follows:

Dtanlr1 exH Σ

(5) • Thereafter, the bit engine 630 receives the updated side messages (e.g., as shown by the check edge message, (4)) from the check engine_ and uses them to update the bit edge messages. Similarly, the bit engine 630 also causes the bit rate received by the bet metric generator 620 to be performed in accordance with LDPC decoding; t/LLR 62l. That is, these updated check edge messages 641 are transmitted back to the bit node (e.g., bit engine (4)) where the soft information 632 of the bit is calculated using the bit metric /lLR621 and the current iteration value of the check edge message. . At each bit (e.g., variable) node, the calculation of the soft information includes the sum of the LLRs that form the received symbols within the inbound message (e.g., check edge message 641) from the check node. The decoded bits are given by the sign of the sum obtained. Each outbound message for the next calculus horse iteration is calculated by subtracting the system from the summed towel. In order to continue the stacking process 635' these bit edge messages 631 are transmitted to the check engine 640 after being updated. ^ Then perform decoding the iteration again. At the check node, the check engine will receive a bit edge message 631' from the bit node (e.g., 'from bit node 63') and update the check edge message accordingly. The updated check edge message 641 is then transmitted back to the bit node (e.g., bit engine 63A) where the soft information 632 of the bit is calculated using the current iteration value of the bit metric/LLR 621 and the check edge message. Thereafter, the soft information of the newly calculated bit is used, and the bit 33 200926615 engine (4) again uses the previous value of the check edge message (from the previous iteration) to update the bit edge message. The iterative process 635 continues between the bit node and the check node according to the mpcma bipartite graph used to encode the signal being solved by the stone, and the political layer executed by the bit node engine 630 and the check node engine _ The generation decoding processing step is repeated until the stop criterion is satisfied, as indicated by the reference numerals (for example, 'after all the number of iterations of the predetermined or adaptive determination has been performed, all the syndromes of the LDPC stone horse are equal to zero (for example, All parity checks are satisfied. And/or another stopping criterion has been met.] Another way LDpc decoding stops is when the current value of the LDPC codeword is satisfied. _ : Ηχτ = 〇 each decoding iteration process The soft information 632 is generated in the bit engine _. In this embodiment shown in the figure, the soft information (10) can be provided to a hard limiter 650 that makes a hard decision, and hard information (for example) The hard/best estimate 65D can be provided to the syndrome calculator _ to determine if the coded syndromes are all equal to zero. That is, the syndrome calculator 66 determines whether or not to use the LDP based on the current estimate of the codeword. Each syndrome associated with the C code is equal to zero. When the syndrome is not equal to zero, the iterative calculus processing is continued, and the bit edge message is updated and passed between the bit node engine 630 and the check node engine _ as appropriate. And verify the rhyme. Perform the conversion of Wei Li's financial step, based on the soft asset 632 output the hard / best estimate of the bit 651. Also need to pay attention to 'in order to report good solution, energy, bipartite graph The length of the middle loop period is as long as possible. A short loop period, such as 4 loops, can be used to reduce the performance of the message passing decoding method for decoding LDPC number signals. The mathematical calculations of the Marsh method include hyperbolic functions and logarithmic functions (see Equation (5)). In hardware implementations, these functions can also be approximated by a lookup table (LUT) or directly through a logic gate. Mathematical calculations only involve Addition, subtraction, and XOR operations. The number of bits required in a fixed-point implementation depends on the required coding performance, the speed at which the decoder converges, and whether it is necessary to suppress the err〇r floor (eg reference file [5] Place Described later) is determined. [5] Zhang, T., Wang, Z., and Parhi, K., -〇n finite precision implementation of l〇w density parity check codes decoder ",

Proceedings of ISCAS, Sydney, Australia, May 2001, pp 202-205. Figure 7 illustrates an embodiment of a non-zero submatrix superposition of multiple LDPC matrices. Embodiment 700 describes two separate LDPC matrices (coded LDPC matrix 〇 and code 2, lDPC matrix 72 对应) corresponding to two separate LDpc codes. Each of the LDPC matrices 710 and 720 includes four sub-matrices, two of which are zero sub-matrices and two of which are non-zero sub-matrices (e.g., containing more than one non-zero element). Encoding 1, LDPC matrix 710 includes a non-zero submatrix 711 and a non-zero submatrix 712; encoding 2, LDPC matrix 720 includes a non-zero submatrix 721 and a non-zero submatrix 722. The LDPC matrices 710 and 720 are superimposed to generate a superimposed LDpc matrix 73〇. As shown, the non-zero sub-matrix and non-zero sub-matrix claws are in the same position in the superimposed LDpc. In this embodiment, only one non-zero submatrix is left in the superimposed LDpc matrix 73. Figure 8 shows a memory supply to accommodate the non-zero submatrix shouting of the overlay LDpc matrix 35 200926615 shown in Figure 7 - Example _. The single memory structure in which the lining performs decoding processing on each pulse code in the superimposed coffee c matrix 730 may adopt a three-memory_configuration (shown as including memory 8 ιι, memory mic and memory 813) or two memories. Construction (shown as including memory 821 and memory 822). In any of the embodiments, each memory can be selectively coupled to the temple engine to perform bit node processing and check node processing, respectively, to more closely identify the border county and verify the information. Figures 9A and 9B show an embodiment 9 〇 1 and a shift of the decoding apparatus for processing the superimposed LDPC matrix wiper sub-matrix of Figure 7. Referring to Fig. 9 VIII', this embodiment includes three memories (i.e., memory memory ## 隐隐813). The bit metric/LLR is provided to a plurality of bit engines (e.g., bit engine 931 and bit engine 932). The switching mode, group 991 is connected between the bit engine 931 932 and the hidden body 811-813. Another switching engine 992 is connected between the verification engine 921-922 and the memory 811-813. It is necessary to pay attention to the switching module 991. (and other switching modules described in this article) can use a multiplexer (jy^) with multiple inputs/outputs, multiple ancestors, or between memory and bit engine and memory and check engine In the process of decoding the LDPC code 1, one memory is not used (for example, the memory 812 shown in the figure), and the memory matrix 811 is used to process the sub-matrix 711 and use the memory. 813 processes the sub-matrix 712, or vice versa. Alternatively, a single switching module can also be used (eg, the check engine 36 200926615 921-922 can be connected to the switching module 991). After performing the appropriate bit node processing and verification After the node processes and satisfies the stop 4, the 'bit engine 931-932 operation generates soft information, from which the best estimate of the LDPC coded 四 (4) coded bits can be edited. See Figure 9B, in In the process of decoding the LDPC code 2, another money body is not used (for example, the note 813 shown in the ® towel), and the memory matrix 811 is used to process the sub-matrix 72 to process the sub-matrix 722 using the memory 812. Alternatively, as a _, a single (four) ray group (for example, the evaluable engine 921-922 can be connected to the switching module 991) can be used. After performing the 7G appropriate bit node processing and verifying the node processing and satisfying the stop criterion The 'bit engine 931-932 operates to generate soft information from which the best estimate of the coded bits in the LDpc coded signal encoded according to code 2 is known. ® The embodiment of Figures 9A and 9B shows direct A simple superposition method in which two separate memories are used. The LDPC coded signals encoded according to the same two LDPC codes can be decoded using a configuration of only two memories. A schematic diagram of an embodiment of a decoding apparatus for superimposing a non-zero submatrix of an LDPC matrix 730 in Figure 7. This embodiment shows how to decode the same LDPC matrices 710 and 720 using only two memories (phase Using two memories). As shown, sub-matrices 712 (of LDPC matrix 710) and 37 200926615 (of LDPC matrix 720) sub-matrix 722 are not in the same sub-shape in each LDpc matrix 71 顶 and top Matrix position. In each LDpc matrix 71〇 and 72〇, the two sub-matrix positions are mutually exclusive (Caiqing (4) heart (4). Therefore, separate memory (such as merged memory) can be used, in the right In the process of decoding the first LDPC coded signal encoded according to the code 1, the decoding process of the sub-matrix ^ is performed, and in the process of decoding the first LDpc coded signal encoded according to the code 2, The decoding process of the sub-matrix 722 is performed. ^ . About merging memory ‘If a memory is not used by LDpc, then ❹ obviously can remove the memory. Therefore, the memory only needs to be supplied to those sub-matrices having non-zero elements in the resulting superimposed LDPC. Moreover, each memory also has a non-zero LDPC code in it (e.g., for decoding the LDpc code). As mentioned above, it is more efficient to combine memory components corresponding to mutually exclusive non-zero sub-matrices. The set of memory in which the mutually exclusive active code group is stored can be combined into a single record. The mutual repudiation of _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Referring to Figure 10, the hai embodiment includes only two memories (ie, memory 1 and memory 2). The bit metric ship provides multiple bitwise columns such as the spur brain and the specific engine. _ is connected between the bit engine and the memory. Another cut is connected between the engine 01 and 1 and the memory. 38 200926615, with the other The example 'notes that the switching module 1091 (and the other switching modules described herein) can (4) have multiple input/output multiplexers (MUXs), multiple MUXs or allow memory and bit engines. Memory and verification. The other devices connected between the engines are selected to implement. In the LDPC code 1 enters the monument to touch the fortune, _ remember, fairy idol. Both are used. Memory 1 is used to process the sub-matrix 711, The memory 1012 is used to process the sub-matrix 712, or vice versa. 0 * After completing the appropriate bit node processing and check node processing and satisfying the stop 'quasi-' bit engine 1〇31·1〇32 operation generates soft information From the soft information, the LDpc coded signal encoded according to the code i can be obtained. The best estimate of the code bits. In the process of decoding LDPC and code 2, two memories 011 1012 are used. Memory 1〇11 is used to process submatrix mi, and memory ion is used for processing. Matrix 722, or vice versa. After performing π appropriate bit node processing and check node processing and satisfying the stopping criteria, the 'bit engine bribe operation generates soft information, from which the encoding information can be encoded for the basis 2 Dpc, the best estimate of the coded bits in the encoded signal. As an alternative, as with another embodiment, a single switching module can also be used (eg, the check engines 1021 - 1022 can be connected to the switching module 1 〇 91). In the figure, the merged memory (e.g., memory 1012 shown in the figure) can be used to perform the processing of the non-zero submatrix verb 2 of code 1 and the 39 200926615 non-zero submatrix 722 for performing code 2 Processing. The principle of using merged memory to perform decoding processing of mutually exclusive non-zero sub-matrices can also be extended to larger LDPC matrices. Figure 11 shows the decoding of non-zero sub-matrices for processing superimposed LDPC matrices. A schematic diagram of an embodiment 1100. This embodiment can be generalized to apply decoding processing for an encoded signal of an LDPC matrix of any desired size. Referring to Figure 11, the embodiment includes a plurality of memories 111 (i.e., memory 1111- 1113). The bit metric/LLR is provided to a plurality of bit engines (for example, the bit engine and bit engine 1133). The switching module 1191 is connected between the bit engine 1131 and the plurality of memories 111G. The other 峨 1192 is connected to the school. Between the engine 1121-1123 and the plurality of memories 111. As another example, it is necessary to note that the switching module 1 (9) (and other switching modules described herein) can use a complex with multiple input/output terminals. A device (MUX), a plurality of MUXs, or other devices that allow selection of connections between a plurality of memory banks (7) and a plurality of bit engines 1131, and between the memory 1UGs and the plurality of checkers (4) coffee 123 are implemented. The LDPC code for de-alcoholization The first subset of the memory measurements is used to process the non-zero sub-matrices in the first LDPC matrix in the first # process encoded according to the -LDPC encoding. The second signal of the code is decoded. In the private, the second subset of the read, body mo is used to process the non-zero sub-matrices in the second LDpc LDPC matrix. , Ma 在 in the third LDPC coded 徨,,, 46, , , , flat code of the third signal is decoded # 200926615 process 'the third subset of memory 1110 is used to process the second LDPC stone horse A non-zero submatrix in an LDPC matrix. ‘And so on... • In some implementations, the same number of eves of the stone 1110 are used in decoding each code record. In other embodiments, a different number of multiple memories are made when decoding different encoded signals. For example, in various embodiments, each of the first subset, the second subset, and the third subset may include a quantity of memory, v or include a different amount of memory. The switching modules 1191 and U92 ensure that the plurality of bit engines 1131_1133 and the plurality of memory mos are connected to obtain the verification rhyme required for updating the execution process of the bit-side message, and switch between touches ΐ9ι and (10). In order to properly connect between the plurality of check engines 1121_1123 and the plurality of memories, the bit edge message required during the execution of the update board checksum is obtained.钱 Money completes the appropriate point-to-point processing and check node processing and satisfies the stop criterion money 'bit engine 113M1_ for generating soft: New, from which the specific LDPC encoding according to the interest can be obtained. The best estimate of the coded bits in the C coded signal. Figure 12 is a schematic illustration of another embodiment 1200 of a decoding apparatus for processing a non-zero sub-matrix of a superimposed E-matrix matrix. Referring to Fig. 12', this embodiment includes a plurality of memories 121 (i.e., memory 12 is called 213). The bit metric (10) is provided to a plurality of bit engines (e.g., bit engine (2) 1 and bit engine 1233). The switching module (10) is connected to a plurality of bit engines 41 200926615. The same switching engine 1191 also provides a selectable connection 1231-1233 between the 1210 and a plurality of memory 121 〇 between the verification engine 1221-1223 and a plurality of memory 0 隹 pairs according to the process, Non-zero submatrices in the LDPC matrix of the first subset. Two yards

In the LDPC 〇 process, the second sub-port of the memory (4) is turned to process the non-zero sub-matrix in the second coffee LDPC matrix. In the process of decoding the third line of the private code encoded according to the third LDPC code, the third child of the memory mo is turned over to the non-zero sub-matrix in the LDPC matrix of the second LDpc code. And so on... In some embodiments 'the same number of multiple memories mo are used in decoding each encoded signal. In other embodiments, a different number of multiple memories are used when decoding different encoded signals. For example, in various embodiments, each of the above-described first, second, and second subsets may include the same number of memories' or include a different number of memories. The switching module 1291 is configured to ensure proper communication between the plurality of bit engines 123M233 and the plurality of memories 1210 to obtain a check edge message required during the execution of the update bit edge message, and switch the mode red 1291 further Used to ensure proper communication between multiple check engine-(four) and multiple records 121〇 to obtain the bit-edge message check processing required during the execution of 42 200926615 update=edge message To the appropriate bit node processing and node stop criterion, the code-coded LDPC coded signal is generated, and the engine 12314232 is optimally estimated to generate soft information, and the best estimate may be based on the LDPC of the specific interest. 〇 · # U The ^ hardware instruction for decoding the non-zero submatrix of the superimposed LDPC matrix is not available. Fig. 13 Mailing Example 43 〇〇 Decoding #Each (10)c coded signal and having the same number of corrective non-zero sub-transitions. The difference in decoding according to each LDK: code code /, % number % is that the subset of memory used for each low coded signal is different. For example, § Decode the code, code! When encoding money, the corresponding (four) C matrix includes, Χ, non-zero submatrices, and all provided bit engines (provisi (d) engines) can be used for bit-point processing. All provided check engines are used for verification processing. The total number of memory elements is Y, which is used, χ, a memory, that is, the subset 1 of these memories is used. When decoding a signal encoded in accordance with code 2, the corresponding LDPC matrix includes, χ, : non-zero sub-matrices, all of which are provided for bit node processing. All provided warrants are used for warrant processing. The total number of memories is 'Υ, and 'X' is used, and the memory is used, that is, the subsets of these 'γ, one memory are used. So analogous, as shown in the figure. 43 200926615 It can be seen that in the embodiment 1300, when the different LDpc stone horse signals are solved, the only difference is the difference in the subset of memory used. When decoding each LDpc bead horse signal encoded by each LDPC code in 13, the number of bit engines and check engines used is the same. Referring to Figure 14, an embodiment 1400 illustrates an embodiment employing varying degrees of parallelism. This embodiment shows a better variability and flexibility in decoding different LDPC coded signals. - For example, when decoding a signal encoded according to code a, the corresponding LDpc matrix packet includes 'al' non-zero sub-matrices. A total of M, a subset of the provided bit engines can be used for bit node processing 'total 'L', the a3 subset of the provided check engines can be used for node check processing, and the total number of uses, z, the available in the new, must or 'phantom' memory, you can use, z, a subset of memory a4. When decoding a signal encoded according to code b, the corresponding 11) 1 > (: matrix includes, pull, non-zero sub-matrices. The total number of b2 subsets of the supplied bit engines can be used for bit node processing, The total number of L's provided in the verification engine can be used in the "node check processing" and can be used in the available memory of the total, z, or 'noisy memory, can be used , z, a subset μ in memory, and so on, as shown in the figure. For example, 'in embodiment 14', multiple sub-laps can be performed using multiple loops (for example, 'tb special node' Processing or gambling processing). Note that the bit-point processing in an example can update the first half of the bit edge messages using the provided number of bit engines in the first time, and can be In the second quarter of 44, 2009,266, the bit engine that provides the number of $ is used to update the post-half of the bit-side message. This can be seen as a semi-parallel bit-point processing method, so that it is completed step by step in two steps. Generation (for example, bit node processing In another embodiment, 'note the node check processing in the other example, which can update the first one of the check edge messages using the provided number of check engines in the first time' and In the second time, the first half of the checksum is updated using the provided number of check engines and the last time the checksum is updated using the provided number of checksum engines in the third time - A three-pointer... This can be seen as a parallelism node check processing method, so that the decoding sub-decade is completed step by step in three steps (for example, node verification processing). Obviously, without deviating from this In the context of the scope and spirit of the invention, various modifications can be made to the invention, and thus the number of turns employed per sub-replacion can be varied according to a particular embodiment. _ Embodiment 1400, each LDPC matrix need not include the same number of Non-❹ zero submatrix. When decoding a specially tuned LDPC coded signal (when not all provided memory is required), the memory of the corresponding zero submatrix of the LDpc may be broken. During the decoding of a particular signal, Special When the memory is not in use, the memory can be disconnected from the rest of the circuit (for example, disconnected) to prevent the idle ship from interfering with the active (aetive_putatiGn) and saving energy. Implementing each variable node and check node's input to the memory to 0 (or the maximum value "maxvai"), respectively, with the particular unused unused for decoding the particular code The sub-moments 45 200926615 arrays (zero sub-matrices) are connected. Figures 15 and 16 show an embodiment using at least one merged memory (merge mem〇ry). In these embodiments, there are memories that can be used as follows. When the signals encoded in accordance with the code 〇 and 1 are decoded, the memory A is available, and when the other codes are decoded, the memory A is idle. Memory b is available when decoding signals encoded in accordance with codes 2 and 3, and memory B is idle when other codes are decoded. - Figure 15 shows the _ connectivity of two 互 mutex memories processed in accordance with the ldpc; decoding process check node. This embodiment shows how memory A is used when decoding signals encoded in accordance with code 〇 and i, and shows how to decouple § mn from a hardware when decoding the coded L number % of other codes (for example) For that, disconnect). Solving the horse number ^, when § 忆 体 A is not used, the memory A is effectively disconnected from the rest of the hardware / circuit (for example, disconnected) to prevent the idle recording interference active, and Save energy. The disconnection of the memory can be achieved by setting the input of each variable node and the check section. The Q (or the maximum value ❹ maxval ) is used to implement 'these variable nodes and check nodes respectively. Solving the specificity of the particular code does not cause the _submatrix (zero submatrix) to be connected. "This practical example does not show how to make the memory and disconnect the memory from the hardware when decoding the encoded signals of other codes when decoding the signals according to the code 2 and 3. (for example, , disconnect). When decoding some signals, Tian. The hidden body B has not made the branch, remember that the marrow B is effectively sweating from the rest of the hardware/wei (for example, # 'unlinking) to prevent idle memory Interference active operation, 46 200926615 and can save energy. The disconnection of this memory can be set to G by using each variable node work point to the memory input (or the maximum value "maxval," and "test" That is, the variable nodes and the check nodes are respectively connected to sub-matrices (zero sub-matrices) used to decode the specific generation, the specific t.

It should be noted that the variable/bit engine to memory A and b, the connection ' is not shown in the figure, nor is it shown in the following. However, for the present technician, when the verification of the connectivity of the engine is shown, the person skilled in the art can understand the connectivity of the relevant variable/specific engine. It can be seen that the memories A and B can be combined into a single memory c. Next, the memory C is available when the code is encoded in accordance with the codes encoded by codes 0, i, 2, and 3, and the memory C is free when the signals encoded by other codes are decoded. Tian should note that 'when the combined memory is provided separately, it maintains all the connectivity that appears. In the _ subgraphs shown in Figs. 15 and 16, the original connectivity of the memory A and the memory B (Fig. 15) can be maintained when the memory C is made (Fig. 16). For example, consider that there is a mutually exclusive code group in memory A and memory ,, and that (4) A is in an embodiment different from the sub-matrix row of memory B (for example, wishing 'A ship A and a record B towel' Each of the sub-matrices corresponding to different positions in the true LDpc matrix, then the memory A and B will be connected to different check nodes and can be combined in the memory C. Similarly, the memory c can maintain the memory of the memory A to the checksum, and maintain the connectivity of the memory b to the check node. 47 200926615 Figure 16 shows an embodiment 1600 for the connectivity of the merged § memory of the check node processing in accordance with the LPDC decoding process. In a two-step embodiment, 3MUX is employed to allow a single memory C to replace memory A and B. Figure 17 illustrates an embodiment of a method 17 for processing an LDPC coded signal. • Referring to Figure 17, as shown in block 1710, the method 17 initially includes receiving a continuous time signal. As shown in block 1712, the receiving and processing of the continuous time signal can include performing any necessary downconversion on the first continuous time signal to generate a second continuous time signal. The frequency conversion can be achieved by directly converting the carrier frequency to the baseband frequency. Alternatively, the frequency transform can be implemented by positive (frequency). In the embodiment of the method, when the method is performed, the continuous time signal of the interface is generally downconverted to the baseband continuous time signal. Similarly, some type of gain adjustment/gain control can be applied to the received continuous time signal.该 As shown in block 1720, the method 17 can also include sampling the first (or second) continuous time signal to generate a discrete signal and extracting jQ (in-phase, split) components therefrom. An ADC (analog-to-digital converter) or similar device can be used to generate discrete money from received continuous time signals that are appropriate = downconverted (and can be processed by the home wave, gain, etc.). It is also possible to extract the I and Q components of a single sample of the discrete number at this step. Next, as shown in the box, the method ° Π00 includes demodulation! And a Q component, and may include a symbol map of the Σ, q component to a constellation of a map having constellation points to generate a sequence of discrete value modulation symbols. 48 200926615 As shown in box mo, the next step of the method involves performing an edge message update until a stop criterion is encountered (for example, the postal algebra, all symbols are equal to 〇, or until other stopping criteria are encountered ). This step can be seen as performing bit engine processing for updating bit edge messages (e.g., variable edge messages) in accordance with various implementations described above - LPDC solution ♦ LPDC decoding (as shown in block 1742) 'and checksum processing for updating the check edge message (as shown in block 1744). As shown in block 1746, method (4) may also include sampling the selected hardware for presentation to the selected coffee code when decoding a particular LPDC encoded letter of interest. For example, the method 1700 is for performing processing of different LDpc encoded signals. These LDPC encoded signals are generated using the same LDpc code (and therefore have different LDPC matrices). Depending on the signal being decoded, the method 17〇〇 is used to select the appropriate LpDc encoding letter that provides the appropriate Wei, the thief Wei. As indicated by block 1750, after encountering the stop criterion, method Π00 includes making a hard decision ((four) decision) based on the bit information corresponding to the latest update. The method 1700 finally includes outputting a best estimate of the LDPC 'coded bits (e.g., LDpc codeword or LDpc code region) (including information bits) extracted from the received continuous time signal. Figure 18 illustrates an embodiment of a method 18 for processing an LDpc encoded signal. As shown in block 1810, the method [mu](8) begins by identifying all of the LDPC matrices required to decode all LDpc 49 200926615 encoded signals. Next, as shown in block 1820, the method 1800 generates a superposition result for all lDPc matrices (e.g., including a superposition of each sub-matrix bit of all LDpc matrices). Next, as shown in block 1830, the method 18 provides a memory of the sub-matrices that are adapted to each of the superimposed results. This can be done with a variety of square wires and can include any number of steps. In one embodiment, $ includes a first-greedy depth search for the last superimposed LDpc matrix to determine the required number of memory (eg, block 1822 + although a polynomial time-combined search algorithm can be employed to obtain the memory) The body provides a method of 'decision' but it does not always provide a solution from the minimum number of entries. The implementation of the node at 4 nodes can be seen in alphabetical order.

50 200926615 For example, merge into memory F). You can also use the 帛-depth shot to hide the lesser ship solution, so that the first king / ritual is a detailed 'shooting the least practical memory solution yet 'Some embodiments show the difficulty in using this solution. When considering that the root of the solution can be adjusted to suit the ieee · his standard and all of the 12 LDPC codes (each code has its own corresponding LDPC matrix), the county has the IEEE8Q2.lln standard. 2G41 branches. The maximum tree depth result is approximately 105. (0(2_G5)'s search domain cannot complete all searches without a lot of processing and time-consuming conditions. One or more heuristics can be used to accomplish the minimum memory requirements (or relatively few) The memory of the search) and the superimposition obtained at the end => c moment memory _ merge (four) simpler. Can be followed by the second order degree of $. In addition, can be used to manage the merge search method Some hypothetical packets, (1) variable/bit nodes can be compressed relative to each other, check nodes can cover relatively large areas in the superposed LDPC matrix obtained, and (2) read, body, and (4) Tightlyelustered around the variable/bit node.

The search can be a cumbersome heuristic, and the e'it body of the last _(iv) plus LDPC matrix is tightly packed, and the check nodes are connected to different columns of the superposed LDPC matrix. The column affine metric can then be generated based on the Wei between the columns and columns of the particular submatrix and other submatrices in the resulting superimposed LDPC matrix. In another 51 200926615 embodiment, the column affine metric can be used to control/manage the first greedy depth search of the resulting superimposed LDPC matrix. As shown in block 1824, this may also include combining the memory with the mutually exclusive active code into the merged body. As shown in block 1826, the method 18a may also include generating a merge mode of memory (for example, based on the first greedy depth search and mutual exclusion merge) and setting the memory based thereon. Next, as shown in block 1831, method 1800 decodes the first LDpc, encoded signal having the first corresponding LDPC matrix using the first subset of the provided memory. ◎ As shown in block 1832, if the LDPC coded signal is to be decoded, then method 1800 can then decode the nth LDPC coded signal having the nth corresponding LDPC matrix using the 11th subset of the provided memory. Figure 19 illustrates a method 1900 for providing hardware for various LDPC coded signal processing. As shown in block 1910, the method 1900 begins by identifying all 〇 LDPC matrices needed to decode all LDPC coded signals based on connectivity between each column and other columns. As shown in block 1920, the method 1900 then generates a superposition result for all LDpc matrices (for example, including a superposition of each sub-matrix position of all LDPC matrices) - as shown in block 1930, method 1900 then uses Column affine, as yield, performs a first greedy depth search of the overlay results to determine the number of memory required and the merged group (for example, merge mode). 52 200926615 As shown in block 1940, the method 1900 then provides appropriate memory to each sub-matrix of the overlay result based on the merge mode. Figure 20 illustrates an alternative embodiment 2 of an overlay LDPC matrix. This embodiment 2000 corresponds to the superposition of 12 individual LDPC matrices to perform decoding processing using 12 codes in the positive EE 802.11 η standard. When 12 separate 1^^(: matrices are erected (and each of their sub-matrices), there are a total of 205 non-zero sub-matrices in the last appearing superimposed LDpc matrix. Corresponding to each non-zero sub-matrix The messages can be stored in memory. The checksum bit engine can be run so that they can properly and selectively retrieve information from the running memory or write information to the running memory to extract each A suitable non-zero submatrix that can be used to decode the apostrophes, which are encoded according to any of the 12 coding schemes used by the 802.11n. In this embodiment, this 205 Only 88 of the memory are available at any time. Of the 2 to 5 memories, at least 117 are always idle. 'When decoding the first, coded signal, you can use 2第 The first subset of the five memories (88 entries), and when decoding the second encoded signal, the second subset of the 205 memories (88 memories) can be used. The merge mode significantly reduces the 2〇5 notes provided The number of volumes, and by using the last (d) plus LDPC - and depth search to determine the number of required memory 'wire with a minimum number (may not be actually the least) memory. This is a merge mode, and this specific fit can be obtained by using column affine as the _ greedy 53 200926615 搜索 search of the last superimposed LDpc matrix of the metric. The merge mode only needs to provide δ丨 丨 丨 ( 与 与 与 与 与 ( ( ( ( ( ( ( ( ( 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见 可见ν in 102 memories (for example, using the first _iG2 tender axis (for example, found after the greedy depth search) has a relatively good regional trade-off ratio and #旎 congestion. Touch at a specific signal Tow, when the mosquito clock is not Wei (four), the memory can be disconnected from the rest of the circuit (for example, disconnected) to prevent the work and the interference from interfering with the active operation and saving energy. Can be printed overnight And the access node sets the input to the memory to be set to 〇 (or the maximum value "service vai"), and the variable node and the check node are respectively used to decode the specific unused sub-matrix of the specific code (zero Submatrix) It should be noted that the multi-code method presented here can be applied to any sub-matrix/subclock based on the LDPC decoder, where the corresponding sub-/sub-clock is stored in a certain area. The memory needle (for paste, SRAM, registration transfer, etc.). In addition, 'when trying to obtain a more efficient memory solution scale, so (4) the test method can be based on the back-end execution, details (backend (four) touch like a butterfly In order to make a more precise adjustment. In other words, depending on the specific code that the multi-code LDpc decoder needs to perform, it is more accurate to adjust the spectrum. 1. It should be noted that the various modules described herein (for example, the encoder, the decanter 54 200926615, the syllabary _ (10) Jane. This type of appeal" read processing 11, micro control 11, fine t No. processor, micro central processing unit, field programmable closed array, programmable logic device, (digital circuit, digital circuit and / or any signal processing ratio according to the operation command (10). _ (four) side of the storage device or Z production Set up such a storage device can be read-only memory, random access

^, the knowledge of the ship, _ note, like face and / or can be stored in the shell - any memory. It should be noted that when the t processing device, the analog, digital circuit, and the domain logic perform one or more functions, the memory storing the operation instructions for the 2 can be implanted in the state machine, analog circuit, digital or In the circuit of the logic circuit. In such an embodiment, the recording device touches at least some of the steps of the sum, and the processing module associated with the tracked object performs the instructions. The invention has been described above by means of method steps which illustrate the specified functions and relationships. For the sake of convenience, the boundaries and order of these Wei composition pools and method steps are specifically defined here. However, as long as the given Wei and relationship can be properly implemented, changes in boundaries and order are allowed. The boundaries or order of any such variations are considered to be within the scope of the appended claims. The present invention has also been described above with the aid of functional modules that illustrate certain important functions. For the convenience of description, the boundaries of these functional component modules are specifically defined herein. When these important functions are implemented, it is permissible to change the boundaries. The flow chart modules and groups are also specifically defined here to illustrate some important functions of the 2009 20091515. The boundaries and order of the groups can be defined separately as long as these important functions are still achieved. Variations in the boundaries and sequence of the above-described functional modules and flow-through functional modules are still considered to be within the scope of the claims. Those skilled in the art are also aware of the functional modules described herein, as well as other illustrative modules, modules, and components, which may be implemented as an example or by discrete components, special functions, body circuits, processing with appropriate software. And a combination of similar devices. Further, although the details are described in detail to understand and understand the above embodiments, the present invention is not limited to the embodiments. Any technical solution known to the skilled person M that makes various changes or equivalent substitutions to these features and embodiments is within the scope of the present invention. The description of the attachment can be made in a variety of ways and in real time to generate a medium hardware in a device for decoding a plurality of LDPC coded signals. A possible embodiment involves decoding in accordance with any of the 12 coding schemes used in the IEEE 802.11n standard. In this embodiment, 'visible' is only required to move a memory when sampling a combined search, and when using a simple superposition method, 2 to 5 memories are required. Attachment (Merge Mode) Uncombined Memory, Row 〇, Code 0 (〇, *〇), Edit; ^ ^), Code 2 (〇0), Code 3 (0, 0), Code 4 (0, 0), code 5 (〇, 〇), code 6 (〇, 〇), code 7 (0, 0), code 8 (0, 0), code 9 (0, 〇) ' Code 1〇 (〇, 〇 ), code 11 (〇 56 56 200926615 uncombined memory, row 0 column 2, code 1 (0, 2), code 2 (0, 2), code 3 (0, 2), code 4 (0, 2) , code 5 (0, 2), code 6 (0, 2), code 7 (0, 2), code j 8 (0, 2), code 9 (0, 2), code 10 (0, 2), Code 11 (0, 2) • Uncombined memory, row 0 column 3, code 1 (0, 3), code 2 (0, 3), code 3 (0, 3), code 5 (0, 3), Encoding 6 (0, 3), encoding 7 (0, 3), encoding 9 (0, 3), encoding 10 (0, 3), encoding 11 (0, 3) uncombined memory, row 0 column 4, encoding 0 (0, 4), code 2 (0, 4), code 3 (0, ❹ 4), code 4 (0, 4), code 5 (0, 4), code 6 (0, 4), code 7 (0, 4), code 8 (0, 4), code 9 (0, 4), code 10 (0, 4), code 11 (0, 4) uncombined memory, row 0 column 7, code 0 ( 0, 7), code 1 (0, 7), edit 2 (0, 7), code 3 (0, 7), code 7 (0, 7), code 8 (0, 7), code 9 (0, 7), code 10 (0, 7), code 11 ( 0,7) Uncombined memory, row 0 column 8, code 0 (0,8), code 3 (0, 8), code 4 (0, 8), code 5 (0,8), code 6 (0 , 8), code 7 (0,8), code 8 (0,8), code 9 ❹ (0, 8), code 11 (0,8) uncombined memory, row 0 column 23, code 0 (0 , 23), code 1 (0, 23), code 2 (0, 23), code 3 (0, 23), code 4 (0, 23), code 5 (0, 23), code 6 (0, 23 ), code 7 (0, 23), code 8 (0, 23), code 9 (0, 23), code 10 (0, 23), code 11 (0, 23) uncombined memory, row 1 0, code 0 (1,0), code 1 (1,0), code 2 (1, 0), code 3 (1,0), code 5 (1,0), code 6 (1,0), Encoding 7 (1,0), encoding 8 (1,0), encoding 9 (1,0), encoding 10 (1,0), encoding 11 (1,0) 57 200926615 uncombined memory, row 1 column 1 , code 1 (1,1), code 2 (1,1), code 3 (1, 1), code 4 (1,1), code 5 (1,1), code 6 (1,1), code 7 (1,1), code 8 (1, 1), code 9 (1,1), edit 10 (1,1), code 11 (1,1) ' uncombined memory, row 1 column 2, code 0 (1,2), code 1 (1,2), code 2 (1, . 2), Code 3 (1, 2), code 5 (1, 2), code 6 (1, 2), code 7 (1, 2), code 9 (1, 2), code 10 (1, 2), code 11 (1,2) Uncombined memory, row 1 column 4, code 0 (1,4), code 1 (1,4), code 2 (1, 4), code 3 (1,4), code 4 ( 1,4), code 5 (1,4), code 6 (1,4), code 7 ❹ (1,4), code 8 (1,4), code 9 (1,4), code 10 ( 1,4), code 11 (1,4) uncombined memory, row 1 column 5, code 0 (1,5), code 3 (1,5), code 6 (1, 5), codema 7 ( 1,5), code 9 (1,5), code 10 (1,5), code 11 (1,5) uncombined memory, row 1 column 7, code 0 (1,7), code 2 ( 1,7), code 3 (1, 7), code 4 (1,7), code 5 (1,7), code 6 (1,7), code 7 (1,7), code 9 (1, 7), code 10 (1,7), code 11 (1,7) uncombined memory, row 1 column 8, code 0 (1,8), code 1 (1,8), code 2 (1, Ο 8), code 3 (1,8), code 4 (1,8), Code 7 (1,8), code 10 (1,8), code 11 (1,8) uncombined memory, row 1 column 22, code 0 (1,22), code 1 (1,22), code 2 (1,22), code 3 (1,22), code 4 (1,22), code 5 (1,22), code 6 (1,22), code 7 (1,22), code 8 ( 1,22), code 9 (1,22), code 10 (1,22), code 11 (1,22) uncombined memory, row 1 column 23, code 0 (1,23), code 1 (1 , 23), code 2 58 200926615 (1, 23), code 3 (1, 23), code 4 (1, 23), code 5 (1, 23), code 6 (1, 23), code 7 (1 , 23), code 8 (1, 23), code 9 (1, 23), code 10 (1, 23), code 11 (1, 23) • unconsolidated memory, row 2 column 0, code 0 (2 , 0), code 1 (2, 0), code 2 (2, 0), code 3 (2, 0), code 4 (2, 0), code 5 (2, 0), code 6 (2, 0 ), stone horse 7 (2,0), code 9 (2, 0), code 10 (2,0), code 11 (2, 0) uncombined memory, row 2 column 1, code 1 (2 , 1), code 2 (2,1), code 3 (2, ❹ 1), code 5 (2,1), code 6 (2,1), code 7 (2,1), code 8 (2 , 1), code 9 (2, 1), code 10 ( 2, 1), code 11 (2, 1) uncombined memory, row 2 column 2, code 1 (2, 2), code 2 (2, 2), code 3 (2, 2), code 4 (2 , 2), Ma Ma 5 (2, 2), Code 6 (2, 2), Code 7 (2, 2), Code 9 (2, 2), Code 10 (2, 2), Code 11 (2, 2) Uncombined memory, row 2 column 3, code 1 (2, 3), code 2 (2, 3), code 3 (2, 3), code 5 (2, 3), code 6 (2, 3 ), code 7 (2, 3), code 8 (2, 3), code 9 〇 (2, 3), code 10 (2, 3), code 11 (2, 3) uncombined memory, row 2 4, code 0 (2, 4), code 2 (2, 4), code 3 (2, 4), code 4 (2, 4), code 5 (2, 4), code 6 (2, 4), Code 7 (2, 4), code 8 (2, 4), code 9 (2, 4), code 10 (2, 4), code 11 (2, 4) uncombined memory, line 2 column 8, edit玛0 (2,8), code 2 (2, 8), code 3 (2, 8), code 4 (2,8), code 6 (2,8), code 7 (2,8), code 8 (2,8), code 10 (2, 8), code 11 (2, 8) uncombined memory, row 2 column 21, code 0 (2, 21), code 1 (2, 21), code 2 59 200926615 (2, 21), code 3 (2, 21), code 4 (2, 21), code 5 (2, 21) Code 6 (2, 21), code 7 (2, 21), code 8 (2, 21), code 9 (2, 21), code 10 (2, 21), code 11 (2, 21) - not merged Memory, row 2, column 22, code 0 (2, 22), code 1 (2, 22), code 2 (2, 22), code 3 (2, 22), code 4 (2, 22), code 5 (2, 22), code 6 (2, 22), code 7 (2, 22), code 8 (2, 22), code 9 (2, 22), code 10 (2, 22), code 11 ( 2, 22) Uncombined memory, row 3 column 0, code 0 (3, 0), code 1 (3, 0), code 2 (3, 〇0), code 3 (3, 0), code 4 ( 3, 0), code 5 (3, 0), code 6 (3, 0), code 7 (3, 0), code 8 (3, 0), code 9 (3, 0), code 10 (3, 0), code 11 (3, 0) uncombined memory, row 3 column 1, code 0 (3, 1), code 1 (3, 1), code 2 (3, 1), code 3 (3, 1 ), code 5 (3, 1), code 6 (3, 1), code 7 (3, 1), code 9 (3, 1), code 10 (3, 1), code 11 (3, 1) Merge memory, row 3 column 2, code 1 (3, 2), code 2 (3, 2), code 3 (3, 2), code 5 (3, 2), code 6 (3, 2), code 7 (3, 2), code 9 (3, 2), code Ο 10 (3, 2), code 11 (3, 2) Merge memory, row 3 column 3, code 0 (3, 3), code 2 (3, 3), code 3 (3, 3), code 4 (3, 3), code 5 (3, 3), code 6 (3, 3), code 7 (3, 3), code 9 (3, 3), code 10 (3, 3), code 11 (3, 3) uncombined memory, row 3 column 4, code 0 (3, 4), code 1 (3, 4), code 2 (3, 4), code 3 (3, 4), code 4 (3, 4), code 5 (3, 4), code 6 (3 , 4), code 7 (3, 4), code 8 (3, 4), code 10 (3, 4), code 11 (3, 4) 60 200926615 uncombined memory, row 3 column 5, code 0 ( 3, 5), code 2 (3, 5), code 3 (3, 5), code 5 (3, 5), code 6 (3, 5), code 7 (3, 5), code 8 (3, 5), code 9 (3, 5), code 10 (3, 5), code 11 (3, 5) • unconsolidated memory, row 3 column 8, code 0 (3, 8), code 1 (3, 8), code 2 (3, 8), code 3 (3,8), code 4 (3,8), code 7 (3,8), stone 8 (3,8), code 9 (3 , 8), code 10 (3, 8), code 11 (3, 8) uncombined memory, row 3 column 20, code 0 (3, 20), code 1 (3, 20), code 2 ( 3, 20), code 3 (3, 20), code 4 (3, 20), code 5 (3, 20) Code 6 (3, 20), code 7 (3, 20), code 8 (3, 20), code 9 (3, 20), code 10 (3, 20), code 11 (3, 20) uncombined memory Body, row 3 column 21, code 0 (3, 21), code 1 (3, 21), code 2 (3, 21), code 3 (3, 21), code 4 (3, 21), code 5 ( 3, 21), code 6 (3, 21), code 7 (3, 21), code 8 (3, 21), code 9 (3, 21), code 10 (3, 21), code 11 (3, 21) ® Uncombined memory, row 4 column 1, code 0 (4,1), code 1 (4, 1), code 2 (4, 1), code 3 (4,1), code 5 (4, 1), code 6 (4,1), code 7 (4,1), code 9 (4, 1), code 10 (4, 1), code 11 (4, 1) uncombined memory, row 4 2, code 1 (4, 2), code 2 (4, 2), code 3 (4, 2), code 4 (4, 2), code 5 (4, 2), code 6 (4, 2), Ma Ma 7 (4, 2), code 9 (4, 2), code 10 (4, 2), code 11 (4, 2) uncombined memory, row 4 column 3, code 1 (4, 3), Encoding 2 (4, 3), Encoding 3 (4, 3), Encoding 6 (4, 3), Encoding 7 (4, 3), Encoding 9 (4, 3), Encoding 10 (4, 3), Encoding 61 200926615 11(4,3) Uncombined memory, row 4 column 4, code 0 (4, 4), edit Code 2 (4, 4), code 3 (4, 4), code 4 (4, 4), code 5 (4, 4), code 6 (4, 4), code 7 (4, 4) , code 8 (4,4), code 9 (4, 4), code 10 (4, 4), code 11 (4, 4). uncombined memory, row 4 column 5, code 1 (4, 5) , code 2 (4, 5), code 3 (4, 5), code 5 (4, 5), code 6 (4, 5), code 7 (4, 5), code 8 (4, 5), code 10 (4, 5), code 11 (4, 5) uncombined memory, row 5 column 0, code 0 (5, 0), code 1 (5, 0), code 2 (5, (〇0), Code 3 (5, 0), code 4 (5, 0), code 5 (5, 0), code 6 (5, 0), code 7 (5, 0), code 8 (5, 0), code 9 (5, 0), code 10 (5, 0), code 11 (5, 0) uncombined memory, row 5 column 1, code 1 (5, 1), code 2 (5, 1), code 3 (5, 1), code 4 (5,1), code 5 (5,1), code 6 (5,1), code 7 (5,1), code 8 (5,1), code 9 (5 , 1), code 10 (5, 1), code 11 (5, 1) uncombined memory, row 5 column 2, code 1 (5, 2), code 2 (5, 2), code 3 (5, 2), code 5 (5, 2), code 6 (5, 2), code 7 (5, 2), code 8 (5, 2), code ❹ 9 (5, 2), code 10 (5, 2), code 11 (5, 2) uncombined memory, row 5 column 4, code 0 (5, 4), code 1 (5, 4), code 2 (5, 4 ), code 3 (5, 4), code 5 (5, 4), code 6 (5, 4), code 7 (5, 4), code 9 (5, 4), code 10 (5, 4), Code 11 (5,4) uncombined memory, row 5 column 6, code 1 (5, 6), code 2 (5, 6), code 3 (5, 6), code 5 (5, 6), code 6 (5,6), code 7 (5,6), code 8 (5,6), code 9 (5, 6), code 11 (5, 6) 62 200926615 uncombined memory, row 5 column 8 , code 0 (5, 8), code 1 (5, 8), code 2 (5, 8), code 3 (5, 8), code 4 (5, 8), code 7 (5, 8), code 8 (5, 8), code • 11(5,8) • Merge memory, code 0 (11,8), code 1 (2, 5), code 3 (2, 5), code 4 (11,8) ), code 6 (2, 5), code 7 (2, 5), code 8 (11, 8), code 10 (2, 5), code 11 (2, 5) merged memory, code 0 (8) , 3), Ma Ma 1 (1,3), Encoding 2 (1,3), Encoding 3 © (1,3), Encoding 4 (8, 3), Encoding 5 (1,3), Encoding 6 ( 1,3), code 7 (1,3), code 8 (1,3), code 9 (1) 3), code 10 (1, 3), code 11 (1, 3) merge memory, code 〇 (4, 19), code 1 (4, 19), code 2 (4, 19), code 3 (3 , 19), Ma Ma 4 (4, 19), Code 5 (4, 19), Code 6 (4, 19), Code 7 (3, 19), Code 8 (4, 19), Code 9 (4, 19), code 10 (4,19) merged memory, code 〇(10, 〇), code 1 (7, 2), code 2 (4,17), code 3 (3, 17), code 4 (10 , 0), code 5 (7, 2), code 6 (3, 17), code 8 (10, ❹ 0), code 9 (7, 2), code 10 (3, 17), code 11 (3, 17) Merge memory, code 0 (9, 0), code 1 (6, 1), code 3 (0, 20), code 4 (9, 0), code 5 (6, 1), code 6 (5 , 7), code 7 (0, 20), code 8 (9, 0), code 9 (6, 1), code 10 (4, 11), code 11 (0, 20) combined memory, code 0 (6,18), code 1 (6,18), code 2 (2,18), code 3 (2,18), code 4 (6,18), code 5 (6,18), code 6 (2 , 18), code 7 (2, 18), code 8 (6, 18), code 9 (6, 18), code 10 (2, 18), code 11 (2, 18) merged memory, code 0 (4, 20), code 1 (4, 20), code 2 (4, 20), edit 63 200926615 code 3 (1,20), edit 4 (4, 20), code 5 (4, 20), code 6 (4, 20), code 7 ( 1, 20), code 8 (4, 20), code 9 (4, 20), code 10 (4, 20), code 11 (1, 20) merged memory, code 〇 (7, 0), code 1 (7, 0), code 2 (0, 18), code 3 (0, 18), code 4 (7, 0), code 5 (7, 0), code 6 (0, 18), code 8 (7 , 0), code 9 (7, 0), code 10 (0, 18), code 1 1 (0, 18) merged memory, code 〇 (11, 13), code 1 (7, 13), code 3 (3, 13), code 4 (11, 13), code 6 (3, 13), code 7 (3, 13), code 8 (11, 13), code 9 (7, 13), code 10 (3 , 13), code 1 1 (3,13) merged memory, code 〇 (8, 0), code 1 (7, 1), code 2 (2, 16), code 3 (2, 16), code 4 (8, 0), code 5 (7, 1), code 6 (2, 16), code 7 (2, 16), code 8 (8, 0), code 9 (7, 1), code 10 (2 , 16), code 11 (2,16) merged memory, code 0 (11,0), code 1 (5, 3), code 2 (5, 3), code 3 (2, 19), code 4 ( 11, 0), code 5 (5, 3), code 6 (5, 3 ), code 8 (11,0), code 9 (5, 3), code 10 (5, 3), code 11 (2,19) merged memory, code 〇 (6, 17), code 1 (6 , 17), code 3 (2, 17), code 4 (6, 17), code 5 (6, 17), code 6 (4, 16), code 7 (2, 17), code 8 (6, 17 ), code 9 (6, 17), code 10 (2, 17), code 11 (2, 17) merged memory, code 0 (4, 0), code 1 (4, 0), code 2 (4, 0), code 3 (1,19), code 4 (4, 0), code 5 (4,0), code 6 (4, 0), code 7 (1,19), code 8 (4, 0) , code 9 (4, 0), code 10 (4, 0), code 1 1 (1,19) merge memory, code 0 (8,16), code 1 (0,16), code 2 (5, 16), code 3 (0,16), code 4 (8,16), code 5 (0,16), code 6 (0,16), code 7 (0, 200926615 16), code 8 (8, 16), code 9 (0,16), code 10 (5,16), code 11 (0,16) merged memory, code 0 (5,19), code 1 (5,19), code 2 (5 , 19), code - code 3 (0, 19), code 4 (5, 19), code 5 (5, 19), code 6 (5, 19), code 7 (0, .19), code 8 ( 5, 19), code 9 (5, 19), edited Code 10 (5, 19), code 1 1 (0, 19) combined memory, code 0 (7, 17), code 1 (7, 17), code 2 (1, 17), code 3 (1, 17 ), code 4 (7, 17), code 5 (7, 17), code 6 (1, 17), code 7 (1, 17), code 8 (7, 17), code 9 (7, 17), Code 1 1 (1, 17) 合并 Combined memory, code 0 (5,12), code 1 (6, 5), code 2 (5, 12), code 3 (2, 12), code 4 (5 , 12), code 5 (5, 12), code 6 (2, 12), code 7 (2, 12), code 8 (5, 12), code 9 (2, 12), code 10 (2, 12) ), code 11 (2, 12) merged memory, code 0 (9, 15), code 1 (7, 15), code 3 (2, 15), code 4 (9, 15), code 5 (7, 15), code 6 (5, 15), code 7 (2, 15), code 8 (9, 15), code 9 (7, 15), code 10 (5, 15), code 11 (2, 15) Merge memory, code 0 (1 1,12), code 1 (7, 6), code 2 (4,12), ❹ code 3 (3,1S), code 4 (1 1,12), code 5 ( 7, 6), code 6 (4,12), stone horse 7 (3, 18), code 8 (1 1, 12), code 9 (4,12), code 10 (4, 12), code 11 (3, 18) merged memory, code 0 (8, 1) 5), code 1 (4, 15), code 2 (3, 15), code 3 (3, 15), code 4 (8, 15), code 6 (3, 15), code 7 (3, 15) , code 8 (8, 15), code 9 (6, 9), code 10 (4, 15), code 11 (3, 15) combined memory, code 0 (9, 2), code 1 (6, 12 ), code 4 (9,1), code 5 (6, 12), code 6 (5, 13), code 7 (1,12), code 8 (10, 2), code 9 (6, 65 200926615 12 ), code 10 (1, 12), code 11 (1, 12) merge memory, code 0 (6, 0), code 1 (6, 0), code 2 (0, 17), code 3 (0) , 17), code 4 (6,0), code 5 (6,0), code 6 (5,17), code 7 (0,17), -code 8 (6,0), code 9 (6, 0), code 10 (5,17) merged memory, code 0 (8, 4), code 1 (3,12), code 2 (3,12), code 3 (3, 12), code 4 (8 , 4), code 5 (3, 12), code 7 (3, 12), code 8 (8, 4), code 9 (7, 14) merged memory, code 0 (9, 4), code 1 ( 1,15), code 2 (1,15), code 3 (1, 15), code 4 (9, 4), code 5 (1,15), code 6 (1, 15), code 7 ( 1, 19), code 8 (9, 4), code 9 (1, 15 ), code 11 (1, 15) merged memory, code 〇 (〇, 12), code 1 (0, 12), code 2 (5, 1 0), code 3 (0, 12), code 4 (0) , 12), code 6 (0, 12), code 7 (0, 12), code 8 (0, 12), code 9 (5, 10), code 10 (5, 10), code 11 (0, 12 ) Merged memory, encoding 0 (10, 4), encoding 2 (0, 15), encoding 3 (0, 15), encoding 4 (10, 4), encoding 5 (0, 15), encoding 7 (0, 15), code 8 (10,4), code 9 (0, 〇15), code 10 (0, 15) merged memory, code 0 (5,18), code 1 (5,18), code 2 ( 5,18), code 3 (1,18), code 4 (5, 18), code 5 (5, 18), code 6 (5, 18), code 7 (1, 18), code 8 (5, 18), code 9 (5,18), code 10 (5,18) merged memory, code 〇(10,13), code 1 (6,7), code 2 (1,13), code 3 (1) , 13), code 4 (10, 13), code 5 (1, 13), code 6 (1, 13), code 7 (1, 13), code 8 (10, 13), code 9 (6, 7 ), code 11 (1, 13) 66 200926615 merge memory, code 0 (7, 16), code 1 (7, 16), code 3 (1, 16), code 4 (7, 16), code 5 ( 7, 16), Code 8 (7, 16), code 9 (7, 16), code 10 (1, 16) - merge memory, code 0 (11, 4), code 1 (2, 13), code 2 (2, 13 ), code 3 (2,13), code 4 (11,4), code 5 (2,13), code 7 (2,13), choreographer 8 (11,4), code 9 (2, 13 ) Merged memory, encoding 0 (9, 8), encoding 1 (3, 16), encoding 2 (3, 16), encoding 3 (3, 16), encoding 4 (10, 5), encoding 5 ( 3,16), code 7 (3,16), code 8 (9, 8), code 9 (3, 16), code 11 (3,16) merged memory, code 0 (10, 1), code 1 (4, 13), code 3 (3, 7), code 4 (10, 1), code 5 (4, 13), code 6 (3, 7), code 7 (3, 7), code 8 (8 , 1), code 9 (4, 13), code 10 (4, 13), code 11 (3, 7) merged memory, code 0 (10, 14), code 1 (6, 14), code 3 ( 2, 14), code 4 (10,1), code 5 (6,14), code 6 (2,14), code 7 (2,14), code ❹ 8 (10, 14), code 9 (2 , 14), code 1 1 (2, 14) merged memory, code 0 (11,11), code 1 (4, 7), code 2 (4, 7), code 3 (3,11), code 4 (3,11), code 5 (4 , 7), code 6 (3, 11), code 7 (3, 11), code 8 (3, 11), code 9 (3, Π), code 11 (3, 11) merged memory, code 0 ( 9,14), code 2 (4,14), code 3 (1,14), code 4 (9,14), code 5 (4,14), code 6 (4,14), code 7 (1, 14), code 8 (9, 14), code 10 (1, 14) merged memory, code 0 (2, 1 1), code 1 (2, 11), code 2 (2, 11), 67 200926615 code 3 (2, 11), code 4 (9, 11), code 5 (2, 11), code 7 (2, 11), code 8 (6, 11) merged memory, coded 〇 (11, 5), Code 1 (0, 14), code 2 (5, 14), code - code 3 (0, 14), code 4 (9, 6), code 5 (5, 14), code 6 (0, 14) , encoding 7 (0, . 14), encoding 8 (9, 5), encoding 9 (5, 14), encoding 10 (0, 14), encoding 11 (0, 14) combined memory, encoding 〇 (7, 11), code 1 (7, 11), code 2 (0, 13), code 3 (0, 13), code 4 (11, 6), code 5 (7, 11), code 7 (0, 13) , code 8 (11, 6), code 9 (7, 11), code 10 (0, 13), code 11 (0, 13) 〇 merge memory, code 0 (6, 4), code 1 (3, 14), code 2 (3, 14), Code 3 (3, 14), code 4 (6, 4), code 5 (6, 4), code 7 (3, 14), code 8 (6, 4), code 10 (3, 14), code 11 (3, 14) Merge memory, code 0 (10, 6), code 1 (5, 11), code 2 (3, 10), code 3 (3, 10), code 4 (11, 7), code 5 (7, 3), code 6 (5, 11), code 7 (3, 10), code 8 (7, 3), code 9 (7, 3), code 10 (5, 1 1), code 11 (3, 10) merge memory, code 〇 (7,1 〇), code 1 (6,1 〇), code 3 (0,10), code number 4 (6,10), code 6 (0, 10), code 7 (0, 1 0), code 8 (11, 10), code 9 (6, 10) combined memory, code 0 (10, 7), code 2 (1, 11), code 3 ( 1,11), code 4 (7, 5), code 5 (7, 5), code 6 (1,11), code 7 (1, 11), code 8 (7, 7), code 9 (1, 11), code 11 (1,11) \ryfirr merge memory, code 0 (2,10), code 2 (2,10), code 3 (2,10), code 4 (2,10), code 5 (2,10), code 6 (2, 10), code 7 (2,10), code 8 (10, 68 200926615 9), code 1 1 (2, 10) merged memory, code 0 (8,9) ), code 2 (0,11), code 3 (0, 11), edit 'code 4 (0,11), edit 5 (0,11), code 7 (0,11), code 8 (0,11), code 10 (0,11),code 11 ( 0, 11) Merge memory, code 0 (9,10), code 1 (4,10), code 2 (4,10), code 4 (10,10), code 5 (4,10), code 6 (4,10), code 8 (4,10), code 9 (4, 10), code 10 (4, 10) 合并 merge memory, code 0 (5, 9), code 1 (5, 9), Encoding 2 (5, 9), encoding 4 (7, 9), encoding 5 (5, 9), encoding 6 (5, 9), encoding 8 (9, 9), encoding 10 (5, 9) combined memory , Ma 0 (4, 6), code 1 (1, 10), code 2 (4, 6), code 3 (1, 10), code 4 (4, 6), code 5 (1, 10), Code 6 (4, 6), code 7 (1,10), code 8 (1,10), code 10 (1,10), code 11 (1,10) merged memory, code 0 (0, 9) , code 1 (0, 9), code 2 (0, 9), code 3 (0, 9), code 4 (8, 7), code 5 (0, 9), code 7 (0, 9), Encoding 8 (8,7), encoding ❹ 9 (0,9), encoding 11 (0,9) combined memory, encoding 0 (6, 6), encoding 1 (1,6), encoding 2 (4, 9 ), code 3 (1,6), code 4 (4, 9), code 5 (6, 6), code 6 (1) , 6), code 7 (1, 6), code 8 (6, 6), code 9 (4, 9), code 10 (4, 9), code 11 (1, 6) combined memory, code 0 (6, 2), code 1 (6, 2), code 2 (1, 9), code 3 (1, 9), code 4 (1, 9), code 5 (6, 2), code 6 (1 , 9), code 7 (1, 9), code 9 (6, 2), code 11 (1, 9) merged memory, code 0 (8, 8), code 1 (3, 6), code 2 ( 3, 6), code 3 69 200926615 (3, 6), code 4 (8, 8), code 6 (3, 6), code 7 (3, 6), code 8 (8, 8), code 9 ( 3, 6), code 10 (3,6), code 11 (3, 6) merged memory, code 1 (2, 9), code 2 (5, 5), code 3 (2, 9), code 4 - (5, 5), code 6 (5, 5), code 7 (2, 9), code 8 (2, 9), code 9 (5, 5), code 10 (5, 5), code 11 (2, 9) merged memory, code 0 (6, 3), code 1 (6, 3), code 2 (0, 6), code 3 (0, 6), code 4 (6, 3), Ma Ma 5 (6, 3), Encoding 6 (0,6), Encoding 7 (0, 6), Encoding 9 (6, 3), Encoding 10 (0, 6), Encoding 11 (0, 6) 〇 Merging Memory, code 0 (4,8), block 1 (2, 7), code 2 (2, 7), code 3 (2, 7), code 4 (4, 8), code 5 (2, 7), code 6 (4, 8), code 7 (2, 7), code 8 (4, 8), code 10 ( 2, 7), code 11 (2, 7) merged memory, code 0 (7,8), code 1 (7,8), code 3 (2, 6), code 4 (7,8), code 5 (7,8), code 6 (2, 6), code 7 (2, 6), code 8 (7,8), code 9 (2, 6), code 10 (2,6) code 11 (2, 6) merge memory, code 〇 (7, 4), code 1 (7, 4), code 3 (3, 9), code 4 Ο (7, 4), code 5 (3, 9), code 6 ( 3, 9), code 7 (3, 9), code 8 (7, 4), code 9 (7, 4), code 10 (3, 9), code 11 (3, 9) combined memory, Ma Ma 0 (6,8), Ma Ma 1 (0, 5), Encoding 2 (0, 5), Encoding 3 (0, 5), Encoding 4 (6, 8), Encoding 5 (6, 8), Encoding 6 (0, 5), edited mother 7 (0, 5), code 8 (6, 8), code 9 (6, 8), code 10 (0, 5), code 11 (0, 5) merged memory, Code 0 (10,8), code 1 (0,1), code 2 (0,1), code 3 (0,1), code 4 (10,8), code 5 (0,1), code 6 (0,1), code 7 (0, 70 200926615 1;), code 8 (10,8), edit 9 (0, 1), code 10 (〇, 1), code 11 (〇, 1) [Simplified description of the drawings] Figures 1 and 2 show different embodiments of the communication system; Figure 3 is not used for An embodiment of a device performing LDPC decoding processing; FIG. 4 shows an alternative embodiment of a device for performing LDPC decoding processing; FIG. 5 shows an embodiment of an LDPC encoding bipartite graph; FIG. 6 shows an LDPC decoding function Figure 7 illustrates an embodiment of a non-zero submatrix superposition of a plurality of LDpc matrices; Figure 8 illustrates the provision of memory to accommodate the processing of non-zero submatrices of the LDPC matrix superimposed in Figure 7; Embodiments; Figures 9A and 9B illustrate an embodiment of a decoding architecture for adapting the processing of non-zero sub-matrices of the LDPC matrix superimposed in Figure 7; Figure 10 illustrates an embodiment of a decoding architecture for adaptation Processing of a non-zero submatrix of the LDPC matrix superimposed in Figure 7; Figure 11 shows an embodiment of a decoding architecture for adapting the processing of non-zero sub-matrices of the superimposed LDpc matrix; Figure 12 shows the decoding architecture An alternative embodiment for adapting to a non-zero submatrix of a superposed LDPC matrix Figure 13 and Figure 14 show an embodiment of providing hardware for decoding a non-zero sub-matrix of a superimposed LDPC matrix; Figure 15 shows an embodiment of a connection between two mutually independent memories, 71 200926615 The check node processing of the body LDPC decoding processing towel; FIG. 16 shows an embodiment of the connectivity of the merged memory, the combined memory is used for check node processing in the LDPC decoding process; ~ Figure 17 shows an embodiment of a method of processing an LDPC coded signal; Figure 18 illustrates an embodiment of a method of processing an LDPC coded signal; Figure 19 illustrates Figure 20 of a method for providing hardware for processing various ldpC coded signals. An alternative embodiment of a superimposed LDPC matrix is shown [Major element notation] Communication system 100 Communication device 110 Transmitter 112 Encoder 114 Receiver 116 Decoder 118 Communication device 120 Receiver 122 Decoder 124 Transmitter 126 Horse coder 128 Satellite communication channel 130 Disc satellite receiving antenna 132, 134 Wireless communication channel ° 142, 144 〇 Local antenna 152, 154 Electric (E/Ο) interface 162 Communication channel 199, 'flat drinker and symbol mapper 2 〇〇 discrete value modulation symbol sequence 203 wired communication channel 150 fiber communication channel 160 optical-electric (Ο / E) interface 164 communication system 200 information bit 201 continuous time to send signals 14 〇 2〇4 72 200926615 Post-Chop Continuous Time Transmit Signal 205 Continuous Time Receive Signal 206 Filtered Continuous Time Receive Signal 207 Discrete Time Receive Signal 208 Symbol metrics 209 Best Estimate 210 Function Block 222 > 224 Transmit Driver 230 Digital to Analog Converter (DAC) 232 Transmit Filter 234 Analog Front End (AFE) 260 Receive Filter 262 Analog to Digital Converter (ADC) 264 Straightness Generator (me ic generator) 270 Ο

Decoder 280 Transmitter 297 Communication Channel 299 Device 300 Memory 310 Processing Module 320 Communication Device 330 Communication System 340 Device 400 Memory 410 Processing Module 420 Communication Device 430 Communication System 440 LDPC Code Bipartite Diagram 500 Bit Node 510 Bits Node 512 Check Node 520 Check Node 522 Edge 524 Edge 530 LDPC Decoding Function 600 Analog Front End (AFE) 610 Discrete Time Signal 611 Measure Generator 620 Bit Measure and/or Log Likelihood Ratio (LLR) 621 Bit Engine 630 Soft information 632 iterative decoding process 635 check engine 640 check edge message 641 hard limiter (hard limiter) 65 0 73 200926615 hard / best estimate embodiment non-zero sub-matrix non-zero sub-matrix superposition LDPC matrix memory memory Volume memory verification engine bit engine switching module memory verification engine bit engine switching module multiple memory verification engine bit engine switching module multiple memory verification engine bit engine switching module 1291 651 syndrome calculator 660 700 LDPC matrix 710 ' 720 711 non-zero submatrix 712 721 non-zero submatrix 722 730 three memory structure 810 811 memory 812 813 memory 821 822 embodiment 901 > 902 921 check engine 922 931 bit engine 932 991 switching engine 992 1011 memory 1012 1021 check engine 1022 1031 bit engine 1032 1091 Switching Engine 1092 1110 Memory 1111-1113 1121 Check Engine 1123 1131 Bit Engine 1133 1191 Switch Engine 1192 1210 Memory 1211-1213 1221 Check Engine 1223 1231 Bit Engine 1233

74

Claims (1)

200926615 X. Patent application scope: 1. A decoder for decoding a low density parity check coded signal, wherein the decoder comprises: a plurality of memories; a plurality of bit engines 'and the plurality of Each bit engine in the bit engine is used to connect to at least one of the plurality of memories; a plurality of check engines, each of the plurality of check engines is ambiguous Connecting to at least one of the plurality of memories; and a plurality of multiplexers for: selectively selecting the plurality of the first low density parity check encoded signals during the decoding process a bit engine and the plurality of check engines are coupled to the first selected one of the plurality of memories; Selectively connecting the plurality of bit engines and the plurality of check engines to the (four) memory (four) two slave clocks during a decoding process of the second low density parity check encoded signal; and wherein: 1 The plurality of memories comprise a predetermined number of memories, wherein the predetermined number of memories is used to represent a plurality of non-zero sub-matrices in a plurality of low-density parity check matrices corresponding to the plurality of health parity check vectors The numerator (4) is for decoding the first low-density parity check code* value, and the second low-density parity check coder signal corresponds to the first health of the plurality of low-density parity check matrices Degree parity conversion, lion generation at the first low 75 200926615: the best estimate of the bits that are compiled in the even parity coded signal. And the decoder is used to decode the ... and the number, m - low read The parity coded parity check matrix of the first: low two = coffee in the plurality of low-density secret accounts 杳俚 n and even the matrix check matrix, thereby generating a second low 2 such as h < The best estimate of the bits being encoded. _ 2, such as the scope of the patent scope of the application of the number of low traits μ, where Wei superimposed on the _ Π Π Π Π 编 的 的 多个 多个 、 、 、 、 、 、 、 、 、 、 、 The plurality of pieces of memory are recorded. The decoder of claim 1, wherein the first greedy is performed by superimposing a plurality of non-zero sub-matrices in the plurality of low-density parity check matrices corresponding to the plurality of low-in-degree parity check codes And searching in depth to determine a part of the memory in the plurality of memories. 4. The solution of claim 1, wherein the execution of the superposition of the plurality of non-C zero sub-matrices in the plurality of low-density parity check matrices corresponding to the plurality of low-degree parity check codes is performed. a first greedy, deep search, determining a portion of the memory in the plurality of memories; and the first negative center and depth search at least partially consider a column affine metric, the 仿 affine i representing the first low The connectivity of the column of the density parity check matrix to at least one other column of the lower low parity parity check matrix and the columns of the second low density parity check matrix. As described in claim i of the patent scope, wherein the layout of the plurality of memories in the confidant device is based on a merge mode, the merge mode is generated by at least partially considering a column affine 76 200926615 metric, the column simulation The shot metric includes a plurality of merged remembers, and a merged memory entropy of the plurality of recorded body pairs, a merged memory entropy of the first low-density parity check matrix t Non-zero ❹: a second non-:::solution singular number in the second low-density parity check matrix, characterized in that a plurality of memories; Each of the Pate engines is used to connect to at least one of the plurality of ships. = 校 尔 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多When the signal is processed, the first node selected by the bit node is connected to the first selected bit engine of the plurality of memories; the field decodes the first low density odd bet In the process of verifying the code, in the process of verifying the node, the first selected memory of the multi-sensitive engine towel is connected to the first selected memory of the plurality of memories; - when the low density parity check encodes the brown signal, in the process of bit node 77 200926615, the second selected bit of the plurality of bit engines is connected = to the second of the plurality of memories a memory, and an engine connected to the plurality of nodes; (4) a second low-density parity-encoded signal, in the process of verifying the processing, the second selected one of the plurality of checksums Wherein the second selected memory in the memory body > the plurality of memory packages a predetermined number of memories, the predetermined number of 2 is used for a plurality of non-zero sub-matrices in a low-density parity check matrix; the second decoder is used to decode the first low-density parity-checked code, the low-density parity check The coded signal is determined by the first low-density parity check of the stored parity check matrix, from the best estimate of the bits that are browned in the first-low-density parity-coded signal; The decoder is configured to decode a second low density parity check code, where the second low density parity check number corresponds to a first low read parity matrix of the multi-heavy density parity check matrix, thereby A best estimate of the fcb characteristic encoded in the second low-density parity check is generated. The decoder of claim 7, wherein the first-selection ratio engine of the plurality of bit engines is the second selected bit engine of the plurality of bit engines; and the plurality of The first selected check engine of the check engine is the second selected check engine of the plurality of check engines. 78 200926615 9. The decoding n of claim 7, wherein the first-selection ratio of the plurality of bit engines is all bit engines of the plurality of_engines; The first selected check engine of the check engines is all check engines of the plurality of check engines. 10 decoders for decoding low density parity check, coded signals, wherein the decoder comprises: , a plurality of memories; a bit bit engine 'and each of the plurality of bit engines a bit engine is connected to at least one of the plurality of memories; a plurality of check engines, each of the plurality of check engines being connected to the plurality of memories At least one memory; and a plurality of multiplexers for: connecting the plurality of bit engines to the plurality of bit engines during bit node processing when decoding the first low density parity check encoded signal a first selected memory in the memory; when decoding the first low density parity check encoded signal, connecting the plurality of verify engines to the plurality of memories during check node processing The first selected memory; when decoding the second low density parity check encoded signal, connecting the plurality of bit engines to the plurality of the plurality of recorded bodies during bit node processing Second selected memory; 79 200926615 ^ code said second low density parity check code hard memory in the 四 (four) axis / pain beer said plurality of codes third low density parity check code _ 2 in the (four) process, will be described a plurality of bit switches are connected to the second selected one of the plurality of memories; and when the third low density parity check coded signal is decoded by the j, in the process of the verifying process, The plurality of check engines are connected to the third selected one of the plurality of 5 recalls; wherein: the read includes, the body includes a predetermined number of memories, and the pre-emptive amount of 2 faces Corresponding to the plurality of non-zero sub-matrices in the low-density and even-coincidence matrix corresponding to the plurality of robustness parity check codes; the decoding (4) decoding the first-low-density parity check coding letter The low-density parity check coding is based on the first-low-density parity check__ of the low-density dipole-check matrix, so that the ratio of the first-low-degree parity coded (10) code is optimal. Estimating; the decoder is configured to decode the second low density parity check code~ The second low-density parity-check coded signal corresponds to the plurality of low-density 偶%%L-inverted second low-density parity check matrix 'Lion generation is encoded in the second low-latency parity coded coded signal a best estimate of the bits; and the decoder is configured to decode the third low density parity check coded signal, the third low density parity check coded signal corresponding to the plurality of low density 200926615 parity The third low density parity check matrix of the matrix is examined to generate a best estimate of the bits encoded within the third low density parity check encoded signal. 81