200926177 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶裝置及其製造方法，且特別 是有關於一種以可編程電阻式記憶材料為主之高密度記 憶裝置及其製造方法’尤其是硫屬化物之類的相變化型記 憶材料、或包括其它相變化材料之記憶材料。 【先前技術】 ❿ 現今，相變化記憶材料正廣泛地應用在可讀寫式光碟 中。這種記憶材料必須包含有至少兩種固相，例如包括一 般非晶（amorphous)固相以及一般結晶（cryStaiiine)固相。在 可讀寫式光碟中’雷射脈波(laser pulse)通常是用於相與相 之間的切換，以及用以讀取記憶材料之相變化的光學特 性。 在相變化記憶材料於集成電路之應用上，像是硫屬化 物、以及硫屬化物之相似材料，也可以藉由電流多位準之 ❹應用來產生相變化，實現於集成電路之應用。一般非晶態 在與一般結晶態比較之下’其特徵在於一般非晶態之電阻 值係大於一般結晶態之電阻值，而且兩者間之電阻值係容 易分辨，以可作為數據資料。因此，這一類的相變化材料 可以扮演成，一種可編程電阻式έ己憶材料（programmable resistive memory material)。上述種種特性已經引起業界對 於相變化材料及其它可編程電阻式記憶材料，應用於形成 非揮發性記憶體集成電路的興趣，尤其是可讀取、可寫入 6 200926177 之隨機存取式記憶體集成電路。 一般來說，非晶態至結晶態之轉變係為一種低電流操 作’而結晶態至非晶態之轉變係為一種高電流操作。對於 這種高電流操作而言，其包括利用一短暫且電流密度高的 脈波，來融化或崩解結晶結構’並在結晶結構融化或崩解 之後’淬火其相變化過程，使相變化材料快速冷卻，以使 得相變結構之至少一部分成為穩定的非晶態。此外，這一 種結晶態至非晶態之轉變，在本發明說明中係稱之為「重 ❹置（reset)」。而目前最期待的，就是如何將這種用以使相變 化材料發生結晶悲至非晶態轉變的重置電流量降至最 低。對於應用相變化材料之記憶胞（mem〇ry CeU)而言，當 中係包括有一作用區（active region)，此作用區係位在此記 憶胞之相變化材料的本體内，而且係為實際發生相變化的 位置。因此’如能運用技術將作用區變小，就可以降低誘 發相變化所需的電流量。而且，如能利用技術將作用區熱 性絕緣在相變化記憶胞當中，就可以將誘發相變化所需的 ©電阻熱（resistive heating)侷限在作用區之中，相對而言， 也可以降低誘發相變化所需的電流量。 另外’也可以利用縮小相變化材料元件於記憶胞中之 尺寸，及/或縮小相變化材料元件於電極與相變化材料之間 的接觸區尺寸，來降低重置操作所需之重置電流量。藉 此’使彳于重置電流在通過相變化材料元件時’可以同時達 到雨電々il松度與低絕對電流值（abs〇iute current vaiue)。 關於本技術領域之一發展方向，係於集成電路結構之 7 200926177 中形成許多小細孔，然後以少量的可編程電阻式材料填滿 這些小細孔。有關於這一類小細孔的研究發展，包括有下 列專利： ◎ Ovshinsky，「Multibit Single Cell Memory Element Having Tapered Contact」，1997 年 11 月 11 日之美國專利 號第 5,687,112 號； ◎ Zahorik et al.，「Method of Making Chalogenide [sic] Memory Device」，1998年8月4日之美國專利號第 ❹ 5,789,277 號； ◎ Doan et al.，「Controllable Ovonic Phase-Change Semiconductor Memory Device and Method of Fabricating the Same」，2000年11月21日之美國專利號第6，150,253 號。 另外，關於由本案受讓人所發展的技術，係屬於一種 相變化橋型記憶胞(phase change bridge cell)。在這種相變 化橋型記憶胞當中，係包括有一非常小塊的記憶材料，其 ❹有如橋樑般地形成穿過一介於兩電極之間的薄膜絕緣 材。而在集成電路方面，這種相變化橋型記憶胞係可輕易 地整合於邏輯類型以及其它類型之電路。該技術專利可 見： ◎ Lung et al.，「Thin Film Fuse Phase Change RAM and Manufacturing Method」’2005 年 6 月 17 曰之美國專利 申請號第11/155,067號。 於此，為了能充分闡述本發明係將Lung et al.該案以 8 200926177 引用方式併入本文之中’且該案於申請日至今係與本案為 相同之受讓人所有。 關於本技術領域之另一方面’係設計一種極小的電 極，其用以傳遞電流予相變化材料本體，藉以解決控制相 變化記憶胞中之作用區尺寸的問題。這種極小的電極結 構，會使相變化材料於與此電極結構之接觸區處’誘發一 如蘑菇頭般的小區域相變化。此類技術可參考下列專利： ◎ Wicker，「Reduced Contact Areas of Sidewall φ Conductor」，2002年8月6日之美國專利號第6,429,064 號； ◎ Gilgen，「Method for Fabricating a Small Area of Contact between Electrodes」，2002 年 10 月 8 日之美國專 利號第6,462,353號； ◎ Lowrey，「Three-Dimensional (3D) Programmable Device」’2002年12月31曰之美國專利號第6,501，111號； ◎ HarshField，「Memory Elements and Methods for © Making Same」’2003年7月1日之美國專利號第6,563,156 本技術領域中，關於熱流問題的解決方法，可參考美 國專利號第 6,815,704 號之「Self Aligned Air-Gap Thermal Insulation for Nano-scale Insulated Chalcogenide Electronics (NICE) RAM」。在該案之中，係於相變化材料 之侧邊上使用數個間隔或空隙，來達成隔離記憶胞之效 果。並且’該案亦提出應用熱絕緣材料來改善將熱侷限於 9 200926177 作用區上的方法。 另外，關於本技術領域之改善熱性絕緣的方法，係包 括使作用區與電極絕緣之方式來形成相變化材料元件。此 案例可見： ® Chen et al. » r I-Shaped Phase Change memory 以11」’2006年2月7曰之美國專利申請號第11/348,848 號。 於此，為了能充分闡述本發明係將Chen et al該案以 ©引用方式併入本文之中，且該案於申請日至今係與本案為 相同之受讓人所有。 請參照第1圖，其繪示習知技藝中一種記憶胞之部分 的剖面圖。記憶胞100包括一由記憶材料組成之記憶元件 no。記憶元件no具有一作用區120，且作用區12〇係鄰 接於第-界面結構130。記憶元件11〇係電、熱耗接於 第-界面結構13〇 ’以及電、㈣接於—第二界面結構 ^電材165係環繞包圍住記憶元件1丨〇，用以提供 熱絕緣予記憶元件11 〇。 第界面結構130包括一第一傳導件132、以及第一 傳導件132之材料接觸記憶元件u〇之記憶材料之一接觸 區134。第一界面結構13〇亦電、熱耦接於存取電路（未繪 =)一。存取電路包括—隔離元件，隔離元件例如為—電晶體 或一極體。第一界面結構130於記憶元件11〇與存取雷 路之間具有一熱阻抗。 电 200926177 第一界面結構140包括一第二傳導件ι42、以及第二 傳導件I42之材料接觸記憶元件110之記憶材料之一接觸 區M4。第二界面結構140亦電、熱耦接於一位元線結構（未 繪不）。位元線結構包括一位元線。第二界面結構14〇於記 憶元件110與位元線結構之間具有一熱阻抗。 於操作期間，偏壓電路施加電壓予隔離元件及位元 線，可以使電流係從第一界面結構13〇經由記憶元件11〇 而流向第二界面結構14〇，或是使電流係以相反方向從第 ❺二界面結構14〇經由記憶元件no而流向第一界面結構 130 (其中，偏壓電路例如為第12圖之偏壓電路電壓源與 電流源1255)。當於電流通過第一及第二界面結構〗3〇及 140而遍及記憶元件110時，在記憶元件11〇當中稱為作 用區120之那一部份的發熱速度，係較記憶元件n〇之其 餘部份快。 ' 於重置期間，記憶胞1 〇〇會受到一重置脈波作用，此 重置脈波作用之時間係為此重置脈波之一脈波長度。重置 脈波係由偏壓電路之施加而產生的，其用以將記憶元件 110之作用區120轉變為一非晶相。重置脈波是一種相當 高能量的脈波，其能量應至少足以升高作用區12〇之溫 度，至超過δ己憶材料之相轉移（結晶）溫度τχ ,同時也超過 記憶材料之熔點Tm,以致至少能使作用區12〇變成液態。 作用區120變成液態後’隨即終止重置脈波，使作用區】2〇 以一相當快的淬火時間，由熔點Tm快速冷卻至低於相轉 變溫度Tx以下的溫度，藉以讓作用區12〇穩定於一非晶 200926177 相。 在第1圖中，此記憶元件110之作用區120係發生在 第一界面結構130鄰接處，此乃因為第一及第二界面結構 130#及140之間的熱阻抗具有很顯著的差異。舉例來說， 於/卞火期間，一明顯的熱阻抗差異可能會造成熱從記憶元 件no到第一界面結構13〇之傳遞，較記憶元件11〇到第 ，界面結構14〇之傳遞來得快很多。如此，將會造成記憶 元件110鄰近第一界面結構13〇之部位所承受的冷卻速 Ο率，較S己憶元件110其餘部位來得快，使得作用區12〇發 生於第一界面結構130鄰接處。 由於作用區120的相變化係由加熱所產生的，而且記 憶元件110與第一及第二界面結構130、140之間的界面， 般來說係較為脆弱的地方。因此，毗鄰於作用區120的 界面在處於高溫作用之下，將會使其界面衰退的風險增 加。所以，若要提高記憶胞100的可靠度，就要使作用區 120同時峨鄰於第一及第二界面結構130、140。 ❹ 日 但是，由於第一及第二界面結構13〇、14〇之熱傳導 係數較高，若作用區120同時毗鄰於第一及第二界面結構 130、140時’將會導致大量的熱會從作用區120排出，因 而需要更多的能量，才能引發想要在作用區12〇上產生的 相變化。然而，若能使作用區120同時與第一及第二界面 結構130、140分隔遠離，記憶元件110之其餘部位就可 以當作熱絕緣體來使用’以降低誘發相變化所需之能量。 有鑑於此，目前實亟待一種記憶胞結構，係具有均與 12 200926177 第-及第二界面結構分隔遠離的作用區，藉以改善可靠度 以及降低重置操作所需之能量。同時，也 胞結構的方法。 t表:^此„己匕 【發明内容】 本發明係有關於一種記憶褒置。此記 一熱阻抗之存取電路、以；5目士 ^ n卜㈣㈣Λ 具有—熱阻抗之位元線結 ❹ 構。此，己憶褒置更包括—由記憶材料組成之記憶元件。記 界面結構接觸，此第一界面結構係將記 憶凡件電、熱輕接於存取電路，並且第 元件與存取電路之間具有一熱阻抗。記憶元件亦與-第f 界面結構接觸，此第二界面結構係將記憶 於位元線結構，並且篦—κ品从讲 ”、、褐按 構之門且^目ί 構於記憶元件與位元線結 冓之I有亦具有-熱阻抗。其中也包括偏㈣路，其用 =施加-重置脈波（⑽t pulse)予存取電路及位元線社 ❹ 構。相較於記憶元件之作賴的溫度變化之下，存取電ς 構之熱阻抗’係使得存取電路與位元線結構之 與第二界面結構之熱阻抗實質上丄= 件之一遠離第，結 ^中，記憶元件之作用區係遠遠地分隔遠離於第一=施 界=構’例如，作用區實質上是發生在記憶元件的中央; 實施例中’第-界面結構包括-第-傳導構件傳 13 200926177 Γ二且Γ導:傳導件具有一第一形狀，第二界面結構包 =，一傳導件，且此第二傳導件具有—第二形狀。盆 值道形狀係為第一形狀之鏡像(mirror —e) ’且第一 闡第二傳導件實質上係由相同之材料所組成。此中 ^種祕係為-種鏡像，是指#中部件以顛倒排列之 =式’排列成為另-個實質上係為相似之物件。就第一及 2面Γ構而言，鏡像形狀與使用實質上為相同之材 〔H憶70件之作用區遠遠地分隔遠離於第一及第 二的=構’同時也可以讓作用區實質上係發生在記憶元 ^艮#^明之另一方面’係有關於一種記憶震置的製 -二、=下列步驟。形成存取電路，存取電路具有 卩杬。形成一位元線結構，位元線結構具有一埶阻 記憶元件’記憶元件包括一記憶材料。此製造 社堪 下列步驟。形成一與記憶元件接觸之第一界面 ©、曰\ ’此第一界面結構係將記憶元件轉接於存取電路，並 第一界面結構於記憶元件與存取電 形成-與記憶元件接觸之第二界面:構有-此第第： =4係將記憶元件減於位元線結構，並且第二界面 、、，。構於記憶元件與位元線結狀間具有—第二_ ^壓轉，此騎電路制㈣加—具有-脈波長产^ ^置脈波予存取電路及位元線結構。她於 度變化之下，存取電路與位元線結構之熱二作 係使传存取電路與位元線結構之溫度在重置脈波施加期 200926177 間内保持相對地不變。第一界面結構之熱阻抗與第二界面 結構之熱阻抗實質上係為相等，錢得重置脈波之施加會 在記憶元件之-遠離第—界面結構與第二界面結構之作 用區中引起一相變化。 於下文實施方式中，將詳細地揭露本發明之結構盥方 法。本發明欲保護之範圍，並非限定於此發明内容/而應 以後附之申請專利範圍為準。並且，為讓本發明之實施態 樣、特徵、外觀和優點内容能更明顯易懂，下文特舉較^ ❹實施例，配合所附圖式，並輔以後附之申請專利範圍，作 詳細說明如下： 【實施方式】 以下說明請搭配參考第2圖至第13圖，並且於圖式 中係省略不必要之元件，關清楚顯示本發明之技 點。 料照第2圖，其繪示依照本發明—實施例之記憶胞 «的剖面圖。記憶胞綱包括一由記憶材料組成之記憶元件 210。記憶元件210具有一作用區22〇，此作用區22〇均與 一第一界面結構230及一第二界面結構24〇分隔遠離。記 憶το件210係電、熱耦接於第一界面結構23〇，以及亦電、 熱麵接於第二界面結構240。一介電材265係環繞包圍住 記憶元件210,用以提供熱絕緣予記憶元件21〇、第一界 面結構230及第二界面結構24〇。記憶元件21〇係為柱狀 體，其具有一圓形、卵形、方形或其他形狀的截面。 15 200926177 第一界面結構230包括一第一傳導件232、以及第一 傳導件232之材料接觸記憶元件210之記憶材料之一接觸 區234。第一界面結構230亦電、熱耦接於存取電路282。 存取電路282包括有傳導柱250以及隔離元件275。此第 一傳導件232亦為圓柱體，其具有一與記憶材料210吻合 的截面。 隔離元件275包括一當作閘極的字元線280、兩個位 在基材270中的摻雜區272及274、以及一與摻雜區274 ❹接觸之電源線285。傳導柱250係與隔離元件275之摻雜 區272接觸，且延伸穿過介電墊層266而與第一傳導件232 接觸。 第二界面結構240包括一第二傳導件242、以及第二 傳導件242之材料接觸記憶元件210之記憶材料之一接觸 區244。第二界面結構240亦電、熱耦接於位元線結構 290。位元線結構290包括有傳導柱260以及位元線295。 傳導柱260係與字元線295及第二傳導件242接觸。此第 ©二傳導件242亦為圓柱體，其具有一與記憶材料210吻合 的截面。 字元線280以及電源線285係沿垂直第2圖剖面的方 向互相平行延伸，而位元線295係沿平行第2圖剖面的方 向延伸。 在記憶胞200重置期間内，偏壓電路施加一具有一脈 波長度之重置脈波予存取電路282及位元線結構290，此 重置脈波誘發之電流係從第一界面結構130經由記憶元件 16 200926177 110而流向第二界面結構140,或是係以相反方向從第二 界面結構140經由記憶元件110而流向第一界面結構130 (其中，偏壓電路例如為第12圖之偏壓電路電壓源及偏壓 電路電流源1255)。當於電流通過第一及第二界面結構230 及240與記憶元件210時，記憶元件210之作用區220的 加熱速度，係較記憶元件210之其餘部份快。重置脈波應 至少足以升高作用區220之溫度，至超過記憶材料之相轉 移（結晶）溫度Tx，同時也超過記憶材料之熔點Tm，以致 ❹至少能使作用區220變成液態。作用區220變成液態後， 隨即終止重置脈波，使作用區220由熔點Tm冷卻至低於 相轉變溫度Tx以下的溫度，藉以使得作用區220穩定於 一非晶相。以下將搭配第3圖來進一步說明第一界面結構 230於記憶元件210及存取電路282之間的熱阻抗，以及 第二界面結構240於記憶元件210及位元線結構290之間 的熱阻抗，對於記憶元件210之作用區220形成位置的影 響。 © 請參照第3圖，其繪示第2圖之記憶胞之等熱電路的 示意圖。如第3圖所示之記憶元件210、第一界面結構 230、第二界面結構240、存取電路282以及位元線結構 290，係各別代表一個熱阻抗。每一個熱阻抗均包括一熱 電阻以及與其並聯之一熱電容。 此中闡述之熱電阻是一種度量單位，其代表一元件阻 止熱通過元件本身之能力。熱電容亦是一種度量單位，其 代表一元件積聚熱之能力。對於一元件之熱電阻與熱電容 17 200926177 而言，係取決於許多種變數，例如包括有材料的特性、元 件的形狀、以及接觸區之大小與接觸區之特性，其均會影 響元件與相鄰元件之間的熱流動。 存取電路282和位元線結構290之熱阻抗係包括相當 大的熱電容，其使得存取電路與位元線結構之溫度於重置 期間内，在與記憶元件之作用區的溫度變化相較之下，係 保持相對地不變。 ❹ 由於存取電路282與位元線結構292之溫度在重置期 間内保持相對地不變，因此第一界面結構23〇與第二界面 結構240係會影響記憶元件21()於重置期間之加熱與冷 卻。所以，作用區220的位置係會受到第一界面結構23〇 與第二界面結構24〇而影響。其中，若使第一界面結構2別 與第二界面結構謂之熱阻抗實質上為相等，則作用區220 可分隔遠離於第-界面結構23〇以及第二界面結構綱。 ❹ 再參考第2圖，由於第一界面結構23〇與第二界面結 240實貝上係為對稱(鏡像）結構^ ^ ^ 同材料之第一傳導件232與第二傳導件242 :;= 相同寬度251之第一傳導件232與第二傳導件24l = 2:、mtu31之第一傳導件232與第二傳導件 貫質上係為相同的接觸區234及244。因此，笛 一界面結構230與第-界而社媸^ U此第 相黧卄s , 界面結構240之熱阻抗實質上係為 並且，較佳地，傳導柱25〇及26〇 寬度261，且實皙仫支4t 負上係為相同 及260盘笛一 Λ 為 材料。因此，在傳導柱250 ，、 第二界面結構230及之間的接觸區與 18 200926177 接觸特性實質上係為相同。 由此可知’在第一及第二傳導件232及234和傳導桎 250及260之實施態樣中，也可以利用材料寬度的變化， 而使用如I呂（aluminum)、氮化鈦（titanium nitride)以及鹤 (tungsten)基之材料、甚或是非晶矽之類的非金屬導電材 料。而在本實施例中，第一及第二傳導件232及242較佳 地係為氮化鈦(TiN)或氮化鈕(TaN)，第一及第二柱250及 260較佳地係為鎢（w)之類的耐熱材料。在另一種選擇情況 ❹之下，第一及第二傳導件232及242和傳導柱250及260 係可以包括氮化鋁鈦（TiAlN)或氮化鋁鈕（TaAIN)，或者包 括選自於由鈦(Ti)、鎢（W)、鉬（Mo)、鋁（A1)、钽（Ta)、銅 (Cu)、鉑（Pt)、銥(Ir)、鑭(La)、鎳(Ni)、氮(N)、氧(〇)、釕 (Ru)、及其組合物所組成的群組之一種或多種材料。由於 第一及第二傳導件230及240係全部地或部分地與記憶元 件210接觸，故第一及第二傳導件230及240較佳地係包 括一種能與記憶元件210之記憶材料具有協調性 ❹（compatibility)的材料。其中，較佳地可選用氮化鈦(TiN)， 因為氮化鈦(TiN)與GST間，係具有良好的接觸性（此GST 係一種記憶材料，而關於GST的部分將於後續再作詳細說 明）。其中，氮化鈦(TiN)在半導體工業中是一種習知常用 的材料’氮化欽（TiN)是在南溫之下，比如GST相變化溫 度（通常約為600〜700。〇，可提供良好的擴散阻絕效果。 在本發明之實施例中，記憶胞200包括之記憶元件 21〇，係含有硫屬化物材料以及其他材料的相變化記憶材 19 200926177 料。其中，硫族元素(chalcogen)係包括周期表VI族之氧 (〇)、硫（S)、碰（Se)、碲（Te)四種元素之任一者。硫屬化物 (chalcogenide)係包括硫族元素與陽電性元素或陽電性根 (radical)之化合物。硫屬化物合金係包括硫屬化物與其他 過渡金屬材料之組合，且通常包含有一或多個周期表第IV 族之元素’比如鍺（Ge)、錫（Sn)。對於常見的硫屬化物合 金，係包括含有銻（Sb)、鎵(Ga)、銦（In)、銀(Ag)中之一或 多者之化合物。在文獻中已記載之相變化材料，其中為合 〇金者包括有鎵/銻合金(Ga/Sb)、銦/錄合金(in/sb)、銦/砸合 金(In/Se)、録/蹄合金（Sb/Te)、錯/碲合金(Ge/Te)、錯/錄/ 碲合金(Ge/Sb/Te)、銦/銻/碲合金(In/Sb/Te)、鎵/碼/碲合金 (Ga/Se/Te)、鍚/錄/蹄合金（sn/sb/Te)、銦/録/鍺合金 (In/Sb/Ge)、銀/銦/銻/碲合金(Ag/In/Sb/Te)、鍺/錫/銻/碌合 金(Ge/Sn/Sb/Te)、錯/録/砸/碲合金（Ge/Sb/Se/Te)、以及蹄/ 錯/錄/硫合金(Te/Ge/Sb/S)。而在鍺/銻/碲合金(Ge/Sb/Te)系 列之中，可以使用的合金成份範圍很廣泛，其成份特徵係 為 TeaGebSb100_(a+b)。 &在本發明之一些實施例中’係有將一些不純物摻雜於 硫屬化物及其他的相變化記憶材料中，藉以改變記憶元件 ^電度' 相變化溫度、炫點以及其他性質。用以摻雜於 ^化物中之不純物’具代表性者係包括氮、梦、氧、二 夕、氮化矽、銅、銀、金、鋁、氧化銘、钽、氧化钽、 6 、鈦、以及氧化鈦。其中技術可參考美國專利號第 ’504號、以及美國專利公開號第2⑻5川〇295〇2號。 20 200926177 關於研究中已有記載之最佳的鍺/錄/蹄合金 (Ge/Sb/Te)。其中，碲(Te)於沈積材料中的平均濃度，較佳 地應低於70% ’較典型地係大約低於60%，一般的範圍係 約為23%〜58%’而最佳的範圍係約為48%〜58%。鍺（Ge) 於沈積材料中的平均濃度應高於5%且在8%〜30%範圍之 内，一般來說應保持低於50%。鍺（Ge)最佳的濃度範圍係 約為8%〜40%。在合金組成中其餘主要元素係為銻。 前述之百分比（％)係為原子量百分比（atomic percentage)， ©其組成元素之原子的百分比總合係為100%。相關說明， 可參照前述文獻Ovshinsky之美國專利號第5,687,112號中 的第10-11段。而在其他研究之中，係評估出之一些特定 合金，其包括有 Ge2Sb2Te5、GeSb2Te4、以及 GeSb4Te7(相 關說明，見期刊文獻：Noboru Yamada，『Potential of Ge-Sb-Te Phase-Change optical Disks for High-Data-Rate Recoding』，SPIE 第 3109 期（1997)，第 28-37 頁）。更普遍 者，係可將過渡金屬，比如鉻(〇)、鐵(Fe)、鎳(Ni)、鈮(Nb)、 ❹鈀(Pd)、鉑（Pt)、以及其之混合物、合金材料，與鍺/銻/碲 合金（Ge/Sb/Te)結合形成具有可編程電阻性質之相變化合 金。於此’在Ovshinsky之美國專利號第5,687，112號中第 10-11段所提及之記憶材料的具體實例，於本發明適用 者，將以引用方式併入本文之中。 相變化合金，係具有在材料於一大致非晶固相之第一 結構態與材料於一大致結晶固相之第二結構態之間轉換 之能力。其中大致結晶固相，是指記憶胞之作用通道區 200926177 (active channel region)為局部有序。所謂的非晶是指一相 對較為不規則的結構，其排列較單晶雜亂很多。所以，非 晶相在與結晶相比較之下*係具有南電阻之特性。而結晶 是指一相對較為規則的結構，其排列較非晶整齊很多。所 以，結晶相在與非晶相比較之下，係具有低電阻之特性。 在完全非晶態與完全結晶態範圍之内，典型的相變化材料 可以以電性轉換於各種可分辨之局部有序的狀態。而其他 會被非晶相與結晶相之改變而影響的材料特性，包括有有 ❹序度（atomic order)、自由電子密度、以及活化能。因此， 對於相變化材料而言，係可以被轉換成各種不同之固相， 也可以被轉換成混合有兩相或兩相以上之固相，從而提供 一灰階度於完全非晶至完全結晶之間，使得材料的電性可 隨之變化。 相變化合金可以藉由電性脈波的應用，而由一相態轉 變至另一相態。而值得注意的是，一個短暫且高振幅的脈 波是有助於相變化材料轉變成一般的非晶態，一個長且低 ❹振幅的脈波是有助於相變化材料轉變成一般的結晶態。在 暫短且高振幅之脈波能量當中，高振幅係能夠破壞結晶結 構的鍵結，短暫的時間係可避免原子再度排列形成結晶 態。其中，可以以經驗為依據或以模組化之方式，並配合 指定的相變化合金之特性，來決定合適的脈波曲線圖。在 下文中所揭露之相變化材料是屬於一種GST相變化材 料，但熟悉本技術領域者應當暸解，本發明係可使用其它 類型之相變化材料，並非僅限定於此。而在本實施例中， 22 200926177 一種較有利於實現相變化記憶體（PCRAM)之材料，係為 Ge2Sb2Te5 〇 本發明之較具代表性的硫屬化物材料，可表示如下： GexSbyTez ’其中x:y:z = 2:2:5 。而其他可用之組 成圍’ X係在〇〜5之間，y係在〇〜5之間，z係在0〜5 之間。在鍺/録/蹄合金(Ge/Sb/Te)内，亦可摻雜如氮(N-)、 石夕（Si)-、鈦（Ti-)、鱗（P-)、神（As-)或其他之元素。這些材 料均可以利用物理汽相沈積濺鍍(PVD sputtering)或磁通 ❹管濺鍍（magnetron-sputtering)的方式來形成，其中係搭配 通以氬氣(Ar)、氮氣(N2)及/或氦氣(He)等氣體，以及硫屬 化物反應氣體，且壓力係設為lmtorr至lOOmtorr。並且， 此沈積反應通常是在室溫下完成的。而且，可以利用一深 寬比為1〜5之準直器（collimator)，來改善薄膜沈積之填充 性。另外，也可以利用數十到數百伏特的直流偏壓，來改 善填充性。或者，也可以同時使用準直器與直流偏壓，來 改善填充性。此外，也須要以真空或氮氣(N2)氛圍進行沈 ❹積後退火處理，來改善硫屬化物的結晶性。其中，典逛的 退火溫度係設在100〜400°c的範圍，退火時間係在30分鐘 之内。 硫屬化物材料的厚度係取決於記憶胞結構的設計° 一 般來說，硫屬化物材料之厚度大於8nm者，係具有一相變 化特性，以使得其材料具有至少兩種穩定的電阻態。 請參照第4圖，其繪示依照本發明第二實施例之記憶 胞的剖面圖。記憶胞400包括一由記憶材料組成之記憶元 23 200926177 記憶元件具有-作用區42〇’此作用區42〇 ^與一第-界面結構430及一第二界面結構帽分隔遠 離。記憶元件41〇係為柱狀體，#具有一圓形、卵形、方 形或其他形狀的截面。其中第4圖相似於第2圖，此兩者 之不同點在於第4圖沒有第2圖實施例之第一及第二傳導 件 232 及 242。 在第4圖中，第一界面結構43〇包括傳導柱25〇之材 料接觸記憶元件410之記憶材料之一接觸區物。第二界 ©面結構440包括傳導柱篇之材料接觸記憶元件41〇之記 隐材料之一接觸區444。傳導柱25〇及260係包括相同材 料，所以，接觸區434與444之接觸特性實質上係為相同。 並且，傳導柱250與260較佳地係為對稱(鏡像)結構，包 括實質上係為相同寬度261之傳導柱250與260、實質上 係為相同厚度261之傳導柱250與260。 第一界面結構430於記憶元件410與存取電路282之 間係具有一熱阻抗，第二界面結構440於記憶元件410與 ❹位元線結構290之間係具有一熱阻抗。這兩個熱阻抗實質 上係為相等’其乃因為兩者之接觸區434與444實質上為 相同’且接觸區434與444之接觸特性實質上亦為相同。 請參照第5圖’其繪示依照本發明第三實施例之記憶 胞的剖面圖。記憶胞5〇〇包括一由記憶材料組成之記憶元 件510。記憶元件51〇具有一作用區52〇，此作用區52〇 均與一第一界面結構530及一第二界面結構540分隔遠 離。記憶元件510係為柱狀體，其具有一圓形、卵形、方 24 200926177 形或其他形狀的戴面。其中第5圖相似於第2圖，此兩者 不问點t於弟5圖沒有第2圖實施例之傳導柱260。 …在弟^圖中’第一界面結構530包括一第一傳導件 詩％Γ及傳導件532之材料接觸記憶元件510之記 ::::接觸區534。此第—傳導件532亦為圓柱體， 八’、有，、5己憶材料510吻合的截面。 第二界面結構540包括—第二傳導件⑷、以及第二 ❹ ❹ 專導件542之材料接觸記憶元件510之記憶材料之一接觸 =44。此第二傳導件542亦為圓柱體，其具有—與記憶 材料510吻合的截面。 第一界面結構530於存取電路282與記憶元件5⑺之 =係具有一熱阻抗’第二界面結構54g於位元線295與記 件510之間係具有一熱阻抗。這兩個熱阻抗實質上係 ς相等:其乃因為第-界面結構53〇與第二界面結構獨 實質上係為對稱(鏡像)結構，係包括相同材料之第 二532與第一傳導件542、實質上係為相同寬度如之第 一傳導件532與第二傳導件542、實質上係為相同厚度別 之第一傳導件532與第二傳導件542、以 同的接觸區534與544。 貨係為相 請參照第6圖’其緣示依照本發明第四實施例之 圖。記憶胞_包括—由記憶材料組成之記憶^ 件610。記憶元件61〇具有一作用區62〇， 均與-第-界面結構630及一第一界面社播：用£ 620 第一界面結構640分隔遠 離。錢^件610係為柱狀體，其 25 200926177 形或其他形狀的截面。其中第6圖相似於第5圖，此兩者 不同點在於第6圖沒有第5圖實施例之第-及第二傳導件 532 及 542。 在第6圖中，第一界面結構㈣包括傳導柱250之材 料接觸記憶元件6H)之記憶材料之一接觸區⑽。第二界 面結構640包括位元、線295之材料接觸記憶元件6ι〇之記 憶材料之-接觸區644。位元線295之表面與傳導柱25〇 之表面較佳地係包括相同材料，以使得接㈣咖與⑷ ❹之接觸特性實質上係為相同。 、 第一界面結構630於存取電路282與記憶元件⑽之 間係具有-熱阻抗，第二界面結構_於位元線Μ5與記 憶几件610之間係具有一熱阻抗。這兩個熱阻抗實質上係 為相等，其乃因為兩者之接觸區634與644實質上為相 同，且接觸區634與644之接觸特性實質上亦為相同。雖 然位兀線295之熱阻抗可能會不同於存取電路282之熱阻 抗，但是位元線295與存取電路282均具有相當大的熱電 各，相較於5己憶元件之作用區的溫度變化之下，可使得存 取電路282之溫度與位元線295之溫度在重置期間内能保 持相對地不變。所以，可以讓作用區62〇分隔遠離於第一 界面結構630及第二界面結構640。 請參照第7圖，其繪示依照本發明第五實施例之記憶 胞的剖面圖。記憶胞700包括一由記憶材料組成之記憶^ 件710。記憶元件710具有一作用區72〇’此作用區72〇 均與一第一界面結構730及一第二界面結構74〇分隔遠 26 200926177 離。第一界面結構730係以一寬度752之介電墊層750， 而與第二界面結構740分隔。記憶元件71 〇包括一記情材 料層780，記憶材料層780之一部份係延伸穿過介電塾層 750 ’而與第一界面結構730及第二界面結構740接觸， 並據以在第一界面結構730及第二界面結構740之間定義 出一電流路徑（或稱為電極間路徑），此電流路徑之路徑長 度係為介電墊層750之寬度752。 在第7圖中’第一界面結構730包括一第一傳導件 ❹732、以及第一傳導件732之材料接觸記憶元件71〇之記 憶材料之一接觸區734。第二界面結構740包括一第二傳 導件742、以及第二傳導件742之材料接觸記憶元件71〇 之記憶材料之一接觸區744。 如第7圖所示，位於記憶材料層78〇與第一傳導件200926177 IX. Description of the Invention: [Technical Field] The present invention relates to a memory device and a method of fabricating the same, and more particularly to a high-density memory device based on a programmable resistive memory material and a method of fabricating the same 'In particular, phase change memory materials such as chalcogenides, or memory materials including other phase change materials. [Prior Art] 相 Today, phase change memory materials are widely used in readable and writable optical discs. Such memory materials must contain at least two solid phases, including, for example, a generally amorphous solid phase and a generally crystalline (cryStaiiine) solid phase. In readable and writable optical discs, laser pulses are typically used for phase-to-phase switching and optical characteristics for reading phase changes in memory materials. In the application of phase change memory materials to integrated circuits, such as chalcogenide and chalcogenide, it is also possible to use a multi-level current application to generate phase changes for integrated circuit applications. Generally, the amorphous state is compared with the general crystalline state, which is characterized in that the resistance value of the general amorphous state is greater than the resistance value of the general crystalline state, and the resistance value between the two is easily distinguishable, so that it can be used as a data sheet. Therefore, this type of phase change material can be played as a programmable resistive memory material. These various characteristics have led to the industry's interest in the formation of non-volatile memory integrated circuits for phase change materials and other programmable resistive memory materials, especially readable and writable 6 200926177 random access memory. integrated circuit. In general, the transition from amorphous to crystalline is a low current operation' and the crystalline to amorphous transition is a high current operation. For such high current operation, it involves the use of a transient and high current density pulse wave to melt or disintegrate the crystalline structure 'and to quench its phase change process after the crystalline structure has melted or disintegrated, making the phase change material Rapid cooling is performed such that at least a portion of the phase change structure becomes a stable amorphous state. Moreover, this transition from crystalline to amorphous is referred to as "reset" in the description of the present invention. What is most expected now is how to minimize the amount of reset current used to make the phase change material crystallize to amorphous transition. For the memory cell (mem〇ry CeU) to which the phase change material is applied, the middle portion includes an active region which is located in the body of the phase change material of the memory cell and is actually generated. The position of the phase change. Therefore, if the technology can be used to reduce the area of action, the amount of current required to induce phase changes can be reduced. Moreover, if the technology can be used to thermally insulate the active region in the phase change memory cell, the resistive heating required to induce the phase change can be limited to the active region, and the induced phase can be reduced. The amount of current required to change. In addition, the size of the reset current required for the reset operation can be reduced by reducing the size of the phase change material element in the memory cell and/or reducing the size of the contact area between the phase change material element and the phase change material. . By virtue of this, the reset current can pass through the phase change material element to simultaneously achieve the rain 々il looseness and the low absolute current value (abs〇iute current vaiue). Regarding one of the developments in the art, many small pores are formed in the integrated circuit structure 7 200926177, and then these small pores are filled with a small amount of programmable resistive material. The research and development of this type of small pores includes the following patents: ◎ Ovshinsky, "Multibit Single Cell Memory Element Having Tapered Contact", US Patent No. 5,687,112, November 11, 1997; ◎ Zahorik et al. , "Method of Making Chalogenide [sic] Memory Device", US Patent No. 5,789,277, August 4, 1998; ◎ Doan et al. "Controllable Ovonic Phase-Change Semiconductor Memory Device and Method of Fabricating the Same", U.S. Patent No. 6,150,253, issued Nov. 21, 2000. In addition, the technology developed by the assignee of this case belongs to a phase change bridge cell. Among such phase change bridge type memory cells, there is a very small piece of memory material which is formed like a bridge through a film insulating material interposed between the electrodes. On the integrated circuit side, this phase-change bridge memory cell can be easily integrated into logic types as well as other types of circuits. The technical patent can be seen: ◎ Lung et al. , "Thin Film Fuse Phase Change RAM and Manufacturing Method", U.S. Patent Application Serial No. 11/155,067, issued June 17, 2005. Here, in order to fully explain the present invention, Lung et al. The case is hereby incorporated by reference in its entirety by reference to the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the disclosure of Another aspect of the art is to design a very small electrode for transferring current to the body of the phase change material, thereby solving the problem of controlling the size of the active region in the phase cell. This extremely small electrode structure causes the phase change material to change in a small area like a mushroom head at the contact area with the electrode structure. Such techniques can be found in the following patents: ◎ Wicker, "Reduced Contact Areas of Sidewall φ Conductor", US Patent No. 6,429,064, August 6, 2002; ◎ Gilgen, "Method for Fabricating a Small Area of Contact between Electrodes" , U.S. Patent No. 6,462,353, October 8, 2002; ◎ Lowrey, "Three-Dimensional (3D) Programmable Device", US Patent No. 6,501,111, December 31, 2002; ◎ HarshField, "Memory US Patent No. 6, 563, 156, issued July 1, 2003, the disclosure of which is incorporated herein by reference in its entirety by reference to U.S. Patent No. 6,815,704, "Self Aligned Air-Gap Thermal Insulation". For Nano-scale Insulated Chalcogenide Electronics (NICE) RAM". In this case, several spacers or voids are used on the sides of the phase change material to achieve the effect of isolating the memory cells. And the case also proposed the use of thermal insulation materials to improve the method of limiting heat to the 9 200926177 active zone. Additionally, a method of improving thermal insulation in the art includes forming a phase change material element by insulating the active area from the electrode. This case can be seen: ® Chen et al. » r I-Shaped Phase Change memory is US Patent Application No. 11/348,848, issued February 1, 2006. In order to be able to fully clarify the invention, the present invention is hereby incorporated by reference in its entirety by reference in its entirety in its entirety in the the the the the the the Referring to Figure 1, there is shown a cross-sectional view of a portion of a memory cell in the prior art. Memory cell 100 includes a memory element no composed of memory material. The memory element no has an active area 120, and the active area 12 is adjacent to the first-interface structure 130. The memory element 11 is electrically connected to the first interface structure 13A' and electrically, and (4) is connected to the second interface structure. The electrical material 165 surrounds the memory element 1 to provide thermal insulation to the memory element. 11 〇. The first interface structure 130 includes a first conductive member 132, and a contact region 134 of the memory material of the first conductive member 132 that contacts the memory element. The first interface structure 13 is also electrically and thermally coupled to the access circuit (not shown). The access circuit includes an isolation element, such as a transistor or a pole. The first interface structure 130 has a thermal impedance between the memory element 11A and the access ramp. The first interface structure 140 includes a second conductive member ι42, and a material contact region M4 of the memory material of the second conductive member I42 that contacts the memory element 110. The second interface structure 140 is also electrically and thermally coupled to a one-dimensional line structure (not shown). The bit line structure includes a bit line. The second interface structure 14 has a thermal impedance between the memory element 110 and the bit line structure. During operation, the bias circuit applies a voltage to the isolation element and the bit line, so that the current can flow from the first interface structure 13 to the second interface structure 14 via the memory element 11 or the current system can be reversed. The direction flows from the second interface structure 14A to the first interface structure 130 via the memory element no (wherein the bias circuit is, for example, the bias circuit voltage source and current source 1255 of FIG. 12). When the current passes through the first and second interface structures 〇3 and 140 and extends over the memory element 110, the portion of the memory element 11 称为 referred to as the portion of the active region 120 is heated faster than the memory device. The rest is fast. During the reset period, the memory cell 1 will be subjected to a reset pulse wave. The time for resetting the pulse wave is to reset the pulse wave length of one pulse. The reset pulse wave is generated by the application of a biasing circuit for converting the active region 120 of the memory element 110 into an amorphous phase. The reset pulse wave is a relatively high-energy pulse wave whose energy should be at least enough to raise the temperature of the active region 12 , to exceed the phase transfer (crystallization) temperature τ δ of the δ recall material and also exceed the melting point Tm of the memory material. So that at least the active zone 12 turns into a liquid state. After the active zone 120 becomes liquid, it immediately terminates the resetting of the pulse wave, so that the active zone is rapidly cooled by the melting point Tm to a temperature lower than the phase transition temperature Tx by a relatively fast quenching time, so that the active zone 12〇 Stabilized in an amorphous 200926177 phase. In Fig. 1, the active area 120 of the memory element 110 occurs adjacent to the first interface structure 130 because of the significant difference in thermal impedance between the first and second interface structures 130# and 140. For example, during / bonfire, a significant difference in thermal impedance may cause heat to pass from the memory element no to the first interface structure 13 ,, and the interface structure 14 〇 is transmitted faster than the memory element 11 第a lot of. In this way, the cooling rate of the memory element 110 adjacent to the first interface structure 13〇 is caused to be faster than the rest of the S-remember element 110, so that the active area 12〇 occurs adjacent to the first interface structure 130. . Since the phase change of the active area 120 is caused by heating, and the interface between the memory element 110 and the first and second interface structures 130, 140 is generally a relatively fragile place. Therefore, the interface adjacent to the active zone 120, under the effect of high temperature, will increase the risk of interface degradation. Therefore, if the reliability of the memory cell 100 is to be improved, the active area 120 is simultaneously adjacent to the first and second interface structures 130, 140. However, since the first and second interface structures 13〇, 14〇 have a high heat transfer coefficient, if the active region 120 is adjacent to the first and second interface structures 130 and 140 at the same time, a large amount of heat will be caused. The active zone 120 is discharged and thus requires more energy to initiate the phase change that is desired to occur on the active zone 12〇. However, if the active region 120 can be separated from the first and second interface structures 130, 140 at the same time, the remainder of the memory element 110 can be used as a thermal insulator to reduce the energy required to induce phase changes. In view of this, there is currently a need for a memory cell structure that has an active region that is spaced apart from the 12th and 26th interface structures, thereby improving reliability and reducing the energy required for reset operations. At the same time, it is also a method of cell structure. t table: ^this „ 匕 匕 【 发明 发明 发明 发明 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己There is a thermal impedance between the circuits. The memory element is also in contact with the -fth interface structure, the second interface structure will be memorized in the bit line structure, and the 篦-κ product is spoken, and the brown gate is constructed. ^I constituting the memory element and the bit line junction I also have - thermal impedance. It also includes the partial (four) way, which uses the = apply-reset pulse wave ((10)t pulse) to access the circuit and the bit line community. The thermal impedance of the access structure is such that the thermal impedance of the access circuit and the bit line structure and the second interface structure are substantially one of the pieces away from the temperature change of the memory element. In the first step, the active area of the memory element is far apart from the first = boundary = structure. For example, the active area essentially occurs in the center of the memory element; in the embodiment, the 'first-interface structure includes - Conductive member transmission 13 200926177 : Γ : : : : : 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导The basin shape is a mirror image of the first shape (mirror - e) ' and the first second conductor is substantially composed of the same material. The secret system is a kind of mirror image, which means that the components in # are arranged in reverse order and become another object that is substantially similar. In the case of the first and second sides, the mirror shape is substantially the same as that used [H memory 70 pieces of the action zone are far apart from the first and second = structure] and can also make the scope substantive The upper system occurs on the other side of the memory element ^^#', and there is a system for a memory shock-two, = the following steps. An access circuit is formed, and the access circuit has a defect. A one-dimensional line structure is formed, the bit line structure having a resistive memory element. The memory element includes a memory material. This manufacturing facility has the following steps. Forming a first interface that is in contact with the memory element. The first interface structure transfers the memory element to the access circuit, and the first interface structure forms a contact with the memory element and the access memory. The second interface: constructed - this first: = 4 is to reduce the memory element to the bit line structure, and the second interface, ,,. Between the memory element and the bit line junction, there is a second _ ^ pressure rotation, and the riding circuit system (4) plus - has a pulse wavelength to generate a pulse wave to access the circuit and the bit line structure. Under the change of the degree, the thermal circuit of the access circuit and the bit line structure keeps the temperature of the transmission access circuit and the bit line structure relatively unchanged during the reset pulse application period 200926177. The thermal impedance of the first interface structure and the thermal impedance of the second interface structure are substantially equal, and the application of the reset pulse wave is caused in the active region of the memory element away from the first-interface structure and the second interface structure. One phase changes. In the following embodiments, the structure of the present invention will be disclosed in detail. The scope of the invention to be protected is not limited to the scope of the invention, and the scope of the appended claims will be limited. In addition, in order to make the embodiment, features, appearance and advantages of the present invention more obvious and easy to understand, the following is a detailed description of the embodiments, the accompanying drawings, and the appended claims. The following is a description of the present invention. The following description refers to the accompanying drawings 2 to 13 and the unnecessary elements are omitted in the drawings, and the technical points of the present invention are clearly shown. Referring to Figure 2, there is shown a cross-sectional view of a memory cell « in accordance with the present invention. The memory cell includes a memory element 210 comprised of a memory material. The memory element 210 has an active area 22〇 that is spaced apart from a first interface structure 230 and a second interface structure 24〇. The device 210 is electrically coupled to the first interface structure 23A, and is electrically and thermally coupled to the second interface structure 240. A dielectric material 265 surrounds the memory element 210 for providing thermal insulation to the memory element 21, the first interface structure 230 and the second interface structure 24A. The memory element 21 is a columnar body having a circular, oval, square or other shaped cross section. 15 200926177 The first interface structure 230 includes a first conductive member 232 and a contact region 234 of the memory material of the first conductive member 232 that contacts the memory element 210. The first interface structure 230 is also electrically and thermally coupled to the access circuit 282. Access circuit 282 includes a conductive post 250 and an isolation element 275. The first conductive member 232 is also a cylindrical body having a cross section that conforms to the memory material 210. Isolation element 275 includes a word line 280 as a gate, two doped regions 272 and 274 in substrate 270, and a power line 285 in contact with doped region 274. Conductive post 250 is in contact with doped region 272 of isolation element 275 and extends through dielectric pad layer 266 to contact first conductive member 232. The second interface structure 240 includes a second conductive member 242 and a contact region 244 of the memory material of the second conductive member 242 that contacts the memory material 210. The second interface structure 240 is also electrically and thermally coupled to the bit line structure 290. The bit line structure 290 includes a conductive pillar 260 and a bit line 295. The conductive pillar 260 is in contact with the word line 295 and the second conductive member 242. The second transmission member 242 is also a cylindrical body having a cross section that conforms to the memory material 210. The word line 280 and the power line 285 extend parallel to each other in the direction perpendicular to the cross section of Fig. 2, and the bit line 295 extends in the direction parallel to the cross section of Fig. 2. During the reset period of the memory cell 200, the bias circuit applies a reset pulse wave pre-access circuit 282 having a pulse length and a bit line structure 290. The reset pulse-induced current is from the first interface. The structure 130 flows to the second interface structure 140 via the memory element 16 200926177 110 or flows from the second interface structure 140 via the memory element 110 to the first interface structure 130 in an opposite direction (wherein the bias circuit is, for example, the 12th Figure bias voltage source and bias circuit current source 1255). When the current passes through the first and second interface structures 230 and 240 and the memory element 210, the active area 220 of the memory element 210 is heated faster than the rest of the memory element 210. The reset pulse should be at least sufficient to raise the temperature of the active zone 220 beyond the phase transfer (crystallization) temperature Tx of the memory material and also exceed the melting point Tm of the memory material such that at least the active zone 220 becomes liquid. After the active region 220 becomes liquid, the resetting of the pulse wave is terminated, and the active region 220 is cooled from the melting point Tm to a temperature lower than the phase transition temperature Tx, whereby the active region 220 is stabilized in an amorphous phase. The thermal impedance between the first interface structure 230 between the memory element 210 and the access circuit 282 and the thermal impedance of the second interface structure 240 between the memory element 210 and the bit line structure 290 will be further described below with reference to FIG. The effect on the position of the active area 220 of the memory element 210 is formed. © Please refer to Figure 3, which shows a schematic diagram of the thermal circuit of the memory cell of Figure 2. Memory element 210, first interface structure 230, second interface structure 240, access circuit 282, and bit line structure 290, as shown in FIG. 3, each represent a thermal impedance. Each thermal impedance includes a thermal resistor and a thermal capacitor in parallel therewith. The thermal resistance set forth herein is a unit of measurement that represents the ability of an element to block heat from passing through the element itself. Thermal capacitance is also a unit of measurement that represents the ability of a component to accumulate heat. For a component thermal resistance and thermal capacitance 17 200926177, it depends on many kinds of variables, such as the characteristics of the material, the shape of the component, and the size of the contact area and the characteristics of the contact area, which will affect the component and phase. Heat flow between adjacent components. The thermal impedance of the access circuit 282 and the bit line structure 290 includes a relatively large thermal capacitance that causes the temperature of the access circuit and the bit line structure to change during temperature during the reset period with the temperature of the active region of the memory element. In contrast, the system remains relatively unchanged. ❹ Since the temperature of the access circuit 282 and the bit line structure 292 remains relatively unchanged during the reset period, the first interface structure 23 and the second interface structure 240 affect the memory element 21 () during reset Heating and cooling. Therefore, the position of the active area 220 is affected by the first interface structure 23 〇 and the second interface structure 24 。. Wherein, if the first interface structure 2 and the second interface structure are said to have substantially the same thermal impedance, the active region 220 can be separated away from the first interface structure 23A and the second interface structure. ❹ Referring again to FIG. 2, since the first interface structure 23〇 and the second interface junction 240 are symmetrical (mirror) structures on the solid shell, the first conductive member 232 and the second conductive member 242 of the same material are: The first conductive member 232 and the second conductive member 24l=2 of the same width 251, the first conductive member 232 of the mtu 31 and the second conductive member are substantially the same contact regions 234 and 244. Therefore, the flute-interface structure 230 is in phase with the first-order boundary, and the thermal impedance of the interface structure 240 is substantially and preferably, the conductive pillars 25〇 and 26〇 are 261 in width, and The real 4x negative is the same as the 260 flute. Therefore, the contact characteristics between the conductive pillars 250, the second interface structure 230, and the contact regions of 18 200926177 are substantially the same. Therefore, it can be seen that in the embodiment of the first and second conductive members 232 and 234 and the conductive turns 250 and 260, variations in the material width can also be utilized, and for example, aluminum or titanium nitride can be used. ) and tungsten-based materials, or even non-metallic conductive materials such as amorphous germanium. In the present embodiment, the first and second conductive members 232 and 242 are preferably titanium nitride (TiN) or nitride nitride (TaN), and the first and second columns 250 and 260 are preferably Heat resistant material such as tungsten (w). In another alternative, the first and second conductive members 232 and 242 and the conductive posts 250 and 260 may comprise titanium aluminum nitride (TiAlN) or aluminum nitride (TaAIN), or may comprise selected from Titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (A1), tantalum (Ta), copper (Cu), platinum (Pt), iridium (Ir), lanthanum (La), nickel (Ni), One or more materials of the group consisting of nitrogen (N), oxygen (〇), ruthenium (Ru), and combinations thereof. Since the first and second conductive members 230 and 240 are in full or in part in contact with the memory element 210, the first and second conductive members 230 and 240 preferably include a memory material that is compatible with the memory material 210. Material of the nature of convenience. Among them, titanium nitride (TiN) is preferably used because titanium nitride (TiN) and GST have good contact properties (this GST is a kind of memory material, and the part about GST will be detailed later). Description). Among them, titanium nitride (TiN) is a commonly used material in the semiconductor industry. [TiN] is under south temperature, such as GST phase change temperature (usually about 600~700. 〇, available A good diffusion barrier effect. In an embodiment of the invention, the memory cell 200 includes a memory element 21, which is a phase change memory material containing a chalcogenide material and other materials. Among them, chalcogen The system includes any one of four elements of oxygen (〇), sulfur (S), collision (Se), and cerium (Te) of Group VI of the periodic table. Chalcogenide includes chalcogen elements and electropositive elements or A compound of a cationic radical. A chalcogenide alloy consists of a combination of chalcogenide and other transition metal materials, and usually contains one or more elements of Group IV of the periodic table, such as germanium (Ge) and tin (Sn). For common chalcogenide alloys, including compounds containing one or more of bismuth (Sb), gallium (Ga), indium (In), and silver (Ag). Phase change materials already described in the literature, Among them, the combined gold alloy includes gallium/niobium alloy (Ga/Sb), /Incoming alloy (in/sb), indium/bismuth alloy (In/Se), recorded/hoof alloy (Sb/Te), wrong/germanium alloy (Ge/Te), wrong/recorded/bismuth alloy (Ge/Sb/ Te), indium/bismuth/niobium alloy (In/Sb/Te), gallium/code/germanium alloy (Ga/Se/Te), tantalum/record/hoof alloy (sn/sb/Te), indium/recorded/锗Alloy (In/Sb/Ge), silver/indium/bismuth/niobium alloy (Ag/In/Sb/Te), niobium/tin/bismuth/luth alloy (Ge/Sn/Sb/Te), wrong/recorded/砸/碲 alloy (Ge/Sb/Se/Te), and hoof/error/recording/sulfur alloy (Te/Ge/Sb/S). Among the 锗/锑/碲 alloy (Ge/Sb/Te) series The alloy composition that can be used is very broad, and its compositional characteristics are TeaGebSb100_(a+b). & In some embodiments of the invention, 'some impurities are doped with chalcogenide and other phase change memories. In the material, the memory element ^ electrical degree 'phase change temperature, smudge point and other properties are used. The impurity used to be doped in the compound is representative of nitrogen, dream, oxygen, celestial, tantalum nitride. , copper, silver, gold, aluminum, oxidized, bismuth, antimony oxide, 6, titanium, and titanium oxide. The technology can refer to US Patent No. '504, and the United States Patent Publication No. 2(8)5 Sichuan No. 295〇2. 20 200926177 The best 锗/record/hoof alloy (Ge/Sb/Te) has been recorded in the study. Among them, the average of cerium (Te) in the deposited material. The concentration, preferably less than 70% 'typically is less than about 60%, the general range is about 23% to 58%' and the optimum range is about 48% to 58%. The average concentration of germanium (Ge) in the deposited material should be above 5% and within the range of 8% to 30%, and should generally be kept below 50%. The optimum concentration range of germanium (Ge) is about 8% to 40%. The other major element in the alloy composition is lanthanum. The aforementioned percentage (%) is an atomic percentage, and the percentage of atoms of the constituent elements thereof is 100%. For a description, reference is made to paragraphs 10-11 of U.S. Patent No. 5,687,112 to Ovshinsky. In other studies, some specific alloys were evaluated, including Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7 (for related instructions, see journal article: Noboru Yamada, "Potential of Ge-Sb-Te Phase-Change optical Disks for High" -Data-Rate Recoding, SPIE, Vol. 3109 (1997), pp. 28-37). More generally, transition metals such as chromium (ruthenium), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures thereof, alloy materials, In combination with a bismuth/niobium/niobium alloy (Ge/Sb/Te), a phase change alloy having programmable resistance properties is formed. Specific examples of memory materials referred to in paragraphs 10-11 of U.S. Patent No. 5,687,112 to Ovshinsky, the disclosure of which is incorporated herein by reference. The phase change alloy has the ability to switch between a first structural state of the material in a substantially amorphous solid phase and a second structural state of the material in a substantially crystalline solid phase. The roughly crystalline solid phase refers to the channel region of the memory cell 200926177 (active channel region) is locally ordered. The so-called amorphous refers to a relatively irregular structure, which is arranged in a much larger arrangement than a single crystal. Therefore, the amorphous phase is characterized by a south resistance in comparison with the crystal. Crystallization refers to a relatively regular structure, which is arranged in a much more uniform arrangement. Therefore, the crystal phase has a low resistance characteristic in comparison with the amorphous phase. Within the range of completely amorphous and fully crystalline states, typical phase change materials can be electrically converted to various resolvable local ordered states. Other material properties that are affected by changes in the amorphous phase and the crystalline phase include atomic order, free electron density, and activation energy. Therefore, for a phase change material, it can be converted into a variety of different solid phases, or it can be converted into a solid phase mixed with two or more phases to provide a gray scale from completely amorphous to fully crystalline. Between, the electrical properties of the material can vary. Phase change alloys can be transformed from one phase to another by the application of electrical pulse waves. It is worth noting that a short-lived and high-amplitude pulse wave contributes to the transformation of a phase change material into a general amorphous state, and a long and low-❹ amplitude pulse wave contributes to the transformation of a phase change material into a general crystal. state. Among the short-wave and high-amplitude pulse wave energies, the high-amplitude system can destroy the bond of the crystal structure, and the short time can prevent the atoms from re-arranging to form a crystalline state. Among them, the appropriate pulse waveform can be determined empirically or in a modular manner with the characteristics of the specified phase change alloy. The phase change material disclosed hereinafter is a GST phase change material, but it should be understood by those skilled in the art that other types of phase change materials may be used in the present invention, and are not limited thereto. In this embodiment, 22 200926177 A material which is more advantageous for implementing phase change memory (PCRAM) is Ge2Sb2Te5. The more representative chalcogenide material of the present invention can be expressed as follows: GexSbyTez 'where x: y:z = 2:2:5 . The other available combinations are X between 〇5 and 5, y between 〇5 and 5, and z between 0 and 5. In the 锗/record/hoof alloy (Ge/Sb/Te), it can also be doped with nitrogen (N-), Shi Xi (Si)-, Ti (Ti-), scale (P-), and God (As-). ) or other elements. These materials can be formed by physical vapor deposition (PVD sputtering) or magnetic flux-sputtering, in which argon (Ar), nitrogen (N2), and/or A gas such as helium (He), and a chalcogenide reaction gas, and the pressure system is set to lmtorr to 100 mtorr. Also, this deposition reaction is usually carried out at room temperature. Moreover, a collimator having an aspect ratio of 1 to 5 can be utilized to improve the filling property of the film deposition. In addition, it is also possible to use a DC bias of tens to hundreds of volts to improve the filling. Alternatively, the collimator and DC bias can be used simultaneously to improve fillability. In addition, it is necessary to carry out a post-deposition annealing treatment in a vacuum or a nitrogen (N2) atmosphere to improve the crystallinity of the chalcogenide. Among them, the annealing temperature of the wandering is set in the range of 100 to 400 ° C, and the annealing time is within 30 minutes. The thickness of the chalcogenide material depends on the design of the memory cell structure. Generally, if the thickness of the chalcogenide material is greater than 8 nm, it has a phase change characteristic such that the material has at least two stable resistance states. Referring to Figure 4, there is shown a cross-sectional view of a memory cell in accordance with a second embodiment of the present invention. The memory cell 400 includes a memory element composed of a memory material. 23 200926177 The memory element has an active region 42 〇 ' this active region 42 〇 ^ is separated from a first interface structure 430 and a second interface structural cap. The memory element 41 is a columnar body, and has a circular, oval, square or other shaped cross section. 4 is similar to FIG. 2, and the difference between the two is that the first and second conductive members 232 and 242 of the second embodiment are not shown in FIG. In Fig. 4, the first interface structure 43 includes a contact region of the memory material of the conductive column 25A contacting the memory element 410. The second boundary © face structure 440 includes a contact region 444 of the material of the conductive column that contacts the memory element 41. The conductive columns 25A and 260 comprise the same material, so the contact characteristics of the contact regions 434 and 444 are substantially the same. Also, the conductive posts 250 and 260 are preferably symmetrical (mirror) structures, including conductive posts 250 and 260 that are substantially the same width 261, and substantially conductive pillars 250 and 260 of the same thickness 261. The first interface structure 430 has a thermal impedance between the memory element 410 and the access circuit 282, and the second interface structure 440 has a thermal impedance between the memory element 410 and the ❹ bit line structure 290. The two thermal impedances are substantially equal 'because the contact regions 434 and 444 of the two are substantially identical' and the contact characteristics of the contact regions 434 and 444 are substantially the same. Referring to Figure 5, there is shown a cross-sectional view of a memory cell in accordance with a third embodiment of the present invention. The memory cell 5 includes a memory element 510 composed of a memory material. The memory element 51 has an active area 52, which is separated from a first interface structure 530 and a second interface structure 540. The memory element 510 is a columnar body having a circular, oval, square, or other shape. The fifth picture is similar to the second picture, and the two do not ask for a point t. The picture 5 is not shown in the embodiment of the second embodiment. The first interface structure 530 includes a first conductive member Γ Γ and a material of the conductive member 532 that contacts the memory element 510 :::: contact region 534. The first conductive member 532 is also a cylindrical body, and the cross section of the eight-, y, and five-remembered materials 510 is matched. The second interface structure 540 includes - the second conductive member (4), and the material of the second conductive member 542 contacts the one of the memory materials of the memory element 510 contact = 44. The second conductive member 542 is also a cylindrical body having a cross-section that conforms to the memory material 510. The first interface structure 530 has a thermal impedance between the access circuit 282 and the memory element 5 (7). The second interface structure 54g has a thermal impedance between the bit line 295 and the memory 510. The two thermal impedances are substantially equal: because the first-interface structure 53A and the second interface structure are substantially symmetrical (mirror) structures, including the second 532 of the same material and the first conductive member 542. The first conductive member 532 and the second conductive member 542 are substantially the same width, and are substantially the same thickness of the first conductive member 532 and the second conductive member 542, and the same contact regions 534 and 544. The same is shown in Fig. 6 which shows the fourth embodiment of the present invention. The memory cell _ includes a memory component 610 composed of memory material. The memory element 61 has an active area 62〇, both of which are coupled to the -first interface structure 630 and a first interface: separated by a first interface structure 640 of £620. The money piece 610 is a columnar body having a cross section of 25 200926177 or other shapes. Fig. 6 is similar to Fig. 5, and the difference between the two is that the sixth and second conductors 532 and 542 of the embodiment of Fig. 5 are not shown in Fig. 6. In Fig. 6, the first interface structure (4) includes a contact area (10) of the memory material of the material of the conductive post 250 contacting the memory element 6H). The second interface structure 640 includes a contact region 644 of the memory material of the bit, line 295 that contacts the memory element 6ι. The surface of the bit line 295 and the surface of the conductive post 25A preferably comprise the same material such that the contact characteristics of the (4) coffee and the (4) crucible are substantially the same. The first interface structure 630 has a thermal impedance between the access circuit 282 and the memory element (10), and the second interface structure _ has a thermal impedance between the bit line Μ5 and the memory element 610. The two thermal impedances are substantially equal because the contact regions 634 and 644 of the two are substantially the same, and the contact characteristics of the contact regions 634 and 644 are substantially the same. Although the thermal impedance of the bit line 295 may be different from the thermal impedance of the access circuit 282, both the bit line 295 and the access circuit 282 have a relatively large thermal power, compared to the temperature of the active region of the 5 memory element. Under variation, the temperature of access circuit 282 and the temperature of bit line 295 can be kept relatively constant during the reset period. Therefore, the active area 62〇 can be separated from the first interface structure 630 and the second interface structure 640. Referring to Figure 7, there is shown a cross-sectional view of a memory cell in accordance with a fifth embodiment of the present invention. Memory cell 700 includes a memory device 710 comprised of memory material. The memory element 710 has an active area 72 〇 '. The active area 72 均 is separated from a first interface structure 730 and a second interface structure 74 26 26 200926177. The first interface structure 730 is separated from the second interface structure 740 by a dielectric pad layer 750 having a width 752. The memory element 71 includes a layer of material 780, and a portion of the layer of memory material 780 extends through the dielectric layer 750' to contact the first interface structure 730 and the second interface structure 740, and A current path (or inter-electrode path) is defined between an interface structure 730 and the second interface structure 740. The path length of the current path is the width 752 of the dielectric pad layer 750. In Fig. 7, the first interface structure 730 includes a first conductive member 732, and a contact region 734 of the material of the first conductive member 732 that contacts the memory material of the memory element 71. The second interface structure 740 includes a second conductive member 742 and a contact region 744 of the memory material of the second conductive member 742 that contacts the memory element 71. As shown in Fig. 7, located at the memory material layer 78〇 and the first conductive member
之部位。如此，對於熱流與電流之傳遞， 上方且鄰近介電墊層750 t傳遞’接觸區734與接 27 200926177 觸區744實質上係為相同的。換句話說，額外的接觸區734 尺寸對於界面結構730之熱阻抗之影響，並不顯著。 在第7圖中’介電材770係將電源線285電、熱分隔 於第二傳導件742。 * 第一界面結構730於存取電路282與記憶元件71〇之 間係具有一熱阻抗，第二界面結構74〇於位元線結構29〇 之傳導柱260與記憶元件71〇之間係具有一熱阻抗。這兩 個熱阻抗貫質上係為相等，其乃因為第一界面結構與 ❹第二界面結構740實質上係為對稱結構，係包括相同材料 之第一傳導件732與第二傳導件742、實質上係為相同厚 度795之第一傳導件732與第二傳導件742、以及實質上 係為相同的接觸區734與744。傳導柱250與260係分別 以與介電墊層750近似相等之距離796a、796b的方式， 而與第一及第二傳導件732、742接觸，藉以確保第一及 第二傳導件732、742具有實質上係為相等之熱阻抗。並 且’傳導柱250、260較佳地係為相同寬度，且為相同材 ®料，藉以使位於傳導柱250、260與第一及第二界面結構 230、240之間的接觸區係為相同，且接觸區之特性亦為相 同。因為第一傳導件732與第二傳導件742之熱傳導性、 電傳導性，係高於記憶材料層780之熱傳導性、電傳導性， 所以’作用區710之位置對於距離796a與796b之間微小 的差距’係較為遲鈍的。 請參照第8〜11圖，其繪示依照本發明第2圖實施例 之s己憶胞之製造過程的剖面圖。 28 200926177 製造過程包括下mmh 一存取電路282，此存取電路282 j 8圖所示，提供 接著，如第9圖所千 、一上表面800。 表面綱之上。此多層結構—包構^於第8圖之上 憶材料層910、一第二值 傳導層900、一記 二傳導層920係包括:同之::20:::傳導層9。〇與第 第一傳導層900氳第一值’ …氮化鈦(ΤιΝ)。且 930 . 940 〇 ”第—傳導層92G係具有相同之厚度 ❹ 然後’如第1 〇圖沉— 形成一第一傳導件二之多層結構，以 傳導件犯。其中第m相變化構件21G、以及一第二 上之第一徨道 導件232包括源自位在傳導柱250 _材㈣910 Μ _的材料’相變化構件210包括源自記 隐材枓層91 〇的姑Μ _ 層920的材料。舉例來 彳242包括源自第二傳導 於第二傳導層上ϋ 刻可以將—柱狀光阻圖案化 作A = ? 考第9圖之92〇)，並以此柱狀光阻 二’、敝物，當蝕刻完成後再將此光阻移除。 砝德接著、’如第U圖所示，形成介電層265於第10圖之 °上並形成傳導柱260。其中，係使傳導柱 260 電、 熱接觸於第二傳導件242，且延伸至介電層撕 1110。 然後，形成一位元線295於介電層265之上表面 111() ’以成為如第2圖繪示之記憶胞200。 印參照第12圖，其繪示依照本發明之一實施例之一 種集成電路的方塊圖。集成電路1200包括-記憶陣列 29 200926177 1205 ’記憶陣列1205係應用上述實施例中之記憶胞，於 記憶胞當中之界面結構具有實質上係為相等之熱阻抗。一 列解碼器（row decoder) 1210，係具有讀取、寫入、重置之 模式’並且此列解碼器1210係耦接複數條於記憶陣列12 0 5 中排列成列的子元線1215。一行解碼器（c〇iUmn decoder) 1220，係耦接複數條於記憶陣列丨205中排列成行的位元 線1225，並用以讀取、寫入、重置記憶陣列12〇5之記憶 胞。位址（address)，係藉由匯排流(bus) 126〇，而提供予列 ❹解碼器1210以及行解碼器1220。感測放大器與數據輸入 結構（sense amplifier/data-in structure) 1230，係包括用於讀 取、寫入、重置之模式的電流源，並透過數據匯排流1235 耦接於行解碼器1220。數據(data)，係從集成電路12〇〇上 之輸入/輸出口，或是從集成電路1200之其他内部或外部 之數據來源，經由數據輸入線1240，而提供予方塊123〇 中之數據輸入結構。在本實施例中，集成電路12⑼包括 其它電路1265,其它電路1265例如為可支援相變化記憶 〇胞陣列之-泛用處理器、或特殊應用用途電路、或是整合 系統功能之晶片模組。數據(Data)，係由方塊123〇中之感 測放大器，經由數據輸出線1245，而提供予集成電路 上之輸入/輸出口，或是提供予集成電路12 或外部數據目的地。 八 ^ 在本實施例中’係以偏置排 场置排列狀態機（bias arrangement state machine) 1250 你盔 k 丄， 作為—控制器，直用來控 制偏壓電路電壓/電流源1255，以勃;μ, ' M執仃偏置排列，並藉由 30 200926177 一存取控制程序，來控制字元線/電源線的操作。其中，偏 置排列包括有讀取、寫入、重置、以及字元線與位元線之 電壓與電流的驗證。此控制器可以係習用的專用邏輯電路 (special-purpose logic circuitry)，比如在另一可選擇的實施 例之中，控制器包括有一泛用處理器（general-purpose processor) ’例如是一般的集成電路，其用以執行一電腦程 式’來控制裝置操作。而在其他實施例中，控制器也可以 係專用邏輯電路與泛用處理器之結合。 ❹ 請參照第13圖，其繪示一種應用本發明實施例之記 憶胞之記憶陣列的示意圖。如第13圖所示，記憶陣列1300 包括四個記憶胞1302、1304、1306、1308，其具有各自的 吕己憶元件1312、1314、1316、1318。其中，第13圖僅繪 示一小部分之記憶陣列，對於整個記憶陣列而言，係可能 包括有上百萬個記憶胞。 在第13圖中，共同電源線132〇以及字元線1322、 1324 ’通常係沿y軸平行方向排列。位元線1326、丨328， ©通常係沿X軸平行方向排列。因此#解碼器與一字 元線驅動器1350，係耦接於字元線1322、1324，字元線 驅動器1350係具有寫入、重置、讀取之模式。位元線電 流源1352、一解碼器與感測放大器（未繪示）係耦接於位元 線1326、1328，位元線電流源1352係用以寫入、重置、 讀取。共通電源線1320係耦接於電源線終端電路1354， 比如一接地端。在一些實施例中’電源線終端電路GW 可以包括有偏壓電路、以及解碼電路。其中，偏壓電路比 31 200926177 如係電壓源及電流源。解碼電路除了接地之外，係用以施 加偏置排列予電源線。 共通電源線1320係耦接於記憶胞13〇2、13〇4、1306、 1308之電源端。字元線1322係耦接於記憶胞13〇2、13〇6 之閘極端。子元線1324係耦接於記憶胞13〇4、1308之閘 極端。 典型的§己憶胞1302、1304係分別包括有記憶元件 1312、1314，記憶胞13〇2之汲極係耦接於記憶元件1312 〇處之第-界面結構1360 ’或者是輕接於記憶元件1312處 之第二界面結構1361。同樣地，記憶胞1304之汲極係耦 接於記憶兀件1314處之第一界面結構1362，或者是耦接 於記憶元件1314處之第二界面結構1363。第二界面結構 1361、1363係耦接於位元線1326。在操作的時候，電源 線1352係操作於一低電流之讀取模式、一種或多種中電 流之寫入模式、以及一高電流之重置模式。當操作於高電 流之重置模式時，透過施加一電壓及電流予位元線η%， 〇並透過施加一足以使通道電晶體至記憶胞1320之間導通 的電壓於字元線1322及電源線132〇 ’形成一電流路徑 1380通過已選擇的記憶胞（例如為包括記憶元件1312之記 憶胞1302) ’以使電流流通電源線〖Mo。 同樣地，當操作於低電壓之讀取模式時，透過施加一 電壓及電流予位元線1326,並透過施加足以使記憶胞132〇 之通道電晶體導通的電壓於字元線1324及電源線132〇， 形成一電流路徑1382通過已選擇的記憶胞（例如為包括記 32 200926177 憶元件1314之記憶胞1304)，以使電流流至電源線1320。 當操作於寫入模式時，係利用一種或多種中電流之位 準，開啟一通道電晶體，其中操作係與讀取模式的敘述相 似0 综上所述，雖然本發明已以較佳實施例揭露如上，然 其並非用以限定本發明。本發明所屬技術領域中具有通常 知識者，在不脫離本發明之精神和範圍内，當可作各種之 更動與潤飾。因此，本發明之保護範圍當視後附之申請專 ❹利範圍所界定者為準。The part. Thus, for heat flow and current transfer, the upper and adjacent dielectric pad 750 t pass 'contact zone 734 and connect 27 200926177 contact zone 744 are substantially identical. In other words, the effect of the additional contact area 734 size on the thermal impedance of the interface structure 730 is not significant. In Fig. 7, the dielectric 770 electrically and thermally separates the power line 285 from the second conductive member 742. The first interface structure 730 has a thermal impedance between the access circuit 282 and the memory element 71?, and the second interface structure 74 has a conductive column 260 between the bit line structure 29 and the memory element 71? A thermal impedance. The two thermal impedances are equal in quality, because the first interface structure and the second interface structure 740 are substantially symmetric structures, including the first conductive member 732 and the second conductive member 742 of the same material. The first conductive member 732 and the second conductive member 742 of substantially the same thickness 795 are substantially the same contact regions 734 and 744. The conductive posts 250 and 260 are in contact with the first and second conductive members 732, 742, respectively, in a manner approximately equal to the distance 796a, 796b of the dielectric pad layer 750, thereby ensuring the first and second conductive members 732, 742. There is a thermal impedance that is substantially equal. And the 'conducting posts 250, 260 are preferably of the same width and are of the same material, whereby the contact areas between the conductive posts 250, 260 and the first and second interface structures 230, 240 are the same, And the characteristics of the contact area are also the same. Because the thermal conductivity and electrical conductivity of the first conductive member 732 and the second conductive member 742 are higher than the thermal conductivity and electrical conductivity of the memory material layer 780, the position of the active region 710 is small between the distances 796a and 796b. The gap 'is slower. Referring to Figures 8 to 11, there are shown cross-sectional views showing the manufacturing process of the memory cell according to the embodiment of Fig. 2 of the present invention. 28 200926177 The manufacturing process includes a lower mmh-access circuit 282, which is shown in FIG. 9 and provides an upper surface 800 as shown in FIG. Above the surface. The multi-layer structure - the cladding structure is shown in Fig. 8. The material layer 910, the second value conducting layer 900, and the second conducting layer 920 comprise: the same:: 20::: conductive layer 9. And the first conductive layer 900 has a first value of ... titanium nitride (ΤιΝ). And the 930. 940" first-conducting layer 92G has the same thickness ❹ and then 'as shown in FIG. 1' to form a multilayer structure of the first conductive member 2, which is exemplified by the conductive member. The m-th phase changing member 21G, And a second upper rail guide 232 includes a material 'phase change member 210 derived from the conductive pillar 250 _ material (four) 910 Μ _ including the austenitic layer 920 from the recording material layer 91 〇 For example, the 彳242 includes from the second conduction on the second conductive layer, and the columnar photoresist can be patterned as A = ? (9), and the columnar photoresist ', sputum, remove the photoresist after the etching is completed. 砝德, 'As shown in Figure U, the dielectric layer 265 is formed on the 10th and forms a conductive column 260. The conductive post 260 is electrically and thermally contacted to the second conductive member 242 and extends to the dielectric layer tear 1110. Then, a bit line 295 is formed on the upper surface 111() of the dielectric layer 265 to become the second image. Illustrated memory cell 200. Referring to Figure 12, a block diagram of an integrated circuit in accordance with one embodiment of the present invention is shown. The integrated circuit 1200 includes a memory array 29 200926177 1205 'The memory array 1205 is a memory cell in the above embodiment, and the interface structure in the memory cell has substantially equal thermal impedance. A row decoder 1210, There is a mode of reading, writing, and resetting' and the column decoder 1210 is coupled to a plurality of sub-line 1215 arranged in a column in the memory array 1200. A row of decoders (c〇iUmn decoder) 1220 The plurality of bit lines 1225 arranged in a row in the memory array 205 are coupled to the memory cells of the memory array 12〇5. The address is addressed by the bus. A bus 126 is provided to the column decoder 1210 and the row decoder 1220. The sense amplifier/data-in structure 1230 is included for reading, writing, and weighting. The current source of the mode is coupled to the row decoder 1220 through the data sink 1235. The data is from the input/output port on the integrated circuit 12 or from other internal circuits of the integrated circuit 1200. Or external data The source is provided to the data input structure in block 123 by data input line 1240. In the present embodiment, integrated circuit 12 (9) includes other circuits 1265, such as a phase-capable memory cell array. Using a processor, or a special application circuit, or a chip module that integrates system functions. Data is provided by the sense amplifier in block 123, via data output line 1245, to the input on the integrated circuit. / Output port, or provided to the integrated circuit 12 or external data destination.八^ In this embodiment, 'bias arrangement state machine 1250, your helmet k 丄, as a controller, used to control the bias circuit voltage / current source 1255, to Bo ;μ, ' M stubs are arranged in an offset, and the operation of the word line/power line is controlled by an access control program of 30 200926177. Among them, the bias arrangement includes reading, writing, resetting, and verification of the voltage and current of the word line and the bit line. The controller may be a conventional-purpose logic circuitry, such as in another alternative embodiment, the controller includes a general-purpose processor 'for example, a general integration A circuit for executing a computer program' to control device operation. In other embodiments, the controller can also be a combination of dedicated logic and a general purpose processor. ❹ Referring to Fig. 13, there is shown a schematic diagram of a memory array of a memory cell to which an embodiment of the present invention is applied. As shown in Fig. 13, the memory array 1300 includes four memory cells 1302, 1304, 1306, 1308 having respective suffix elements 1312, 1314, 1316, 1318. Of these, Figure 13 shows only a small portion of the memory array, which may include millions of memory cells for the entire memory array. In Fig. 13, the common power supply line 132A and the word lines 1322, 1324' are generally arranged in the y-axis parallel direction. The bit lines 1326, 丨328, and © are usually arranged in parallel directions along the X axis. Therefore, the # decoder and the word line driver 1350 are coupled to the word lines 1322 and 1324, and the word line driver 1350 has a mode of writing, resetting, and reading. A bit line current source 1352, a decoder and a sense amplifier (not shown) are coupled to the bit lines 1326, 1328, and the bit line current source 1352 is used for writing, resetting, and reading. The common power line 1320 is coupled to the power line termination circuit 1354, such as a ground. In some embodiments, the power line termination circuit GW may include a bias circuit and a decoding circuit. Among them, the bias circuit is a voltage source and a current source than 31 200926177. In addition to grounding, the decoding circuit is used to apply an offset to the power line. The common power line 1320 is coupled to the power terminals of the memory cells 13〇2, 13〇4, 1306, and 1308. The word line 1322 is coupled to the gate terminals of the memory cells 13〇2, 13〇6. The sub-element 1324 is coupled to the gate terminals of the memory cells 13〇4, 1308. The typical § MSC1, 1304, respectively, includes memory elements 1312, 1314, the drain of the memory cell 13 〇 2 is coupled to the first interface structure 1360 ' at the memory element 1312 或者 or is lightly connected to the memory element A second interface structure 1361 at 1312. Similarly, the drain of the memory cell 1304 is coupled to the first interface structure 1362 at the memory element 1314 or to the second interface structure 1363 at the memory element 1314. The second interface structure 1361, 1363 is coupled to the bit line 1326. In operation, power line 1352 operates in a low current read mode, one or more medium current write modes, and a high current reset mode. When operating in the high current reset mode, a voltage and current are applied to the bit line η%, and a voltage sufficient to turn the channel transistor to the memory cell 1320 is applied to the word line 1322 and the power source. Line 132'' forms a current path 1380 through the selected memory cell (e.g., memory cell 1302 including memory element 1312) to cause current to flow through the power line Mo. Similarly, when operating in the low voltage read mode, a voltage and current are applied to the bit line 1326, and a voltage sufficient to turn on the channel transistor of the memory cell 132 is applied to the word line 1324 and the power line. 132A, a current path 1382 is formed through the selected memory cell (e.g., memory cell 1304 including memory element 1314) to cause current to flow to power line 1320. When operating in the write mode, a channel transistor is turned on using one or more levels of current, wherein the operating system is similar to the description of the read mode. In summary, although the present invention has been described in a preferred embodiment As disclosed above, it is not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
33 200926177 【圖式簡單說明】 弟1圖繪示習知技藝中一種記憶胞之部分的剖面圖。 第2圖繪示依照本發明一實施例之記憶胞的剖面圖。 第3圖繪示第2圖之記憶胞之等熱電路的示意圖。 第4圖繪示繪示依照本發明第二實施例之記憶胞的 剖面圖。 第5圖繪示依照本發明第三實施例之記憶胞的剖面 圖。 ❹ 第6圖繪示依照本發明第四實施例之記憶胞的剖面 圖。 第7圖繪示依照本發明第五實施例之記憶胞的剖面 圖。 第8-11圖繪示依照本發明第2圖實施例之記憶胞之 製造過程的剖面圖。 第12圖繪示依照本發明之一實施例之一種集成電路 的方塊圖。 ^ 第13圖繪示一種應用本發明實施例之記憶胞之記憶 陣列的示意圖。 【主要元件符號說明】 100、200、400、500、600、700 :記憶胞 110、210、410、510、610、710 :記憶元件 120、220、420、520、620、720 :作用區 130、230、430、530、630、730 :第一界面結構 34 200926177 732 :第一傳導件 534、634、734 :接觸區 540、640、740 :第二界面結構 742 :第二傳導件 544、644、744 :接觸區 介電材33 200926177 [Simple Description of the Drawings] Figure 1 shows a cross-sectional view of a portion of a memory cell in the prior art. 2 is a cross-sectional view of a memory cell in accordance with an embodiment of the present invention. Fig. 3 is a schematic view showing the thermal circuit of the memory cell of Fig. 2. Fig. 4 is a cross-sectional view showing a memory cell in accordance with a second embodiment of the present invention. Fig. 5 is a cross-sectional view showing a memory cell in accordance with a third embodiment of the present invention. Figure 6 is a cross-sectional view showing a memory cell in accordance with a fourth embodiment of the present invention. Figure 7 is a cross-sectional view showing a memory cell in accordance with a fifth embodiment of the present invention. 8-11 are cross-sectional views showing the manufacturing process of the memory cell in accordance with the embodiment of Fig. 2 of the present invention. Figure 12 is a block diagram of an integrated circuit in accordance with an embodiment of the present invention. ^ Figure 13 is a diagram showing a memory array of a memory cell to which an embodiment of the present invention is applied. [Main component symbol description] 100, 200, 400, 500, 600, 700: memory cells 110, 210, 410, 510, 610, 710: memory elements 120, 220, 420, 520, 620, 720: active area 130, 230, 430, 530, 630, 730: first interface structure 34 200926177 732: first conductive members 534, 634, 734: contact regions 540, 640, 740: second interface structure 742: second conductive members 544, 644, 744: Contact area dielectric
231、531 :厚度 250 :傳導柱 251、551 :寬度 260 :傳導柱 261 :寬度 262 :厚度 266、750 :介電墊層 270 :基材 272 :摻雜區 274 :摻雜區231, 531: thickness 250: conductive column 251, 551: width 260: conductive column 261: width 262: thickness 266, 750: dielectric underlayer 270: substrate 272: doped region 274: doped region
132 、 232 、 532 、 134 、 234 、 434 、 140 、 240 、 440 、 142 > 242 ' 542 > 144 、 244 、 444 、 165 、 265 、 770 : 275 :隔離元件 280 :字元線 282 :存取電路 285 :電源線 290 :位元線結構 295 :位元線 752 :寬度 780 :記憶材料層 35 200926177 795 :厚度 796a、796b :距離 800、1110 :上表面 900 :第一傳導層 910 :憶材料層 920 :第二傳導層 930、940 :厚度 1200 :集成電路 ❹ 1205:記憶陣列 1210 :列解碼器 1215、1225 :字元線 1220 :行解碼器 1230 :感測放大器/數據輸入結構 1235 :數據匯排流 1240 :數據輸入線 1245 :數據輸出線 〇 1250 :偏置排列狀態機 1255 :偏壓電路電壓/電流源 1260 :匯排流 1265 :其它電路 1300 :記憶陣列 1302、1304、1306、1308 :記憶胞 1312、1314、1316、1318 :記憶元件 1320 :共同電源線 36 200926177 1322、1324 :字元線 1326、1328 :位元線 1350 :字元線驅動器 1352 :位元線電流源 1354 :電源線終端電路 1360、 1362 :第一界面結構 1361、 1363 :第二界面結構 1380、1382 :電流路徑132, 232, 532, 134, 234, 434, 140, 240, 440, 142 > 242 ' 542 > 144, 244, 444, 165, 265, 770: 275: isolation element 280: word line 282: Take circuit 285: power line 290: bit line structure 295: bit line 752: width 780: memory material layer 35 200926177 795: thickness 796a, 796b: distance 800, 1110: upper surface 900: first conductive layer 910: Material layer 920: second conductive layer 930, 940: thickness 1200: integrated circuit ❹ 1205: memory array 1210: column decoder 1215, 1225: word line 1220: row decoder 1230: sense amplifier / data input structure 1235: Data sink drain 1240: data input line 1245: data output line 〇 1250: offset alignment state machine 1255: bias circuit voltage / current source 1260: sink stream 1265: other circuit 1300: memory array 1302, 1304, 1306 1308: memory cells 1312, 1314, 1316, 1318: memory component 1320: common power line 36 200926177 1322, 1324: word line 1326, 1328: bit line 1350: word line driver 1352: bit line current source 1354 : Power line termination circuit 1360, 1362 : First interface structure 1361, 1363: Second interface structure 1380, 1382: Current path
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