TW200925825A - Method of balancing path delay of clock tree in integrated circuit (IC) layout - Google Patents

Abstract

A method of balancing the path delay of a clock tree for minimizing clock skew of the clock tree in the IC layouts is described. The method includes the following steps: (a) A design tool calculates a plurality of path delay values from the root cell to each sink via some of the inverters, wherein the maximum one of the path delay values recorded on the sinks serves as a target value, respectively; (b) The design tool compares the path delay value of each sink with the delay value of the adjacent sink from each sink to the root cell for recording the compared higher value on each inverter until the higher compared values are recorded, respectively, in the inverters and the root cell; (c) The design tool compares the path delay value on each inverter with the target value from the root cell to the sinks to determine whether to change the cell type of the inverter from a current cell type to a new cell type by selecting the new cell type from the type database; (d) The design tool adds the difference value to the original value for updating the original value recorded in this inverter; and (e) The design tool adds the difference value to the values recorded on the downstream inverters relative to the inverter for repeatedly updating the values recorded on the downstream inverters and sinks to minimize the clock skew of the clock tree.

Description

200925825 IX. Description of the invention: 'The technical field of the invention belongs to the same'. The present invention is a method for designing a _------------------------------------------------------------------------------------------- A method of balancing the amount of time delay to effectively minimize the clock skew of the clock tree structure. [Prior Art] The Japanese Temple signal is a very important control signal in the digital system, mainly to synchronize the data signal of the signal path of the clock tree (4). In order to achieve a better execution scale for the digital system, the word _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The time of the target component is almost the same, in accordance with the requirements of the clock design specification of the integrated circuit, wherein the time of the arrival of the clock signal to each component is not _offset, and the destination component is, for example, a register ( Register) or the flip-flop (out (four) 叩). Fine, in the process of performing clock tree structure synthesis (cl〇ck_柳如也, cts), it is not easy _ clock design specifications, especially In high-speed (or high-frequency) digital systems, it is even more difficult to design. Even if the cts-structure synthesis (cts) design tool performs clock-like transitions, the _ shifter Qian Laifan, the implementation of riding fruit will be worse', such as the time offset in the physical synthesis design tool for detailed age (such as after the coffee and coffee (four) steps will also be worse' detailed ton line steps are mainly for the clock tree structure components Connection line (four), " his magnetic connection line. Due to the winding layout pattern (four) (four) to In the meantime, the difference between the surface and the capacitance value of the gate}}, the time delay of the path of each clock-like path in the clock tree structure (four) delay becomes more difficult to correct (Qian Yu et __ shift is not easy Minimizing 200925825 or 疋 correction. Therefore, it is necessary to develop a new design method to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a path time delay amount in a clock tree structure of an integrated circuit design. The balancing method is mainly to minimize the clock offset of the clock tree structure by adjusting the type of the element in the clock structure. The present invention is also directed to providing a kind of pro The method of designing the balance of the inter-turn delay between the clock and the Wei-junction path is such that the setting of the component and the result of the detailed winding remain unchanged after the execution of the process of synchronizing the tree structure. For the above purposes, The invention proposes a method for balancing the path time delay amount in the clock tree structure of the touch circuit design, which mainly comprises the following steps: (4) Establishing a clock tree structure by using a CTS tool. (9) Using an anus Calculate the path delay value of the inverter from the root component to each of the end-point components, where the largest of the duty time delay values recorded in the endpoint component is the target path delay value. C) From the hand of each end element recording component, the tool will compare the path time delay value of each end element with the path time delay value of the adjacent end element, and compare the resulting higher path. The time delay value is recorded in the upstream component until all the higher path time delay values are recorded in the inverter and the root component respectively. (4) From the root element, the light axis end element of the smart towel, the anus will turn the inverter The path time delay value is compared with the target path delay value, and is used to determine whether to change to the _inverted (four) cake surface by selecting the -new element _ ' of the component type database towel to replace the inverter starting from the original 7 200925825 The component type. When comparing the path time delay value of each inverter benefit with the target path

(4) When comparing the path time delay value of each inverter with the target path delay value, if the value of the path avoidance value is recorded, if the path time delay value of the component type of the inverter from the inverter is smaller than the target The path delay value, the previous component type is changed to the new component type. © (7) The design tool Wei calculates the component _ delay amount of the inverter with the new component _. (g) The design tool adds the difference to the path time delay value of the original inverter component type, to update the original component type's 3^ time delay value, where the difference is defined as the new component of the inverter The difference between the time delay value and the original component time delay value. When the updated path time delay value is equal to or close to the target path delay value, it indicates that the change in the component type of the inverter is acceptable. In contrast, when the updated path time delay value is greater than the target path delay value, the changed component type is ignored and the original component type is still used. When the component type of an inverter is changed, the s-free tool adds the difference to the path time delay value recorded by the inverter downstream of the inverter in the tree branch. (h) the design tool adds the difference to the path time delay value recorded in the inverter downstream of the inverter to repeatedly update the path time delay value recorded on the downstream inverter and the end element to Minimize the clock offset of the clock tree structure. (i) When comparing the path time delay value of each inverter with the target path delay value, if the path time delay value recorded in the inverter is greater than the target path delay value, the design tool uses the original 8 200925825 component type, And returning to step (d), the next inverter is compared with the target path delay value. In an embodiment of the invention, the design tool allows the path delay values recorded in each of the inverters and the destination elements to contiguous with each other. In the preferred embodiment, the tool adjustment adjustments are recorded in the inverters. The path delay value to approximate the target path delay value. In an embodiment, the design tool adjusts the path delay value by changing the inverted component time delay value. For example, during the execution of Clock Tree Structure Synthesis (CTS), the design tool first uses the © 7G class with zero output load. Then, after performing the clock tree structure synthesis (CTS) and the winding (_(4) program, the present invention adjusts the component time delay value by increasing the output load so that the path delay value recorded in the inverter is equal to or close to The target pinch delay value. Even after the component type is changed, the result of setting the m-winding of the component remains unchanged after the execution of the clock tree synthesis (cts) procedure.

Use the Clock Tree Structure Synthesis (CTS) tool to insert additional components (9) such as inverters or buffers into the root component (thus (4)) when performing a Clock Tree Synthesis (CTS) program and Between the complex number of sinks (sinks), to adjust the tree branch to reveal the path between the components (4) recorded in the component, the scale-protected clock tree structure reproducibly transmits the clock pulse from the root component to each point Component, suppressing the offset of the material pulse (Ms (4) is minimized. After the cts tool completes the CTS program to generate the clock tree structure, the design tool will execute the message = connection execution _ sequence., _ oyster __ (four) structure In the pulse offset, the amount of time delay between each tree branch in the day-to-day reading structure becomes larger and smaller. Therefore, the calculation of ___ will shift with the clock of __ 2009 200925 This is a big deal that makes the entanglement shift. This (four) akisaki adjusts (for example, fine-tunes) the clock offset by changing the _ of the component after the cts program and the wrap-line program, and by means of the component type data. Pe database) different component types but with the same area and very similar component layout, Provided Laid elements, and the detailed results of the same age. That is, changing or adjusting the component type to balance the path time delay of the clock tree structure to improve the clock offset to meet the requirements of the clock offset, avoiding the component setting and details. The step of winding. The above contents of the "scale" can be more specific, and the following is a detailed description of the preferred embodiment, and is described in detail with reference to the following drawings: [Embodiment] The present invention provides a hybrid structure of a frequency sharp design (dQek (4) The method of balancing the amount of time delay is mainly to adjust the type of the element in the clock tree structure (listening e) to effectively make the clock offset of the clock tree structure (d〇ck skew). In addition, the present invention provides a method for balancing the path time delay amount of the clock tree structure in the integrated circuit design, so that the placement of the components and the result of the detailed winding are performed in the clock tree structure. The program of synthesis (CTS) remains unchanged. When executing the program of clock tree structure synthesis (cts), each element (cell) is set between the root element and the plurality of destinations (sinks). For example, inverters have the same area, input capacitance, and output load (output 1〇ading). Then, the 'integrated circuit design tool uses the present invention to perform path time delay. Amount of flat In the method of balancing, each element between the root element and the plurality of end-point elements has the same area 200925825 and has no load. Performing this day's grazing tree, setting the buckle from the component class - the frequency of the database The component_, and the selection of the component type. Instead of the original component_, the component_ to update the component ei-delay I (eeU delay) of the inverter in the clock-length structure, the technical field has the usual It should be noted by the knowledge that the various non-element types have their output loads, and the component_ is associated with the cell delay. FIG. 1 is a schematic diagram of a clock tree structure constructed by a design tool of a clock-integrated structure (CTS) according to an embodiment of the present invention. The clock tree structure synthesis (cts) design tool constructs a B-tree-like structure, which includes a root element, a plurality of clock inverters, a plurality of terminal elements, and a component at the root element. A complex signal connection line between the pulse inverter and the scale element. The root component is labeled R〇, and the complex clock inverters are labeled as

Cll, C12, C21, C22, C23, C24, C31, C32, C33, C34, C41, C42, C43, C44, C51, C52, C53, C54, C55, C56, C57 and C58, multiple end points are marked separately For S1 ~ S16. The root element receives a clock signal and transmits the clock signal to the downstream destination elements (S1 to S16) via the 5 Hz inverter (Cl 1 to C58), and the root element is placed at the L0 level. Inverter Cl 1 and inverter C12 are set at L1 level, inverters C21, C22, C23, C24 are set at L2 level, inverters C31, C32, C33, C34 are set at L3 level, inverter C41, C42, C43, and C44 are set at the L4 level, inverters C51, C52, C53, C54, C55, C56, C57, and C58 are set at the L5 level, and the complex destination elements (S1 to S16) are set at the L6 level. The path time delay (pathdelay) from the root element R〇 to each of the 200925825 end elements (S1 to S16) is calculated using a clock tree structure synthesis (CTS) design tool. In a preferred embodiment, the SDF file contents generated by the static timing analysis (STA) tool are used to calculate the path time delay amount of the root element R〇 to each of the end elements (S1 to S16), respectively, and A path time delay amount is recorded in each of the end point elements (S1 to S16). In the clock tree structure, each path time delay amount corresponding to each of the end point elements (S1 to S16) respectively represents a portion from the root element R〇 passing through a part of the inverters (C11 to C58) to reach each end point. The time delay value of the components (S1 to S16). For example, the time delay values of the end elements (S1 to S16) are respectively recorded as the end points of the elements S1 (60), S2 (50), S3 (4 〇), S4 (50), S5 (60), S6 (70). ), S7 (60), S8 (40), S9 (40), S10 (50), S11 (40) ' S12 (60), S13 (70), S14 (80), S15 (80), and S16 (90) In the example of the vehicle, the path time delay value in the brackets marked by each end element is the time unit, and the clock offset (ci〇ck Skew) is defined as the largest path. The difference between the time delay value and the minimum path time delay value. In this embodiment, the clock offset is 5 〇, that is, the end element S16 (90) and the end element S3 (4 〇), The difference between -S of S8 (40), S9 (40), and S11 (40). In the embodiment, the balancing method of the present invention may also specify that the maximum path time delay value of the destination element si6 (four) is the target path delay value (target vaiue). Referring to FIG. 1 and FIG. 2', FIG. 2 is a schematic diagram of a clock tree structure according to an embodiment of the present invention, which uses a design tool to compare a path delay value with another path delay value adjacent to the same level and The axis records the value of each of the two roads with a larger value of the delay value in the inverter of the different level. Returning from the lowest level of the L6 level to the previous _ ^ level, setting the value of the tool comparison-end point component's miscellaneous time delay value to the path time delay value of the adjacent other end point element, and delaying the larger path time The value is recorded in the end element 12 200925825 in the order. Then the 'design tool compares the magnitude between the time delay value recorded by an inverter in the L5 level and the path time delay value of the adjacent inverter until the larger path is compared in the L5 level to the L1 level. The time delay value is sequentially recorded in the inverter from the L5 level to the L1 level, and the larger path time delay value is sequentially recorded in the arrow direction 200 shown in FIG. The final design tool selects the larger path time delay value recorded by the inverter in the L1 level and records the larger path time delay value at the root element R〇 of the L〇 level. From L5 level to L1 level, inverters cu, C12, (3), C22, (2), C24, (3),

The path time delay values recorded by C32, C33, C34, C41, C42 'C43, C44, C51, C52, C53, C54, C55, C56, C57 and C58 are denoted as vu, V12, V2^V22, V23, V24, respectively. V3 Bu V32, V33, V34, V4 Bu V42, V43, V44, V52, V53 V54 V55 'V56, V57 and V58' and record the root element R〇 of the l〇 step. The path time delay values (V11 to VS8 and VQ) recorded in the inversions ^(3) to (10) and the root elements respectively indicate that there is a large path time delay between the paths through the inverters cn to (3) and the root element R? That is, the path from the root element R0 to the end element S1 and the other path from the root element RQ to the end element phantom are selected by the inversion Θ(3)' of the level, and the mixed time delay values of the two paths are selected and The larger road 彳 峨 峨 峨 咖 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Hidden, from the root element (4) through (3) to the end point to w, S2 - Lu Xin and Na part of the element through the inverter «2 to reach the end point to S3, Hong's other path through the μ level of the inverter (9) After the iron, the two views _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The larger of C52, the rest of the path and so on. From the root element R〇 through the inverting 'C11, C21, C22, C31, C32, C4, C42, C5, C52, C53 and C54 to a path of the end elements S1 to S8 and from the root element R〇 through the inverter C12, C23, C24, C33, C34, C43, C44, C55, C56, C57, and C58 The other path to the end elements S1 to S8 passes through the root element R0 of the L0 level, and then the larger between the two paths is selected. The path time delay value is recorded, and the larger path time delay value is recorded in the root element R〇©, and the selected larger path time delay value is the larger of the inverters C11 and C12 in the L1 level. For example, the design tool compares the endpoint element S1 (6〇) with the endpoint element S2 (5〇) and specifies a larger si(6〇) for the inverse ϋ CM ' s. The path time delay value (60) is There is a larger path time delay value in the path through the inverter C51, and the path time delay value (10) is recorded in the inverter C51. Similarly, the design tool compares the end elements S3 S S16 to select a larger path time delay value 'and records these larger path_delay values in the inversions of the u-levels C52 to C58, respectively, and the remaining paths are Such a push until the design tool compares the inverse phase benefit CU (7〇) and the inverter Cl2 (9〇) of the u-order to produce a larger path time delay value (4) and is recorded in the root element R0 of the L0 level. Therefore, in the clock tree structure, the delay value 90 (v〇) between the paths (4) of the root element R0 recorded in the level is a larger path time delay value in the path through the root element R〇. In general, the path time delay includes the component time delay (4) coffee plus connection time delay f (azhou ay), its towel element depends on the navigation device (four) and the output 14 200925825 load, and the tree tree When the component's component setting (pkcement) and its size have not changed, the connection line time delay remains unchanged. According to the above, the design tool compares a path time delay value with another adjacent path time delay value' and sequentially records the larger path time delay value to an inverter command of a different level to display the inverter and the path time. The state between the delay values. As shown in Fig. 2, the design tool finds the maximum path time delay value among these end elements, that is, the end point element S16 (90), and sets the maximum path time delay value (9 〇) as the target © path delay. I rget value). If the direction of the arrow shown in Fig. 3A_3c is from the U level to the L5 level, then the design tool compares the path time delay value of the inverters (3) to (10) recorded in each order called 7) with the target path delay value, As shown in Figure 3A_3c. Figure 3A is a schematic diagram of a clock tree structure in accordance with an embodiment of the present invention, using a design tool to compare path delay values and - target path delay values for each of the records recorded in L1 bit_inverted n. When the path delay value recorded in the inverter is less than the target path delay value, the design tool replaces the component type of the original inverter by the new component type in the selected component type database 3〇2. The design tool then recalculates the component time delay (four) delay of the inverter with the new component type, and delays the component time delay between the new component type and the original inverter component type. The difference DDiff is added to the component inter-turn delay of the original inverter element face to update the component time delay amount of the original component type. The new component type is available for use when the updated time delay amount recorded in the inverter is equal to or close to the target path delay value. Conversely, if the updated component time delay recorded in the inverse (4) exceeds the target path delay value, the new component type is ignored and the original component class 15 200925825 is used. After updating the county (four) pieces _ for the new supplement _, the design q will be recorded in the delay value of the phase value of the phase device. In an embodiment of the invention, changing the upstream inversion "元件" element type will have an effect on the downstream delay value, such as the path delay value. It should be noted that in order to simplify the τ sequence read noise, when changing the upstream After the element type of the reverse ohm, according to the direction of the transmission of the clock α Κ, the amount of time delay of each inverter and each component occupying the component itself in the tree structure below the upstream inverter _ (4) Set to maintain the same value. For example, as shown in Figure 2 and Figure 3A, the path delay value of the signal recorded in the inverter is 70 as shown in Figure 2, and the target path delay value is 9〇. Because the path delay value 70 of the inverter (3) is less than the target path delay value of 9 〇, the design tool selects a new component type from the component type database (to listen to e database) 302 to change the component type of the reverse paste cu. The design tool recalculates the component time delay amount of the simplified component class (3), and adds the difference 20 between the amount of time delay of the new component type and the component time delay of the original inverter component type to Original inverter component The component has a time delay of 7 〇 to update the original component type of the inverter C11 with a time delay of 9 〇. When changing the upstream component of the inverter cii, the difference will be to the downstream inverter. The path delay values recorded by C2, C22, C3, C32, C41, CM2, C51, C52, C53, C54 and the destination elements S1 to S8 are affected. When changing the components of the inverter C11 downstream of the upstream inverter After the type, each of the inverters C21, C22, C31, C32, C41, C42, C51, C52, C53 and C54 and each of the end elements S1 to S8 in the tree structure below the upstream inverter C11 The amount of time delay of the component itself remains unchanged. Then the new component type is assigned to the inverter C11, and its updated time delay amount is 90' equal to the target path delay value of 90. Due to the component type of the inverter C11 Already changed, 16 200925825 So the design tool needs to add the difference 20 to the components downstream of the inverter C11, ie each inverter - C21, C22, C3, C32, C4, C42, C51, C52, C53 and c54 And the path delay value recorded by each of the final point elements S1 to S8 To update the downstream inverter and the path time delay amount of the end element C11. Fig. 3B is a schematic diagram of the clock tree structure according to the embodiment of the present invention, using a design tool to compare each record at the 1^2 level. The path delay value in the inverter and a target path delay value. Figure 3B is similar to Figure 3A. The design tool knows the inverter c2i(s〇) © and the inverter C23 (60) recorded in the 12-bit order. The amount of time delay, as shown in Figure 3A, and find the target path delay value of 90. Because the path delay value of the inverter C21 (80) is less than the target path delay value of %, the design tool slave component type data A new component type is selected in the type database 3〇2 to change the component type of the inverter C21. In addition, the path delay value of the inverter C23 (6〇) is less than the target delay value of 90, and the design tool selects a new component type from the type database 3〇2 to change the inversion. The component type of C23. Then, the design tool replaces the values recorded in the inverters C31, C33, C41, C43, C51, C52, C55, C56, S1 to S4, and S9 to S129, respectively, to update each inverter recorded downstream and The path delay value of the endpoint component. Figure 3C is a schematic diagram of a clock tree structure in accordance with an embodiment of the present invention, using a design tool to compare the path delay value and a target path delay value for each of the inverters recorded in the L5 level. 3C is similar to FIG. 3B, and the design tool knows the amount of time delay of the inverters C52 (90), C54 (90), C55 (90), and C57 (90) recorded in the L5 level, and the target path delay value. It is 90. As shown in Figure 3B, because the path delay value 80 of the inverters C52 (80), C54 (80), C55 (80), and C57 (8 〇) is less than the target path delay value of 90, the design tool slave component type data. A new component type is selected in library 17 200925825 (type database) 302 to change the component types of inverters C52, C54, C55, and C57. Then, the design tool replaces the values recorded at the destination elements S3, S4, S7 to S10, S13, and S14, respectively, to update the path delay value of the destination element recorded downstream. In an embodiment of the invention, the design tool allows the path delay values recorded at each of the inverters and the end elements to tend to be identical to each other. In the preferred embodiment, the design tool adjusts the path delay value recorded in the inverter to be low to approach the target path delay value. In an embodiment, the design tool adjusts the path delay value by changing the inverted component time delay value. For example, during the construction of a Temple Pulse Structure Synthesis (CTS), the design tool first selects the type of τ that has a zero output load. In the execution time, the job structure is combined with the TS and the age program is read. The invention adjusts the component time delay value by increasing the output load, so that the path delay value recorded in the inverter is equal to or close to the target delay. . Even after the component_change, the component settings and the detailed winding results remain unchanged after the execution of the clock tree synthesis (cts) program. Specifically, when performing clock tree structure synthesis (CTS) and detailed winding procedures, the chip tool selects one or more different inverters with a specific wheel load, such as a zero (difficult) output load. Rib element. In the implementation of this (4) road _f boat delay balance method 'design tool from the component __ (type database) hat riding meta-type type has _ area and has not _ wheel (four) load. In the embodiment, the component type information Guo ypedatab (4) mainly derivatizes the single-component to expand other types of rotation, and the single-yuan rotation is fine (four) and the sharpness is different from the load. For example, selecting a specific type of inverse m (if the round is zero), and based on this specific 18 200925825 inverter, expands a variety of inverters with different output loads but with the same area. Very similar component layout. The secret element has a non-output load, so that the time-delay of the incident side corresponding to the single element produces a time schedule of the components of the paved type, for example, the larger the output load, the greater the amount of time delay. In addition, since the original component and the replaced non-type component have the same area and a very similar component layout, the original component can be directly replaced with a new type component without being moved to the vicinity of the original component. The component's words are free of place, and the difference between the different types of components is only the difference in output load. Therefore, the present invention does not require a more flexible winding after the execution of the CTS program and the winding procedure. When the design tool changes the component type of the inverter in part of the LH step L5 level, the design 4 (four) element Lai Yun changes the knot 姨 verilGg job and the design exchange format (DEF) file. The above file is then used to perform the analysis (STA) to improve the clock offset. ® According to the above, use the Clock Tree Structure Synthesis (CTS) tool to insert additional components (such as inverters or buffers) into the root element during the execution of the clock tree synthesis sequence (root cell) And the path time delay value recorded between the plurality of destination elements (sinks) to adjust the tree branch buckle (also to prevent), to ensure that the clock tree structure can synchronously transmit the clock signal from the root element To each end element, the clock offset is also minimized. In general, after the CTS tool completes the CTS program to generate the clock tree structure, the design tool will perform the routing procedure for the signal connection. Then the design tool calculates the clock offset of the clock tree structure again. Since the path of the __ branch of the 2009 20092525 tree-like burst is larger and smaller, the calculation is performed. The resulting _pulse offset will be larger than the time gland offset during the CTS procedure' to make the clock offset worse. The feature of the present invention is that after the CTS program and the winding procedure are executed, the type of the component is changed (different), and the material library has the same area and is very similar. The layout of the components, the setting of the component and the result of the material winding L (4) the type of the feminine component to flatten the value of the __, _ path time delay to improve the clock offset, In order to meet the specifications of the person's clock offset, the steps of setting the scale and detailed winding are avoided. Referring to FIG. 2, FIG. 3A-3C, and FIG. 4, FIG. 4 is a diagram showing a method for balancing the delay of the clock-like tree structure of the clock tree structure according to the embodiment of the present invention, which is used for the clock tree structure In the integrated circuit design. The method for balancing the path time delay amount of the present invention, which is turned into the clock tree structure of the integrated circuit, includes the following steps: In step S400, the clock tree structure is established by using the CTS master.

In step S, a design tool is used to calculate the UW coffee inverter path time delay value from the root element (10) to each end element (S (four) 6), wherein the path time delay value recorded in the end element is the largest Target path delay value. In the step input, from the end point component (8) to the root component help path, the design tool will record the path time delay value recorded in each terminal element (8) to postal time and the path time delay of the adjacent end point component. The values are compared, and the resulting higher path time delay value is recorded in the upper-off element, and the ___ view is recorded in the inverter 20 200925825 (C11 to C58) and the root element R0. In step S406, from the path of the root element R0 to each of the end elements (S1 to S16), the design tool compares the path time delay value of each inverter with the target path delay value for determining whether to borrow A new component type in the component type library 302 is selected to change to the new inverter type of the inverter to replace the component type of the original inverter. In step 〇6, when comparing the path time delay value of each inverter with the target path delay value, after changing the component type of the upstream inverter, in the tree structure below the upstream inverter Each inverter is set to maintain a constant value with © and the component time delay amount of each of the end elements themselves. In the step, in step s, when comparing each of the inverter lag time delay value and the target path delay value, if the inter-route delay value recorded in the inverter is smaller than the target path delay value, the inverter is The component type is changed from the current component type to the new component type. In step S·, the tool does not count the component time delay of the inverter with the new component type. ❹ In 4S412 + „ again. Ten tools add the difference DDiff to the original inverter component type path time delay value' to update the original component type predicate time delay value, where the difference is defined as the inverter The difference between the new read time delay value and the original tree time delay value. When the updated road «intervalence and other thieves are the ship's target delay value, the change of the component type of the inverter is accepted. In contrast, when the updated path time delay value is large, the component of the Wei is ignored. The component of the Jian County uses the target path delay value.

Doiff is added to the tree type. After the -inverting (10) component type is changed, the design fixture will set the difference between the inversion and the downstream of the reverse phase. 21 200925825 In step 8414, a ten tool adds the difference DDiff to the path time delay value recorded in the inverter downstream of the inverter to repeatedly update the record recorded in the downstream inverter and the end element. Path time delay value to minimize the clock offset of the clock tree structure. In step S416, when comparing the path time delay value of each inverter with the target path delay value, if the path time delay value recorded in the inverter is greater than the target job delay value, the design tool uses the original component type, And returning to the step pass, the path time delay value recorded by the next inverter is compared with the target path delay value. Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the invention, and the invention is to be construed as being limited by the scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a clock tree structure constructed using a design tool of a clock tree structure synthesis (CTS) according to an embodiment of the present invention. 2 is a schematic diagram of a clock tree structure according to an embodiment of the present invention, which utilizes a design tool to compare the 路径-road delay with another path value of the adjacent __ series, and sequentially treats each of the two A larger path delay value in the path delay value is recorded in an inverter of a different level. 3A-3C is a schematic diagram of a clock tree structure in accordance with an embodiment of the present invention, using a design tool to compare each path delay value recorded within the inverter with a target path delay value. Figure 4 is a diagram showing the balance of the path time delay amount of the clock tree structure according to the embodiment of the present invention. 22 200925825 The method flow chart is used for the integrated circuit design. [Description of main component symbols] Direction of the arrow from the 200th order L5 to the step L1 Direction of the arrow from the 300th order L1 to the step L5 302 Component type database

twenty three

Claims (1)

200925825 X. The scope of application for patents: 1. - The balance of the delay of the clock tree-like knot path, the green of the delay, after the execution of the pulse tree structure and the winding procedure, so that the clock of the clock tree structure Minimizing the offset, wherein the clock tree structure includes a root element, a plurality of inverters, a plurality of destination elements, and a plurality of signal connections between the inverters and the destination elements a line, the balancing method comprising the steps of: establishing the clock tree structure; calculating a plurality of inter-office delay values from the inverters passing through the portion of the inverters to each of the end elements, wherein The largest of the path time delay values of the secret element is defined as a target kneading delay value; from each of the end elements to the root element, the path time delay of each of the end elements is compared a value of the path time delay value of each of the adjacent end elements, and recording the higher path time delay value generated by the comparison to each of the two inverters upstream; Some of the higher path time delay values are respectively recorded in the corresponding > each of the inverters and the root element; comparing the path time delay value of each of the inverters with the target path delay value By determining whether a new component type in a component type database is selected to change the component type of an inverter from the original component type to the new component type; The ratio of the path time delay value of the phase comparator to the target path delay value is again updated to update the inverters downstream of the inverter and the path time delay values of the destination elements. The path time delay value approaches the target path delay value, and the time scale is 1: 彳 b. 24 200925825 2. As stated in the application of the scope of the patent item i, "the medium compares the time delay value of each of the inverters with the target path delay value from the root element to each of the The path of the end elements is compared. 3. For example, Shen Baoyi 1 Isaaki Heng, (4) 嶋 - the delay value of the road between the inverters and the target path delay value, each of these downstream The time delay values of the inverters and the component time delay values of each of the end elements remain unchanged. © "如巾细卿丨_状平衡村,射编_料库 includes multiple component types and each Each of the component types corresponds to a different component time delay value. 5. The balancing method of claim 4, wherein the component X member i of each of the inverters corresponds to an output load, And the output load is proportional to the component time delay value. 6. The balancing method of claim 2, wherein comparing the path time delay value of each of the inverters with the target path delay value In the steps, when recording each When the path time delay value of the inverters is less than the target path delay value, the component type of the inverter is changed from the original component class plow to the new component type. 7. The balancing method, after the step of changing the component type of the inverter from the original component type to the new component type, further comprising recalculating the component time of the inverter having the new component type A delay method as described in claim 7, wherein after the step of recalculating the component time delay value of the inverter having the new component type, the method further includes adding a difference to 25 200925825 a path time delay value to the inverter to update a path time delay value of the inverter, wherein the difference is defined as a difference between a new component time delay value of the inverter and an original component time delay value 9_ The balancing method as described in claim 7 of the patent application, further comprising repeatedly updating the component time delay value recorded in the downstream inverter to make the updated The path time delay value is equal to or close to the target path delay value. 10. The balancing method as described in claim 7 further includes updating the record downstream of the inverter having the new element type The path time delay value of the inverter. 11. The balancing method according to claim i, wherein in the step of comparing the path time delay value of each inverter with the target path delay value, when recorded in The path time delay value of the inverter is greater than the target path delay value, and the inverter uses the original component type. 12. A method for balancing the path time delay amount of the clock tree structure, executing the clock After the tree structure is synthesized and the winding process is minimized, the clock offset of the clock tree structure is minimized, wherein the clock tree structure comprises a component, a plurality of inverters, and a plurality of terminal elements And the plurality of signal connection lines between the _element and the _phase-inverting-transfer element, the balancing method includes the following steps: calculating an inverter passing through the - part of the root element to reach each of the end points a plurality of path time delay values, wherein the largest one of the path time delay values recorded by the secret point element is defined as a target path delay value; comparing the path time delay value of each of the end element to the adjacent The path time delay value of each of the end points 26 200925825 components, and the resulting higher scale scale delay value is recorded in each of the upstream inverters until all of the higher path time delay values are respectively Recorded in each of the corresponding inverters and the root element; from "Higan." Comparing the component to each of the path elements of the destination elements, comparing the path time delay value of each of the inverters with the target path delay value to determine whether to select a new component in a component type database a type such that the -inverting (four) component type is changed from the original component type to the new component type; and updating according to the ratio of the path time delay value of each of the inverters to the target path delay value The inverters downstream of the inverter and the path delay of the destination elements cause the path (four) to extend the ship (four) target mismatch value to minimize the clock offset of the clock tree structure .如如巾, please use the balancing method described in item 12, wherein each of the downstream inverters is used for each of the inter-surface delay values of the inverters and the target path delay value. Several time delay values and the lag time delay values for each of these endpoint elements remain unchanged. 14. The balancing method of claim 12, wherein the component type database comprises a plurality of component types, and each of the component types corresponds to a different component time delay value. 15_ The balancing method according to claim n, wherein comparing the path delay value of each of the inverters with the target path #delay value, when recording each of these When the inter-floor delay value of the inverter is less than the target path delay value, the element 27 of the service inverter 200925825 type is changed by the component of the county_(10) new component type. 16. 17. ❹ 18. 19. ❹20· As in the balancing method described in the patent application, the _ the inverse component class is changed to the new component type after the step of changing the original component _, including recalculation The time delay value of the inverted phase of the new component _. The balancing method of claim 16, wherein after the step of recalculating (10) the inverse time value of the inverted element in the new bull, the method further comprises adding the difference to the path of the inverse The _delay value is used to update the miscellaneous time delay of the inverter. The difference between the new component time delay value and the original component time delay value is defined as the difference between the new component time delay value and the original component time delay value. The balancing method described in the item further includes repeatedly updating the component time delay value recorded in the downstream inverter so that the updated path time delay value is equal to or close to the target path delay value. The balance method of the 16th item is included, and the path time delay value of the downstream inverter of the inverted phase having the new type of rotation is further included. The balance method described in Item 12 of the U. , wherein the path time delay value of the sister inverter is the same as the target road view, the time delay value recorded in the inverter is larger than the target path delay value, and the LR inverter uses the original one. Component class 28