200924361 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電源電路及其控制方法。 【先前技術】 請參閱圖1，其係一種先前技術電源電路之電路結構示 意圖。該電源電路1包括一輸入端101、一整流電路11、一 第一濾波電容（未標示）、一變壓器12、一整流二極體13、一 第二濾波電容14、一負載15、一脈寬調變電路（Switch IC)16、一電晶體17、一反饋電路18及一輸出端102。 該變壓器12包括一初級線圈121及一次級線圈122。該 輸入端101藉由該整流電路11及該第一濾波電容接地。該 初級線圈121 —端藉由該第一濾波電容接地，該初級線圈 121另一端電連接該電晶體17之汲極。該次級線圈122 —端 藉由該整流二極體13電連接該輸出端102,該次級線圈122 另一端接地。該第二濾波電容14及該負載15分別電連接於 該輸出端102與地之間。 該電晶體17之源極藉由一電阻（未標示）接地，其閘極電 連接該脈寬調變電路16。該反饋電路18電連接於該脈寬調 變電路16及該輸出端102之間。該反饋電路18根據該輸出 端102輸出之電壓提供一反饋電壓至該脈寬調變電路16。 請一併參閱圖2，係圖1所示電源電路10之電壓電流波 形示意圖。其中，VI表示該脈寬調變電路16加載於該電晶 體17閘極之電壓波形圖，V2表示該整流二極體13輸出之 7 200924361 電壓波形圖，II表示該濾波電容14向該負載15提供之電流 波形圖。外界交流電壓藉由該輸入端101輸入該整流電路 11，經該整流電路11整流後提供一直流電壓於該變壓器12 之初級線圈121。 該脈寬調變電路16加載脈衝電壓VI於該電晶體17之 閘極。在該脈衝電壓VI控制下，該電晶體17交替導通與截 止，該變壓器12之初級線圈121產生變化之電流，該變壓 器12之次級線圈122產生一感應電壓，該感應電壓經該整 流二極體13整流後輸出如V2所示之電壓。當該二極體13 輸出尚電平時’該電壓V2向該苐二遽波電容14充電’該電 壓V2同時向該負載15供電。當該二極體13輸出低電平時， 該第二濾波電容14放電，該第二濾波電容14之放電電流向 該負載15供電。 然，當該二極體13輸出低電平之時間tl較長時，該第 二濾波電容14放電時間較長，該第二濾波電容14需要不斷 的充、放電以向該負載15供電。因此’該電源電路10之輸 出端102輸出電流II之波動範圍較大。 【發明内容】 有鑑於此，提供一種減小輸出電流波動範圍之電源電路 實為必要。 有鑑於此，提供一種減小輸出電流波動範圍之電源電路 控制方法實為必要。 一種電源電路，其向負載供電，包括一輸入端、一輸出 端、N個變壓單元及一脈寬調變電路，N為大於1的自然數。 8 200924361 該輸入端用於接收外部電路輸入之電壓。該N個變壓單元分200924361 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a power supply circuit and a control method therefor. [Prior Art] Please refer to Fig. 1, which is a schematic diagram of the circuit configuration of a prior art power supply circuit. The power circuit 1 includes an input terminal 101, a rectifier circuit 11, a first filter capacitor (not labeled), a transformer 12, a rectifying diode 13, a second filter capacitor 14, a load 15, and a pulse width. A switching circuit (Switch IC) 16, a transistor 17, a feedback circuit 18 and an output terminal 102. The transformer 12 includes a primary coil 121 and a primary coil 122. The input terminal 101 is grounded by the rectifier circuit 11 and the first filter capacitor. The primary coil 121 is grounded by the first filter capacitor, and the other end of the primary coil 121 is electrically connected to the drain of the transistor 17. The secondary coil 122 is electrically connected to the output terminal 102 by the rectifying diode 13, and the other end of the secondary coil 122 is grounded. The second filter capacitor 14 and the load 15 are electrically connected between the output terminal 102 and the ground, respectively. The source of the transistor 17 is grounded by a resistor (not shown), and its gate is electrically connected to the pulse width modulation circuit 16. The feedback circuit 18 is electrically coupled between the pulse width modulation circuit 16 and the output terminal 102. The feedback circuit 18 provides a feedback voltage to the pulse width modulation circuit 16 based on the voltage output from the output terminal 102. Please refer to FIG. 2 together with a schematic diagram of the voltage and current waveforms of the power supply circuit 10 shown in FIG. 1. Wherein, VI represents a voltage waveform diagram of the pulse width modulation circuit 16 applied to the gate of the transistor 17, V2 represents a voltage waveform diagram of the output of the rectifier diode 13 200924361, and II represents the filter capacitor 14 to the load. 15 provides the current waveform diagram. The external AC voltage is input to the rectifier circuit 11 through the input terminal 101, and is rectified by the rectifier circuit 11 to provide a DC voltage to the primary coil 121 of the transformer 12. The pulse width modulation circuit 16 applies a pulse voltage VI to the gate of the transistor 17. Under the control of the pulse voltage VI, the transistor 17 is alternately turned on and off, the primary coil 121 of the transformer 12 generates a varying current, and the secondary coil 122 of the transformer 12 generates an induced voltage through which the induced voltage is passed. The body 13 is rectified and outputs a voltage as indicated by V2. When the output of the diode 13 is still level, the voltage V2 charges the second wave capacitor 14 and the voltage V2 simultaneously supplies power to the load 15. When the diode 13 outputs a low level, the second filter capacitor 14 is discharged, and the discharge current of the second filter capacitor 14 supplies power to the load 15. However, when the time t1 at which the diode 13 outputs a low level is long, the second filter capacitor 14 has a longer discharge time, and the second filter capacitor 14 needs to be continuously charged and discharged to supply power to the load 15. Therefore, the output current of the output terminal 102 of the power supply circuit 10 has a large fluctuation range. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a power supply circuit that reduces the fluctuation range of the output current. In view of this, it is necessary to provide a power supply circuit control method that reduces the fluctuation range of the output current. A power supply circuit for supplying power to a load includes an input terminal, an output terminal, N transformer units, and a pulse width modulation circuit, wherein N is a natural number greater than one. 8 200924361 This input is used to receive the voltage of the external circuit input. The N transformer units are divided into
，別電連接於該輸入端與該輪出端之間。該脈寬調變電路分Z 電連接該N個變鮮元。該脈寬觀電路分職供N個不 同相位之控龍號於該N個變壓單^，每二控制訊號之相位 差為360/(Ν+1)度，該N個變塵單元分別接收該脈寬調變電 路提供之N個控制訊號，並分別輸出N個不同相位之電壓 於該輸出端。 一種電源電路之控制方法，其包括如下步驟：產生N個 不_位之㈣訊號，N為大於1的自㈣，每二控制訊號 之相位差4 36〇/(N+1)度；分別發㈣n則目位 3:( N + i )度之控制訊號於N個變壓單元，使該n個變壓單 元分別輸出不同相位之N個電壓於一負載。 —，^先前技術相，’本發明之電源電路包括N個變壓單 壓單元分別向負載供電。由於分職送則固 ===於該n個變壓單元，每二控制訊號之相 4差為360/(Ν+1)度。因此’該分別加 壓於該負載。由於加載於該負載之N個電壓相二立之電 個電壓對應之低電料間互相補充，從=、目=== :載之電壓之低電平時間，進而減小該電= 波動範圍。 电塔翰出電、机之 【實施方式】 明參閱圖3 ’係本發明電源電路之 結構示意圖。該電源電路包括-輸入端2〇1、1二2電路 -脈寬調變電路22、一第，單元23、；::= 200924361 24、一濾波電容25、一負載26、一反饋電路27及一輸出端 202。 該整流電路21為一全橋式整流電路或一半橋式整流電 路。該脈寬調變電路22分別提供不同相位之控制訊號於該 第一、第二變壓單元23、24。該第一、第二變壓單元23、 24分別接收該脈寬調變電路22之控制訊號，並根據該控制 訊號輸出不同相位之輸出電壓。該反饋電路27根據該輸出 端202輸出之電壓提供一反饋電壓於該脈寬調變電路22。 該第一變壓單元23包括一第一變壓器230、一第一電晶 體231、一第一整流二極體232。該第一變壓器230包括一 第一初級線圈233及一第一次級線圈234。該第一電晶體231 係一 N型通道增強型金屬氧化物半導體場效電晶體。 該第二變壓單元24包括一第二變壓器240、一第二電晶 體241、一第二整流二極體242。該第二變壓器240包括一 第二初級線圈243及一第二次級線圈244。該第二電晶體241 係一 N型通道增強型金屬氧化物半導體場效電晶體。 該輸入端201藉由該整流電路21分別電連接該第一、 第二初級線圈233、243之一端。該第一初級線圈233另一 端電連接該第一電晶體231之汲極。該第一電晶體231之源 極藉由一電阻（未標示）接地，其閘極電連接該脈寬調變電路 22。該第一次級線圈234 —端接地，另一端經由該第一整流 二極體232之正、負極電連接該輸出端202。該濾波電容25 及該負載26分別電連接於該輸出端202與地之間。 該第二初級線圈243另一端電連接該第二電晶體241之 200924361 汲極。該第二電晶體241之源極藉由一電阻（未標示）接地， 其閘極電連接該脈寬調變電路22。該第二次級線圈244 —端 接地，另一端經由該第二整流二極體242之正、負極電連接 該輸出端202。該反饋電路27電連接於該脈寬調變電路22 與該輸出端202之間。 請一併參閱圖4，係圖3所示電源電路20之電壓電流波 形圖。其中，VI 、V2分別表示該脈寬調變電路22加載於 該第一、第二電晶體231、241閘極之電壓波形圖。V3 、 V4分別表示該第一、第二整流二極體232、242輸出之電壓 波形圖。V5表示該濾波電容25兩端之電壓波形圖。12表示 該濾波電容25向該負載26提供之電流波形圖。外界交流電 壓藉由該輸入端201輸入該整流電路21，經該整流電路21 整流後分別提供一直流電壓於第一、第二初級線圈233、243。 該脈寬調變電路22分別加載脈衝電壓VI、V2於該第 一、第二電晶體231、241之閘極，其中，V2較V 1有一 120 度之相位延遲。在該脈衝電壓VI控制下，該第一電晶體231 交替導通與截止，該第一初級線圈233產生變化之電流，該 第一次級線圈234產生一感應電壓，該感應電壓經該第一整 流二極體232整流後輸出如V3所示之電壓，設電壓V3的 低電平時間為t2。在該脈衝電壓V2控制下’該弟二電晶體 241交替導通與截止，該第二初級線圈243產生變化之電 流，該第二次級線圈244產生一感應電壓，該感應電壓經該 第二整流二極體242整流後輸出如V4所示之電壓。其中， V4較V3有一 120度相位延遲。 11 200924361 該第一整流二極體232加載電壓V3至該濾波電容25， 在該電壓V3之低電平時間t2内，該第二整流二極體242加 載電壓V4至該濾波電容25，因此，實際加載於該濾波電容 25之電壓係V5，則加載於該濾波電容25之實際電壓V5之 低電平時間為t3，t3<t2。該濾波電容25在該電壓V5作用 下不斷充、放電，從而向該負載26提供如12所示電流。 與先前技術相比，本發明之電源電路20包括第一、第 二變壓單元23、24，該脈寬調變電路22分別提供具有120 度相位差之脈衝電壓於該第一、第二變壓單元23、24,該第 一、第二變壓單元23、24分別加載具有120度相位差之電 壓於該濾波電容25。由於在該第一變壓單元23輸出電壓V3 之低電平時間t2内，該第二變壓單元24加載電壓V4於該 濾波電容25，因此，實際加載於該濾波電容25之電壓V5 之低電平時間減小為t3，從而減小了該濾波電容25之放電 時間，進而減小了該電源電路20輸出電流之變化範圍。 由於該濾波電容25僅在時間t3内向該負載26供電， 該濾波電容25之供電時間縮短，從而降低了該濾波電容25 之工作溫度，進而延長了該濾波電容25之壽命。本發明之 電源電路20之第一、第二變壓器230、240採用單向推動， 該脈寬調變電路22輸出電壓之佔空比可達到50%以上而不 會損壞該第一、第二變壓器230、240。同時，較採用雙向推 動變壓器（如全波推挽式變壓器）之電源電路，該電源電路20 之第一、第二變壓器230、240之工作頻率降低，從而降低 該電源電路20之磁彳貝耗。 12 200924361 請參閱® 5，係本發明電源電路之第二實施方式 結，不，圖:該電源電路3Q與第—實施方式之電源電路如, not electrically connected between the input end and the wheel end. The pulse width modulation circuit electrically connects the N fresh elements. The pulse width circuit is divided into N different phase control dragons in the N transformers, and the phase difference of each of the two control signals is 360/(Ν+1) degrees, and the N dust collecting units respectively receive The pulse width modulation circuit provides N control signals and outputs N different phase voltages to the output terminals. A method for controlling a power supply circuit, comprising the steps of: generating N (four) signals that are not _ bits, N is self (four) greater than 1, and the phase difference of each two control signals is 4 36 〇 / (N + 1) degrees; (4) n is the target 3: (N + i) degree control signal in the N transformer units, so that the n transformer units respectively output N voltages of different phases to a load. —, ^ Prior art phase, the power supply circuit of the present invention includes N voltage swing single voltage units that respectively supply power to the load. Since the split service is fixed === in the n transformer units, the phase difference of each of the two control signals is 360/(Ν+1) degrees. Therefore, the pressure is applied to the load separately. Since the low voltages corresponding to the voltages of the two voltage phases of the load are complementary to each other, the low voltage time of the voltage from the =, the target ===: the voltage is further reduced. . [Electrical Method] Referring to Figure 3, the structure of the power supply circuit of the present invention is shown. The power supply circuit includes an input terminal 2〇1, a 1 2 circuit-pulse width modulation circuit 22, a first unit 23, a frequency converter capacitor 25, a load 26, and a feedback circuit 27. And an output terminal 202. The rectifier circuit 21 is a full bridge rectifier circuit or a half bridge rectifier circuit. The pulse width modulation circuit 22 provides control signals of different phases to the first and second voltage transforming units 23, 24, respectively. The first and second voltage transforming units 23 and 24 respectively receive the control signals of the pulse width modulation circuit 22, and output output voltages of different phases according to the control signals. The feedback circuit 27 provides a feedback voltage to the pulse width modulation circuit 22 based on the voltage output from the output terminal 202. The first transformer unit 23 includes a first transformer 230, a first transistor 231, and a first rectifier diode 232. The first transformer 230 includes a first primary coil 233 and a first secondary coil 234. The first transistor 231 is an N-type channel enhancement type metal oxide semiconductor field effect transistor. The second transformer unit 24 includes a second transformer 240, a second transistor 241, and a second rectifier diode 242. The second transformer 240 includes a second primary coil 243 and a second secondary coil 244. The second transistor 241 is an N-type channel enhanced metal oxide semiconductor field effect transistor. The input terminal 201 is electrically connected to one end of the first and second primary coils 233, 243 by the rectifier circuit 21, respectively. The other end of the first primary coil 233 is electrically connected to the drain of the first transistor 231. The source of the first transistor 231 is grounded by a resistor (not shown), and its gate is electrically connected to the pulse width modulation circuit 22. The first secondary winding 234 is grounded and the other end is electrically connected to the output terminal 202 via the positive and negative terminals of the first rectifying diode 232. The filter capacitor 25 and the load 26 are electrically connected between the output terminal 202 and the ground, respectively. The other end of the second primary coil 243 is electrically connected to the 200924361 drain of the second transistor 241. The source of the second transistor 241 is grounded by a resistor (not shown), and its gate is electrically connected to the pulse width modulation circuit 22. The second secondary winding 244 is grounded and the other end is electrically connected to the output terminal 202 via the positive and negative terminals of the second rectifying diode 242. The feedback circuit 27 is electrically connected between the pulse width modulation circuit 22 and the output terminal 202. Please refer to FIG. 4 together with the voltage current waveform diagram of the power supply circuit 20 shown in FIG. Wherein VI and V2 respectively represent voltage waveforms of the gates of the first and second transistors 231 and 241 loaded by the pulse width modulation circuit 22. V3 and V4 respectively show voltage waveforms of the outputs of the first and second rectifying diodes 232 and 242. V5 represents a voltage waveform diagram across the filter capacitor 25. 12 denotes a current waveform diagram of the filter capacitor 25 supplied to the load 26. The external AC voltage is input to the rectifier circuit 21 via the input terminal 201, and is rectified by the rectifier circuit 21 to supply a DC voltage to the first and second primary coils 233 and 243, respectively. The pulse width modulation circuit 22 respectively applies pulse voltages VI, V2 to the gates of the first and second transistors 231, 241, wherein V2 has a phase delay of 120 degrees from V1. Under the control of the pulse voltage VI, the first transistor 231 is alternately turned on and off, the first primary coil 233 generates a varying current, and the first secondary coil 234 generates an induced voltage, and the induced voltage passes through the first rectification. After the diode 232 is rectified, the voltage shown by V3 is output, and the low time of the voltage V3 is set to t2. Under the control of the pulse voltage V2, the second transistor 241 is alternately turned on and off, the second primary coil 243 generates a varying current, and the second secondary coil 244 generates an induced voltage, and the induced voltage passes through the second rectification. The diode 242 is rectified and outputs a voltage as shown by V4. Among them, V4 has a 120 degree phase delay compared to V3. 11200924361 The first rectifying diode 232 is loaded with a voltage V3 to the filter capacitor 25. During the low time t2 of the voltage V3, the second rectifying diode 242 is loaded with the voltage V4 to the filter capacitor 25. Therefore, When the voltage V5 is actually applied to the filter capacitor 25, the low level time of the actual voltage V5 applied to the filter capacitor 25 is t3, t3 < t2. The filter capacitor 25 is continuously charged and discharged under the action of the voltage V5, thereby supplying a current as indicated by 12 to the load 26. Compared with the prior art, the power supply circuit 20 of the present invention includes first and second voltage transforming units 23, 24, respectively, which provide pulse voltages having a phase difference of 120 degrees to the first and second The voltage transforming units 23 and 24 respectively load a voltage having a phase difference of 120 degrees to the filter capacitor 25 . Since the second voltage-varying unit 24 loads the voltage V4 to the filter capacitor 25 during the low-level time t2 of the output voltage V3 of the first voltage-dividing unit 23, the voltage V5 actually applied to the filter capacitor 25 is low. The level time is reduced to t3, thereby reducing the discharge time of the filter capacitor 25, thereby reducing the variation range of the output current of the power circuit 20. Since the filter capacitor 25 supplies power to the load 26 only during the time t3, the power supply time of the filter capacitor 25 is shortened, thereby reducing the operating temperature of the filter capacitor 25, thereby prolonging the life of the filter capacitor 25. The first and second transformers 230 and 240 of the power supply circuit 20 of the present invention adopt a one-way push, and the duty ratio of the output voltage of the pulse width modulation circuit 22 can reach 50% or more without damaging the first and second Transformers 230, 240. At the same time, the operating frequency of the first and second transformers 230 and 240 of the power supply circuit 20 is lower than that of the power supply circuit of the two-way push transformer (such as a full-wave push-pull type transformer), thereby reducing the magnetic mussel consumption of the power supply circuit 20. . 12 200924361 Please refer to ® 5, which is the second embodiment of the power supply circuit of the present invention. No, the power supply circuit 3Q and the power supply circuit of the first embodiment are as shown.
::別：·該電源電路3〇包括N個變壓單元(未標 其中，N為大於2之自然數。 J 一脈寬調變電路32分職供N個不 於該N個變壓單亓，兮μ加w w ^工利几就 爻埜早兀该Ν個控制訊號中，每二 相位差為360/(Ν+1)度。個辦厭+ 制汛唬之 下八別挺也、 該N個交壓早兀在該控制訊號控制 ^ 目電塵於—濾波電容35，設該N個電壓分別 門〜11，如圖6所示。該N個電壓v!〜v n互相低電平時 :波電：ST於該濾、波電容35之實際電壓如V〇所示。該 提供如！3所示電流。Μ下充、放m向負載36 一與先前技術相比，本發明之電源電路％包括n個變壓 早凡’該脈寬調變電路32八 號於該N個㈣屬供N個不同相位之控制訊 下分別提個變辭元在該控制訊號控制 咏供N個不同相位之電壓vl〜Vn於該濾波電容％， ν' 相鄰電壓之相位差為36〇/(N+1)度。該n個電壓 該^♦互^補充低電平時間，# N足夠大時，實際加載於 調:壓之低電平時間近似為〇。因此，該脈寬 而每雨电壓之佔空比可在1%〜99%範圍内變化， 〇。’該丁雷^於該遠波電容％之電壓之低電平時間近似為 且幹"屮φΙ路3〇不需該濾波電容35即可實現直流輸出， 則出電流13變化範圍進一步減小。 晏實際加載於誠波電容35之電壓之低電平時間近似 13 200924361 ^〇時:僅由該變星單元向該負載供電，該遽波電 知:供輕載濾、波之功能兮者 僅 〜刀月匕，該濾波電容％ 作 波電容35亦可採用低 作二度降低。該渡 〇α - , _ . ^ 之電合。同日守，由於由Ν個轡懕 兀〜負載36供電’該電源電路 從而提高輪出功率。 貝見大電流供電’ 惟’本發明之特徵不僅可應 奋^ 依需求而作適當摩用上的 w ^方式，更可::Do not: · The power circuit 3〇 includes N transformer units (unlabeled, N is a natural number greater than 2. J-pulse width modulation circuit 32 is divided into N for not less than N transformers Single 亓, 兮μ plus ww ^工利 few on the wilderness of the first control signal, each two phase difference is 360 / (Ν +1) degrees. The N voltages are controlled by the control signal to control the dust in the filter capacitor 35, and the N voltages are respectively gated to 11, as shown in Fig. 6. The N voltages v!~vn are low with each other. Normal: Wave: ST is the actual voltage of the filter and wave capacitor 35 as shown by V 。. This provides the current as shown in !3. Under charge, put m to the load 36 - Compared with the prior art, the present invention The power circuit % includes n transformers, and the pulse width modulation circuit 32 is provided in the control signal of the N (four) genus for N different phases. The voltages of different phases vl~Vn are at the filter capacitor %, and the phase difference between adjacent voltages of ν' is 36〇/(N+1) degrees. The n voltages are mutually complementary to the low level time, #N When it is large enough, it is actually loaded on The low-level time of the voltage is approximately 〇. Therefore, the pulse width and the duty cycle of each rain voltage can vary from 1% to 99%, 〇. The voltage of the far-wave capacitor % The low level time is approximately and dry "屮φΙ路3〇 does not require the filter capacitor 35 to achieve DC output, then the range of the output current 13 is further reduced. 晏The voltage actually applied to the capacitor 35 is low. Level time approx. 13 200924361 ^〇: Only the variable star unit supplies power to the load. The chopper knows that the function of light load filter and wave is only ~ 刀月匕, the filter capacitor % wave capacitor 35 It can also be reduced by a low degree. The crossing of the 〇α - , _ . ^ is the same as that of the same day, because the power supply circuit is powered by a 辔懕兀 辔懕兀 ~ load 36 to increase the power of the turn. The power supply 'only' features of the present invention can not only be used in accordance with the needs of the w ^ way, but also
個反饋電路，每—反饋 私原電路可包括N rr ^ ^ ^ ^ ^ 電路反饋—變壓單元輸出之電壓於节 脈丸_電路’衫限於上述實施方式所述。4於該 紅上所述，本發明確 利申請。惟，以上今者件’羑依法提出專 口哀者僅為本發明之較佳實 之範圍並不以上述實施方41 只轭方式，本發明 方式為限，舉凡孰朵 援依本發明之精神所作 ‘…β本案技藝之人士 申請專利範圍内。 Τ 乂支化白應涵盍於以下 【圖式簡單說明】 圖1係一種先前技術電源 岡9总国， 甩原、電路之電路結構示意圖。 圖2係圖1所示電源電路之 — 圖3係本發明電源電路 一 ^㈣示意圖。 圖4係圖3所示電源電 ^ =方式之電路結構示意圖。 ς . , ^ 峪之电壓電流波形圖。 圖5係本發明電源電路之第_ 、 圖6係圖5所示電源電路、％方式之％路結構示意圖。 rm: 電壓電流波形圖。 【主要70件符號說明】 電源電路 20、μ U 30輪入端 。 整流電路 2i 2〇1 脈寬調變電路 22 % 14 200924361 .第一變壓單元 23 第一變壓器 230 第一電晶體 231 第一整流二極體 232 第一初級線圈 233 第一次級線圈 234 第二變壓單元 24 第二變壓器 240 第二電晶體 241 第二整流二極體 242 弟 >—初級線圈 243 第二次級線圈 244 濾波電容 25、35 負載 26 > 反饋電路 27 輸出端 202 36 15The feedback circuit, each feedback feedback circuit can include N rr ^ ^ ^ ^ ^ circuit feedback - the voltage of the transformer unit output is limited to the pulse mode_circuit's shirt. 4 The invention is described in the above description. However, the above-mentioned ones are not limited to the scope of the present invention. The person who made the '...β method of the case applied for a patent. Τ 乂 化 化 应 应 应 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 图 图 图 图Figure 2 is a schematic diagram of the power supply circuit of Figure 1. Figure 3 is a schematic diagram of the power supply circuit of the present invention. FIG. 4 is a schematic structural diagram of a circuit of the power supply mode shown in FIG. 3. ς . , ^ 电压 Voltage and current waveform diagram. FIG. 5 is a schematic diagram showing the structure of the power supply circuit of the present invention, FIG. 6 and the power circuit of FIG. Rm: Voltage and current waveform diagram. [Main 70-symbol description] Power circuit 20, μ U 30 wheel-in terminal. Rectifier circuit 2i 2〇1 pulse width modulation circuit 22% 14 200924361. First transformer unit 23 First transformer 230 First transistor 231 First rectifier diode 232 First primary coil 233 First secondary coil 234 Second transformer unit 24 second transformer 240 second transistor 241 second rectifier diode 242 brother> primary coil 243 second secondary coil 244 filter capacitor 25, 35 load 26 > feedback circuit 27 output 202 36 15