200923656 •九、發明說明： .【發明所屬之技術領域】 本發明係關於一種 SPI(Serial Peripheral Interface，串列週邊介面）設備通訊電路。 【先前技術】 在電腦系統中，SPI是一種允許在兩種設備（一 個稱主設備’另一個稱從設備）之間進行串列資料交 換之介面。SPI最常應用於電腦系統之CPU (Central processing unit，中央處理器）與週邊晶片之間之通 訊電路系統中’ spi匯流排由串列資料登錄（Serial data input ’ SDI)，串列資料輸出（serial data output，SDO )， 串列時脈（Serial clock，SCK)，晶片選擇（chip select， cs)四種訊號構成，當有cs訊號時，SPI匯流排才可透 過其他二條δίΐ號線路進行資料之接受和發送，一般CPU所 提供之SPI匯流排數量有限。 请參閲圖1，當主設備1〇〇需要透過SPI匯流排 與從設備200進行通訊時，一般主設備與spi從設備之 連接方式是：該主設備100具有資料輸出埠M〇si，資 料登錄埠MISO,串列時脈埠SCLK，從屬選擇埠ss〇;從 設備200具有一串列資料登錄埠sm、一串列資料 輸出埠SDO、-串列時脈埠SCLK及一晶片選擇蜂 cs。其中’該主設備刚之資料輸㈣m〇si與該從 設備200之串列資料登铩迨ςΓ>τ如4 寸a錄垾SDI相連，該主設備1〇〇 之資料登錄槔ΜIS 0盘該從抓据？ n n /、邊從a又備200之串列資料輸出埠 200923656 • SDO相連，該主設備loo之串列時脈埠scLK與該從 設備200之串列時脈埠sCLK相連，該主設備ι〇〇之 從屬選擇埠SS0與該從設備200之晶片選擇埠CS相 連，該主設備1〇〇透過該從屬選擇埠Ss〇提供之晶片選 擇訊號來選擇連接於該主設備100之從設備200與其進行 通訊。在習知技術中該主設備1〇〇僅能提供一個晶片選擇 5礼號，因此只能透過一條SPI匯流排連接一個從設備 200。然而當需使用多個從設備2〇〇時，則產生spi匯流 排不夠使用之問題。 【發明内容】 鑒於上述内容’有必要提供一種可擴充SPI匯流排之 SPI設備通訊電路，以解決SPI匯流排使用數量不足之問 題。 一種串列週邊介面（SPI)設備通訊電路，其包括 一主設備、複數從設備及一解碼器，該主設備之資 ; 料輸出端、資料登錄端及串列時脈端分別與每一從 設備之串列資料登錄端、串列資料輸出端及串列時 脈端對應連接，該主設備之從屬選擇璋與該解碼器 之貪料接收端相連，該主設備之複數GPI0引腳與 該解碼器之複數輸入埠分別相連，該複數從設備之 晶片選擇崞分別對應連接該解碼器之複數輸出蜂， 該GPI〇引腳之選通訊號組合控制該解碼器之輸出 蜂之選通’使該主設備之從屬選擇埠之訊號透過該 解碼器之資料接收端及被選通之輸出埠輪出到對應 7 200923656 之從設備之晶片選擇埠。 • 相較習知技術，該SPI設備通訊電路在該主設備與 該從設備之間連接該解碼器，該GPIO引腳之選通 訊號組合控制該解碼器使該主設備之從屬選擇埠之 訊號透過該解碼器之資料接收端對應輸出到該解碼 益之一個輸出埠’並傳輸到與其對應之一個該從設 備之晶片選擇埠上’以使該從設備與該主設備進行 通訊。根據該GPIO引腳之選通訊號組合，可選通 不同之從設備’從而擴充了 SPI匯流排之使用數量。 【實施方式】 請參閲圖2，本發明SPI設備通訊電路之較佳實施方 式包括一主設備10、複數從設備20及一解碼器30, 這裡以十六個從設備20為例加以說明。 該主設備10包括一資料輸出埠MOSI、一資料登錄 埠MISO、一串列時脈埠SCLK、一從屬選擇埠SS0及複 數 GPIO ( General purpose input/output P〇rt，通用 輪入輸出埠）引腳。該主設備可以為CPU、微控制器 或疋 PIC(Peripheral Interface Controller，週邊設備 控制器）。每一從設備20包括一事列資料登錄埠 S DI、一串列資料輸出埠S D 0、一串列時脈蟑s C L K 及一晶片選擇埠CS。 其中，每一從設備20之串列資料登錄琿SDI 與該主設備10之資料輸出埠Μ 0 SI相連，每—從設 備20之串列資料輪出埠SD0與該主設備1〇之資料 200923656 .登錄埠MISO相連’每一從設備2〇之串列時脈蜂 .SCLK與該主設備10之串列時脈埠sclK相連，每 一從設備20之晶片選擇埠CS分別依次與該解碼I 30之輸出蜂Y〇~Y 15連接，該解碼器3〇之資料接收 端D連接該主設備1〇之從屬選擇埠ss〇，該解碼器 30之輸入埠A0~A3分別依次連接該主設備ι〇之: 個 GPIO 引腳 PIOO〜PI03。 本實施方式中，利用該主設備10之四個GPI0 引腳PI〇0~PIO3,可以將SPI匯流排擴充為十六組， 進而可以連接十六個從設備2〇，本發明在該主設備 1〇與該從設備20之間設計了該解碼器3〇,該Gpi〇 引腳PIOO〜PI03之選通訊號組合控制該解碼器 使該主設備10之從屬選擇埠ss〇透過該解碼器之資 料接收端D對應輸出到該解碼器3〇之一個該輪出 埠，並傳輸到與其對應之一個該從設備2〇之晶=選 擇埠cs上，以使該從設備20與該主設備ι〇進行通 訊。-該解碼器30之輸入埠與輸出埠之對照表如表一 2示，其中0代表低電位選通訊號，1代表高電位 選通訊號，Y代表該解碼器3〇之輸出埠，下述十六 種選通訊號分別用以控制該解碼器30選通對應之 —個從設備20與該主設備10之間進行通訊。〜 土工作時，如果該主設備10要與第一從設備2〇透過spi 匯流排通訊時，該主設備1〇透過Gpi〇引腳ρι〇〇〜ρι⑴ 發出對應該第-從設備2 0之晶片選擇埠C S之選通訊號， 9 200923656 . 如A3~A0 = 0000，該解碼器30將該主設備10之從屬選擇 埠SS0之訊號透過該解碼器30之資料接收端D分配給該 第一從設備20之晶片選擇埠CS使用，其他從設備20則 無權使用主設備10之從屬選擇埠SS0,此時該第一從設備 20就有SPI匯流排之使用權並與該主設備10通訊。如果 該主設備10要與該第十一從設備20透過SPI匯流排通訊 時，該主設備10透過GPIO引腳PIOO〜PI03發出對應該第 十一從設備20之晶片選擇埠CS之選通訊號，如 A3〜A0 = 1011，該解碼器30將該主設備10之從屬選擇埠 SS0之訊號透過該解碼器30之資料接收端D分配給該第 十一從設備20之晶片選擇埠CS使用，其他從設備20則 無權使用主設備10之從屬選擇埠SS0,此時該第十一從設 備20就有SPI匯流排之使用權並與該主設備10通訊，其 他從設備與主設備10之間之通訊與上述工作原理相同，不 再贅述。 表一200923656 • Nine, invention description: [Technical field of invention] The present invention relates to a SPI (Serial Peripheral Interface) device communication circuit. [Prior Art] In a computer system, SPI is an interface that allows serial data exchange between two devices (one called a master device and the other called a slave device). SPI is most commonly used in the communication circuit between the CPU (Central Processing Unit) of the computer system and the peripheral chip. The 'spi bus is serial data input 'SDI', serial data output (Serial data input 'SDI) Serial data output (SDO), serial clock (SCK), chip select (cs) four kinds of signals. When there is a cs signal, the SPI bus can be used to transmit data through two other δίΐ lines. The acceptance and transmission, the general CPU provides a limited number of SPI bus. Referring to FIG. 1, when the master device 1 needs to communicate with the slave device 200 through the SPI bus, the connection between the general master device and the spi slave device is: the master device 100 has data output 埠M〇si, data. Log in 埠MISO, serial clock 埠SCLK, slave select 埠ss〇; slave device 200 has a list of data logs 埠sm, a list of data outputs 埠SDO,-serial clock 埠SCLK and a wafer selection bee cs . The data of the master device (4) m〇si is connected to the serial data of the slave device 200, and the data of the master device is recorded in the 槔ΜIS 0 disk. From the arrest? Nn /, side from a and 200 serial data output 埠 200923656 • SDO connected, the master device loo serial clock 埠 scLK is connected to the slave device 200 serial clock sCLK, the master device ι〇 The slave select 埠SS0 is connected to the chip select 埠CS of the slave device 200, and the master device 1 selects the slave device 200 connected to the master device 100 through the chip select signal provided by the slave select 埠Ss〇 communication. In the prior art, the master device 1 can only provide one wafer selection number, so that only one slave device 200 can be connected through one SPI bus. However, when multiple slave devices are required, the problem arises that the spi bus is not used enough. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide an SPI device communication circuit that can expand the SPI bus to solve the problem of insufficient number of SPI buss. A serial peripheral interface (SPI) device communication circuit, comprising a master device, a plurality of slave devices and a decoder, the master device; the material output terminal, the data login terminal and the serial clock terminal respectively and each slave The serial data registration end, the serial data output end and the serial clock end of the device are correspondingly connected, and the slave device of the master device is connected to the greedy receiving end of the decoder, and the plurality of GPI0 pins of the master device and the The complex input ports of the decoder are respectively connected, and the complex number is selected from the chip of the device, corresponding to the plurality of output bees connected to the decoder, and the selected combination of the GPI pin pins controls the output of the decoder. The signal of the slave device of the master device is transmitted through the data receiving end of the decoder and the gated output to the chip selection of the slave device corresponding to 7 200923656. • Compared to the prior art, the SPI device communication circuit connects the decoder between the master device and the slave device, and the selected communication number combination of the GPIO pin controls the decoder to enable the master device to select the slave signal. The data receiving end of the decoder is outputted to an output of the decoding device and transmitted to a corresponding chip selection of the slave device to enable the slave device to communicate with the master device. According to the combination of the selected GPIO pins, the number of different slave devices can be selected to expand the number of SPI busses. [Embodiment] Referring to FIG. 2, a preferred embodiment of the SPI device communication circuit of the present invention includes a master device 10, a plurality of slave devices 20, and a decoder 30. Here, sixteen slave devices 20 are taken as an example for description. The master device 10 includes a data output 埠MOSI, a data register 埠MISO, a serial clock 埠SCLK, a slave select 埠SS0, and a GPIO (General purpose input/output P〇rt). foot. The master device can be a CPU, a microcontroller, or a PIC (Peripheral Interface Controller). Each slave device 20 includes an event data register SDI, a serial data output 埠S D 0 , a serial clock 蟑 C L K and a wafer selection 埠CS. The serial data registration 珲SDI of each slave device 20 is connected to the data output SI 0 SI of the master device 10, and the data of each slave device 20 is outputted by SD0 and the master device 1 2009 200923656 The login 埠MISO is connected to each of the slave devices 2's serial clock bee. SCLK is connected to the serial device clock sclK of the master device 10, and the chip selection 埠CS of each slave device 20 is sequentially associated with the decoding I. The output beacon Y〇~Y 15 of 30 is connected, and the data receiving end D of the decoder 3 is connected to the slave device selection 埠ss〇 of the master device, and the inputs 埠A0~A3 of the decoder 30 are respectively connected to the master device. Ι〇之: One GPIO pin PIOO~PI03. In this embodiment, by using the four GPI0 pins PI〇0~PIO3 of the master device 10, the SPI bus bar can be expanded into sixteen groups, and thus sixteen slave devices can be connected, and the present invention is in the master device. The decoder 3 is designed to be connected to the slave device 20. The selected combination of the Gpi〇 pins PIOO~PI03 controls the decoder to enable the slave select 埠ss〇 of the master device 10 to pass through the decoder. The data receiving end D corresponds to one of the rounds of the decoder 3, and is transmitted to a corresponding one of the slave devices 2=埠埠cs, so that the slave device 20 and the master device 〇 Communicate. - The comparison table of the input port and the output port of the decoder 30 is shown in Table 1, wherein 0 represents a low potential selection communication number, 1 represents a high potential selection communication number, and Y represents an output of the decoder 3, as follows The sixteen selected communication numbers are respectively used to control communication between the slave device 20 and the master device 10 corresponding to the strobe of the decoder 30. ~ When the soil works, if the master device 10 is to communicate with the first slave device 2 through the spi bus, the master device 1 transmits the corresponding slave-to-slave device through the Gpi〇 pin ρι〇〇~ρι(1) Chip selection 埠CS selection communication number, 9 200923656. If A3~A0 = 0000, the decoder 30 assigns the signal of the slave selection 埠SS0 of the master device 10 to the first data receiving terminal D of the decoder 30. The slave device selection device 埠CS is used by the device 20, and the other slave devices 20 are not authorized to use the slave device selection 埠SS0 of the master device 10. At this time, the first slave device 20 has the right to use the SPI bus and communicate with the master device 10. . If the master device 10 is to communicate with the eleventh slave device 20 through the SPI bus, the master device 10 sends a selection signal number corresponding to the wafer selection 埠CS of the eleventh slave device 20 through the GPIO pins PIOO~PI03. For example, A3~A0=1011, the decoder 30 allocates the signal of the slave selection 埠SS0 of the master device 10 to the chip selection terminal CS of the eleventh slave device 20 through the data receiving end D of the decoder 30. The other slave device 20 does not have the right to use the slave option 埠SS0 of the master device 10. At this time, the eleventh slave device 20 has the right to use the SPI bus and communicate with the master device 10, and the other slave devices and the master device 10 The communication between the two is the same as the above, and will not be described again. Table I
A3 A2 A1 A0 Y 0 0 0 0 Y0 = D 0 0 0 1 Y1=D 0 0 1 0 Y2 = D 0 0 1 1 Y3=D 0 1 0 0 Y4=D 0 1 0 1 Y5 = D 10 200923656 οο ο 1 1 1οοο οο ο ο 1 ο 1 1 1 1 1 οο 1ο 1 1 ο 1 ~Υ8^γι〇ΐϋΥ12^ Yl4=D υι^ 透過本發明之實施方式，該主設備料過該GPK)引 腳PIOO〜PI03將選通訊號輸入到該解碼器3〇中 =ΠΓ主設備10之從屬選擇埠ss。之輪出訊ΐ 二二？：主設備10對應與一從設備20進行通訊。 該SPI通戒電路方法簡單、成本低。 綜上料，本發明符合發料利要件，綠法提出專 利以上所述者僅為本發明之具體實施方式，舉 凡沾悉本案技#之人士，在爰依本發明精神所作之等效修 飾或變化’皆應涵蓋於以下之申請專利範圍内。 / 【圖式簡單說明】 圖1為習知之SPI設備通訊原理圖。 圖2為本發明SPI設備通訊電路之較佳實施方式之原 11 200923656 . 理圖。 【主要元件符號說明 主設備 解碼器A3 A2 A1 A0 Y 0 0 0 0 Y0 = D 0 0 0 1 Y1=D 0 0 1 0 Y2 = D 0 0 1 1 Y3=D 0 1 0 0 Y4=D 0 1 0 1 Y5 = D 10 200923656 οο ο 1 1 1οοο οο ο ο 1 ο 1 1 1 1 1 οο 1ο 1 1 ο 1 Υ 8^ γι〇ΐϋΥ 12^ Yl4=D υι^ By the embodiment of the present invention, the master device feeds the GPK) pin PIOO ~PI03 inputs the selected communication number to the decoder 3〇=ΠΓsubordinate selection of the master device 埠ss. The round of the news ΐ 22? The master device 10 corresponds to a slave device 20 for communication. The SPI pass circuit method is simple and low in cost. In summary, the present invention is in accordance with the requirements of the present invention, and the above-mentioned patents are only specific embodiments of the present invention, and those who have been exposed to the present technology are equivalently modified in accordance with the spirit of the present invention. Changes shall be covered by the following patent applications. / [Simple diagram of the diagram] Figure 1 is a schematic diagram of the communication of the conventional SPI device. 2 is a schematic diagram of a preferred embodiment of a communication circuit of an SPI device according to the present invention. [Main component symbol description Master device Decoder