200922095 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種切換式調節器，特別是關於一種為 切換式調節器提供精準平均電流限制的電路及方法。 【先前技術】 通用序列匯流排（Universal Serial Bus; USB)的規範規 定’ USB在中止（suspend)模式下只能從上游埠抽取500# A，配置模式下為500mA ,而未配置模式下則是100mA， 且中止模式下的消耗電流不能超過500mA。這些規範是非 系重要的特性，因此，提供電流給Usb的供電裝置必須要 能提供穩定的輸出電流。 切換式調節器（SWitChing RegUlat〇r)是直流對直流 /DC)轉換器巾電轉換率最高，但電源潔淨度也最難 旱控的一^ ^ 由一 。无、^電源轉換技術者當知，切換式調節器係 換路控制其功率級中關的切換，將輸入電墨轉 圖1、繪示咸電抓，對輸出電容充電以產生輸出電壓，例如 者時種固疋盼脈切換式調節器的電感電流的波形， 成電产下2 CLK切換到低準位時，功率級被切換使得電 二:電感直::：…剩高準位，才又切 OC)電路，在^ 並配合電流過載（Over Current; 感電流下降。然=4相臨界料強迫切換功率級使電 和輸出電壓門換式調節器的電感電流與輸入電壓 楚間的關係有關，例如將切換式調節器做為充電 5 200922095 器來說，在一開始充電時，被充電端的電壓低，對充電器 而言即為其輸出電壓低，此時輸入電壓與輸出電壓之間的 差異大，電感電流大，但充電一段時間後，被充電端的電 壓會上升，對充電器而言即為其輸出電壓變高，換言之， 輸入電壓和輸出電壓變得接近，使得電感電流降低。因此 在輸入和輸出電壓之間的關係不固定的情況下，即使以峰 值電流(peak current)做電流過載觸發控制，切換式調節器 輸出的平均電感電流仍難固定。 圖2繪示一種藉由上下緣觸發控制之切換式調節器的 電感電流波形，電感電流上升到上緣時觸發電流限制使得 功率級切換，電感電流下降到下緣時，電流限制釋放，電 感電流再次上升，如此重覆使得電感電流在一範圍内變 動，但仍無法精準地控制電感電流的平均值。 因此，一種可以精準調控電感電流平均值的切換式調 節器及其方法，乃為所冀。 【發明内容】 本發明的目的之一，在於提供一種為切換式調節器提 供精準平均電流限制的電路。 本發明的目的之一，在於提供一種為切換式調節器提 供精準平均電流限制的方法。 本發明的目的之一，在於提供一種可精準調控平均電 感電流的切換式調節器。 根據本發明，藉由設置一感測元件感測切換式調節器 6 200922095 的電感電流而產生與其相關的第一訊號，一電流過載比較 器在比較該第一訊號與一輸入電壓而決定一過載訊號，一 濾波電路對該第一訊號濾波產生一第二訊號，一偏移電路 偏移該輸入電壓而產生一第三訊號，一電流過載誤差放大 器根據該第二訊號及該第三訊號之間的差值回授一補償 訊號給該電流過載比較器，使該電流過載比較器因應該補 償訊號調整其產生該過載訊號的條件。 【實施方式】 圖3係應用本發明的第一實施例，繪示一個升壓 (Boost)的切換式調節器，晶片20中的邏輯及驅動電路24 提供驅動訊號給MOS Si，使MOS S!導通或截止，輸入電 壓Vin被轉換成電感電流IL對輸出電容C〇ut充電以產生 輸出電壓VOUT，電阻RF1和RF2串聯組成一分壓電路， 提供一回授訊號給比較器28與參考電壓VREF相比較以 供邏輯及驅動電路26做回授控制，0C比較器24則用來 "ί貞測是否發生電流過載。本實施例在輸入電歷Vin和電感 L1之間插入一感測電阻Rs，以產生與電感電流IL相關的 訊號VA，VA=VIN- ILxRs。在本實施例中，當電感電流IL 高時，訊號VA低，因此，0C比較器24根據訊號VA是 否低於一臨界值而判斷是否發生電流過載，並據以提供過 - 載訊號給邏輯及驅動電路26，以強迫MOS Si關閉，降低 電感電流IL。訊號VA經電阻Rf和電容Cf濾波後，產生 直流訊號VB提供給0C誤差放大器22。另一方面，輸入 7 200922095 電壓Vin經電壓源VOF S偏移產生電壓VC ’ VC = Vin — VOFS，再由OC誤差放大器22根據VC和VB產生補償 訊號給OC比較器24。偏移電壓VOFS的大小係由電路設 計者決定’例如在預設感測電阻Rs為〇. 1Ω、電感電流IL 為0.5A時，計算得出感測電阻Rs上的壓差為LIxRs = 0.5A χ0.1Ω=0.05ν，此一條件下的VOFS即設計為0.05V。 OC誤差放大器22根據訊號VB及VC之間的差值產 生一補償訊號給OC比較器24，以改變OC比較器24發 出過載訊號的條件，藉以調整電感電流IL。 圖4繪示當系統穩定時，訊號VA、VB、VC與電感 電流IL、輸入電壓VIN之間的關係。電感L1將直流的輸 入電壓Vin轉換成電感電流IL。訊號VC為·—低於輸入電 壓VIN的直流訊號。訊號VA與電感電流IL反相關，電感 電流IL大時，感測電阻Rs上的壓差大，使得訊號VA小， 電感電流IL小時，在感測電阻Rs上造成的壓差也小，訊 號VA大。訊號VB係從訊號VA濾波產生的，因此雖有微 幅波動，但大致上而言是訊號VA的平均值。D是電流過 載的訊號，在VA低於預設值時切換到高準位。由於補償 訊號是根據訊號VB和VC之間的差值產生的，藉偏移電 路VOFS將VC設定為不同大小，可以改變電感電流IL的 平均值的設定值。 圖5係運用本發明之第二實施例，繪示一降壓（Buck) 的切換式調節器，本實施例之功率級的上橋MOS Pi及下 橋MOS S!都在晶片30中，特別地，本實施例利用上橋 8 200922095 MOS Pi導通時的導通電阻做為感測電阻。與圖3之實施 例相同地，OC誤差放大器32根據訊號VC與VB之間的 差值產生一補償訊號給OC比較器34，使OC比較器34 提供給邏輯及驅動電路36的電流過載訊號改變，藉以使 邏輯及驅動電路36切換上橋MOS Pi和下橋MOS Si的速 度改變，因而達到調控電感電流IL的目的。 除了圖3所示的電阻Rs及圖5所示的上橋MOS P1， 也可以使用其他電路及方法來產生訊號VA。例如，在某 些實施例中，電阻電容電路跨接到電感，可以感測出電感 電流。 不同的電路也可以用來充作偏移電路。例如二極體或 二極體串可以用來決定偏移電壓VOFS。 圖6繪示一種降低電感電流IL的方法，補償訊號使 得OC比較器觸發過載訊號的臨界值改變，例如將VA低 於0.55V觸發改成VA低於0.5V觸發，則峰值電流會降低 (0.05/Rs)安培，使得電感電流IL的平均值降低。 圖7則是一種提高電感電流IL的方法，補償訊號改 變過載訊號D的延遲，使得電感電流IL下降的時間延後， 因而產生較南的電感電流平均值’例如將過載訊號D延後 10ns送出，則峰值電流上升（電感電流斜率xl 0ns)安培。 【圖式簡單說明】 圖1係一種習知的固定時脈切換式調節器的電感電流 波形圖； 9 200922095 圖2係一種習知的上下緣觸發控制的切換式調節器的 電感電流波形圖； 圖3係根據本發明之第一實施例； 圖4繪示圖3中各訊號的波形； 圖5係根據本發明之第二實施例； 圖6係根據本發明降低電感電流的波形圖；以及 圖7係根據本發明升高電感電流的波形圖。 【主要元件符號說明】 20 晶片 22 OC誤差放大器 24 OC比較器 26 邏輯及驅動電路 28 比較器 30 晶片 32 OC誤差放大器 34 OC比較器 36 邏輯及驅動電路 比較器 38200922095 IX. INSTRUCTIONS: FIELD OF THE INVENTION The present invention relates to a switching regulator, and more particularly to a circuit and method for providing a precise average current limit for a switching regulator. [Prior Art] The specification of Universal Serial Bus (USB) stipulates that 'USB can only extract 500# A from the upstream port in the suspend mode, 500mA in the configuration mode, and in the unconfigured mode. 100mA, and the current consumption in the abort mode cannot exceed 500mA. These specifications are non-essential features, so a supply that supplies current to Usb must provide a stable output current. The switching regulator (SWitChing RegUlat〇r) is the DC-to-DC/DC converter with the highest conversion rate, but the power cleanliness is also the most difficult for drought control. No, ^ power conversion technology knows that the switching regulator is switching to control the switching of its power level, turning the input ink into Figure 1, drawing the salt and catching, charging the output capacitor to generate the output voltage, for example The waveform of the inductor current of the switch regulator is fixed. When the 2 CLK switch to the low level, the power level is switched so that the power is high: the inductance is straight:::...the high level remains. Also cut OC) circuit, in conjunction with current overload (Over Current; sense current drop. However = 4 phase critical material forced switching power stage to make the relationship between the inductor current of the output voltage regulator and the input voltage For example, if the switching regulator is used as the charging device, the voltage at the charging terminal is low at the beginning of charging, and the output voltage is low for the charger. At this time, between the input voltage and the output voltage. The difference is large, the inductor current is large, but after charging for a period of time, the voltage of the charged terminal will rise, and for the charger, the output voltage becomes high. In other words, the input voltage and the output voltage become close, so that the inductor is electrically Therefore, in the case where the relationship between the input and output voltages is not fixed, even if the current overload trigger control is performed with the peak current, the average inductor current of the switching regulator output is still difficult to fix. The inductor current waveform is controlled by the upper and lower edges of the switching regulator. When the inductor current rises to the upper edge, the trigger current limit causes the power stage to switch. When the inductor current drops to the lower edge, the current limit is released, and the inductor current rises again. The overshoot causes the inductor current to vary within a range, but it is still impossible to accurately control the average value of the inductor current. Therefore, a switching regulator that can accurately adjust the average value of the inductor current and its method are the same. It is an object of the present invention to provide a circuit for providing a precise average current limit for a switching regulator. One of the objects of the present invention is to provide a method for providing a precise average current limit for a switching regulator. One is to provide a switching type that can precisely control the average inductor current. According to the present invention, a first signal associated therewith is generated by sensing a sense current of the switching regulator 6 200922095, and a current overload comparator compares the first signal with an input voltage. Determining an overload signal, a filter circuit filtering the first signal to generate a second signal, an offset circuit offsetting the input voltage to generate a third signal, and a current overload error amplifier according to the second signal and the third The difference between the signals is fed back a compensation signal to the current overload comparator, so that the current overload comparator adjusts the condition for generating the overload signal due to the compensation signal. [Embodiment] FIG. 3 is the first application of the present invention. In an embodiment, a boost regulator is shown. The logic and driver circuit 24 in the chip 20 provides a driving signal to the MOS Si to turn on or off the MOS S!, and the input voltage Vin is converted into an inductor current IL. The output capacitor C〇ut is charged to generate an output voltage VOUT, and the resistors RF1 and RF2 are connected in series to form a voltage dividing circuit, which provides a feedback signal to the comparator 28 and the reference voltage. The VREF is compared for feedback control by the logic and drive circuit 26, and the 0C comparator 24 is used to detect if a current overload has occurred. In this embodiment, a sense resistor Rs is inserted between the input electric field Vin and the inductor L1 to generate a signal VA, VA=VIN-ILxRs, related to the inductor current IL. In this embodiment, when the inductor current IL is high, the signal VA is low. Therefore, the 0C comparator 24 determines whether a current overload occurs according to whether the signal VA is lower than a threshold value, and accordingly provides an over-load signal to the logic and The drive circuit 26 is forcing the MOS Si to turn off, reducing the inductor current IL. After the signal VA is filtered by the resistor Rf and the capacitor Cf, the DC signal VB is generated and supplied to the 0C error amplifier 22. On the other hand, input 7 200922095 voltage Vin is generated by voltage source VOF S offset to generate voltage VC ' VC = Vin - VOFS, and OC error amplifier 22 generates a compensation signal to OC comparator 24 based on VC and VB. The magnitude of the offset voltage VOFS is determined by the circuit designer. For example, when the preset sense resistor Rs is 〇 1 Ω and the inductor current IL is 0.5 A, the voltage difference across the sense resistor Rs is calculated as LIxRs = 0.5A. χ 0.1 Ω = 0.05 ν, the VOFS under this condition is designed to be 0.05V. The OC error amplifier 22 generates a compensation signal to the OC comparator 24 based on the difference between the signals VB and VC to change the condition in which the OC comparator 24 issues an overload signal, thereby adjusting the inductor current IL. Figure 4 shows the relationship between the signals VA, VB, VC and the inductor current IL and the input voltage VIN when the system is stable. Inductor L1 converts the DC input voltage Vin into an inductor current IL. The signal VC is - a DC signal lower than the input voltage VIN. The signal VA is inversely related to the inductor current IL. When the inductor current IL is large, the voltage difference across the sense resistor Rs is large, so that the signal VA is small, the inductor current IL is small, and the voltage difference caused by the sense resistor Rs is small, the signal VA is small. Big. The signal VB is generated by the signal VA filtering, so although there is a slight fluctuation, it is roughly the average value of the signal VA. D is the current overload signal, which switches to the high level when VA is lower than the preset value. Since the compensation signal is generated based on the difference between the signals VB and VC, the VC is set to a different size by the offset circuit VOFS, and the set value of the average value of the inductor current IL can be changed. FIG. 5 is a schematic diagram of a switching regulator according to a second embodiment of the present invention. The upper bridge MOS Pi and the lower bridge MOS S! of the power stage of the embodiment are all in the chip 30, in particular In this embodiment, the on-resistance when the upper bridge 8 200922095 MOS Pi is turned on is used as the sensing resistor. As with the embodiment of FIG. 3, the OC error amplifier 32 generates a compensation signal to the OC comparator 34 based on the difference between the signals VC and VB, causing the OC comparator 34 to provide a current overload signal change to the logic and drive circuit 36. Therefore, the logic and drive circuit 36 switches the speeds of the upper bridge MOS Pi and the lower bridge MOS Si to change, thereby achieving the purpose of regulating the inductor current IL. In addition to the resistor Rs shown in FIG. 3 and the upper bridge MOS P1 shown in FIG. 5, other circuits and methods can be used to generate the signal VA. For example, in some embodiments, a RC circuit is coupled across the inductor to sense the inductor current. Different circuits can also be used as the offset circuit. For example, a diode or a diode string can be used to determine the offset voltage VOFS. FIG. 6 illustrates a method for reducing the inductor current IL. The compensation signal causes the OC comparator to trigger a critical value change of the overload signal. For example, if the VA is less than 0.55V and the trigger is changed to VA below 0.5V, the peak current is reduced (0.05). /Rs) Amperes, which reduces the average value of the inductor current IL. FIG. 7 is a method for increasing the inductor current IL. The compensation signal changes the delay of the overload signal D, so that the delay time of the inductor current IL is delayed, thereby generating a souther inductor current average value, for example, delaying the overload signal D by 10 ns. , the peak current rises (inductor current slope xl 0ns) amps. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a waveform diagram of an inductor current of a conventional fixed-clock switching regulator; 9 200922095 FIG. 2 is a waveform diagram of an inductor current of a conventional switching controller with upper and lower edge trigger control; 3 is a first embodiment of the present invention; FIG. 4 is a waveform diagram of each of the signals of FIG. 3; FIG. 5 is a second embodiment of the present invention; FIG. 6 is a waveform diagram for reducing an inductor current according to the present invention; Figure 7 is a waveform diagram of increasing the inductor current in accordance with the present invention. [Major component symbol description] 20 Chip 22 OC error amplifier 24 OC comparator 26 Logic and drive circuit 28 Comparator 30 Chip 32 OC error amplifier 34 OC comparator 36 Logic and drive circuit Comparator 38