TW200921507A - Scheduling of background scrub commands to reduce high workload memory request latency - Google Patents

Abstract

A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of relatively light memory workload versus a period of relatively heavy workload. The memory controller provides a relatively higher priority for scrub requests near an end of a scrub period if scrub progress is behind an expected scrub progress.

Description

200921507 IX. Description of the invention: [Technical field to which the invention pertains] The large system of the invention relates to a memory controller in a computer system. More specifically &'' is directed to efficient scheduling of purge processing commands. This application is related to: 2007--Application of the US application serial number _ (agent case number ROC920070424US1), its title is five to seven prices & heart to do "sigh ^ Background Scrub Commands 〇 [previous technology] modern The computer system contains a memory and a memory controller. In a memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), the data stored in the memory can be corrupted, for example, by one or more forms of radiation. . This damage often presents itself as a "soft error". For example, a single bit in a read data block (such as a read cache line) can be read as "〇", and a single bit has been written as "1". Before passing the data block to the processor, the most modern computer system uses an error correction code (ECC) circuit to correct a single bit error (SBE> SBE can be a permanent error (memory or entity in the memory interconnect) Error), or SBE can be "soft error." Some modern computer systems can correct more than one error in the data block being read. For the sake of simplicity of explanation, this article will be described in terms of correcting a single bit error. The Ecc circuit in the present invention, but the invention is not limited to computer systems having an ECC circuit that corrects only a single bit error. The soft error in the memory is often corrected by a purification process. The cleansing area 133927.doc 200921507 refers to periodically Or read the data in other ways, correct any calibratable: error and write the corrected data back to the memory. The purification process prevents the early bit soft error from becoming ECC circuit over time. For example, it is important to correct the multi-bit error. For example, 'Assume that the ECC circuit (4) corrects the coffee, and the first soft error occurs in the specific cache line. The Ecc circuit can correct the coffee and send the correction data to the processing. g. In addition, 'assuming that the _ soft error is uncorrected and after a period of time 'a second error (hard or soft steep error $) occurs in a particular cache line. Hard ', the error is a permanent error, for example , disconnected signal connector or failed driver or receiver. ECC circuit can not correct the error! Capture line ' and report the error has been detected, but can not be corrected, which may lead to faster request The termination of the task of the line, the restart of the computer system. Therefore, in order to reduce the possibility of uncorrectable multi-bit errors, the memory is processed in the specified purification process cycle. For example, in two or four hours. The entire memory of the purification processing computer line in the purification processing cycle specifies the memory reliability rate according to the completion of the purification process in the specified cycle. The hidden memory controller determines the connection to The memory of the memory controller is set to purify the entire amount of the servo cleaning process required during the purification processing cycle (for example, one day) and to clean the processing interval. Knife and animal husbandry for the net memory control H through the order The entire number of purification treatments required, a person's purification treatment order, which needs to be cleaned during each purification treatment interval. 133927.doc 200921507 Service-purification treatment = Figure 3Α and Figure 3Β, at a specific purification treatment interval During the production interval, if the servo purge processing command does not affect the normal read command issued by the second = (or in some cases, write the second command: this is done. If the first cleansing interval is at the first cleansing interval)仏 间 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 尚未 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 』 Processing requirements '祠服净化#理服°Get and write) Normal command stream. The demand purification process reduces the computer system = the second recovery to increase the read and write requirements of the delay == the amount of delivery, because this is done by drawing the process. Into ^ chat. In the diagram, during the purification process, the process of the process is shown as a straight line during the purification process cycle (for the purpose of the illustrative goal, the positive cycle of demand is one day). The memory 贞 is shown to increase at about 8 am, remain relatively high straight = handsome, and then gradually decrease. Between time and time (10), memory: The workload is relatively light. Between the time axes, the 'memory demand work is too heavy, and often occurs during the first cleanup interval of the purification process interval. In order to maintain a straight line "process", it is necessary to perform a purging operation in the second purification processing sub-interval of the money processing interval. The bow 1 is required to perform the purging processing request, and the reading request and the writing request issued by the processor wait. SUMMARY OF THE INVENTION In one embodiment of the present invention, a purge processing slack value is determined. 133927.doc 200921507 The purge processing delay value indicates whether the purification process progresses before or after the desired purification process is performed at a given time. The memory workload is determined at any time by dynamically measuring the workload or by using a predetermined estimate of the memory workload. The memory workload can be dynamically determined by reading in the memory controller or reading the fullness _ness of the queue. If the array is read and/or written in the basin, Relatively full, (four) heavy. The purification process priority is adjusted in response to the purification process and the memory workload. Advantageously, when the memory H load is relatively light, the memory controller attempts to "exceed" the desired purge process by servoing more purge processing requirements during a given time interval. When the memory workload is relatively heavy, the memory controller servo is relatively less cleaned to reduce the read and/or write latency associated with the read and write requirements issued by the processor. Further, if the purification process lags behind the desired purification process while the purification process is near completion, the purification process priority is increased so that the memory controller completes the entire memory purification process during the purification process cycle. In a practical example, the cleaning process priority is adjusted by extending or shortening the purge processing interval. In one embodiment, the first purification processing subinterval and the purification processing requirement during the purification processing request having the first priority relative to the read and/or write request are higher than the first priority by changing the purification processing interval. The second priority is adjusted relative to the allocation between the read request and/or the second cleanup processing subinterval during the write request period. [Embodiment] 133927.doc 200921507 In the preferred embodiment, the w-phase description towel is described in detail with reference to the accompanying drawings, and is shown by way of illustration in the accompanying drawings. Particular embodiments of the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. Referring now to the drawings (and in detail, Figure _. Figure i), the computer system 100 is shown. The computer system (10) includes - or a plurality of processors 102, and processes the processor to the memory controller 106.

L = the hub 105, and is consuming to the memory 1 〇 8 of the memory controller 106 by the memory bus 1 〇 7. The memory ι 8 further includes a memory chip i H) (shown as a memory chip iU - or a plurality of memory levels U2 (shown as a memory hierarchy. The memory chip 11 is usually called a DRA) Dynamic Random Access Memory (DRAM). As shown in Figure 2, each memory chip includes one or more memory banks (1) (shown as memory banks 111a_llld). Memory 13⁄4 layers 112 and 5 I remember the library! i! is an example of a memory component. The memory cell is a memory accessed during the servo request by the memory controller 1G6 for the read request, write request, or contention processing request. Units. For the purpose of explanation, the memory hierarchy 112 and the memory bank ln will be used as examples of memory components in this document. It should be understood that a typical computer system! 〇〇 further includes many other components, such as network connection facilities, The sheet and disc controller, the user interface and the like are well known and the discussion thereof is not necessary for the understanding of the embodiments of the present invention. Turning now to Figures 4A to 4D, see this article Implementation of the invention to be described 1 33927.doc

Fig. 4A shows a purification processing interval 13Q which is divided into a first purification processing sub-interval (1) and a second purification processing sub-interval 134, and a second purification processing starts at a purification processing demand start 135. In the purge processing interval (3), if the read delay is not increased (and in some embodiments, if the write delay is not increased), the purge processing request is performed. In other embodiments, the 'first purification process priority' is during the first purge process subinterval, and the I second higher purge geography priority is actually during the second purge process subinterval. In an implementation, if the duration of the purge processing interval is θ, χ, the %-purification processing interval elapses after "X" seconds, and immediately after, the processing interval. In an alternative embodiment, if Purification „ ^ Your Coin – Purification treatment requirements during the purification treatment interval, then the completion of the purification treatment requirements of the servo, 200921507, 纟 果 fruit level summary. Figure 4A shows the desired progress line indicating the desired sentence in the process of purifying the memory in a predetermined purge processing cycle (__day in the example of Figure). If the rate is higher than the average purification rate, the percentage of the purification process at any given time will be expressed as the first 131" in the region. On the other hand, if it has been executed at a given time. The percentage of purification treatment processed by a given time is less than the average expected process and is marked as "after i32" in the region. During times when the memory workload is low, embodiments of the present invention provide a purification process at a faster rate than the average rate, reading into the front region, the first (1) region becoming higher, or attempting to escape after the i field . If the memory is heavily loaded and the percentage of the memory being cleaned is in the first 131 area, then the lower purge can be purged, μ is achieved with respect to read requirements (and in some implementations and situations) The lower latency of the write request). I33927.doc 200921507 π is the same as the beginning of the four purifications short 4 s _3 Q _ long or shrink, 'w processing interval 13G will cause an increase in the situation that must be processed in the reading or writing service requirements, thereby increasing Purification rate. The purification treatment rate is the rate at which the purification treatment is performed, for example, = purification treatment. It is also possible to increase the purification processing rate by lowering the first cleaning processing subinterval and the fourth processing subinterval (four) (ie, moving to the left in the _), increasing the purification processing rate, which is caused by the second More time is spent in the processing subinterval, during which time the delay of writing 'may also be selected for the cleaning process for the feeding service = two to increase the duration of the purification treatment interval 130 and / or to increase the first purification interval The ratio of the second purification treatment sub-interval will reduce the purification treatment. The embodiment of the present invention provides the first purification treatment requirement presented to the requirement selection description) and the second purification=second=the purification treatment requires the force to be enhanced. Medium rate, =: required (or possibly, write request) delay of the sheep to increase the purification process rate. Expected 彳壬hhs purification treatment requirements. It is expected that any number of simultaneous presentations == what use Memory work during the purification process cycle = "purification process rate. In the second example of Figure - "normal operating hours" (shown as approximately 8 p) is significantly higher. The purification treatment cycle is defined as starting at approximately 133927.doc -12- 200921507 pm 'and stylized purification treatment The rate (e.g., by shortening the purge processing interval 130 and/or increasing the: purge processing sub-interval 134). The purification process progresses without progress in Figure 4C at a relatively high purge processing rate "slope A". During the expected higher workload during the usual hours, the purification process interval 130 or "rightward" mobile purge process demand begins (i.e., reduces the first-purification process interval 133 and the second purge process interval). 134 ratio) and reduce the purification process rate to "slope B," in negative memory work

The purification process at the rate of "slope B" is displayed during the loading time. In one embodiment I'm moving the purge processing requirement 135 such that the second purge processing interval 134 is zero, in which case no purification processing requirements are required, and only if the purification processing requirements do not affect the read # (and possibly write) Servo purification processing requirements only when the delay is entered. Usually, the write request is accumulated in the write queue, and the write request is servoed with a lower priority than the read request. However, if the write queue becomes full, the processor can stop 'because it can no longer transmit new write requests. Therefore, when the write queue becomes almost the same, some memory controllers will increase the write request priority. In many cases, purification processing requirements can be performed without affecting the read (or write) requirements. For example, referring to Figures 1 and 2, the first read request is transmitted and will be handled by the memory bank (memory bank) of the memory chip 11 in the memory hierarchy 112. Depending on the particular memory chip technology, it will take many read request cycles. After the reading is completed, the memory bank (11 la) can be closed. At this time, the read data must be written back to the memory bank, and the bit line must be recharged, which takes extra time. Therefore: B3927.doc 200921507 The memory controller can't send the second read to the memory level u 2〇 in the double-talker's request selector loop (δ 隐 hidden library Ilia (memory bank) ). However, the right 'purification processing requirement will be π π 4 to the different memory of the 5 memory level or even the memory level 1120. The net servant bundles the seven stocks (lub, Ulc, llld), Bay, J can The servo is cleaned up and the processing requirements are not affected (4).

(4) Computer system HH) is likely to have a large memory matrix ιΐ2. It has been 108, so the embodiment of the present invention can be improved by simultaneously: many purification processes are required to be issued to different memory levels and/or memory (4) without affecting the reading requirements (or writing requirements). For example, if the memory 108 has eight memory levels 112, then a purification process is required for each of the memory levels 112. Or an embodiment issues a cleansing request from each of the memory banks ln of a particular memory hierarchy 112. In addition, the implementation of the fiscal, for each of the memory layer 112 of each memory bank 丨丨i issued a simultaneous purification processing requirements. Another advantage of simultaneously purging purification requirements from multiple memory levels and/or memory banks is the early discovery of mechanical or electrical problems. For example, in the previous memory controller, the purification processing requirements are issued one at a time, moving to different memory levels! Step 12 passes through all of the memory banks U1 in the particular memory level layer 112. It is assumed that the purification processing cycle is in hours and there are twelve memory levels 112. A poor connection or a bad receiver or driver on a particular signal at the memory level will be detected during the 22nd hour of the purification processing cycle during the purification process until the 12th memory level is finally cleared. In the case of the described embodiment (with purification processing requirements from different memory levels and/or memory banks), it is determined that each memory hierarchy will have a frequent basis. At least the purification treatment requirements of the above feeding, and the failure should be faster. Fig. 4D illustrates another embodiment of the present invention in which the purification process is increased as the memory king is negative (four) small and (4) the memory workload is increased to reduce the purification process rate. Based on actual memory workload relative to

The shape of the memory workload described by the deduction is estimated to be (4) net prior weight. W f Figure 5 shows a block diagram of the memory controller 1〇6. The processor bus 〇5 connects the 5 memory controller 106 to the processor 1〇2, as shown in the figure; the memory bus 1〇7 connects the memory controller bay to the memory 1〇8 1; it should be understood that 'in various implementations' a buffer wafer (not shown) may be used to buffer the transfer to or from the memory chip 110. 俨==body_1()6 contains Storing the material issued by the processor (10) 121 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H The memory controller 1〇6 LLi φSpecially requires the net processing of the purge processing requirement (in the embodiment, multiple purification processing requirements) during the selector cycle. ^15125^ The intrusion and purification processing requirements conflict. The selector 124 is required to select the request and the self-cleaning processing unit 125 during the request cycle of the selector 12 or the self-cleaning processing controller 125. The memory of the specific memory hierarchy of the memory 108 is Μl 疋"The hidden library selector loop;; Γ can be asked as an example of 'in-request 顼$ I *, The requirements and the two purification treatment requirements are presented as the selector 124, and at the end of the cycle of the selector is required, the 133927.doc -15-200921507 selector 124 is required to be in the memory busbar! A selection request from the reading request and two purification processing requirements is issued on 〇7 (Fig. 5).

The conflict register 1 29 knows when each request is sent to the memory 1 〇 8 and to which memory level u 2 and memory bank 丨 n each request is issued. In addition, the conflict queue 129 knows that each request will occupy the duration of the memory hierarchy 112 and the memory bank π 1 to which the request is issued, and will prevent the requesting descendants 124 from issuing subsequent requests to the memory class i 12 and The memory bank 111 is available until the memory level and the memory bank are available again. The memory controller 106 includes an ECC (Error Check and Correction) 12〇 that will correct the first number of bits having errors read from the memory 108 and will have the detection read from the memory 108. The second digit of the wrong number. The ECC 120 ensures that all data sent back to the processor 1〇2 on the bus 1〇5 is correct, or that the ECC 12〇 cannot correct the data read from the memory 1〇8. The ECC 120 is also used during the purification process to correct any correctable bit in the data prior to rewriting the data read during the reading of the purification process request into the memory 1 8 yuan. During the purification process, the purification processing controller 125 remembers which memory hierarchy has been detected and the repetition of the memory bank 4 from a specific location (4) is recognized by the purification processing controller 丨 25 and can indicate that the memory 1 〇 8 can be ^ is a faulty data bit, a faulty wire, a faulty drive, or a defective location with a (iv) receiver. The purification process controller 125 may include some or all of the following: a 21 〇, a purification process prioritizer 212, a purification process state 214, and a two-load monitor 216, each of which will now be described, and This will be described in more detail in the line 133927.doc •16- 200921507. The cleanup process controller 125 can include a time instant 210 (such as a clock or access to a clock elsewhere in the computer system 100). Time 2 10 is used in the embodiment of the memory controller 1 〇 6 that adjusts the purge processing rate based on a predetermined estimate of the memory workload. The purge process controller 125 can include a workload monitor 216 that monitors the busyness of the memory system 108 and the purge process controller ι25 adjusts the purge process rate accordingly.

The purification process controller 125 includes a purge process state 214 that may be retained in the memory 108, in each memory level 112, and/or in each memory bank 111 of each memory bank 112. The rate of memory. The purge process controller 125 includes a purge process prioritizer 212 that issues one or more purge process requests to the demand selector 丨24. The purification treatment state 2丨4 is now shown in more detail with reference to Figs. 6A to 6D'. FIG. 6A shows purge processing state 214 as including memory state 173 and memory hierarchy state 181 for each memory level in memory 108. Memory state 173 is shown in more detail in Figure 6B. The total number of memories 174 contains the total number of purification processes that must be performed during the purge processing cycle for the entire memory 108. The cleaned memory 175 is reset at the beginning of the purge processing cycle and is incremented each time the servo purge process requires it. The percentage of total memory cleaned is the memory 175 of the cleaned process divided by the total number of memory 174. The purge processing interval 176 maintains the value of the duration of the first purification processing subinterval I33927.doc 200921507 177 that can be used to specify the first purification processing subinterval 133 (Fig. 4B) and can be used to specify the second purification processing subinterval 134 (Fig. 4B). The value of the duration of the second purge processing subinterval 178. As explained earlier, the duration of the first purge subinterval and the second purge subinterval can be adjusted to increase or decrease the purge processing rate. When the memory state 173 is used by itself (without the additional "to be described below" by the memory hierarchy and/or "from the memory bank"), the purification processing rate can be adjusted, but only in the memory 108 basically. FIG. 6C illustrates one embodiment of a memory hierarchy state 181. In the embodiment in which the purification processing state 214 uses the memory hierarchy state, the purification process is maintained by the memory hierarchy, which is used to prioritize the backward memory hierarchy. For example, if the memory level 丨12^ is cleaned by 8〇%, but the memory level 1123 is only 4%% cleaned, the memory level HI should be increased relative to the memory processing rate of the memory level ΐ2〇. Purify the processing rate. The total S 1 84 contains the total number of purification processing requirements that must be servoed to complete the cleaning process of the memory hierarchy. The cleaned memory layer 185 is reset at the beginning of the purge processing cycle and is incremented each time the servo is required for the purification process of the memory hierarchy. The percentage of the purification process done in the memory hierarchy is the value of the memory level of the cleaned process divided by the total number of memory levels of 184. The purge treatment interval 186 contains the first purification that can be used to control the duration of the first purification treatment sub-interval 133 and the fifth purification treatment sub-interval IB as described above, as required for the purification treatment of the transient § memory layer hierarchy. The subinterval 187 and the second purification processing subinterval 188 are processed. The memory hierarchy state 181 can further include a plurality of memory banks 183' which can be used to control the purification processing rate by the memory bank lu in the memory hierarchy 112. 133927.doc -18- 200921507. A block diagram showing the state of the memory bank 183. Memory bank status (8) 匕 “The total number of memory banks 194, which contains the total number of purification processes that must be performed during the purification process. The record of the purification process (4) Library 195 at the beginning of the purification week” (4) Whenever the servo is required to purify the memory bank, it is incremented. The ratio of the memory processing done by the memory bank to the memory bank is the ratio of the memory bank 195 and the total number of memory banks (9). 196 includes a first purification processing subinterval 197 and a second purification processing subinterval 198, which may be used together with the other first subintervals and second subintervals described above to increase or decrease the purification processing rate of the memory bank. "The above discussion has described an example of the overall rate of purification processing that can control memory 1〇8, either by the δ-remembered hierarchy 1丨2 or by the memory bank lu β θ in each memory hierarchy. The figure shows a workload monitor 216. The workload monitor 2i6 provides an indication of how busy the memory 108 is. Figure 7 shows a workload monitor 216 that uses the full scale 161 of the read queue to determine the full extent of the read queue 121 and uses the full scale 162 of the write queue to determine the full extent of the write queue 123. The fullness of the read queue 161 remembers that the number of entries in the read queue 121 is relative to the capacity of the read queue 121. As shown in Figure 5, the read queue 121 has a space for storing "η" requirements. The zero request to "η" value indicates the number of read requests that are present in the read queue 121. If the read queue i 2 is full or almost full (as indicated by the full scale of the read queue 16 ,), then the memory 1 〇 8 is busy. Similarly, the write queue 123 is shown to be useful. In the space of "m" items, 133927.doc •19- 200921507 and the value of zero to "m" indicates the number of items currently present in the write queue 123. The full scale of the write queue is 162 to some A mode (e.g., a fraction of the maximum capacity) indicates the degree to which the write queue 23 is full at a given time. If the read 伫 = 121 and the write queue 123 is relatively empty (for example, each is four) The memory system 1 具有 8 has a relatively low memory workload, and the workload determiner 163 reports this on the cleanup processing priority 164. The cleanup processing priority 164 can be a single bit Meta (for example, "〇" is "not busy

And "1'' is, busy"), or may contain a plurality of bits to indicate only the memory operation: the degree at which the given time is light or heavy. In general, as the read <dot fullness 161 and write rank fullness 162 report increased full-scale processing priority 164 report memory red load is increasing, and the purification processing rate is correspondingly reduced Small (for example, by adding a plurality of purification processing intervals by the purification processing controller 125, "the whole one or more first-purification processing sub-intervals and the respective second purification processing intervals t + i = i intervals" Ratio or even elimination - or multiple second purification processing sub-intervals). And (d) purification treatment priority 164 should be required to select the selector "column, using two-dimensional purification processing priority 164, beans in" "〇〇&quot Work negative ruling||Not very complicated TM, meaning that the memory work can be sent two: Γ processing priority 164 is "〇 °", when the selector 124 is required to find == two (even if the purification processing requirements affect three Reads can be issued, Γ: / priority 164 is "°1", which requires selection (10) processing requirements (even if the purification processing requirements affect two readings; =); purification processing priority is, Then ask for a coffee ^, processing requirements (if purification treatment requirements) The reading requirement 133927.doc -20- 200921507 =) The virtual purification processing priority is "11", the selector is required to not send the Japanese word processing to the axis to do so, then the impact-reading request is delayed. As described earlier, the write request is handled with a lower priority to > until the write queue begins to become quite full. (Two-body: Allows the purification process to increase the read requirement when the load is light: 乍7::: The delay is acceptable because when the memory is read, the same read requirement will usually have to wait for many other read requests on the servo. Wait for one or pre-processing requirements. It will not delay the read request delay that will be incurred during the time when the heavy memory is loaded as a load. The pre-determined read request requires a predetermined number of pre-purification processing requirements: :)) equals new The purification process requires an average number of read requests that will be expected to wait during the heavy memory workload time. ^Describes the 'cleaning process requirements during the period of the memory::light time period during the memory: or during the period of the heavy memory work, the servo cleaning process request instead of reading The request will reduce the delivery of I^IGG1. Further, if the processing progress is at the end of the purification processing cycle at "after||, the purification processing rate must be increased to complete the purification processing before the end of the purification processing cycle. Therefore, the purification process optimizer 212 advantageously includes the memory workload and the first (1) " or, the latter two and the amount of time remaining in the purification process cycle to determine ', " Therefore, detail the above examples with the two-dimensional purification treatment priority, including the burden and quantity "first 131" or "post 132" information together with the time left in the purification geography cycle, consider the next paragraph Example. 133927.doc 21 200921507 Again, using the two-dimensional purification process priority 1 64. For the first half of the purification process, when the purification process priority is "〇(Τ,"0Γ,, '1〇" and "11", the purification process requires relative to reading (or possibly, writing The processing required is as in the above example. For one quarter of the purification treatment cycle (that is, the purification treatment cycle is between 5〇% and %), if the purification process is in the process More priority must be given. When the purge treatment priority 4 is 00, the selector 124 is required to issue a purge treatment request (even if the purge treatment request affects the delay of the two read requests). When the purge treatment priority is " When 01", the selector 124 is required to issue a purification processing request (if the servo cleaning requirement affects the delay of five or less readings (writers) required). The processing priority is "丨〇" The selector 124 is required to issue a purification processing request (if the servo cleaning processing requirement affects the delay of three or more reading (writing wide) requirements). When the purification processing priority is "", a selection is required. Hair purification Requirements (if the servo cleaning process requirements will affect one, zero read (write) requirements). After the last quarter of the purification process cycle 1 right 'contention process is in,', then must be cleaned The processing rate is relatively high compared to the γ turbulence, so that the net Ifci treatment is completed before the end of the purification treatment cycle. 求. Selecting the choice 'When the purification treatment priority is 〇〇,,, Processing requirements (if the servo purification processing requirements will be first (write) requirements). When the purification treatment is selected as 124, the purification treatment requirements can be issued (even if the servo purification processing requirements will affect the demand). Apricot, Qin π * The next ten-to-six read (write) to the field purification treatment priority is 丨1〇丨 processing requirements (ie, I want to choose the benefit m can issue a net 1 service money processing requirements will affect people or eight to J33927 .doc -22- 200921507 Under reading (writing) requirements). When the purification treatment priority is (1): What is the requirement for the purification treatment of the device 12 (even if the feeding service is cleaned at two or two == or four or less readings (writing) )))) purification treatment The prioritizer is guilty of using the current purification process lags "after" prioritization of the desired process value/1 prioritization of the purification process. If the purification process (for example) only ^4 is expected, the process does not have to be performed The significant purge treatment rate increases until it lags behind during the purge treatment cycle. Referring now to Figure 5, the purge process prioritizer 212 sends one or more purge process requests to the demand selector 124 at a time. As described earlier, the complex number is transmitted. At the same time, the requirement is to increase the probability of at least one of the servo-cleaning processing requirements without the delay of feeding (or possibly, writing) (even when the memory workload is relatively high). In addition, as described earlier, the transmission of the purification processing request from the plurality of memory levels U2 may increase the discovery of the driver earlier than the completion of all the purification processing in the first memory level before starting the purification processing at the second memory level. The probability of a problem with the receiver or interconnect. In one embodiment, the decontamination process prioritizer 212 uses only the purge process state 214 and transmits - or multiple purge process requests, and (d) corresponds to the duration of the first purge process subinterval and the second purge process subinterval. In the second embodiment, the decontamination processing prioritizer and the corresponding first decontamination processing subinterval and the second decontamination processing subinterval are sent to each of the __memory levels (1) to be cleaned to help ensure a memoryless hierarchy.丨丨 2 is allowed to lag significantly behind other memory classes. For example, assume that the first memory level ιΐ2 contains millions of cache lines that must be cleaned, and the second memory level layer only has 256, cache lines that must be cleaned. As explained above, 133927.doc -23- 200921507 explains that the per-memory level m has a purification treatment rate of a percentage of the purification treatment performed therewith. If the first memory level 112 and the second memory level 112 have an equal number of performed purification processes during the time period, the first memory level 112 will lag behind as a percentage of the purification process performed. Then, the first memory level is given a higher purification processing speed t (for example, 'by shortening the purification processing interval 13 〇 for the first memory level U2' or by relatively increasing the first memory level ι ΐ 2 The second > (10) intervals 134)' to servo the more clean processing requirements for the first memory level "2. Or 'reporting the first-memory level U2 on a percentage basis"trailing" post-purification processing prioritizer 212 issues a purification process request for a plurality of memory banks (1) of the first memory level 112 and only A one (or none) purge processing requirement for the second memory level m is issued. A high level flow chart showing an embodiment of the method of the present invention. Method · Start: Steps follow. In the step, the purification processing retardation value is determined. If the purification = sluggish value is "positive", then the purification process " advance scheduling,, that is, in the area before the map (3). If the purification processing delay value is " negative purification treatment, backward row Light". / cow / that is, in the area shown in Figure 4A as the latter (1) is not currently busy dealing with: Has: Γ: wide its indication _ is 罝 has been issued by the processing state for reading (and possible = body ^ ^ In step 708, the purification processing delay value and the = body workload are used to adjust the purification processing rate. If the memory workload is relatively low, it is necessary to pull and take the cleaning processing requirement to be more than a certain number of readings. ;^'Writer) requires priority to increase the purification rate. If the memory workload is relatively high, then the purge processing rate is reduced, which allows very few 133927.doc -24- 200921507 number (if any) purification processing requirements to add a delay to the read (or possibly, write) requirement. Similarly, if the purge treatment retardation value begins to become more and more negative, the purge treatment rate is increased to "catch" so that the entire S memory will be cleaned during the purge treatment cycle. The memory workload can be measured dynamically, or an estimate of the § memory workload can be stored in the system, for example, as described earlier, by time. 9 is a flow chart showing the more detailed steps of step 704 of FIG. Step 710 begins with a more detailed embodiment of step 704. Step 712 determines the total memory (the number of data blocks, e.g., the cache line) to be cleaned in the total memory of the computer, in the memory hierarchy, or in the memory bank. Step 714 determines the percentage (percentage) of the total memory to be cleaned that has been cleaned up in the -cleaning process cycle. For example, if one million is needed, the purification process is to completely purify a memory and 5 〇〇 has been performed, the _ human purification process '% has completed the purification process for the memory 5 (4). Step (4) 6 determines the fraction (percentage) of the purge treatment cycle that has elapsed. For example, „ 'The right purification treatment cycle is twenty-four hours and six hours have elapsed since the beginning of the purification treatment cycle'. The purification treatment cycle is completed by 25%. Step: m is subtracted from the fraction of the self-purified purification process. The elapsed rate of the processing cycle is judged (purification processing delay value. For example, if the purification treatment is 〇. 7 5 忐曰 忐曰 鬼 鬼 鬼 鬼 处理 处理 处理 处理 处理 处理 处理 处理 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳 彳Other implementations of purifying the rate n of the purification treatment delay value are possible. For example, the fraction of the treatment divided by the completed purification treatment cycle is divided by the above example 7^ sex fraction, 0·7, .50=1.50 In this case 133927.doc •25· 200921507, exactly the desired process line in Figure 4A will have a value of one, rather than the “positive” or “negative” delay caused by the subtraction. In, before " More than __; in "after" will be compared to -* 〇 step 719 to complete the expansion method of step 7〇4 to determine that the purification process is slow. Figure 10A shows the first step 7〇6 (Fig. 8) in more detail. An embodiment, which is represented as 706A in FIG. 1A, begins at step 720 In step 722, a measure of the fullness of the read queue is performed. For example, if the read queue has a fixed read request position and currently holds four read requests, the read queue is eight points. One is full. Step 724 similarly determines the fullness of the write queue. Step 726 similarly determines the fullness of the conflict queue in the implementation with the conflict queue. Step 728 uses the read queue, the write queue, and The value of the conflict 伫 fullness is used to determine the negative 胄. If the 仔 或 或 或 或 或 或 或 或 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若 若Or almost empty, the memory workload is relatively light. Step 729 completes the expansion method of step 7 。 6. Figure 10B provides a second embodiment of step 706 (Figure 8), which is represented in Figure _ as 7 嶋. 730 starts method 7〇6B. In step 732, the time is determined by reading the time clock. In step 734, by using the time determined in step 732 and the memory of the memory stored in the computer system Preload estimation of the load to determine the memory workload, the case mouth, to the workload The method relative to the time table or equation is sought. Step 739 ends the method 7. Figure 11 is an extension of the step 7G8 (Fig. 8) for adjusting the purge processing rate. The method 708 begins at step 75. In step 7 5 2 , using # a* . Han used '• 隐 hidden body workload and purification delay value to 133927.doc -26 - 200921507 Adjust the duration of the purification treatment interval (4) 1 mitigation indicator purification treatment when ° right purification treatment late - time amount two The net::::: the interval is shorter, the more the cleaning processing interval is: the second writing requirement) the delay is the cost and the purification process is forcibly (or possibly, and the cleaning process interval is changed to the first purification process) The subinterval handles the allocation within the subinterval. If it is relatively long, the possibility of selecting a purification processing request in the read processing is increased (W, in order to be selected in step 756, by requiring a selector (such as shown in FIG. 5). It is necessary to long. $ (2) to receive one or more net "^-sa. ^ where the clothing is needed. Advantageously, by = several purification processing requirements (for different memory levels, nesting彳& This table sees at least one purification treatment in the case of not affecting the delay of reading (or possibly asking for .·, )

Ci can be used to determine whether the ship can be cleaned without affecting the reading (or two 'persons) requirements. If so, the servo cleaning process is required in step 762; if not, the step Judgment: 匕 processing demand period (that is, 'second purification processing sub-interval) is active. Right, then, by step 762, the servo purification processing is required to be U, and the cutting service reading request (or possibly, the writing request) It should be noted that the method of interpreting the graph U for the sake of explanation. As explained earlier, depending on the workload and the sluggish processing delay, if the memory workload is reported to be light, step 758 may branch to step 762. Servo purification processing requirements (even if - or multiple readings (or I33927.doc -27· 200921507 can be 'written') is about to occur. [Simplified schematic] Figure 1 shows the inclusion of the processor, memory hidden A block diagram of a computer system with one or more memory levels. Figure 2 shows a block diagram of a memory chip containing one or more memory banks used by the computer system of Figure 1. Figure 3A and Figure 3B for the description in advance A prior art diagram of the operation of a conventional memory controller that maintains a clean process during a purge process. Figures 4A-4D show how an embodiment of the present invention provides a feed comparison during a relatively light memory workload cycle. Multiple purification processing requirements and less robust purification processing requirements during a relatively heavy memory servo load cycle. Figure 5 is a memory control block diagram suitable for use in the computer system of Figure i. Figures 6A-6D show various A block diagram of a memory cleanup process state. Figure 7 is a block diagram of an embodiment of a workload monitor suitable for use in a memory controller. Figure 8 is a high level diagram illustrating the rate at which servo cleanup processing requirements are adjusted for a memory workload. Fig. 9 is a flow chart showing how to determine the value of the depletion processing delay. Fig. 10A and Fig. 10B are flowcharts showing how to determine the memory workload. <Fig. 11 shows the use of the memory demand and the purification processing delay. Flowchart of information to adjust the rate of servo cleaning processing requirements. 133927.doc -28- 200921507 [Key component symbol description] 100 Cerebrospinal system/computer 102 processor 105 processor bus 106 memory controller 107 memory bus 108 memory 110 memory chip 11 memory chip 〇n-. memory chip 111a memory bank 1 lib Memory bank 111c Memory bank llld Memory bank 112 〇 Memory level 112m., Memory level 120 ECC (Error check and correction) 121 Read queue 123 Write queue 124 Request selector 125 Purification processing controller 129 Conflict queue 130 Purification processing interval 131 Front 133927.doc -29- 200921507 f 132 After 133 First purification processing subinterval 134 Second purification processing subinterval 135 Purification processing demand start 161 Reading the fullness of the array 162 Write 伫Column fullness 163 Workload determiner 164 Purification processing priority 173 Memory state 174 Total memory 175 Purified processing memory 176 Purification processing interval 177 First purification processing subinterval 178 Second purification processing subinterval 181 Memory Hierarchy status 183 Memory bank status 184 Total number of memory levels 185 Memory of purification processing Level 186 Purification processing interval 187 First purification processing subinterval 188 Second purification processing subinterval 194 Total memory bank 195 Memory bank for purification processing 196 Purification processing interval 133927.doc -30- 200921507 197 First purification processing subinterval 198 Second Purification Processing Subinterval 210 Time 212 Purification Processing Prioritizer 214 Purification Processing Status 216 Workload Monitor 133927.doc -31 -

Claims (1)

200921507 X. Patent application scope: 1. A method for purifying and processing a computer containing a reading method of th W, which determines a purification processing delay value; determining a memory workload; and determining a delay value according to the purification processing And the purification treatment rate. The step of adjusting the delay value by the load is as follows: 2. The method of claim 1 determines that the purification processing step includes the following steps: a processing period; determining that one of the memory periods must be cleaned and processed during the cleaning process. The total amount of the pure field must be periodically determined in the cycle to determine the amount of the memory that has been cleaned; to determine the desired process for purifying the memory; and: to compare the amount and purification of the memory by the purification process The desired process of the memory is processed to determine the purge processing delay value. 3. The method of claim 2, wherein the step of adjusting the purification processing rate further comprises the step of: increasing the cleaning process state if the cleaning process state lags behind the desired process and a current time is near one of the end of the purification processing cycle Purification processing rate. According to the method of claim 1, the step of adjusting the purification processing rate further comprises the following steps: when the memory workload is at a first memory workload value and 133927.doc 200921507, the purification processing is slow in a first- When purifying the processing delay value, adjusting the purification processing rate to be at a first purification processing rate; when the memory workload is at a second memory workload value greater than the first workload value and the purification processing is slow At the first value, the purification processing rate is adjusted to be at a second purification processing rate that is less than the first purification processing rate; and the residual memory workload is at the first memory workload value and When the purification process is delayed by a second purge process retardation value that is smaller than the first purge process retardation value, the purge process rate is adjusted to be at a third purge process rate that is greater than the first purge process rate. 5. The method of claim 4, further comprising the steps of: delaying the third purification process when the memory workload is at a third memory workload value and the purification process is slow in a third purification process delay value The value indicates that the purification process lags behind the desired purification process, and when the current time is at the first time value, the purification process rate is adjusted to be at a fourth purification process rate; and when the memory workload is at the The three memory workload value, the cleansing portion S is delayed (four) the third purification processing delay value, and the current time is at a second time value, the purification processing rate is adjusted to be greater than the fourth purification processing rate And a fifth purification processing rate, the second time value being closer to one end of the purification processing period than the first time value. 6. The method of claim 1, wherein the step of determining a memory workload further comprises the step of determining a full degree of reading the queue. 133927.doc 200921507 The method of calling ', the method of item 1 according to the purification processing delay value and the memory processing and planting to adjust the purification processing rate further comprises the step of adjusting the duration of a purification processing interval. In the method of claim 1, the step of adjusting the purification processing rate according to the purification processing delay value and the memory processing and planting further comprises: changing the first requirement relative to the reading requirement for the purification processing requirement An allocation between the first purification processing subinterval during the priority period and a second purification processing subinterval between the second priority period during which the purification processing request is given to the drinking request The steps. 9- A computer system comprising: a processor configured to issue a read request and a write request; a memory; and a memory controller configured to receive the read request and The 2 write request 'and the configuration further to control the read and write to the memory to satisfy the read request and the write request, the memory controller further includes: a purification processing controller configured to purify the entire memory during a purification processing cycle; wherein the purification processing controller is configured to adjust a purification processing rate depending on a memory workload and a purification process delay . 10. The computer system of claim 9, wherein the purification processing controller is configured to: when the memory workload is at a first memory workload value and the purification process is sluggish - the first purification processing delay value At the time, the net 133927.doc 200921507 processing rate is adjusted to be at a first purification processing rate. First = body: the load is at a greater value than the first-workload value... the memory value of the memory The purification processing is retarded at the first value X to adjust the purification processing rate to be at a second purification processing rate that is smaller than the first purification processing rate; and when the memory workload is in the first memory working (four) value And the purification treatment is sluggishly - the first value is lower than the first purification treatment delay value When the depletion processing delay value is set, the purification treatment rate is adjusted to be at a third purification treatment rate which is greater than the first purification treatment rate. 11. A computer system as claimed, wherein the purification processing controller is further configured to: j when the memory workload is at a third memory workload value and d purification processing is slow at a third purification processing delay value The third purification processing retardation value indicates that the purification processing progress lags behind the woven purification processing process' and - when the current time is at a first time value, the purification processing rate δ is rounded to a fourth purification processing rate; When the memory workload is in the third memory workload value, the purification processing is slow in the third cleaning process, and the current time is in a second time value, the cleaning processing rate is adjusted to be in a ratio The fourth purification processing rate is a fifth purification processing rate, and the first time value is closer to one end of the purification processing period than the first time value. 133927.doc