TW200919944A - Pade approximate calculation and conversion circuit of directly digital frequency synthesizer - Google Patents

Abstract

The invention relates to a pade approximate calculation and conversion circuit of directly digital frequency synthesizer. A multiplier receives and a first input signal and a variable signal and multiplies them to generate a multiplied signal. A divider receives the variable signal and has it divided by a second input signal to generate a division signal. An adder receives and adds the multiplied signal and the division signal up to generate an output signal which is returned to the divider. A sine wave signal of quarter cycle is then completed by a second order direct operation. Therefore, the operation time of the entire sine wave and the area of the operation circuit can be reduced.

Description

200919944 IX. Description of the Invention: [Technical Field] The present invention relates to a phase-to-sine amplitude conversion circuit of a direct digital frequency synthesizer, which is a direct digital synthesis (four) conversion of the Pade approximation algorithm. The circuit 'converts the phase to a quarter of the sine wave signal. [Prior Art] Direct Digital Frequency Synthesis (DDFS) includes the use of a phase accumulator 1〇, (phase Accumuiat〇r) and a phase-to-sine amplitude converter 20' (Phase-to-Sinusoid Amplitude) Converter, 卩5 gossip generation - the required digital form, re-production - number shop conversion (10)igital threat

Converter, DAC) converts this digital form into an analog waveform. As shown in the first figure, it is a conventional direct digital fresh synthesizer, such as _, which includes - she is decremented by 1 (), and a phase versus sinusoidal amplitude Hz H 20' and - number spread n 3Q. The phase of the direct number side rate synthesizer accumulates H 1G 'received - digital money, and outputs to the phase alignment video converter 20 ' and corresponding to the output signal, and then converted to an analog signal by the digital analog converter 3 〇 . The analog signal of the output of the 'digital analog converter 3' can be smoothed using a low pass filter (not shown) to generate a chat signal, such as a sine wave. Because the direct digital frequency synthesis technology has high resolution, fast frequency switching, continuous linear phase change, low cost and architecture (4), it has a wide range of applications in digital communication. At present, the direct computational architecture of direct digital frequency synthesis technology includes Taylor's polyg^nial and C0RDIC algorithm, in which Taylor's polynomial is directly developed for sine wave approximation. 'This method realizes the architecture of the simple stomach, she loses The person through the silk _ calculation and the sine wave f-like co-formation, resulting in the completion of the wave. Furthermore, the ω 丽 algorithm, the trigonometric characteristic operation of the test corresponds to the structure of the positive suffix of the input, and the method of silk, addition and translation is used to calculate the wei, and then she passes the addition (8) and then rides the langzheng green. And the idea of turning the angle but fixing it to _11(2) causes the multiplier to be replaced by a shifter. Through the sinusoidal symmetry structure, 200919944 produces a complete sine wave signal. The eight-only Taylor polynomial directly expands into a sine wave approximation. The phase input realizes a sine wave approximation. • The multiplication of the multiplication operation, the operation phase # consumes time and implements the algorithm in the initial coordinate rotation (four) degree of the selected image rotation iteration Private Wei, so the reduction of the number of people and the number of rotation iterations is too high, so achieving a complete sine wave is quite time consuming. Hand-cutting R: The above-mentioned problem is proposed - a novel direct digital frequency synthesizer, which not only (4) transports the time of the sine wave, but also saves the circuit area to save costs, so the problem. SUMMARY OF THE INVENTION It is an object of the present invention to provide an approximate arithmetic conversion circuit for a direct digital synthesizer that saves time for computing a complete sine wave by the Pade approximation algorithm. The purpose of μ is to provide a kind of direct digital de-emphasizing approximation of the conversion circuit, which saves the circuit area by saving the circuit operation by a quarter of the Pade approximation. The Pade approximation algorithm of the present invention is a Pade approximation algorithm which uses a Pade approximation algorithm to compile a conversion circuit comprising a multiplier, a __ divider and an adder. Multiplication II receives and multiplies - the first-input signal and the - variable, and generates a multiply signal; and the divider receives and divides the variable signal and a second input signal to generate - divide the city, - the adder receives and Add multiplication and division, and generate - output 峨 and pass back to the divider ' to complete the quarter-cycle sine wave signal. Use the first Cong and the second intestine to restore the quarter-cycle sine wave signal to a complete sine wave signal. Furthermore, the Pade approximate calculation conversion of the present invention further includes a complex multiplexer, and respectively cooperates with - selects, and sequentially inputs the simple to the multiplier and the divider, and shouts into a quarter-cycle sine wave signal. 200919944 [Embodiment] For the purpose of understanding and understanding the structural features and the achievable effects of the present invention, please refer to the preferred embodiment and the detailed description. Figure ' is a block diagram of a direct digital frequency synthesizer in accordance with a preferred embodiment of the present invention. As shown in the figure, the direct digital synthesizer of the present invention comprises a phase accumulator 1〇, a phase-to-sine amplitude converter 2〇, a digital analog converter 3〇 and a low-pass filter 4〇. The phase accumulator 1G receives the -N bit it input signal, and generates a "phase accumulating signal" and transmits it to the phase-to-sine amplitude converter 20 to convert the phase accumulating signal into a sine wave signal, and then through the number-pitch conversion (four) In the case of the thief-county-class analogy, the low-pass filter 40 filters the noise of the sine wave signal to smooth the sine wave signal. Wherein, the phase accumulator 10, the phase-to-sine sine amplitude converter 20, the digital analog converter 3 〇 and the low-pass filter 40 are based on a clock signal, and the synthesized output frequency is an output signal, and then The phase-to-sine amplitude converter 20 further includes a mutually exclusive logic gate 22, a pa (je approximate arithmetic conversion circuit 24 and a mutually exclusive logic gate 26. The exclusive circuit gate 22 receives the phase accumulation signal of the M-2 bit. A phase accumulating signal with the first one bit (2 MSB) is used to map the slope signal of the phase accumulating signal to generate a triangular wave signal. The Pade approximate arithmetic conversion circuit 24 converts the triangular wave signal to generate a periodic one-half sine wave signal. The mutually exclusive logic gate 26 receives the periodic half-sine wave signal and the first high-order element (MSB) phase accumulation signal to map a half sine wave signal to generate a sine wave signal, wherein The remaining phase accumulation signals of the first high bit and the second high bit are transmitted to the Pade approximation calculation conversion circuit 24 to convert a quarter of the sine wave signal. As described above, the Pade approximation Conversion circuit 24 and into the line-based design algorithm using a pade recent times, by which the analysis algorithm Pade: first assumed that an outer Taylor

>=〇J Polynomial, where Taylor's polynomial /7th order coefficient and the knife belongs to a positive integer; Pade 200919944 Approximate objective function is, where the molecular part is (Χ)=Λ+尺...+ , which is a multiple of Qm{x ) and the denominator part (x) = l + W + ." + know / is a polynomial. Let Pade approximate the objective function and the Taylor polynomial is J(x)-A^=〇, so there are the following relations:

Qm(x) a0 =P〇 αι + a〇qx = Pi Q2 — Pi (1)

+ % = A aM ^~aL(l\ "* ^ aL-M+\(}M = 〇^L+M αΐ+ΜΑ^\ + · · · + ClLqM = 0 To generate a quarter-cycle sine wave The fifth-order Taylor polynomial approximation is (2) 3(x) = sin(x) β X -丄X3 + 丄文5 3! 5! The relationship between (1) and (2) can give the following coefficient correspondence v αη « 2=.4=0, α1=1, α3=--,«5=_ (3) Therefore, the Pade approximation objective function is Φ) _ ΰΛχ)

~Χ + X 1 +

X (4) 20 Then the Pade approximation objective function is reduced to a continuous fraction (continued ~x 200 fraction) to 3jc + 60. This liter type requires only one multiplier, one adder and one divider to form a quarter cycle of 200919944. Sine wave. Please refer to the third figure, which is a block diagram of an approximate calculation conversion circuit of the preferred embodiment of the present invention. For example, the Pade approximate calculation conversion circuit 24 of the present invention is constructed by the above

The continuous score derived from the Pade algorithm—^ 臓 出 本 本 翻 近似 近似 近似 3 3 3 3 3jc + ~

The X conversion circuit 24 includes a multiplier 240, a divider 241, and an adder 242. First, the multiplier 240 receives the -first input signal A and the variable signal, and multiplies the first input signal A0 and the variable signal to generate a first multiplication signal, wherein the variable signal is a phase accumulation signal, that is, a slope The signal 'divider 241 receives the variable signal and a second input signal BG, and divides the variable signal and the second input signal B0 to generate a second dividing signal. The adder 242 receives and adds the multiplication signal and the dividing signal. Generate - the first - output signal. The first-input signal A〇 and the second input-subtractive BG domain are respectively 3 and 6G. The output of the first-order Pade approximation calculation circuit 24 is 3 and is transmitted back to the divider 24. The scale multiplier receives a new one. The first input «A Bu and the variable signal - the second multiplication signal, the divider 2 receives the first output signal and is divided by the second input signal B1 - the second division signal, plus 2 The second multiplication signal and the second division signal are generated to generate a second output signal, wherein the values of the first input signal A1 and the second input signal B1 are respectively AND, and she approximates the conversion circuit μ-time After the direct operation, the second output signal is generated, which is the continuous score we need. Thus, the present invention uses the Pade approximation algorithm to directly synthesize the sine wave, increase the speed of the operation, and only multiply-multiplier A divider and an adder can complete the operation in 200919944, so the circuit realizes a small area, thereby reducing the cost. In addition, since the Pade approximate calculation conversion circuit 24 must perform the second direct operation to obtain the required output signal, the multiplier 240 and the divider 241 must input the non-input signal according to the operation of different times, so the side is The Pade approximate calculation conversion circuit % includes a complex multiplexer, which is a first multiplexer 243, a second multiplexer 244, and a third 245 'the multiplexer 243 receives the plurality of first input signals. A〇, ai, and one of the first input signals is output according to a & selection signal Sel A, the second multiplexer recovers the second input signal BO, B and corrects according to the second selection signal And the third multiplexer 245 receives the variable signal and the first round of output: according to the third selection signal, the tiger Sel c outputs the variable signal and the _ output signal, When the Pade approximate calculation conversion circuit 24 performs the first calculation, the first multiplexer/, the 244 and the third multiplexer 245 select the signal according to the first selection signal and the second selection signal respectively. People suspect u AG, the third loser Xunlong and change ^ - times of transport Shouting the mth number: When the operation secret 24 performs the second ^, : the worker 240, the second multiplexer 244 and the third multiplexer are respectively based on the basis; ―: select the second-second selection signal and the third selection Signal, and select the first-input message selection, and the second-order operation with the first-output signal, and generate the required second round of the money number B1, as described above, using the Pade approximate calculation of the present invention. The conversion circuit 2 is divided into error integral quasi-error differentiation (4) in the error quasi-financial plane, and the sine wave and Pade approximation objective function error_offence#. The effect of the towel on the error product sine wave body error can be expressed as (5), and its whole E(x):= Jf sin(x) =f sin(x)-| + + 3x 200 jc, 60 + 3^ dx dx 8.63x10 means that the error is slightly discerned, and the maximum efficiency of Qian’s work can be made by (6) 10 (5) 200919944 dx sin(x)- 7 — JC + 3 60 200 &gt ;0 v

X (6) / π 0.0042 Therefore, the equations (5) and (6) can be used to know that the quarter--the chatter and the Padei^ seem to have a very small error in the objective function. Therefore, the Pade approximation algorithm of the present invention is used in the time-talking and sine wave synthesis. The thief is not only computing the frequency, but also has a small circuit area and small error. In summary, the invention relates to an approximate calculation algorithm conversion circuit of a direct-link frequency synthesizer of the present invention, which designs a conversion circuit by a Pade approximation algorithm, which is received by a multiplier and multiplied by a ^ input signal and - Wei Xun, and the generation of the secret signal; - division and touch and change the variable money and - the second input domain, and the generation - division method; - the adder receives and adds the multiplication signal and the division signal 'produces - output signal And _ to the divider, so after a second operation, to complete the quarter-cycle thief signal, can save the time to complete the complete sine wave and the area of the circuit. The invention is actually - has a clear, progressive and available for industry _ should meet the requirements of the patent application stipulated in China's patent law undoubtedly, 提出 filed an invention patent application according to law, the prawn bureau gave a patent early, to the sense prayer. a Only the above mentioned 'prefecture of the county's hair-touch implementation _ has, and _ to limit the hair: the scope of implementation, according to the shape, structure, characteristics and spirit of the scope of the patent Variations and modifications are to be included in the scope of the patent of the present invention. [Simple description of the figure] The first figure is a direct digital frequency synthesizer of the prior art; ^The second figure is the direct digital solution of the failure-health implementation Synthetic ϋ square side; and the second picture is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ For sinusoidal amplitude converter 30, digital to analog converter 10 phase accumulator 20 phase to sine amplitude converter 30 digital analog converter 40 low pass chopper 22 mutual exclusion logic gate 24 Pade approximation calculation conversion circuit 26 mutual exclusion logic gate 240 Multiplier 241 Divider 242 Adder 243 First multiplexer 244 Second multiplexer 245 Third multiplexer 12

Claims (1)

200919944 X. Patent application scope: 1. A Pade approximate calculation conversion circuit applied to a direct digital frequency synthesizer, comprising: a multiplier 'receiving and multiplying a first input signal and a '-variable signal' to generate - a multiplier signal; a divider that receives and divides the variable signal and a second input signal to generate a divide signal; and an adder that receives and adds the multiplication signal and the divide signal to generate an output signal and Return to the divider. 2. The Pade approximate calculation conversion circuit according to claim 1, wherein the pade-like calculation conversion circuit converts the signal to a quarter-cycle sine wave signal. 3. The pade approximate calculation conversion circuit of claim 1, further comprising: a multiplexer receiving the plurality of first input signals and outputting one of the first input signals to the multiplier. 4. The Pade approximate calculation conversion circuit of claim 3, wherein the multiplexer outputs one of the first input signals to the multiplier according to a selection signal. 5. The Pade approximate calculation conversion circuit of claim 3, wherein the first input signals have a value of 3 or -+. 6. The pade approximate calculation conversion circuit of claim 1, further comprising: - the multiplexer 'receiving the plurality of second input signals' and outputting one of the second input signals to the Divider. 7. The pade approximate calculation conversion circuit according to claim 6, wherein the multiplexer outputs one of the second input signals to the divider according to a selection signal. The pade approximate calculation conversion circuit of claim 6, wherein the second input signals have a value of 60 or 200. The Pade approximate calculation conversion circuit of claim 1, further comprising: - the multiplexer is connected to the signal and the flip, and outputs one of the variable signal and the output signal to the divider. 9. The invention relates to a Pade approximate calculation conversion circuit according to claim 9, wherein the multiplexer outputs one of the variable signal and the output signal to the divider according to a selection signal. 11. The Pade approximate calculation conversion circuit of claim 1, wherein the variable signal is a phase accumulation signal. 14