200917501 九、發明說明： 【發明所屬之技術領域】 本發明大體係關於光電元件，且更特定言之係關於半導 體光電元件及其製造方法。 【先前技術】 基於地球上有限的資源及對能量之需求與日俱增，人類 對於能源開發之關注更是大幅提升。近年來，太陽能已成 為最重要可用能源之一。能夠將太陽能轉換成電能之光電 疋件，例如太陽能電池，已受到相當大的關注。太陽能電 池可製造於例如矽（si)晶圓之半導體晶圓上。大體而言， 半導體太陽能電池可包括在p型半導體與η型半導體間的 Ρ-η接面。在太陽能電池中，光子提供能量以激發出電子_ 電洞對。所產生之電子及電洞可分別朝著ρ型及η型半導 體移動，且隨後聚集在獨立的觸點中。#光人射於太陽能 電池上時’可產生電流且可形成電壓。 轉換效率可為太陽&電池效能的重要指#，其通常被表 :成太陽能電池之電輸出與入射光之量的比率。大體而 言’轉換效率愈高，太陽能轉換成電能之轉換損耗愈小。 因此，可能需要一具有相對較高之轉換效率的半導體光電 凡件。亦可能需要-製造具有相對較高之轉換效率的半導 體光電元件之方法。 【發明内容】 一本發明係關於可達到相對較高的轉換效率之半導體光電 元件及其製造方法。 200917501 根據本發明之-範例’提供一種半導體光電元件，其包 :·· -半導體基板，其具有一第一表面及一第二表面，該 弟-表面與該第二表面彼此相對；複數個溝渠，該等溝渠 自該第-表面延伸至該半導體基板中，該第一表面為一： 體平坦的表面；一摻雜區，其位於該半導體基板中且靠近 該第-表面及該複數個溝渠；—第一傳導層，其位於該半 導體基板上方’以及—第二傳導層，其位於該半導體基板 之該第二表面上。 根據本發明之另一範例，提供—種半導體光電元件，其 包含：—半導體基板；-紋理結構，其位於該半導體基板 上方，該紋理結構包括複數個角錐狀物；複數個溝渠，該 等溝渠延伸至科導體隸中’㈣溝$中之每一者處於 及複數個角錐狀物中之至少兩個相鄰角錐狀物之間；一摻 雜區，其位於該半導體基板中且靠近該複數個溝渠；一第 一傳導層，其位於該紋理結構上方；以及一第二傳導層， 其位於該半導體基板下方。 根據本發明之另一範例，提供—種製造一半導體光電元 件之方法，該方法包含：提供具有一第一表面及一第二表 面之半導體基板，該第一表面與該第二表面彼此相對；蝕 刻忒半導體基板以在溝渠該半導體基板中形成複數個溝 渠；在該半導體基板中靠近該第一表面及該複數個溝渠處 形成一摻雜區；在該半導體基板上方形成一第一傳導層； 以及在該半導體基板之該第二表面上形成一第二傳導層。 根據本發明之另一範例，提供—種製造一半導體光電元 200917501 件之方法’該方法包含：提供一半導體基板；在該半導體 基板上方形成—紋理結構，該紋理結構包括複數個角錐狀 :;钮刻該紋理結構以在該半導體基板中形成複數個溝 木，"亥等溝渠中之每—者處於該複數個角錐狀物之至少兩 個相鄰角錐狀物之間；在經紋理化之半導體基板中靠近該 複數個溝渠處形成—摻雜區；在該紋理結構上方形成—第 -傳導層；以及在經紋理化之半導體基板下方一 傳導層。 本發明之附加特徵及優點將於隨後之敘述中加以陳述部 分之特徵及優點，且自敘述可明顯得知部份之特徵及優 點’或可藉由對本發明之實踐而習得部份之特徵及優點。 本么月之特徵及優點將經由在所附中請專利範圍中特別指 出之元件及組合而實現及獲得。 應眘解刖述之大體描述及隨後之詳細描述僅為例示性及 說明性的且不對所主張的本發明加以限制。 【實施方式】 結合隨附圖式進行閱讀將更佳地瞭解前文所述之本發明 的【發明内容】及以下【實施方式】。為達成闡示本發明之 在圖式中展不了目前為較佳的實施例。然而應瞭解， 本發明不限於所示之精確配置及手段。 現將詳細參考本發明之當前實施例’該等實施例之範例 於隨附圖式中示明。圖式中盡可能地使用相同參考數字來 代表相同或類似部分。 。 圖1 F為έ兒明製造根據本發明之一範例的半導體 200917501 光電7C件之方法的橫截面圖。參考圖1A，提供可包含p型 雜貝之基板1 〇。在一範例中，基板i 〇可包括石夕晶圓、坤 化鎵（GaAs )晶圓及碟化辞（Znp )晶圓中之一者。基板 ίο之電阻率（p)可在大致0 〇1至2〇歐姆_公分 之範圍内，但此範圍可隨其他應用而有所改變。此外，基 板1〇可具有在大致180至230微米（Mm)之範圍内的厚 度’但此厚度可更薄或更厚。 參考圖1Β，可自基板丨0之第一表面13而在基板1〇中 开> 成複數個溝渠基板1〇之第一表面13可為平坦表面。 溝渠1 2可藉由諸如電化學蝕刻（eiectr〇chemical etching ; )製％之濕式姓刻製程形成。在一範例中，適用於電 化冬餘刻製私之蝕刻溶液可包括碟酸，例如，氟化氫（HF )、 —甲基甲醜胺（DMF)、HF與去離子水（h2〇)之混合物、 DMF與Ηζ〇之混合物、HF與乙醇（c2H5〇h )之混合物及 HF DMF與h20之混合物中之一者。在另一範例中電化 干蝕刻製程之蝕刻溶液可包括氫氧化鉀（κ〇Η )。另外，溝 渠12可藉由乾式蝕刻製程並配合遮罩而形成。溝渠12中 之每者的寬度可在大致0·1至10 μιη之範圍内，且直接 相鄰之溝渠12之間的距離可在大致〇1至1〇〇 μιη之範圍 内此外溝¥12中之每一者自基板1〇之第一表面Η起 算的深度可在大致〇·1至200 μπι之範圍内。 圖1G及圖1Η為分別展示圖1Β中所示之溝渠12之橫截 面圖及平面俯視圖的例示性掃描電子顯微鏡（scanning electron microsc〇pe; SEM)照片。參考圖 ，溝渠 i2 中 200917501 之每一者可具有側面陡峭之輪廓。具體言之，在一範例中， 溝渠12中之每一者可包括陡峭或垂直的側壁12-1。參考圖 ，複數個溝渠】2可隨機分布在基板1〇上方。 參考圖1C，可藉由例如擴散、蟲晶及植入製程之—或其 :適當製程而將摻雜區14形成於第—表面13及複數個溝 木12之表面附近。在_範例中，摻雜區μ可藉由使用三 氯氧k ( P0C13)氣體在攝氏大致84G度（t)之溫度下持 續大致二十分鐘的擴散製程而被重度摻雜冑η型雜質。〇 型雜貝之濃度可為大致1〇〗8 cm'此外，摻雜區自第一 表面13及溝渠12之表面（未標號）的厚度可在大致 至〇·2μιη之範圍内，但此範圍可隨其他應用而有所改變。 ，考圖1〇,塗層16可藉由化學氣相沈積（chemical vapor P ition，CVD)製程、賤鑛製程或其他適當製程而形成 :基板H)上方。塗層16可在第一表面13及溝渠12上方 等t地延伸。在-|&例中’塗層i 6可包括抗反射材料，例 士氮化矽（SiNx) &氧化矽（例如二氧化矽，中之 一者。此外H 16之厚度可為大致0.08 μιη，但此厚度 可更薄或更厚。 多考圖1Ε，第一傳導層18彳藉由絲網印刷（呂⑽⑼ Printing)、電鑛（electr〇plating)、賤鍍（sputtenng)及蒸 錢製程（eVap〇ratingprocess)之—或其他適當製程而形成 於基板1G上方。在本範例中’隨後可形成光電元件之第一 電極層的第一傳導層18可包括一包含鋁（ai)及銀（Ag) 中之-者的圖案化結構。在另一範例中，該第一傳導層ι8 200917501 可包括一包含氧化銦錫（IT0)及氧化銦辞（ιζ〇)中之— 者的非圖案化結構。該第一傳導層18之厚度可在大致〇 3 至5 μηι之範圍内，但此範圍可隨其他應用而有所改變。此 外，溝渠12中之一些可完全被該第—傳導層18覆蓋而 溝渠12中之另一些可僅被部分覆蓋。 參考圖1 F，第二傳導層1 9可藉由絲網印刷、電鍍、濺 鍍及蒸鍍製程之一或其他適當製程而形成於基板1〇之第 二表面15上。在一範例中，該第二傳導層19可包括μ及 Ag中之一者。該第二傳導層19之厚度可為大致〇 3 μηι， 但此厚度可更薄或更厚。隨後，可在大致5〇〇〇c至95〇它之 範圍内的溫度下進行大致10分鐘的退火處理，例如快速高 熱退火（rapid thermal annealing; RTA )處理。該第二傳導 層19可隨後形成光電元件之第二電極層。 圖2A及圖2B為說明製造根據本發明之另一範例的半導 體光電元件之方法的橫截面圖。參考圖2A，可依序形成基 板20、複數個溝渠22及摻雜區24。基板20、溝渠22及 摻雜區24可分別類似於參考圖ία、圖1B及圖1C所描述 及所說明之基板1〇、溝渠12及摻雜區14,因此無需作進 一步論述。 第一傳導層26可藉由絲網印刷、電鍍、濺鍍及蒸鍍製程 之一或其他適當製程而形成於基板20上方。在一範例中， 隨後可成為光電元件之第一電極層的該第一傳導層26玎 包括Al、Ag ITO及IZO中之一者。該第一傳導層％自 基板20之第一表面23起算的厚度可在大致〇3至5mm之 -10- 200917501 範圍内。此外，溝準？ ’、 中之一些可完全被該第一傳| 26覆蓋，而溝準22 Φ + σ ^層 ^ 中之另一些可僅被部分覆蓋。 參考圖2Β，沴層28·^ΓΡ , 了藉由化學氣相沈積（CVD)製 鍍製程或其他適當製尹而彡表程、淹 ^ 、田裹孝王而形成於基板20上方。塗層28 沿第-表…第—傳導層26等形地延伸。在一範例中°， 塗層28可包括抗反射材料，諸如氮切（SlNx)及二氧化 石夕（Si〇2 )中之―去。Ll_ 此外，塗層28之厚度可為大致〇 〇8200917501 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to photovoltaic elements, and more particularly to semiconductor light elements and methods of fabricating the same. [Prior Art] Based on the limited resources on the earth and the increasing demand for energy, human attention to energy development has been greatly enhanced. In recent years, solar energy has become one of the most important sources of energy available. Optoelectronic devices capable of converting solar energy into electrical energy, such as solar cells, have received considerable attention. Solar cells can be fabricated on semiconductor wafers such as silicon (si) wafers. In general, a semiconductor solar cell can include a Ρ-η junction between a p-type semiconductor and an n-type semiconductor. In solar cells, photons provide energy to excite electron-hole pairs. The resulting electrons and holes can be moved toward the p-type and n-type semiconductors, respectively, and then gathered in separate contacts. When a light person is shot on a solar cell, current can be generated and a voltage can be formed. The conversion efficiency can be an important reference for solar & battery performance, which is usually expressed as the ratio of the electrical output of the solar cell to the amount of incident light. In general, the higher the conversion efficiency, the smaller the conversion loss of solar energy into electrical energy. Therefore, a semiconductor optoelectronic component having a relatively high conversion efficiency may be required. It may also be desirable to have a method of fabricating a semiconductor optoelectronic component having a relatively high conversion efficiency. SUMMARY OF THE INVENTION One invention relates to a semiconductor optoelectronic component that can achieve relatively high conversion efficiency and a method of fabricating the same. 200917501 According to the present invention - an exemplary embodiment provides a semiconductor photovoltaic device comprising: a semiconductor substrate having a first surface and a second surface, the di-surface and the second surface being opposite each other; a plurality of trenches The trenches extend from the first surface to the semiconductor substrate, the first surface being a body-flat surface; a doped region located in the semiconductor substrate adjacent to the first surface and the plurality of trenches a first conductive layer above the semiconductor substrate and a second conductive layer on the second surface of the semiconductor substrate. According to another example of the present invention, a semiconductor optoelectronic device is provided, comprising: a semiconductor substrate; a texture structure over the semiconductor substrate, the texture structure comprising a plurality of pyramids; a plurality of trenches, the trenches Each of the '(four) trenches $ extending into the family conductor is between at least two adjacent pyramids of the plurality of pyramids; a doped region located in the semiconductor substrate and adjacent to the plurality a trench; a first conductive layer over the texture; and a second conductive layer under the semiconductor substrate. According to another example of the present invention, a method of fabricating a semiconductor photovoltaic device is provided, the method comprising: providing a semiconductor substrate having a first surface and a second surface, the first surface and the second surface being opposite each other; Etching the semiconductor substrate to form a plurality of trenches in the semiconductor substrate; forming a doped region in the semiconductor substrate adjacent to the first surface and the plurality of trenches; forming a first conductive layer over the semiconductor substrate; And forming a second conductive layer on the second surface of the semiconductor substrate. According to another example of the present invention, there is provided a method of fabricating a semiconductor photocell 200917501. The method includes: providing a semiconductor substrate; forming a texture structure over the semiconductor substrate, the texture comprising a plurality of pyramids: Engraving the texture structure to form a plurality of trenches in the semiconductor substrate, each of the trenches being at least two adjacent pyramids of the plurality of pyramids; Forming a doped region adjacent to the plurality of trenches in the semiconductor substrate; forming a first conductive layer over the textured structure; and a conductive layer under the textured semiconductor substrate. The features and advantages of the present invention are set forth in the description which follows. advantage. The features and advantages of the present invention are realized and obtained by means of the elements and combinations particularly pointed out in the appended claims. The general description and the following detailed description are to be considered as illustrative and not restrictive. [Embodiment] The invention of the present invention and the following [Embodiment] will be better understood by reading in conjunction with the drawings. The presently preferred embodiment is shown in the drawings for the purpose of illustrating the invention. It should be understood, however, that the present invention is not limited to the precise arrangements and means shown. Reference will now be made in detail to the preferred embodiments of the present invention Wherever possible, the same reference numerals are used to the . Fig. 1F is a cross-sectional view showing a method of manufacturing a semiconductor 200917501 photovoltaic 7C member according to an example of the present invention. Referring to Fig. 1A, a substrate 1 可 which may contain p-type shells is provided. In one example, the substrate i 〇 can include one of a Shihwa wafer, a gallium arsenide (GaAs) wafer, and a Znp wafer. The resistivity (p) of the substrate ίο can range from approximately 0 〇 1 to 2 〇 ohm _ cm, but this range can vary with other applications. Further, the substrate 1〇 may have a thickness in the range of approximately 180 to 230 micrometers (Mm) but the thickness may be thinner or thicker. Referring to FIG. 1A, the first surface 13 of the plurality of trench substrates 1 may be a flat surface from the first surface 13 of the substrate 而0 and opened in the substrate 1〇. The trench 1 2 can be formed by a wet-type etching process such as electrochemical etching (eiectr〇 chemical etching). In one example, an etching solution suitable for use in an electrothermal winter etching process may include a dish acid such as hydrogen fluoride (HF), methyl methacrylate (DMF), a mixture of HF and deionized water (h2 〇), One of a mixture of DMF and hydrazine, a mixture of HF and ethanol (c2H5〇h), and a mixture of HF DMF and h20. In another example, the etching solution for the electrochemical dry etching process may include potassium hydroxide (κ〇Η). Alternatively, the trench 12 can be formed by a dry etching process and with a mask. The width of each of the trenches 12 may be in the range of approximately 0·1 to 10 μηη, and the distance between the immediately adjacent trenches 12 may be in the range of approximately 〇1 to 1〇〇μηη. Each of the depths from the first surface of the substrate 1 can be in the range of approximately 〇1 to 200 μm. 1G and 1B are exemplary scanning electron microscopy (SEM) photographs showing a cross-sectional view and a plan top view of the trench 12 shown in FIG. Referring to the figure, each of 200917501 in the ditches i2 may have a steep profile on the side. In particular, in one example, each of the trenches 12 can include a steep or vertical sidewall 12-1. Referring to the figure, a plurality of trenches 2 can be randomly distributed above the substrate 1〇. Referring to Fig. 1C, doped regions 14 may be formed adjacent the surfaces of first surface 13 and plurality of trenches 12 by, for example, diffusion, insect crystal, and implantation processes, or by a suitable process. In the _ example, the doped region μ can be heavily doped with 胄n-type impurities by using a trichlorooxo-k (POC13) gas at a temperature of approximately 84 G degrees (t) to maintain a diffusion process for approximately twenty minutes. The concentration of the cockroach type shell may be approximately 1 〇 8 cm'. Further, the thickness of the doped region from the first surface 13 and the surface of the trench 12 (not numbered) may be in the range of approximately 〇·2 μηη, but the range Can vary with other applications. 1, the coating 16 can be formed by a chemical vapor deposition (CVD) process, a beryllium process or other suitable process: above the substrate H). The coating 16 can extend over the first surface 13 and the trench 12, etc. In the case of -|&, the coating i 6 may comprise an anti-reflective material, such as one of SiNx & yttrium oxide (for example, cerium oxide). Further, the thickness of H 16 may be approximately 0.08. Ιιη, but this thickness can be thinner or thicker. In addition, the first conductive layer 18彳 is screen printed (L(10)(9) Printing), electr〇plating, sputtenng and steamed money. The process (eVap〇rating process) - or other suitable process - is formed over the substrate 1G. In this example, the first conductive layer 18, which may subsequently form the first electrode layer of the photovoltaic element, may comprise an aluminum (ai) and silver a patterned structure of (Ag). In another example, the first conductive layer ι8 200917501 may include a non-pattern including indium tin oxide (IT0) and indium oxide (ITO) The thickness of the first conductive layer 18 may range from approximately 〇3 to 5 μηι, but the range may vary depending on other applications. Further, some of the trenches 12 may be completely covered by the first conductive layer. The 18 covers and the other of the trenches 12 may only be partially covered. Referring to Figure 1 F The second conductive layer 19 may be formed on the second surface 15 of the substrate 1 by one of screen printing, electroplating, sputtering, and evaporation processes or other suitable processes. In an example, the second conductive layer 19 may include one of μ and Ag. The thickness of the second conductive layer 19 may be approximately 〇3 μηι, but the thickness may be thinner or thicker. Subsequently, it may be approximately 5〇〇〇c to 95〇 Approximately 10 minutes of annealing treatment, such as rapid thermal annealing (RTA) treatment, is performed at a temperature within the range. The second conductive layer 19 can then form a second electrode layer of the photovoltaic element. Figure 2A and Figure 2B show A cross-sectional view illustrating a method of fabricating a semiconductor photovoltaic device according to another example of the present invention. Referring to Figure 2A, a substrate 20, a plurality of trenches 22, and a doped region 24 may be sequentially formed. The substrate 20, the trenches 22, and the doped regions 24 may be similar to the substrate 1 〇, trench 12 and doped region 14 described and illustrated with reference to FIG. 1A, FIG. 1B and FIG. 1C, respectively, and thus need not be further discussed. The first conductive layer 26 may be screen printed, One of electroplating, sputtering and evaporation processes or other The process is formed over the substrate 20. In an example, the first conductive layer 26, which may subsequently become the first electrode layer of the photovoltaic element, includes one of Al, Ag ITO, and IZO. The thickness from the first surface 23 of the substrate 20 may be in the range of approximately 〇3 to 5 mm - 10 200917501. In addition, some of the grooves may be completely covered by the first pass 26 Some of the 22 Φ + σ ^ layers ^ can only be partially covered. Referring to Fig. 2, the ruthenium layer 28 is formed on the substrate 20 by a chemical vapor deposition (CVD) plating process or other suitable yoke, yttrium, flooding, and tian xiao xiao. The coating 28 extends in a shape along the first-to-first conductive layer 26. In one example, the coating 28 can include an anti-reflective material such as nitrogen cut (SlNx) and SiO2 (Si〇2). Ll_ In addition, the thickness of the coating 28 can be approximately 〇 〇 8
μΐΏ，但此厚度可更薄或更厚。 . 弟二傳導層29可藉由絲網印刷、電鑛、誠及蒸錄製程 之—或其他適當製程而形成於基板20之第二表面25上。 該第二傳導層29可隨後成為光電元件之第二電極層。參考 圖2Α及圖2Β所描述及所說明之範例可類似於參考圖丄八 至圖IF所描述及所說明之範例，不同之處在於，例如，第 —傳導層26比塗層28更早形成。然、而在其他範例中，第 二傳導層29形成之時間可早於第一傳導層％及塗層28。 圖3A至圖3F為說明製造根據本發明之又一範例的半導 體光電元件之方法的橫截面圖。參考圖3A，提供可類似於 參考圖1A所描述及所說明之基板1〇的基板3〇。參考圖 3 B，可藉由（例如）一蝕刻製程而形成紋理結構3丨。在一 範例中紋理結構31可包括複數個角錐狀物。角錐狀物之尺 寸範圍可介於面積大致5χ5μηι2且高度大致為3至之 較小基座至面積大致為10x10 μιη2且高度大致為6至7 之較大基座。此外，該蝕刻製程可包括使用例如i ·5莫耳 (1 ·5 Μ ) ΚΟΗ溶液在大致8〇°C之溫度下持續大致2〇分鐘 200917501 的各向異性#刻製程。在可自基板30之第一表面33起而 餘刻基板3 0的各向異性餘刻製程中，沿方向[丨〇〇]之触刻速 度可大於沿方向[111 ]之蝕刻速度。 參考圖3C ’複數個溝渠32可形成於基板3〇中。在一範 例中，溝渠32可藉由電化學蝕刻（ECE)製程以類似於參考 圖1 B所描述及所說明之方式而形成。此外，溝渠32之大μΐΏ, but this thickness can be thinner or thicker. The second conductive layer 29 can be formed on the second surface 25 of the substrate 20 by screen printing, electro-minening, and steam recording, or other suitable processes. The second conductive layer 29 can then become the second electrode layer of the photovoltaic element. The examples described and illustrated with reference to FIGS. 2A and 2B can be similar to the examples described and illustrated with reference to FIGS. 8 through IF, except that, for example, the first conductive layer 26 is formed earlier than the coating 28. . However, in other examples, the second conductive layer 29 may be formed earlier than the first conductive layer % and the coating 28. 3A through 3F are cross-sectional views illustrating a method of fabricating a semiconductor photo-electric element according to still another example of the present invention. Referring to Figure 3A, a substrate 3A that can be similar to the substrate 1 described and described with reference to Figure 1A is provided. Referring to FIG. 3B, the texture structure 3 can be formed by, for example, an etching process. In an example, the texture structure 31 can include a plurality of pyramids. The pyramid may have a size ranging from approximately 5 χ 5 μηι 2 and a height of approximately 3 to a larger pedestal to a larger pedestal having an area of approximately 10 x 10 μηη 2 and a height of approximately 6 to 7. In addition, the etching process can include an anisotropic process in which, for example, an i.5 molar (1.5 Å) lanthanum solution is maintained at a temperature of approximately 8 ° C for approximately 2 〇 minutes 200917501. In an anisotropic coke process that can be used to etch the substrate 30 from the first surface 33 of the substrate 30, the etch rate in the direction [丨〇〇] can be greater than the etch rate in the direction [111]. Referring to Fig. 3C', a plurality of trenches 32 may be formed in the substrate 3''. In one example, the trench 32 can be formed by an electrochemical etching (ECE) process in a manner similar to that described and illustrated with reference to Figure IB. In addition, the size of the ditch 32
小及尺寸參數可類似於參考圖1 B所描述及所說明之溝渠 12的大小及尺寸參數。 參考圖3D，摻雜區34可形成於第一表面33及複數個溝 渠32之表面附近。接著，參考圖3£ ’塗層％及第一傳導 層38可形成於基板30上方。在本範例中，可早於第一傳 導層38形成之塗層36可在第一表面33及溝渠32上方等 形地延伸。在另一範例中，可晚於第一傳導層38形成之塗 層36可在第一表面33及第一傳導層”上方延伸。摻雜區 34、塗層36及第-傳導層38之製造過程及結構可分別類 似於參考圖1C、圖1D及圖1E所描述及所說明之捧雜區 14、塗層16及第一傳導層18。 參考圖3F，第二傳導層39可形成於基板％之第二表面 35上。該第：傳㈣39之製造過程及結構可類似於參考 圖1 F所描述及所說明之第二傳導層丨9。 圖4A至圖4G為說明製造根據本發明之另一範例的半$ P電元件之方法的正面透視圖。參考圖4a，提供可推身 有P型雜質的基板4〇。美柄4 基板4〇之結構及電性特徵可類4 、考圖3A所描述及所說明之基板3〇。 -12- 200917501 2考圖4B，可形成一呈例如複數個角錐狀物之形態的紋 里、。構41。該紋理結構w之製造過程可類似於參考圖3b 所^述及所說明之紋理結構31。接著，參考圖W，複數個 溝木42可形成於基板4〇中，該複數個溝渠42之大多數可 位於該複數個角錐狀物中之至少兩個相鄰角錐狀物之間。 溝渠42可以類似於參考圖3C所描述及所說明之用於形成 溝渠32之製程的製程而形成。The small and dimensional parameters may be similar to the size and size parameters of the trench 12 described and illustrated with reference to Figure 1B. Referring to FIG. 3D, doped regions 34 may be formed adjacent the surfaces of the first surface 33 and the plurality of trenches 32. Next, the coating % and the first conductive layer 38 may be formed over the substrate 30 with reference to FIG. In this example, the coating 36 formed prior to the first conductive layer 38 can be contoured over the first surface 33 and the trench 32. In another example, a coating 36 that may be formed later than the first conductive layer 38 may extend over the first surface 33 and the first conductive layer. Fabrication of the doped region 34, the coating 36, and the first conductive layer 38 The process and structure can be similar to the doping region 14, the coating 16 and the first conductive layer 18 described and illustrated with reference to Figures 1C, 1D, and 1E, respectively. Referring to Figure 3F, the second conductive layer 39 can be formed on the substrate. The second surface 35 of the second surface 35. The manufacturing process and structure of the first: (four) 39 can be similar to the second conductive layer 丨 9 described and illustrated with reference to Figure 1 F. Figures 4A through 4G illustrate the fabrication according to the present invention. A front perspective view of another example of a method of a half-P electrical component. Referring to FIG. 4a, a substrate 4 is provided which can push P-type impurities. The structure and electrical characteristics of the substrate 4 can be classified as 4 The substrate 3A described and illustrated in Fig. 3A. -12- 200917501 2 Referring to Fig. 4B, a pattern in the form of, for example, a plurality of pyramids can be formed. The structure 41 can be similarly manufactured. The texture structure 31 is described with reference to Fig. 3b. Next, referring to Fig. W, a plurality of trenches 42 can be shaped In the substrate 4, a majority of the plurality of trenches 42 may be located between at least two adjacent pyramids of the plurality of pyramids. The trenches 42 may be similar to those described and illustrated with reference to FIG. 3C. Formed in the process of forming the trench 32 process.
參考圖4D，摻雜區44可形成於基板4〇之第一表面幻 及複數個溝渠42之表面的附近。在_範例中，摻雜區μ 可藉由-使用P〇Cl3氣體之擴散製程而㈣有n㈣質。 摻才隹區44之尺寸參數及電性特徵可類似於參考圖π所^ 述及所說明之摻雜區34之尺寸參數及電性特徵。 田 ，考圖4E，傳導層49可藉由例如蒸鑛製程及隨後的退 火製程而形成於基板60之第二表面65上。退火製程，例 如快速熱退火（RTA)處理，可在大 J π八双MJU C之溫度下進行 大致1 0分鐘。傳導層49可晬尨士 & , &Referring to FIG. 4D, a doping region 44 may be formed in the vicinity of the surface of the first surface of the substrate 4 and the plurality of trenches 42. In the _ example, the doping region μ can be made by using a diffusion process using P〇Cl 3 gas and (iv) having n (qua) quality. The size and electrical characteristics of the doped region 44 can be similar to the size and electrical characteristics of the doped region 34 as described with reference to Figure π. Field, Figure 4E, conductive layer 49 can be formed on second surface 65 of substrate 60 by, for example, a steaming process and a subsequent annealing process. The annealing process, such as rapid thermal annealing (RTA), can be carried out for approximately 10 minutes at a temperature of a large J π eight double MJU C. Conductive layer 49 can be gentleman & , &
Tik後成為光電元件之第二電極。 參考圖4F-1，包括諸如IT〇 <求分材枓之另一傳導層 48-1可藉由（例如）射頻（d 鴻 Uad10 frequency; RF)濺鍍製程 而形成於基板40上方。在一範例中，隨後可成為第一電極 之傳導層48 1可具有大致。3 _之厚度。或者，參考圖 4F-2，包括諸如A1之全屬从柯+抽、若 金屬材科之傳導層48-2可藉由（例 如）蒸鍍製程而形成於基板4〇 乃 在乾例中，傳導層 48-2可具有大致1 i p^ + <厚度，但此厚度可更薄或更 參考圖4G，塗層46可藉 v W如J罨名增強化學氣相 -13- 200917501 沈積（PECVD)劁鉬二 塗層46可包括^ 基板6〇上方。在—範例中， 之厚戶可為大6 Μ4之抗反射材料。此外，塗層46 又’、,、収〇 8 μ m，但此厚度可更薄或更厚。 項技術者應瞭解，在特 …、為此 形成傳導層49、傳導層4S彳$俏道a ^ 订用於 予等層48-1或傳導層48_2及塗層46之步 驟0 圖5A及圖5B為展示在入射光之各種波長下的反射率之 實驗結果的曲線圖。參考圖5A，第_曲線51可表示未形 成溝渠之基板之反射率。第二曲線52可表示諸如圖 所說明之基板Η)的基板的反射率，其中已基於—使用Μ HF作為姓刻溶液、施加具有大纟1 ί安培/平方公八 (一。之電流密度的電流達一小時之電化學姓刻製： 形成複數個溝渠。因此形成之溝渠可具有大致〇i pm之深 度。同樣，在類似的蝕刻製程下，第三曲線53可表示在大 致3 mA/cm2之電流密度下溝渠深度可達4 μηι之情況下的 基板之反射率，且第四曲線54可表示在5 mA/cm2之電流 密度下溝渠深度可達8 μιη之情況下的基板之反射率。實驗 結果可揭示基板之反射率可隨溝渠深度增加而減小，而反 射率減少可接著導致電流密度增加。此外，若入射光具有 大致400 nm至800 nm之波長，基於電化學蝕刻製程而形 成溝渠之基板之反射率可在大致1〇%至4〇%的範圍内 參考圖5B ,第一曲線61可表示未形成圖案化結構及溝 渠之情況下的基板之反射率。第二曲線62可表示諸如圖 4B中所§兒明之基板40的基板之反射率，其中使用κ〇η作 200917501 為蝕刻溶液在溝渠形成之前形成了 一圖案化結構。第三曲 線63可表示諸如圖4C所說明之基板40的基板之反射率， 其中使用KOH溶液形成了 一圖案化結構，且隨後基於一使 用2M HF作為蝕刻溶液、施加了具有大致1 mA/cm2之電 流密度的電流達一小時之電化學蝕刻製程形成了複數個溝 渠。第四曲線64可表示其中使用KOH溶液形成一圖案化Tik becomes the second electrode of the photovoltaic element. Referring to FIG. 4F-1, another conductive layer 48-1 including, for example, an IT 〇 求 求 求 求 可 。 。 。 。 。 48 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In an example, the conductive layer 48 1 that may subsequently become the first electrode may have a substantially. 3 _ thickness. Alternatively, referring to FIG. 4F-2, a conductive layer 48-2 including a metal such as A1 may be formed on the substrate 4 by, for example, an evaporation process, in a dry case, The conductive layer 48-2 may have a thickness of approximately 1 ip^ + < but the thickness may be thinner or refer to FIG. 4G, and the coating 46 may be enhanced by chemical vapor-13-200917501 deposition (PECVD). The bismuth molybdenum dioxide coating 46 may comprise a substrate 6 above. In the example, the thicker household can be a large 6 Μ 4 anti-reflective material. In addition, the coating 46 is ',, and is 8 μm, but the thickness can be thinner or thicker. It should be understood by those skilled in the art that the conductive layer 49, the conductive layer 4S, and the conductive layer 4 are used for the pre-layer 48-1 or the conductive layer 48_2 and the coating 46. FIG. 5A and FIG. 5B is a graph showing experimental results of reflectance at various wavelengths of incident light. Referring to Fig. 5A, the _ curve 51 may indicate the reflectance of the substrate on which the trench is not formed. The second curve 52 can represent the reflectivity of the substrate, such as the substrate illustrated in the figures, wherein it has been based on the use of Μ HF as the surname solution, applying a current density of greater than 1 ί amp / square 八 (one. Electrochemical surname for one hour: forming a plurality of trenches. The trench thus formed can have a depth of approximately 〇i pm. Similarly, in a similar etching process, the third curve 53 can be expressed at approximately 3 mA/cm2. The reflectance of the substrate at a current density of up to 4 μηι in the depth of the trench, and the fourth curve 54 can represent the reflectance of the substrate with a trench depth of up to 8 μηη at a current density of 5 mA/cm 2 . The experimental results show that the reflectivity of the substrate can be reduced as the depth of the trench increases, and the decrease in reflectivity can then lead to an increase in current density. Further, if the incident light has a wavelength of approximately 400 nm to 800 nm, it is formed based on an electrochemical etching process. The reflectance of the substrate of the trench may be in the range of approximately 1% to 4% by weight with reference to FIG. 5B, and the first curve 61 may indicate the reflectance of the substrate in the case where the patterned structure and the trench are not formed. The second curve 62 can represent the reflectivity of the substrate, such as the substrate 40 of FIG. 4B, wherein a patterned structure is formed prior to trench formation using κ〇η 200917501 as an etch solution. The third curve 63 can represent, for example, a graph. 4C illustrates the reflectivity of the substrate of the substrate 40, wherein a patterned structure is formed using the KOH solution, and then a current having a current density of approximately 1 mA/cm 2 is applied for one hour based on the use of 2M HF as an etching solution. The electrochemical etching process forms a plurality of trenches. The fourth curve 64 can represent a pattern in which a KOH solution is used to form
結構且隨後基於一使用2M HF作為蝕刻溶液、施加了具有 大致5 mA/cm2之電流密度的電流達一小時之電化學蝕刻製 程形成複數個溝渠的基板之反射率。實驗結果可揭示在形 成一圖案化結構之情況下基板之反射率可減小。此外，若 入射光具有大致400 nm至800 nm之波長，具有一圖案化 結構之基板的反射率可在大致5%至1 7%之範圍内。 圖6A及圖6B為分別展示藉由符合本發明之範例的方法 在溝渠形成前所形成之紋理結構61的橫截面圖及平面俯 視圖之例示性掃描電子顯微鏡照片。參考圖6A及6B，紋 理結構61可包括複數個角錐狀物62。角錐狀物62中之^ 者可在界面部分62-1處接觸其相鄰角錐狀物。 圖6C及圖6D為分別展示藉由符合本發明之範例的方法 在溝渠64形成後所形成之紋理結構63的橫截面圖及平 俯視圖之例示性掃描電子顯微鏡照片。參考圖6C及圖阳 溝渠64中之每一者可形成於相鄰角錐狀物65之界面部二 (未標號）處或形成於至少兩個相鄰角錐狀物65之間。刀 圖7為展示形成於符合本發明之範例的紋理結 溝渠73的示意性橫戴面圖。參考圖7,紋理結構7〇可： •15· 200917501 括複數個角錐狀物71 ’其每—者在界面部分72處接觸其 相鄰角錐狀物。溝渠73可自界面部分72形成於紋理結構 70中。在根據本發明之一範例中，溝渠73中之每一者可 對應於界面部分72中之一者。 」目較之下’習知方法中，溝渠74 (以虛線說明）可以預 疋圖案或相對於彼此以預^：距離形成於紋理結構（未標號） 中。此外，溝渠74中之每-者之寬度可跨越若干溝渠乃。The structure was then based on a reflectance of a substrate forming a plurality of trenches using an electrochemical etching process using 2 M HF as an etching solution, applying a current having a current density of approximately 5 mA/cm 2 for one hour. The experimental results reveal that the reflectance of the substrate can be reduced in the case of forming a patterned structure. Further, if the incident light has a wavelength of approximately 400 nm to 800 nm, the reflectance of the substrate having a patterned structure may be in the range of approximately 5% to 1 7%. 6A and 6B are cross-sectional views and an exemplary scanning electron micrograph of a top view of a textured structure 61 formed prior to trench formation by a method consistent with an example of the present invention, respectively. Referring to Figures 6A and 6B, the texture structure 61 can include a plurality of pyramids 62. Any of the pyramids 62 may contact its adjacent pyramid at the interface portion 62-1. Figures 6C and 6D are cross-sectional and top plan views, respectively, showing a cross-sectional view and a plan view of a texture structure 63 formed after the trench 64 is formed by a method consistent with the present invention. Each of the reference vane 64 and the male trench 64 may be formed at the interface portion two (not numbered) of the adjacent pyramid 65 or between at least two adjacent pyramids 65. Knife Figure 7 is a schematic cross-sectional view showing a textured knot channel 73 formed in accordance with an example of the present invention. Referring to Figure 7, the texture structure 7 can: • 15· 200917501 includes a plurality of pyramids 71' each of which contacts its adjacent pyramid at the interface portion 72. Ditch 73 may be formed in texture structure 70 from interface portion 72. In an example in accordance with the invention, each of the trenches 73 may correspond to one of the interface portions 72. In the conventional method, the trenches 74 (illustrated by dashed lines) may be pre-patterned or formed in a textured structure (not numbered) with respect to each other. In addition, each of the trenches 74 may span a plurality of trenches.
熟習此項技術者應瞭解，在不脫離本發明之廣泛發明概 念之情況下可對上述實施例進行更改。因此應瞭解，本發 明不限於所揭示之特定實施例，而是意欲涵蓋在隨附申請 專利範圍所界定之精神及範疇内的修改。 另外，在描述本發明之代表性實施例的過程中， :本發明之方法及/或過程提出為特定的步驟序列。就方法 或過程不依賴於本文所陳述之特定步驟次序而言，方法或 者Ϊ =限I，34之特定步驟序列。-般熟習此項技術 者應瞭解’其他的步驟序列為可行的。因&，說明 ^東述之特定步驟次序不應被理解為對中請專利範圍曰之限 =外，：對本發明之方法及/或過程之申請專利範圍不 應限於輯書寫之次序執行其步驟，且熟習此項技 於瞭解序列可被更改而仍保 易 内。 荇處於本發明之精神及範疇 【圖式簡單說明】 圖1A至圖1F為說明製造根據 t _ * 71 < 輕*例的丰遵辦 光電元件之方法的橫截面圖； 導體 -16- 200917501 圖1G及圖1H為分別展示圖1β _所示之溝渠之橫截面 圖及平面俯視圖的例示性掃描電子顯微鏡（SEM)照片； 圖2A及圖2B為說明製造根據本發明之另一範例的半導 體光電元件之方法的橫截面圖； 圖3A至圖3F為說明製造根據本發明之又一範例的半導 體光電元件之方法的橫截面圖； 圖4A至圖4G為說明製造根據本發明之另一範例的半導 體光電元件之方法的正面透視圖； 圖5A及圖5B為說明入射於根據本發明之各範例的基板 上之光之反射率的圖； 圖6A及圖6B為分別展示藉由符合本發明之範例的方法 在溝渠形成前形成之紋理結構的橫截面圖及平面俯視圖之 例示性掃描電子顯微鏡照片； 圖6C及圖6D為分別展示藉由符合本發明之範例的方法 在溝渠形成後形成之紋理結構的橫截面圖及平面俯視圖之 例示性掃描電子顯微鏡照片；以及 圖7為展示形成於符合本發明之範例的紋理結構中之溝 渠的示意性橫截面圖。 ' 【主要元件符號說明】 10基板 12溝渠 12 _ 1溝渠之側壁 13基板之第一表面 14摻雜區 200917501 15基板之第二表面 16塗層 1 8第一傳導層 1 9第二傳導層 20基板 22溝渠 23基板之第一表面 24摻雜區 25基板之第二表面 26第一傳導層 28塗層 29第二傳導層 30基板 31紋理結構 32溝渠 33基板之第一表面 34摻雜區 35基板之第二表面 36塗層 38第一傳導層 39第二傳導層 40基板 41紋理結構 42溝渠 200917501 43基板之第一表面 44摻雜區 46塗層 48-1傳導層 48-2傳導層 49傳導層 5 1第一曲線 52第二曲線 53第三曲線 54第四曲線 61第一曲線（圖5B) /紋理結構（圖6A) 62第二曲線（圖5B) /角錐狀物（圖6A) 62-1界面部分 63第三曲線（圖5B ) /紋理結構（圖6C ) 64第四曲線（圖5B ) /溝渠（圖6C ) 65角錐狀物 70紋理結構 71角錐狀物 72界面部分 73溝渠 74溝渠 -19-It will be appreciated by those skilled in the art that the above-described embodiments may be modified without departing from the broad inventive concept of the invention. It is understood that the invention is not limited to the specific embodiments disclosed, but is intended to cover modifications within the spirit and scope of the invention. In addition, in describing a representative embodiment of the invention, the method and/or process of the invention is presented as a particular sequence of steps. The method or process is not dependent on the particular sequence of steps set forth herein, the method or the sequence of specific steps of the limits I, 34. Those skilled in the art should be aware that 'other sequences of steps are feasible. Because of the &, the specific sequence of steps of the description is not to be construed as limiting the scope of the patent application. The scope of the patent application for the method and/or process of the present invention should not be limited to the order in which it is written. Steps, and familiar with the technique to understand that the sequence can be changed and still within the warranty. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are cross-sectional views illustrating a method of manufacturing a photovoltaic device according to t _ * 71 < light example; conductor-16- 200917501 1G and 1H are exemplary scanning electron microscope (SEM) photographs showing a cross-sectional view and a plan top view of the trench shown in FIG. 1β, respectively; FIGS. 2A and 2B are diagrams illustrating the fabrication of a semiconductor according to another example of the present invention. FIG. 3A to FIG. 3F are cross-sectional views illustrating a method of fabricating a semiconductor photovoltaic element according to still another example of the present invention; FIGS. 4A to 4G are diagrams illustrating another example of manufacturing according to the present invention. Front perspective view of a method of semiconductor optoelectronic components; FIGS. 5A and 5B are diagrams illustrating reflectance of light incident on a substrate according to various examples of the present invention; FIGS. 6A and 6B are respectively shown by the present invention An exemplary scanning electron micrograph of a cross-sectional view and a plan top view of a textured structure formed prior to the formation of the trench; FIGS. 6C and 6D are respectively shown by the present invention. Illustrative cross-sectional view of a textured structure formed after trench formation and an exemplary scanning electron micrograph of a plan top view; and FIG. 7 is a schematic cross-sectional view showing a trench formed in a textured structure consistent with an example of the present invention; . 'Major component symbol description】 10 substrate 12 trench 12 _ 1 trench sidewall 13 substrate first surface 14 doped region 200917501 15 substrate second surface 16 coating 1 8 first conductive layer 1 9 second conductive layer 20 Substrate 22 trench 12 substrate first surface 24 doped region 25 substrate second surface 26 first conductive layer 28 coating 29 second conductive layer 30 substrate 31 texture structure 32 trench 33 substrate first surface 34 doped region 35 Second surface 36 of the substrate coating 38 first conductive layer 39 second conductive layer 40 substrate 41 texture structure 42 trench 200917501 43 first surface of the substrate 44 doped region 46 coating 48-1 conductive layer 48-2 conductive layer 49 Conduction layer 5 1 first curve 52 second curve 53 third curve 54 fourth curve 61 first curve (Fig. 5B) / texture structure (Fig. 6A) 62 second curve (Fig. 5B) / pyramid (Fig. 6A) 62-1 interface part 63 third curve (Fig. 5B) / texture structure (Fig. 6C) 64 fourth curve (Fig. 5B) / trench (Fig. 6C) 65 angle cone 70 texture structure 71 angle cone 72 interface portion 73 trench 74 ditch -19-