TW200915432A - Metallization process - Google Patents
Metallization process Download PDFInfo
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- TW200915432A TW200915432A TW097114537A TW97114537A TW200915432A TW 200915432 A TW200915432 A TW 200915432A TW 097114537 A TW097114537 A TW 097114537A TW 97114537 A TW97114537 A TW 97114537A TW 200915432 A TW200915432 A TW 200915432A
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- Prior art keywords
- metallization process
- semiconductor substrate
- layer
- heat treatment
- conductive region
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 230000008569 process Effects 0.000 title claims abstract description 55
- 238000001465 metallisation Methods 0.000 title claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 57
- 239000004065 semiconductor Substances 0.000 claims abstract description 57
- 238000005054 agglomeration Methods 0.000 claims abstract description 11
- 230000002776 aggregation Effects 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims description 62
- 238000010438 heat treatment Methods 0.000 claims description 35
- 238000000137 annealing Methods 0.000 claims description 14
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 13
- 238000011282 treatment Methods 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 8
- 229910001507 metal halide Inorganic materials 0.000 claims description 8
- 150000005309 metal halides Chemical class 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- -1 nitrogen ion Chemical class 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 230000008439 repair process Effects 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 150000002736 metal compounds Chemical class 0.000 claims 3
- 239000006096 absorbing agent Substances 0.000 claims 1
- 238000004140 cleaning Methods 0.000 claims 1
- 235000015170 shellfish Nutrition 0.000 claims 1
- 238000002513 implantation Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 230000007613 environmental effect Effects 0.000 description 4
- 229910052744 lithium Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000635 electron micrograph Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910018999 CoSi2 Inorganic materials 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- KPLQYGBQNPPQGA-UHFFFAOYSA-N cobalt samarium Chemical compound [Co].[Sm] KPLQYGBQNPPQGA-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910001922 gold oxide Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 229910000938 samarium–cobalt magnet Inorganic materials 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
200915432 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種金屬化製程,且特別是有關於一 種可減少金屬矽化物的結塊現象之金屬化製程。 【先前技術】 隨著積體電路(Integrated Circuit, 1C)的元件尺寸縮 小,内連線或淺接面的對應阻抗也隨之增加’而使IC運 1 作速度無法有效提高。如最常被用來形成閘極與局部連線 的多晶石夕(poly silicon ),即使重度摻雜後仍帶有相當咼的 電阻率,這會造成元件功耗及訊號延遲(RC delay)的問 題。一般所使用的改善方式為進行金屬化製程’以自動對 準(self-alignment)形成金屬碎化物(salicide)於如電晶 體結構中的導電區域。然而,例如以鈷金屬與多晶矽閘極 在高溫下反應形成如CoSi2之金屬矽化物時,由於CoSU/Si 界面並不平整且有熱凹槽(thermal grooving),將導致所 £ " 謂的結塊現象(agglomeration ),而大幅影響金屬石夕化物的 熱穩定性及元件的運作性能。 【發明内容】 本發明係有關於一種金屬化製程,其係於沈積金屬層 之前,先將半導體基材進行熱處理,可得到較佳之沈積條 件,並且可減緩後方熱處理步驟中金屬矽化物之結塊現 象。 200915432 根據本發明,提出一種金屬化製程。首先,提供一半 ,體,材,此半導體基材具有至少一含矽導電區域。其 ^,提供一改善結塊現象之離子植入於含矽導電區域。接 著,對此半導體基材進行第一熱處理。而後,形成一金屬 2於此半導體基材表面,金屬層係覆蓋含矽導電區域。再 來,對覆蓋有金屬層之此半導體基材進行第二熱處理,以 形成一金屬矽化物層於含矽導電區域上。 根據本發明,另提出一種金屬化製程。首先,提供一 半導體基材,半導體基材具有至少一導電區域。其次了植 入氮離子至導電區域内。接著,對半導體基材進行:第一 熱處理,以修復半導體基材表面。而後,形成—金屬層於 半導體基材表面,金屬層覆蓋導電區域。再來,形二沪 散障礙層於金屬層上。然後,對覆蓋有金屬層之 =進行r第二熱處理’以於導電區域上形成—金屬石夕化i200915432 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a metallization process, and more particularly to a metallization process which can reduce the agglomeration of metal telluride. [Prior Art] As the element size of the integrated circuit (1C) is reduced, the corresponding impedance of the interconnect or shallow junction is also increased, and the speed of the IC operation cannot be effectively improved. For example, polysilicon, which is most commonly used to form gates and local interconnects, has a fairly high resistivity even after heavy doping, which causes component power dissipation and RC delay. problem. A general improvement is used to perform a metallization process to automatically form a self-alignment of a metal salicide in a conductive region such as an electromorphic structure. However, for example, when a cobalt metal and a polysilicon gate are reacted at a high temperature to form a metal telluride such as CoSi2, since the CoSU/Si interface is not flat and has thermal grooving, it will result in a knot. Block phenomenon (agglomeration), which greatly affects the thermal stability of the metallurgical compound and the operational performance of the component. SUMMARY OF THE INVENTION The present invention is directed to a metallization process for thermally treating a semiconductor substrate prior to depositing a metal layer to provide better deposition conditions and to slow agglomeration of metal telluride during the subsequent heat treatment step. phenomenon. 200915432 In accordance with the present invention, a metallization process is proposed. First, a half, body, and material are provided, and the semiconductor substrate has at least one germanium-containing conductive region. It provides an ion-implantation in the conductive region containing germanium. Next, the semiconductor substrate is subjected to a first heat treatment. Thereafter, a metal 2 is formed on the surface of the semiconductor substrate, and the metal layer covers the conductive region containing germanium. Further, the semiconductor substrate covered with the metal layer is subjected to a second heat treatment to form a metal halide layer on the germanium-containing conductive region. According to the invention, a metallization process is also proposed. First, a semiconductor substrate is provided having at least one electrically conductive region. Secondly, nitrogen ions are implanted into the conductive region. Next, the semiconductor substrate is subjected to a first heat treatment to repair the surface of the semiconductor substrate. Thereafter, a metal layer is formed on the surface of the semiconductor substrate, and the metal layer covers the conductive region. Then, the shape of the second Shanghai scattered barrier layer on the metal layer. Then, a second heat treatment is performed on the metal layer covered with the metal layer to form a metal layer on the conductive region.
二Γί後之半導體金屬層表面係減緩進行第二熱處理時 金屬化合層之結塊現象。 為讓本發明之上述目的、特徵、和優點 ^下了文特舉較佳實施例,並配合所_式,作詳細= 【實施方式】 請參照第1目,係依照本發明之金屬化 首先,於步驟110中’提供一半導體基材:此半= 土材具有至少一導電區域。然後,於步驟12”,對此半 200915432 導體基材進行第一熱處理。接著,於步驟13〇中,於此 導體基材表面形成一金屬層,金屬層係覆蓋導電區域。最 後’於步驟14G中’對覆蓋有金屬層之此半導體基材進行 第二熱處理’以形成一金屬化合層於導電區域上。 以下將以應用於一般場效電晶體為例進一步具體戈 明本發明之金屬化製程,其中半導體基材之導電區域係^ 一含矽導電區域為例做說明,且半導體基材進行第二熱處 理後係對應地形成一金屬矽化物層於含石夕導電區域上。= 於本發明所屬技術領域中具有通常知識者當可理解,本發 明可應用於任何積體電路中來改善内連線或元件特性,二 提升積體電路整體效能,也使得1C製程設計更具有彈性。 請依序參照第2A〜2E圖,係分別為依照本發明較佳 實施例之金屬化製程應用於電晶體元件時之製程剖面 圖。如第2A圖所示,係為步驟no中提供之半導體基材 200。半導體基材2〇〇包括基材210及承載於基材21〇上 的電晶體元件220。於本實施例中,基材210係使用P型 或N型之ί夕基材,但在其他實施例中,基材210可為矽覆 絕緣(Silicon-On-Insulator,SOI)基材。電晶體元件 220 例如為一般之金氧半(MOS)電晶體元件,並包括閘極G、 汲極D與源極S等含矽導電區域。形成於閘極氧化層221 上之閘極G為經沈積及圖案化之多晶矽層。汲極D及源極 S為與基材210電性相反之砷或硼等物質之摻雜區,間隙 壁222則可作為後續形成金屬矽化物時的遮罩。 然而,此時半導體基材200上可能留有一些無機或有 200915432 λ. < · ^ · wvr· λ m 機污染物,如製程環境中的雜質粒子或光阻、蝕刻及圖案 化過程中的殘餘物或副產品(如polymer ),甚或基材210 的原生氧化物等等。此外,半導體基材200之表面結構亦 可能留有前段製程中造成的不平整現象。而金屬化製程的 品質即相當取決於含矽導電區域的表面乾淨平滑與否。 如第2B圖所示,係於步驟120中,對半導體基材200 進行第一熱處理。於本實施例中,第一熱處理為一般使用 高溫爐火的退火處理(annealing),使半導體基材200在The surface of the semiconductor metal layer of the second layer is slowed down by the metallization layer during the second heat treatment. The above-mentioned objects, features, and advantages of the present invention will be described in detail with reference to the preferred embodiments of the present invention. Referring to the first aspect, the metallization according to the present invention is first. , in step 110, 'providing a semiconductor substrate: the half = soil material has at least one conductive region. Then, in step 12", the first heat treatment is performed on the semi-200915432 conductor substrate. Then, in step 13, a metal layer is formed on the surface of the conductor substrate, and the metal layer covers the conductive region. Finally, in step 14G The second semiconductor treatment is performed on the semiconductor substrate covered with the metal layer to form a metallization layer on the conductive region. The following will be applied to the general field effect transistor as an example to further specifically describe the metallization process of the present invention. The conductive region of the semiconductor substrate is exemplified by a conductive region, and the semiconductor substrate is subjected to the second heat treatment to form a metal telluride layer on the conductive region. It will be understood by those skilled in the art that the present invention can be applied to any integrated circuit to improve the characteristics of interconnects or components, and to improve the overall performance of the integrated circuit, and to make the 1C process design more flexible. Referring to Figures 2A to 2E, respectively, a cross-sectional view of a process for applying a metallization process to a transistor component in accordance with a preferred embodiment of the present invention. 2A is a semiconductor substrate 200 provided in step no. The semiconductor substrate 2 includes a substrate 210 and a transistor element 220 carried on the substrate 21A. In this embodiment, the substrate 210 The P-type or N-type substrate is used, but in other embodiments, the substrate 210 may be a Silicon-On-Insulator (SOI) substrate. The transistor element 220 is, for example, a general gold oxide. A half (MOS) transistor element, and includes a germanium-containing conductive region such as a gate G, a drain D, and a source S. The gate G formed on the gate oxide layer 221 is a deposited and patterned polysilicon layer. The pole D and the source S are doped regions of a substance such as arsenic or boron which are electrically opposite to the substrate 210, and the spacer 222 can serve as a mask for forming a metal halide later. However, at this time, the semiconductor substrate 200 is on the substrate. There may be some inorganic or have 200915432 λ. < · ^ · wvr· λ m machine contaminants, such as impurity particles or photoresist in the process environment, residues or by-products (such as polymer) during etching and patterning, Or even a native oxide of the substrate 210, etc. Further, the surface structure of the semiconductor substrate 200 The unevenness caused by the front-end process may be left behind. The quality of the metallization process depends on whether the surface of the conductive region containing the germanium is clean and smooth. As shown in Fig. 2B, in step 120, the semiconductor substrate is used. 200. Performing a first heat treatment. In the present embodiment, the first heat treatment is an annealing treatment generally using a high temperature furnace, so that the semiconductor substrate 200 is
产N 溫度450至700°C之間的氮氣環境(流量約1至10 slm, 壓力約1 atm)中進行約20分鐘至3小時左右的退火處理。 於其他實施例中,第一熱處理也能使用溫度設定較高的快 速退火處理(Rapid Thermal Processing,RTP)。藉由執行 第一熱處理,即能有效除去前述半導體基材200上對後續 金屬化製程不利之物質,同時修復半導體基材2〇〇的表面 結構,使電晶體元件220的含矽導電區域更乾淨平滑。 U 傳統金屬化製程在進行金屬沈積步驟前,僅以如使用 氟化氫等之預洗(pre-clean)步驟來使半導體基材表面儘 可Sb達到適當之沈積環境條件。然而,預洗步驟對於前述 的不利物質之清除作用相當有限,且無法對半導體基材 2〇〇的表面結構有所改善。因此,本發明係以—道熱^理 步=來達到更㈣沈積環境條件。#然,錢行步驟13〇 之如’也可再進行一次預洗步驟。 :第2C圖所示,於步驟13",由步驟⑽獲得適 田之次積環境條件後,能以賤鑛沈積方式形成所需之金屬 200915432 層310。於本實施例中,金屬層310係以包含钻(cobalt, Co ) 為例作說明。於其他實施例中,金屬層310也可使用如鈦 (titanium, Ti)、鎳(nickel,Ni)及銦(molybdenum, Mo) 等等。一般來說,可在金屬層310上再形成一吸收層320 及一擴散障礙層330 ( diffusion barrier) ’如第2C圖所示。 吸收層320例如使用鈦來幫助反應掉基材210的原生氧化 物,以減少後續形成金屬石夕化物的過程中的氧污染。擴散 障礙層330例如使用氮化鈦來減少金屬層31 〇在後續熱處 i 理中的擴散逸失。另外,值得一提的是,形成金屬層310 之前,也可以提供一離子佈植於所需之含矽導電區域,例 如氮離子(N )佈植,藉此改變後續熱處理中的金屬石夕 化物的晶粒大小(grain size)而改善結塊現象。 如第2D圖所示,於步驟140中,對覆蓋有金屬層310、 吸收層320及擴散障礙層330之半導體基材2〇〇進行第二 熱處理,如溫度400至550°C的退火處理。藉此,使包含 ❹鈷之金屬層31〇與閘極G、汲極D及源極§反應而形成為 錄單矽化物之金屬矽化物層311(1), 311(2)及311(3)。 “请參恥附圖1及附圖2,附圖1為未經過預先處理之 半導體基材形成金屬矽化物層後之電子顯微鏡照片;附圖 2為經過預先處理之半導體基材形成金屬矽化物層後之電 子顯微鏡照片。未經過包括第一熱處理及氮離子佈值之預 先處理的半導體基材,進行第二熱處理之退火步驟之後, ::於3妙?電區域(附圖1中淺色梯形區域)上形成不規 、且不連續之金屬矽化物層,即附圖1中淺色梯形區域上 200915432 端之深色不規靠域。㈣第—讀處職氮離子佈植之 預先處理时導㈣材,騎第二熱相之敎步驟之 後,係於含石夕導電區域(附圖2中淺色梯形區域)上形成 f教完整之金屬魏物層,即_ 2中淺色梯形區域上 端之深色區域。由附圖1及附圖2可知,對於半導體基材 進行第-熱處理及氮離子佈植之後,可以有效改善金屬石夕 化物層之結塊現象。 、睛繼續參照第2D圖,因為金屬矽化物層311(〗),311(2) 及311 (3)的阻值仍相當尚,因此以一般钱刻方式選擇性地 移除第2D圖中除金屬石夕化物層311⑴,1(2)及(3)外 之物貝後,一般會再進行一次溫度約7〇〇至9〇〇。匚的退火 处而彳于到如第2E圖所示之為二石夕化銘的金屬碎化物層 = 2(1),312(2)及312(3)(阻值約降至3〜8歐姆)。如此一 來,即完成本發明較佳實施例之金屬化製程。當然,於其 他實知例中’步驟14〇的第二熱處理亦可使用快速退火處 理來直接一次形成為二石夕化始的金屬石夕化物層。 如此一來,藉由步驟12〇中的第一熱處理而得到較佳 的沈積環境條件後,可有效降低後續一次或兩次的熱處理 中金屬矽化物的結塊現象而獲得均勻度較高之金屬矽化 物層。藉此,無須為了因應可能的結塊現象而增加金屬層 之沈積厚度’同時也避免漏電流的情形,而大幅提高金屬 矽化物的熱穩定性及電晶體元件的運作性能及產品良率。 本發明上述實施例所揭露之金屬化製程,係於沈積金 屬層之刚,對半導體基材進行一次熱處理以獲得較佳的沈 200915432 積環境條件,從而減少後續熱處理中金屬矽化物的結塊現 象。當然,如前述,本發明之金屬化製程可應用於任何積 體電路中來改善内連線或元件特性,以提升積體電路整體 效能,也使得製程範圍(process window)更有彈性。 綜上所述,雖然本發明已以較佳實施例揭露如上,然 其並非用以限定本發明。本發明所屬技術領域中具有通常 知識者,在不脫離本發明之精神和範圍内,當可作各種之 更動與潤飾。因此,本發明之保護範圍當視後附之申請專 D 利範圍所界定者為準。An annealing treatment is carried out in a nitrogen atmosphere (flow rate of about 1 to 10 slm, pressure of about 1 atm) at a temperature of 450 to 700 ° C for about 20 minutes to 3 hours. In other embodiments, the first heat treatment can also use a Rapid Thermal Processing (RTP) with a higher temperature setting. By performing the first heat treatment, the material on the semiconductor substrate 200 which is unfavorable to the subsequent metallization process can be effectively removed, and the surface structure of the semiconductor substrate 2〇〇 is repaired, so that the germanium-containing conductive region of the crystal element 220 is cleaner. smooth. U Conventional Metallization Process Prior to the metal deposition step, only the pre-clean steps, such as the use of hydrogen fluoride, are used to achieve the desired deposition environmental conditions on the surface of the semiconductor substrate. However, the pre-washing step has a rather limited effect on the removal of the aforementioned unfavorable substances and does not improve the surface structure of the semiconductor substrate. Thus, the present invention achieves (4) depositional environmental conditions by means of a heat treatment step. #然, Money step 13 〇 如 ' can also perform a pre-wash step. : In Fig. 2C, in step 13", after obtaining the secondary environmental conditions of the field by step (10), the desired metal 200915432 layer 310 can be formed by tantalum deposition. In the present embodiment, the metal layer 310 is illustrated by including a diamond (Co) as an example. In other embodiments, the metal layer 310 may also use, for example, titanium (ti), nickel (nickel), indium (molybdenum, Mo), or the like. Generally, an absorbing layer 320 and a diffusion barrier 330 may be formed on the metal layer 310 as shown in Fig. 2C. The absorbing layer 320, for example, uses titanium to help react the native oxide of the substrate 210 to reduce oxygen contamination during the subsequent formation of the metalloid. The diffusion barrier layer 330, for example, uses titanium nitride to reduce diffusion loss of the metal layer 31 后续 in subsequent thermal processes. In addition, it is worth mentioning that before the formation of the metal layer 310, an ion implantation may be provided on the desired ytterbium-containing conductive region, such as nitrogen ion (N) implantation, thereby changing the metal lithium in the subsequent heat treatment. The grain size improves the agglomeration. As shown in Fig. 2D, in step 140, the semiconductor substrate 2 covered with the metal layer 310, the absorbing layer 320, and the diffusion barrier layer 330 is subjected to a second heat treatment such as an annealing treatment at a temperature of 400 to 550 °C. Thereby, the metal layer 31〇 containing samarium cobalt is reacted with the gate G, the drain D and the source § to form a metal halide layer 311(1), 311(2) and 311(3) for recording a single telluride. ). "Please refer to Figure 1 and Figure 2, Figure 1 is an electron micrograph of a metal halide layer formed on a semiconductor substrate without pretreatment; Figure 2 is a metal halide formed on a pretreated semiconductor substrate. Electron micrograph of the layer after the layer. The semiconductor substrate including the first heat treatment and the nitrogen ion cloth value is not subjected to the annealing step of the second heat treatment, and the light-emitting region (Fig. 1) A rectangular and discontinuous metal telluride layer is formed on the trapezoidal region, that is, the dark color irregularity at the end of 200915432 on the light trapezoidal region in Fig. 1. (4) Pre-treatment of the nitrogen-ion implant at the first reading The time guide (four) material, after riding the second hot phase, is formed on the conductive area containing the stone (the light trapezoidal area in Fig. 2) to form a complete metal Wei layer, namely _ 2 light trapezoid The dark region at the upper end of the region. As can be seen from Fig. 1 and Fig. 2, after the first heat treatment and the nitrogen ion implantation of the semiconductor substrate, the agglomeration phenomenon of the metal lithium layer can be effectively improved. 2D map because of gold The resistance values of the germanide layers 311 ( 〗), 311 (2) and 311 (3) are still quite good, so the metal removal layer 311 (1), 1 (2) in the 2D image is selectively removed in a general manner. And (3) after the object, usually another temperature of about 7 〇〇 to 9 〇〇. The annealing of 匚 彳 到 到 如 如 如 如 如 如 如 金属 金属 金属 金属 金属 金属 金属 金属The chemical layer = 2 (1), 312 (2) and 312 (3) (the resistance is reduced to about 3 to 8 ohms). Thus, the metallization process of the preferred embodiment of the present invention is completed. Of course, other In the embodiment, the second heat treatment of the step 14 can also be directly formed into a metal-lithium layer of the first stone by using a rapid annealing treatment. Thus, by the first heat treatment in step 12 After obtaining better deposition environment conditions, the agglomeration of the metal telluride in the subsequent one or two heat treatments can be effectively reduced to obtain a metal halide layer with higher uniformity, thereby eliminating the need for possible agglomeration. Increasing the deposition thickness of the metal layer also avoids the leakage current, and greatly increases the heat of the metal telluride Qualitative and operating performance of the transistor component and product yield. The metallization process disclosed in the above embodiments of the present invention is performed on the semiconductor substrate immediately after the deposition of the metal layer to obtain a better environmental condition of the 200915432 product. , thereby reducing the agglomeration of the metal telluride in the subsequent heat treatment. Of course, as described above, the metallization process of the present invention can be applied to any integrated circuit to improve the characteristics of the interconnect or the component to improve the overall performance of the integrated circuit. The process window is also more flexible. In summary, although the invention has been disclosed above in the preferred embodiments, it is not intended to limit the invention. Various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope defined in the appended claims.
11 200915432 【圖式簡單說明】 第1圖係依照本發明之金屬化製程之流程圖。 第2A〜2E圖係分別為依照本發明較佳實施例之金屬 化製程應用於電晶體元件時之製程剖面圖。 【主要元件符號說明】 200 :半導體基材 210 :基材 1 1 220 :電晶體元件 221 :閘極氧化層 222 :間隙壁 310 :金屬層 320 :吸收層 330 :擴散障礙層 311(1)、311(2)、311(3)、312(1)、312(2)、312(3):金 屬石夕化物層 I G:閘極 S :源極 D :汲極 1211 200915432 [Simple description of the drawings] Fig. 1 is a flow chart of a metallization process in accordance with the present invention. 2A to 2E are process cross-sectional views respectively showing a metallization process applied to a transistor element in accordance with a preferred embodiment of the present invention. [Description of main component symbols] 200: semiconductor substrate 210: substrate 1 1 220 : transistor element 221 : gate oxide layer 222 : spacer 310 : metal layer 320 : absorption layer 330 : diffusion barrier layer 311 (1), 311(2), 311(3), 312(1), 312(2), 312(3): metal lithium layer IG: gate S: source D: drain 12
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US11/902,228 US20090081859A1 (en) | 2007-09-20 | 2007-09-20 | Metallization process |
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TW200915432A true TW200915432A (en) | 2009-04-01 |
TWI393187B TWI393187B (en) | 2013-04-11 |
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CN (1) | CN101393855B (en) |
TW (1) | TWI393187B (en) |
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CN102117744B (en) * | 2010-01-05 | 2013-04-03 | 无锡华润上华半导体有限公司 | Method for forming self-aligned metallic silicide |
CN102142366B (en) * | 2010-01-28 | 2013-04-03 | 无锡华润上华半导体有限公司 | Method for forming self-aligned metallic silicide |
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US5834800A (en) * | 1995-04-10 | 1998-11-10 | Lucent Technologies Inc. | Heterojunction bipolar transistor having mono crystalline SiGe intrinsic base and polycrystalline SiGe and Si extrinsic base regions |
KR100367740B1 (en) * | 2000-08-16 | 2003-01-10 | 주식회사 하이닉스반도체 | Method for fabricating gate oxide film |
US6890854B2 (en) * | 2000-11-29 | 2005-05-10 | Chartered Semiconductor Manufacturing, Inc. | Method and apparatus for performing nickel salicidation |
US6514843B2 (en) * | 2001-04-27 | 2003-02-04 | International Business Machines Corporation | Method of enhanced oxidation of MOS transistor gate corners |
US7396697B2 (en) * | 2003-04-28 | 2008-07-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and method for manufacturing the same |
US7119012B2 (en) * | 2004-05-04 | 2006-10-10 | International Business Machines Corporation | Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation |
US7544610B2 (en) * | 2004-09-07 | 2009-06-09 | International Business Machines Corporation | Method and process for forming a self-aligned silicide contact |
US7435651B2 (en) * | 2005-09-12 | 2008-10-14 | Texas Instruments Incorporated | Method to obtain uniform nitrogen profile in gate dielectrics |
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2007
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CN101393855A (en) | 2009-03-25 |
CN101393855B (en) | 2012-12-12 |
TWI393187B (en) | 2013-04-11 |
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