TW200915123A - Architectural physical synthesis - Google Patents

Abstract

The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement. and the incremental improvements on placement made with knowledge of current circuit logic.

Description

200915123 IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to the field of integrated circuit design, and more particularly to the design of an integrated circuit that passes through a synthesis program according to a high-order description. RELATED APPLICATIONS This application claims the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit. This application is also related to 申请 Application No. _, entitled “Physical Synthesis of the Framework” (Archive No. 02986.P059) and applied for it on the same day. [Prior Art] Regarding the design of digital circuits on the scale of VLSI (Great Scale Integration) technology, designers often use computer-aided technology. Standard languages such as Hard Description Language (HDL) have been developed to illustrate digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved into industry standards. VHDL and Verilog are general-purpose hardware description languages that allow abstract data types to be used to define a hardware model at the wafer prototype level, scratchpad transfer level (RTL), or behavior level. - As device technology continues to advance, various product design tools have been developed to make HDL suitable for newer devices and design styles. In the design of an integrated circuit using an HDL code, the code is written first and then compiled by an HDL compiler. The HDL source code describes the circuit components at a level, and then the compiler generates an RTL circuit plan list (netlist) based on this compilation. An RTL circuit planning list consists of a plurality of RTL objects or 133330.doc 200915123 components and a plurality of networks, which are signal connections between the components. The RTLf road planning list can be (4)—a technically independent circuit planning list because it is independent of the technology or architecture of the integrated circuit of a particular vendor, such as a field programmable inter-array (FPGA) or a specific application integrated circuit (ASIC). ). The RTL circuit plan list corresponds to a schematic representation (relative to the - behavioral representation) of the circuit elements. Then carry out the mapping operation to (4), the independent RTL circuit specification (4) to the m branch (four) road planning early morning 'it can be used to establish circuits in the supplier's technology or architecture, including placing the examples and arranging the mutual The path is such that the circuit satisfies a given timing, space, and power constraints. Early Electronic Design Automation (EDA) A was synthesized and separated from the placement/arrangement shown in Figure 4. At the time of shooting, prepare the HDL code. In the operation towel, the legs prepared by the synthetic money towel are compiled to produce a circuit planning list, which is preferably optimized by performing logic optimization. Thereafter, a mapping program maps the circuit planning list to a specific target technology/architecture. At the end of operation 13, the synthesis has been completed and a list of force circuit plans is provided, which is specific to the technology/architecture used by the supplier 1 (: This circuit planning list is effectively at the gate level, timing The analysis is based on pre-amplification information such as fan-out count or connection component type and size using a statistical model of the interconnect characteristics. After synthesis, a conventional placement operation is performed on the logic circuit at operation 15_ The circuit planning list (only in a wafer prototype or unit or gate level) is changed in the operation port to meet the timing performance. Then, a conventional arrangement path operation is performed in operation ί9 to be in each IC of the iCs. Establish a circuit design. If there is 133330.doc 200915123, the program does not meet the constraint', then the program uses the loop to return and modify it repeatedly. From the shovel, § the case delay dominates the early synthesis tool, based on the statistical model The timing estimation is sufficiently accurate, so that the separation synthesis and the relatively low requirements of the text are returned to the hdl and synthesis stages. However, the iw technology node is constantly Small, the interconnect delays become significant, thus exceeding the gate delays. This results in less and less delay estimates in the synthesis operation associated with the actual delays after placement and scheduling of the path operations, causing post-synthesis and post-synthesis The timing predictability between layout results is not s °. In many cases, after these placement and scheduling procedures, the circuit entity layout cannot meet the circuit design criteria, so designers often have to start from the synthesis step and Repeating such synthesis/relocation/arrangement path procedures. In order to improve sigma, it is important to describe the physical characteristics associated with the design (eg, placement) during the synthesis process. A series of techniques have been employed to bring the placement information into the synthesis program. Xiao Ru floorplan, site optimization (IPO) and physical synthesis. “In the floor plan technology, the design is divided into multiple regions on the wafer and the placement-based interconnect is used for estimation. Inter-area interconnections, using statistical models to estimate interconnections within the area. The floor plan can be made in the early RTL phase. It can also be used after running an initial synthesis. The floor plan can be extended to divide the RTL component into 'multiple regions and copy (10) ce into multiple regions and combine the RTL hierarchical timing and area models. It can then be used from inter-regional timing. Improved timing to drive RTL level optimizations more accurately. Manually generated - better quality floor plan is challenging and requires users who are fascinated with 133330.doc 200915123. Similar to those from Tera Plus (US Patents 17 and 6, The automatic floor plan of 36G, 356) can establish the area and assign RTL to it, and the accuracy of the timing and area information during the floor plan is poor because the synthetic system solves the surface and follows the automatic floor plan. The technique of optimization (IP) provides placement and scheduling of inverse interpretation of path delays into the synthesis domain. The critical path is re-optimized, but because the detailed placement is not updated, the interconnect delay for the modified network is returned to the statistical model. If many changes are made, the following normalization of the resulting circuit plan list may require that the case be moved away from its initial position, resulting in a larger k-delay D-time error. For this reason, the IPO is unstable when significant changes are required to obtain timing closure. Another technique is entity synthesis, which is an improvement over one of the IPO techniques, in which a small amount of optimization and incremental recombination on the mapping circuit planning list is used to maintain the fidelity of delay and resource metrics. One of the technologies is limited; individual changes are limited to the most appropriate resource increase or the re-surface treatment of IPO technology. For example, there are several different algorithms for entity synthesis. The algorithm is not an algorithm that uses a near-release timing estimate based on placement examples to provide an entity synthesis engine. After the initial circuit planning list in operation 23, in operation 24 performed only at the wafer prototyping level, portions of the poetic synthesis function selection circuit are used for incremental optimization and relocation. According to the above, ^^ ‘improvement. It can be seen that '4 algorithms to be used for electronic design automation are as patented, or wafer synthesis, and these patents include: 133330.doc 200915123 US Patent 6,519,754, 6,711,729, 7,010,769, 6,145,117 and 6,360,356. The placement algorithm was recently written in: Bo Hu , Timing_

Driven Placement for Heterogeneous Field Programmable Gate Array (IEEE/ACM International Computer Aided Design Seminar, IEEE/ACM International Computer Aided Design Workshop, 2, 6 years, 丨j (ICCAD '06), 383 Go to page 388 (ISSN: 1092-3152, ISBN 1- 59593-389-1). SUMMARY OF THE INVENTION The present invention discloses a method and apparatus for designing an integrated circuit. In an exemplary embodiment, the circuit design of the present invention reveals a repetitive process of synthesis and placement that begins with an RTL or behavioral level where each of the inverses provides an incremental change through the transformation of the integrated circuit design. In a particular aspect, the transformation can be a composite or placement transformation. A synthetic transformation modifies the objects within the circuit plan list and/or the network forming a connection between the objects. A placement transformation modifies the location of one or more objects in the circuit planning list. The present invention <at least, the specific embodiment t incremental repeat scheme uses a suitable synthesis and placement transformation of the mosquitoes such as the current circuit circuit planning list, placement, timing, resource availability, and electrical design to provide a connection - monthly In the special cancer sample, after each transformation, the affected design metrics are updated, so that the future transformation decision is based on accurate statistics. The procedure is repeated in response to the 30th final timing resource and power closure. At least a particular embodiment of the present invention - the key aspect is that placement occurs before a particular resource type has been identified for a higher order component. For example, the classification is used for, and the alternative implementation of the required weights and associated resources is 133330.doc

* 1U 200915123 scenario and the placer evolves the placement to move the components close to the resource type used for the desired implementation. In a preferred embodiment, the invention begins with a diagram representing one of the wafer resources RTL or behavioral design (circuitry) and a physical map. The inverse transformation is carried out, and one of the circuits or objects in the transformation generating circuit is optimized or refined. In a particular embodiment, the transformation consists of - high order optimization. This translating-(four) or mathematical transformation to optimize a component or a plurality of components into a set of functionally equivalent alternative components, the source consumes excellent features. This transformation algorithm improves the delay sharing by reducing the height of the tree. It has examples such as timing, power, or capital to reorganize arithmetic operations. Another example is resource sharing or not, in another embodiment, the high order optimization transform refines the circuit object(s) of the group(s) from a more abstract form to a more specific form. An example of a refined transformation maps an arithmetic expression to a DSP resource on the wafer. When it comes to refinement—the abstract form, there are usually many implementers. For example, '-arithmetic expressions can be performed by on-wafer-special-purpose arithmetic functions (a DSP block), by a) 秸 隹 己 己 己 己 己 己 己 己 己 己 或 或Build - find the bait on the slap on the low-level logic components to implement. From a behavioral spoon. The components that are captured may have a registration based on sex scheduling and resource sharing. Such alternatives for behavioral components can also be dynamically based on the current use of source and interconnect delays. In another embodiment, the privilege transformation is also based on the alternative 133330.doc 200915123 The quality of the scheme has an emergency metric and is selected in a chronological order. The quality of an embodiment is measured based on design goals such as area consumption, power consumption, or timing. Other more esoteric targets such as single event flip hardness can also be included. For example, if a design includes a large memory and a plurality of small memories, and the large memory has a relatively poor implementation quality when implemented by a logical fabric, the large memory and the scarcity on the wafer are specially designed in the design. The use of memory resources is much more important than the medium memory. The emergency metric for this large memory will be much higher than the metric used for these small memories. Once the components are mapped to a particular implementation and associated with particular resources on the wafer, the connections to the components serve as anchors for the remainder of the placement circuitry, thereby improving the quality of timing and available resource estimates. In a particular embodiment, the placement transformation may be based on one or more locations where the object can be placed - refined to improve placement metrics, such as: example female routing and circuit performance. A configurable object can be comprised of a behavioral composition component, an unmapped logic RTL chunk, mapping logic, or any combination of these. In a particular embodiment, the placement transformation can modify objects of different levels of abstraction. For example, some of the configurable objects may be RTL chunks, but may be mapped gates. , . In a particular embodiment, the triggering-refining transformation is triggered when the placement is fully evolved such that the available resources are scheduled to be delayed (10).疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 13- 200915123 Select in any order, but only for its functionality. The circuit design automatically selects the next transformation based on the selection function, ie synthesis or placement. The cost of each of the repeated ' δ1• is used to calculate the list of changes. This cost may include projections of changes in costs of other transformations. For example, if the -Arithmetic Maps-ROM', the R〇M option can be removed to perform another operation, thereby increasing its cost. The optimal transformation is selected based on cost convergence criteria such as current placement, circuit planning inventory, resources, timing, or power.

The down-transformation can be a placement update, a resource assignment, a synthesis optimization placement optimization, or an arrangement path update. As a result, the state of the 1C design progresses toward the final circuit specification and layout. In another embodiment, the placement transformations are performed repeatedly until the critical path begins to form or until the resource is fully distributed according to a predetermined congestion threshold. The criteria for repetitive performance are the Japanese temple order, congestion per resource layer, area utilization, and electricity. Congestion per resource layer can be determined by using the resource layer. There is a resource layer for each of the different prototype type resources on the wafer. For example, today's FPGAs and structured ASICs have introduced irregular layouts of prototype wafer resources. Some prototype types include logic (LUT), flip-flops, special I/O units for high-speed serial interconnects (such as SERDES), and various memory components with different capacity and high-speed arithmetic blocks to accelerate the Dsp algorithm. In addition to logic and flip-flops, in general, these resources are included in a sparse and possibly irregular manner. Many FPGAs have a limited amount of RAM, DSP, and other dedicated logic blocks that are sparsely arranged on the wafer. For example, a 'DSP trick block may be available in only 2 lines within the wafer layout. A 133330.doc 14 200915123 Resource layer - a distribution map established for each prototype type and records the location of available resources for that type and the placement of each type of prototype of that type exists in the presence - use more localized entities than supply The area is considered to be plugged. In this method, the typical state, from the high-order representation with timing constraints and placement constraints (such as 10 pins, existing floor plan or existing placement) - the initial state of the integrated circuit design. The higher order representation may be a hardware description language (ship) code or a technically independent RTL circuit planning list after being compiled according to the hardware description language (hdl) code. In one embodiment, the green is used to optimize the circuit planning list for the initial state of the integrated circuit design by series-neutral optimization. Such neutral optimization may be based on the revoked-area-recovery (such as resource sharing or non-common); plus crying human μ ^ } to steal the tree decomposition, preferably based on the fan-out table Timing; - Resource assignment, circuit planning checklist - Hauen to promote optimization across the hierarchy; multiplexer capture or reconstruction. In a specific embodiment, the general state of the design state of the integrated circuit proceeds from the - RTL circuit planning list to - decomposition and factorization followed by a mapping and scheduling path; fk circuit planning list. Placement modifications, resource assignments, and area or timing optimization are implemented through the entire flow. In a particular embodiment, the process of 'refinement placement and circuit architecture is repeated until all high-level components have been given-specific implementations and resource assignments and the placement has been spread over w such that each__ has sufficient nearby resources for implementation . - A more traditional physical synthesis stream can be used to complete the implementation from now on. In the other embodiment, the transformation applied and its potential substitution are recorded 133330.doc -15· 200915123. This stream can be repeated and these alternative transformations can be applied to obtain better results. The invention also discloses apparatus comprising a software medium that can be used to design an integrated circuit. For example, the present invention includes a digital processing system capable of designing an integrated circuit in accordance with the present invention, and the present invention also provides a machine readable medium that causes the digital processing system to be executed on a digital processing system, such as a computer system A method for designing an integrated circuit is implemented. Other features of the invention will be apparent from the description and drawings. [Embodiment] i, i describes a method and apparatus for designing an integrated circuit or a plurality of integrated circuits. In the following (4) _ ′ A, the description of the present invention is made in order to provide a thorough understanding of the present invention, and it will be understood by those skilled in the art that the present invention can be practiced without the specific details. In other instances, well-known structures, <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The present invention discloses a method and body embodiment for designing an integrated circuit that is placed and combined in a single-action combination. A specific embodiment discloses an entity synthesis procedure, referred to as architectural entity synthesis, in which the interaction between composition and placement is at an architectural level: This allows for the synthesis and actual physical placement on one of the substrates of the integrated circuit to occur, thereby providing a usable local resource and delay estimation, which is closely related to the synthesis of the actual circuit timing from the placement, and thus can be considered simultaneously The interaction between synthesis and placement. In addition, this provides an automated method for making surface-level architectural decisions, mapping high-order groups in a way. I33330.doc 16 200915123 = Performing high-order circuit transformations, making placement, congestion estimation, and ambiguity (including but not limited to The physical distribution of different resources; interconnection delay) is considered. According to the invention, the state of the invention is given to the circuit-setting of the ship, and the weight is as follows: In order to achieve - the best design implement / such as two based on the current available circuit data collected through the resettlement

Backtracking an earlier synthesis decision (such as timing or power). Thus, in one aspect of the invention 'in a high-order design or behavioral representation in an early synthesis cycle, such as in a circuit architecture hierarchy, an implementation is implemented to allow for an accurate assessment of the applicability of various design implementations. This is especially important for pre-diffused wafers such as FPGAs and structured ASICs where the distribution is unevenly distributed across the wafer. In pre-diffused wafers, resource locations and negative source types are predetermined and distributed in a sparse manner. For example, today's FPGAs and structured ASICs have introduced irregular layouts of wafer resources. Such

The components can include logic, flip-flops, special I/O cells (such as SERDES) for high-speed serial interconnects, and various memory components with different capacities and high-speed arithmetic blocks to accelerate DSP algorithms. Many FPGAs have a limited amount of RAM, DSP, and other dedicated logic blocks that are sparsely configured on the wafer. For example, a DSp arithmetic chunk may be available only within 晶片 within the wafer layout. In a bad case, the present invention addresses this change in wafer architecture evolution to integrate physical placement and architectural selection at the beginning of the composite stream. This requirement can be at the RTL level or at the behavioral synthesis level, where the number of different types of requirements is determined 133330.doc 17 200915123. The current awareness and placement of resource layout information in an early synthesis process (such as when an implementation of many components of an design has not been selected) provides integration - optimal resource utilization. For example, one of the resource layout information is not aware of the RTL synthesis program, which may result in an intermediate circuit planning list that overuses some resource material while other resource types are underutilized. In addition, these resource type decisions may not be compatible with the physical location of such resources. For example, multiple DSP resources beyond the available ones can be found in one of the localized portions of the wafer. This synthesis method can provide an efficient use by understanding the distribution of such resources on the wafer and not only knowing that there is a sufficient amount of specific resources, but also knowing that there are sufficient resources nearby. As a result, large interconnect delays due to the delivery of signals to different placed resources can be avoided. In accordance with one aspect of the present invention, various placement decisions are made while the synthesis is still in a higher order circuit representation (e.g., many components in a design may still not have a selected implementation) or a gate alignment description is yet to be determined. These placement decisions may enable accurate evaluation of circuit parameters, such as timing delay or power consumption, thereby permitting an incremental path toward an optimal design implementation. In a specific embodiment, as shown in FIG. 3, in operation 3, the program starts with an initial state of one of § §, which may include an ESL or HDL language, a behavior abstraction, or a compiled HDL code to RT1. Circuit Planning Checklist - High-level abstraction, plus timing, floor plan, power, and placement constraints. In operation 31, a synthetic transformation is performed which will be a higher order transformation in the early stages of the procedure. This composite transformation may only be part of this design. In 133330.doc -18- 200915123::32, the placement transformation is carried out on the existing circuit representation, and in an early F white section, it will be tied to an architectural layer - human - female. This placement transformation may only be part of the '... and #. Such resettlement decisions during this operation may require a variety of observations, as it may be missed in this early (four) paragraph and then ready to evaluate the position at operation 34, and if it meets 4 and the legal target' then Moving to the traditional entity composition continues in operation 48. As may be possible at this early stage, if these targets are not met, the loop will be returned to another round of synthesis. The next synthetic iteration (current operation 31) will improve the design representation, especially after having the physical placement information (previous operation 32). And similarly, the next placement reversal (current operation 32) will improve its circuit parameter estimates after having a synthetic improvement. Using such close loops, the synthesis and placement can work closely together to provide a - path to - optimal design representation without significant redoing. In a specific embodiment, the synthesis operation is provided as a circuit design representation, and the placement operation can perform circuit parameter analysis to help narrow down the options. For example, if implementation #1 is clearly outstanding, it will be selected and the number of potential implementations will be reduced to -. Alternatively, if implementation #2 clearly exceeds the design constraints, it will be excluded, thereby reducing the number of potential implementations by one. In accordance with one aspect of the present invention, an exemplary method for designing a plurality of integrated circuits is presented from an abstract machine specification - integration, interaction, and recombination and placement. In a particular embodiment, the design assembly The exemplary method of the circuit incrementally changes the state of the 1C design. Start with 1 (: design an initial state, which contains ESL or HDL language, a behavioral abstraction or - compile 133330.doc • 19- 200915123 HDL code to RTL circuit planning list, high-order abstraction, plus timing, floor plan 'Electricity and placement constraints, the exemplary method incrementally and repeatedly changes the 1C β 状 Sense until an optimized design state is reached. The optimization ‘% is better to satisfy the timing and placement constraints —— The wafer prototype hierarchical circuit planning list 'may be (4) passed to the transmission and arrange the path procedure without any extensive redoing. According to one aspect, the present invention discloses a repetitive procedure of synthesis and placement, wherein each of the repetitive processes is repeated An incremental variation is provided in the circuit design. A general example of a particular embodiment of the present invention will be provided with reference to Figure 4. The method of Figure 4 begins with the initial state of the Ic design generated in operation 4G '纟. The initial state of the design includes A behavioral representation or high-order RTL circuit planning list, which can be compiled by the HDL source code, which describes the circuit and logic. A higher-order behavioral representation of the design. This saves the abstract information for use by the program before the final mapping step. This is different from traditional compositing tools, which segment the design into fine, low-level (slam) immediately after language compilation. ) By storing a higher-order behavioral representation, a synthesis tool can perform optimization, partitioning and planarizing the map at a far more global level and generally submitting better images (4), the synthesis tool can also be more The high-order RTL circuit planning list contains a hierarchical abstraction independent of any particular vendor technology or architecture, such as a circuit block representation. The initial state of the 1C design further includes timing constraints, power constraints, and placement. Constraints, such as 10 pin locations, existing floor plans or existing placements (e.g., 1C wafer size and shape, ΙΡ block). In operation 42, increment 133330.doc -20· 200915123 to change the state of the ic design. The state of the circuit design _ generally includes the road planning list, timing data, resource information, resettlement information 'arrangement path information and power resources. Incremental changes in the design state can be modified or placed, and will be further described below. In one of the departures of the invention, the changes are incremental, meaning that the design optimization is generally modified with minor modifications. Continue with all current information such as timing estimation and placement constraints. These incremental changes allow the design to progress with confidence, making it steadily, exhibiting. In the -state, 'the incremental changes involve-incrementing global placement algorithms such as force guidance In another aspect, the incremental changes involve a global optimization algorithm, such as simulated annealing. In operation 44, the state of the ic design is evaluated, and in operation 46 it is determined whether to continue with the return operation 42. Progress is repeated 'or making a decision to complete the design flow at operation 48. This circuit-X juice method provides a highly integrated and interactive procedure between two basic steps in the design of an integrated circuit, namely synthesis and physical design (eg placement and routing). Conceptually, the synthesis and placement are strongly interdependent. Since the designation constraints cannot be accurately estimated in the synthesis, and there is no synthesis, it is impossible to implement the placement. Therefore, the design method of the present invention uses the incremental and repeated scheme to effectively combine the synthesis and the female placement into one. Step procedure. In the specific example, the present invention provides a reversal of the synthesis/placement transformation. § The main body of the remake procedure can be a combination of placement transformation, synthesis transformation or synthesis and replacement. In either case, the state of the integrated circuit design changes incrementally and repeatedly toward the synthesis or placement of the wafer prototype hierarchical circuit planning list that satisfies one of the design goals. Figures 5 and 56 show two examples for a portion of a stream of 6 and 1C; in the case of the method 133330.doc -21 - 200915123 shown in Figure 5A, the occurrence-placement transformation occurs first, followed by a The transformation is synthesized, and in the ®I 5B, the reverse occurs. The synthesis, placement or synthesis/placement and reversal transformations provide a continuous reversal between synthesis and placement in the design-state. The incremental and repetitive progress of the synthesis and placement ensures that the synthetic transformation always has the most up-to-date and accurate design state information, including delay information from the placement transformation and local resource availability, and wherein the 2-position transform is based on the most recent synthetic circuit gauge The bill of materials provides the best estimate of the path information for the entity, #set and women's volleyball. The set and synthesis transformations continue until the circuit planning list consists of only the wafer level prototypes, satisfying the set t targets, and then reducing the placement congestion to the level, and the t-detailed placement is independently legalized. Small local area. This stream can be followed by a conventional entity synthesis stream to complete the implementation. Figure 6 shows a specific embodiment of the invention for incrementally changing the design state. The present invention can place all levels of abstraction simultaneously. In the early days: the overlap between the objects at a higher level of abstraction than the one in which the design was mainly composed of a prototype of the wafer was more common. These wafer prototypes are generally the lowest order representations. Synthetic transformations gradually modify the circuit plan list to turn those objects at a higher level of abstraction into more specific objects. These specific items have more specific &gt; source requirements and are then considered in the following synthesis and placement transformations. The placement transformation determines the location of the circuit planning list item, ie, the RTL instance, the unmapped instance, the mapping instance, or the wafer prototype level instance, thereby determining the length and delay of the network in the circuit along with the router. The placement change can be placed over a legally placed gradual repetitive circuit, where legal placement means that the rules governing the use of resources for the 1C chip are met. In general, at 133330.doc -22- 200915123, these early reversals will not be legal. Since the placement change is incrementally changed at the position of the object, the single-reverse of the placement transformation will not be established in a legal placement. The placement will become legal through repeated placement changes. In this embodiment, the placement transformation is the center of the electronic design automation. In each of the repetitive, the criteria for repetitiveness may be time series data, congestion per resource layer, area utilization, power level, or any combination thereof. . The method may further include - possibly internal loop reversal to optimize the design to shape the critical path, or to spread the resources to a predetermined threshold. One of the methods of the present invention that uses incremental inversion of the synthesis and placement transformations. The physical design information is always available in the synthetic conversion wipes at all stages of the design. Thus, such optimizations and transformations in the synthesis are always up-to-date in terms of timing and region and also in arranging pathological effects. The decision-making and placement of the circuit structure is fully coordinated in the synthesis. The inventive method of incrementally recombining and arranging transformations has (iv) combining the synthesis and placement transformations to simultaneously optimize the logical structure and the spatial placement of a circuit. In the typical example of this method, the design of the integrated circuit is steadily moving toward the final circuit specification and layout. The progress of the reversal placement transformation may be one of a circuit planning list or a placement configuration to increase the maturity level. The maturity of a design is made up of only the wafer level prototypes by the circuit planning list, satisfying the design goals, and reducing the placement congestion to the -level H detail placer, which can easily legalize any small local area. To measure the degree. The progress of the inverse synthetic transformation can be optimized for synthesis, such as object 133330.doc -23-200915123 or entity reconstruction or replication to meet timing constraints. Synthesis optimization includes, but is not limited to, a circuit optimization, an abstract component decomposition, an arithmetic mapping, an undo/restore resource sharing, an adder tree decomposition, a placement-based and/or gate decomposition, a path replication, and a Path detour removal, an assignment to discrete resources such as RAM or DSP, a logic factorization, multiplexer reconstruction, or a circuit planning list is flattened to facilitate optimization across the hierarchy. A specific embodiment of the method is shown in Figure 6, beginning with an operation 61, where one produces an initial state of the 1C design. The state of the 1C design can be an RTL network with associated status information such as timing information, resource information, placement information, routing information, and/or power data. In general, the state of the 1C design contains sufficient information to specify such circuit requirements, such as functionality, timing, power, and floor plan. The hierarchical RTL circuit planning list contains a circuit planning list in which most of the objects are abstractions of these low-order wafer prototypes. The associated primitives of multiple groups can be compared to objects using a higher order table, which is the functionality encoded by the table M RTL. The higher order or abstract representation of the integrated circuit design can be a logical object that represents an RTL code or portion thereof. Each object generally represents a plurality of wafer prototypes&apos; such as more complex functions such as adders, multipliers, multiplexers and sequential logic, and AND functions, OR functions. Objects represented by higher order may also include memory chunks or private (intellectual property chunks or Ip) chunks. Other logic objects can be part of the RTL code to provide support functions such as glue logic (providing buffer or interface functions), timing logic, control logic, or memory logic. Some high-order RTL objects may also be wafer level prototypes. 133330.doc •24· 200915123 The list of object circuit plans also includes information on the various items associated with wiring and placement. The objects may include information to map back to the corresponding rtL code. In addition, the RTL code can include a hierarchy in which the functions are grouped together. In some cases, components can be regrouped from one level to another to optimize timing, routing, area, or power requirements. In other cases, the merged functional rtl hierarchy may be flattened, in whole or in part, during the incremental repeat procedure. The initial state of the design at the beginning may include constraints such as timing constraints, power constraints, and/or placement constraints. For example, the placement constraints may include the location of the pin, the existing floor plan, or existing placement information. In an exemplary embodiment, the initial state of the design is optimized by a series of timing-based neutral optimizations. These neutral optimizations include any area replies that can be easily undone, such as undo/restore resource sharing; adder tree decomposition based on fan-out table timing; significant resource refinement, such as 'if there is a huge in design RAM and only one RAM chunk resource is available, then the RAM has to go there; flatten the merged circuit plan list to promote optimization across the hierarchy; and capture and reconstruct the multiplexer structure. Based on the current design state (current placement, circuit planning list, timing, power, and scheduling path), a change is selected in operation 62 to incrementally change the state of the 1C design. Operations 63 through 70 are typical transformations in accordance with an embodiment of the present invention, including placement or update placement (63), assignment of resources (64), factorization (65), mapping (66), optimization logic (67) , establish/refine the implementation plan (68), update the route (69) and other synthesis (7〇). These 133330.doc -25- 200915123 transformations are generally small, incremental operations to permit seamless integration of placement and synthesis, thus using placement knowledge to perform the synthesis and using synthetic knowledge to implement the placement. The repeated and incremental transformations 63 to 70 thus include placement and synthesis operations, including optimization transformations such as undo/restore resource sharing, adder tree decomposition, AND/OR gate decomposition, logical replication, bit splicing (吣一μ ton), round-trip removal, factorization and placement transformations (such as assignment to discrete resources (ram, DSP, etc.)) and scheduling paths. In an exemplary embodiment, various potential transformations are evaluated based on the -cost function at each iteration, i.e., (10). The cost function is designed to operate with the best transformation selected, and thus includes design status information such as timing, female congestion, scheduled path congestion, area utilization, and power. The best transformation is performed after the evaluation and the continuation continues until the design constraints are met. In the case of I, the design can then continue to the conventional gate placement and arrangement path. In each case, the method selects the list and then selects the best transformation based on a cost function. For example, the choice between the 'placement transformation' and the -formation transformation is based on the timing closure criterion. On the critical path, such as the moon, you can try to shorten the critical network. If critical networks cannot be shortened, they can be used for physical synthesis optimization. According to another aspect of the local month, an exemplary method for designing an integrated circuit provides a "transformation" in which the synthesis and placement transformations are not selected for their functionality. The method provides a better integration between the synthesis and the female device. In the reverse, the state is based on the state of the integrated circuit design 133330.doc -26- 200915123, and the next step is to set the next _ m ^ The most advanced configuration progress with timing and placement constraints. In a 1, /, embodiment, the method provides a transform selection / where the next transform is selected based on criteria such as timing, per-resource layer congestion, area utilization, and a special criterion. The next transformation can be placed in A &quot; the circuit will undergo a repetitive process to make placement changes under less resource congestion, or better meet the design goal = transformation can be optimized for synthesis , such as a factorization 'one optimization' or - eight

The home knife-transformation can be a synthetic optimization 'such as points. Refactor or copy to meet timing or critical path requirements. The next transformation can be made up of * ; ^ ^ α , which can be mapped to the lower level of the circuit specification and the path of the layout or update arrangement toward the wafer prototype hierarchical circuit planning list. Next: Transforms can be tied to placement optimization, such as floor plan partitioning, lean source assignment, logical reconstruction or replication to meet timing or critical path requirements, or to route updated arrangements for routines. The next transformation can be a synthetic operation in which the current circuit plan list can be mapped to a lower level of abstraction to the finality of the circuit specification and layout. 'Using incremental transforms' such as timing and power design status information is up to date and optimized because of the ability to accurately view the impact on the target. In an alternative embodiment, several transforms are selected. Each t疋i is then applied to measure the effect on the design state and return or revoke. Then select and apply the best transformation. In a specific embodiment of the circuit planning list, one of the key steps of the present invention is operation 68, the implementation of which each RTL object is established or refined. 133330.doc • 27· 200915123 Scheme selection. - The associated function implements an estimate of the shape and resources required for the alternative embodiments of the example: In the second embodiment, operation 68 may also assign weights to each implementation: in the other two specific φ φ, . 4th is not a better solution. The advantage of the present invention incorporating the synthesis and placement at the architectural level is that it allows for the evaluation of different architectural implementations. Without using the entity synthesis of this architecture, the mTL synthesis stage selects the quasi-relocation stage of the gate, and Jiang Heding _ is unable to recover high-level information at the A n. This can lead to goodness if other embodiments are preferred. Therefore, if you use the implementation decision at the RTL level, you can get better conversions that are difficult to implement. Female and women's volleyball road segment mapping circuit, this degeneration:: chemical, operation - ^ Μ, the function implementation F = s &amp; (A * c;: * will be used to: the operation number S is 1, Then F phase phase (B right choice letter

The result of multiplication. Falling 68A right _’__C example. Fig. ==: The possible implementation alternatives to the two functions that can be created by the function; = refined implementations can be used for this multiplier with a multi::, alternative to the scheme. It is desirable to use the two-order key and select the implementation scheme, which may indicate that the utilization-single 1^, / recent material_ is displayed when the F system is output. Figure _ In (4) The most recent multiplex 11 implementation, which will be more desirable at the time of transmission / F non-timing critical and requires area reduction. Use this function for 7 examples to explain #source sharing / not sharing. No, and placement information, a typical high-level synthesis performance 133330.doc -28- 200915123 The algorithm will evaluate the resources used for two extremely expensive multipliers, such as the heart of the map. Even in the case where the placement of the traditional stream is placed in the vicinity of the dedicated unused multiplication method, the output is critical and

In the case where the selection signal S arrives after A, ΒΚ, this will still be the case. In this invention, operation 68 will establish both of these embodiments, and possibly other 'so that the alternative is excluded when it is clearly below the standard. . For example, as it goes on, it may be obvious that the output F is not critical. In this case, operation 68 will refine the implementation selection to only the figure, since this alternative uses less resources. Alternatively, operation 68 may exclude the embodiment of FIG. 10B when F is more critical with selection line $ and there is an access to the site, the store, the &amp; h 1 nt using the source to implement the singular multiplier . The ^ga chip generally has a plurality of pre-diffused memory resources, such as positive and negative, and variable blocks (such as 512, 4K) chunks and defeats. - The memory components required by the design also vary in size. In general, it is not clear how these memory components will be implemented. For example, a modest size RAM between two and 512 bits can be implemented using a flip-flop, a resource, or even a 4k resource. Moreover, resource locations for larger memories are generally sparsely available only on the wafer. In previous eda tools, placement information was not available during the memory implementation phase. Therefore, implementation decisions are made without local use and precise timing information. This limitation can result in severe performance degradation. If a modest amount of RAM is implemented as a $1 2 resource and the only available 512 location is located away from the logic to which the RAM is connected, then forcing the RAM to become a 512 will result in a longer interconnect and enable implementation in a gallop The delay benefit of using a 5丨2 site on the solution is invalid. Even if 133330.doc -29- 200915123 one of the implementations using a flip-flop may have a longer delay, if this implementation allows a shorter link between the logic of the RAM's flip-flop and the RAM connected, this can be Lead - faster design. Alternatively, if there is a 4Kf source available near the connection logic of the RAM, it may be advantageous to implement as a 4 Κ. Memory implementation decisions should therefore be made within the consideration of the various available memory resources and the location of the components connected to the memory. #图9Α An example of a memory implementation decision. The figure shows a memory of the top and bottom of a &amp;a&apos; A 4-bit RAM is connected to a contact and a gate on the right side of the wafer. If the RAM is implemented as a memory and placed on top of the wafer, it can result in the interconnection of the pole = to its contact input and to the AND gate it drives. Figure 叩 shows the same logical-alternative mapping. This RAM is implemented using nearby logic and thus shorter interconnects and delays. /Mission is associated with the system-function of operation 68, which estimates the shape and resources required for a real &amp; scheme. In a particular embodiment, this function implements a mapping for the purpose of estimating resources for the hunger component. In another embodiment, this mapping is specific to the target wafer architecture. The resource estimates are based on the logic requirements and inputs that are designed to estimate the particular component and output requirements to implement the module in the target architecture. In addition, the one-piece body ~ the case towel 'the function material' the &amp; piece estimates the sequence change. Figure 7 illustrates an example of an adder that adds two busbars: 〇] and 叩1: 〇] to produce - a third bus 〇 [3i: g]. Through-transformation to estimate the logical region used to implement the adder, estimating the implementation, "the required resource and the internal transition delay from its input to its output. At 133330.doc •30· 200915123 For example, two logic array blocks (LABs) can be used to implement the adders' each consisting of 16 lookup tables (LUTs). Operations 65 through 67 and operation 70 are exemplary synthesis conversions, for example, logic Factorization (Operation 65), Logical Mapping (Operation 66), Logic Optimization (Operation 67), and Abstraction (Operation 70) 'where the components and connections represented by the RTL circuit plan list are modified, resulting in a functionality Equivalent circuits that improve design states, such as timing, power. These transformations can add or remove components and their interconnections. Transformation examples include performing one of the components to replicate, or splitting an integral RTL component. One of the very simple implementations of a very large class implementation for 1/〇, different sized memory, CPU, and DSP. Different designs may want to use this in different ways. Resources. The abstract transformation of the present invention (ie, operation 7) can depend on timing information, connections, and location of components, utilization of resource types, and routing of arrangements. Transformation (i.e., operation 68). Although operation 68 establishes a plurality of alternative implementations that are maintained and evaluated in future reversals 'but the abstract operation is instead abstracted from the more detailed implementation to the abstract component. Consider the abstract component Various implementations and alternative embodiments are chosen to replace the original implementation. This capability avoids alternatives that enumerate all possible architectural mapping choices and run all of them from top to bottom from mapping, placement, and scheduling paths. An example of the abstract transformation of the twitch m is given in Figure 11, which shows an adder tree decomposition operation. The added eucalyptus decomposition splits the reader adder into a -m input adder tree. No delay is derived from the placement. , this optimization will not be 133330.doc 200915123 has information about where to place such input to the S-Hai adder and can only be based on such input One of the times roughly estimates the formation of the tree. In this example, if all inputs come from the scratchpad, they have roughly the same arrival time. 3 Hai is the solution that will pick up (a, b) for the leaf nodes, (c, d) and (e, f) combinations. However, 'puts b and d, &amp; and c can be placed close together. Use this placement information to pick up (a, c), (b, d), (e, better combination. This will produce better timing at the output. Another abstract example of gate tree decomposition is shown in Figure 12. A key step in a composite stream will have many inputs. One of the large gates (such as a 32-input AND gate) is broken down into a tree representation. This stage is usually implemented early in the stream and the decision on the tree decomposition does not include any of the locations of the drivers for the large gate. News. The present invention includes damper decomposition and re-decomposition as a transformation&apos; with placement and timing awareness. The least critical earliest arrival input is placed at the leaf level of the tree and grouped together with fewer nearby key inputs. When the timing is not a factor, the input signals are grouped by the position of the signal driver. The optimized logic transformation (i.e., operation 67) changes the circuit planning list to be optimal. An example of this optimization transformation

Set goals such as timing or power. The slicing operation as shown in Fig. 13A. If it is far apart, it will be delayed. 133330.doc •32- 200915123 Components. For example, the display-memory of the image shown in Figure 3B has been split into three or one-join based on the position of the fan-out of the U-body. Thus, the original group _ two new components of the horse one morning and one block have been divided and divided according to their corresponding loads. A similarity can be applied based on a set of input signals. This optimization is more general and not limited to memory. Another exemplary operation is a logical copy of Figure 14. These conditions for copying are very similar to segmentation. It is possible to place a key load placement on a component that is both input and output that is separate and has a separate input or output. This optimization can only be carried out based on Anjin Shenshui. The following example is for - component a shows this point - times π, & z, lip condition, the output of the edge component is very far apart. its

It can be divided into two cases a 1 fish a ? M only l, a_2, which can be placed very close to its output. This is very common when the fanout of the drive is high. Save only one copy of the instance within a given entity. Another exemplary operation is shown in Figure 15 for Shannon. For logic at the input (four) of the RTL component with a large delay, such as an adder or a multiplier, the key input network can be &quot;pre-pulled&quot; to improve timing. Copy the logic and use the default inputs 0 and 1 to replace the critical network. Then use the -multiplexer to select the rounds of the two operators. The key network chooses which operator copy is the output. The two logical copies can be further simplified based on the constant inputs. Again, this is an optimization that is best performed at the logical location and by the drivers of the critical networks that drive the logic. ° Another example operation is Mux/PMux (-PMux is defined as having a -one-bit effective code selection - multiplexer) folding (c〇Uapse) and timing drive 133330.doc -33- 200915123 This is shown in Figures 16A and 16B. Large multiplexers are very common in commercial circuits. Decomposing a multiplexer is similar to the adder tree and/or tree decomposition mentioned earlier, but the selection logic makes the Mux decomposition more difficult, because moving in the tree a little later to reach the input will not only affect the tree structure, but also affect the selection. logic. As with other decompositions, the present invention includes timing information based on placement and scheduling paths to determine appropriate decomposition. Operation 69 is updating the path of the arrangement. This incrementally repeating method provides better arrangability for integrated circuits to improve design performance, noise sensitivity, yield, area, and power. The incremental repeating process can gradually improve the wiring congestion on the wafer, that is, the dense wiring required by the wiring resources required per unit area, many of which are very popular, 丄, 丄, k A A .

Connect, you can use accurate delay information.

Or the wafer prototype level item, the length and delay of the network in the road. Or an update placement transformation. The placement change location, such as an RTL object, an unmapped instance, and thus the router's operation, may depend on the circuit planning list and various placement methods.

133330.doc and the maturity of the woman to make the 'placer use ..., input changes to produce -34- 200915123 an algorithm for the change of output. For example, global placement such as force guided placement can be used to place less mature circuit planning lists and placements. The Force Directed Placement (FDP) method is one of the preferred choices for global placement in the present invention because it is a one-step method in which one of the FDPs in turn produces incremental placement changes. In general, FDP uses a quadratic stylization technique to model the networks and determine how overlapping instances should be spread. In a specific embodiment, the first step FDP addresses an unconstrained quadratic stylization problem that only models the networks interconnecting the instances. This initial solution usually has very high congestion. FDp then repeatedly constructs the spread to move the instance from over-congested (higher use) areas to under-congested areas (higher resource availability). The nature of these repetitive steps makes FDp an incremental method. The circuit plan list or other design status data can be changed between these reversals. As these state changes increase, the resulting changes in FDp should also be incremental in the absence of design state changes. There are various FDP algorithms, but all share the basic concept of calculating the direction in which an item should be moved to resolve an over-congested area. In a particular arrangement, it is assumed that the instances connected by a network are proportional to the second-order distance between the instances and impose an attraction on each other. In this previous work, all instances were excluded from each other and attracted to all placements, even if the site was not suitable for the case. The instance is then removed until the system is equalized in a minimum energy state. Thus the 17 £&gt;1&gt; method moves the instances based on the direction of the total force imposed thereon. In one aspect, the present invention provides novel heterogeneous resource placements from many numbers 133330.doc -35- 200915123

The machine can be reprogrammed to reprogram the wafer and some ASIC design streams to solve heterogeneous resources such as βHai. For example, most FPGAs have a variety of predefined wafer resources, such as 10' DSP, RAM, LUT, FF, etc., which are only available in specific locations. These predefined resources are the result of the pre-diffusion properties of the FpGA wafer. Each resource location has a limit on the number of entities that can be placed in the location. For example, for Altera Stratix_chips, 16 or fewer 1^1 can be placed in a LAB location, and there are 3 different ram locations with 5 12 octets, 4K octets, and 64 Κ bits. In an exemplary embodiment, the incremental placement solves the problem of heterogeneous resources. In an FPGA, a structured ASIC and some ASICs and resources may be placed only in a specific place where frequently uneven sentences are distributed over the placement area. Most global placers (including all previous FDp) have adopted homogeneous resources, regardless of their type, any of the items can be placed at any effective area within the wafer boundary. This previous solution simplifies the placement problem due to all The range can be considered as a simple linear object 'and as long as the objects do not overlap and are placed within the wafer boundary' placement will be legal. This simple rectangular model can allow adjacent inappropriate resources to be placed. This assumption is not abbreviated. For these heterogeneous resources, each resource has a group-specific place where the item must be placed. Although this, the combination "placement may not have any overlap but when considering the actual Source Type 0 wins' The placement may not be legal. Some previous work in the simulated annealing placer has taken into account the resource information, but only the placers have been placed to place the static mapping circuit specification sheet, not the rtl object. In addition, using simulated annealing for far smaller designs and It becomes difficult to use for large designs due to time. &lt;133330.doc -36 - 200915123 In one aspect, the present invention separately models different resource locations, and in all placement transformations, the placement device optimizes the resource requirements in an aspect, the present invention Modeling any number of place types into &quot;reed&quot; in these layers is used to determine the gentleman-department body of each instance

In V, the layers are established in the 4 initialization phase. A layer is created for each type of source on the wafer. The resource locations of one level are recorded in the supply distribution recorded in the layer. - Distribution - Matrix 2 data structure, where the value of the position gives the value of the supply at that location. - The dimension items are assigned to the (etc.) layer for which they consume resources. These items of the type of resource are called prototype items, while those that consume multiple are non-prototypes. - Non-prototype - The example will be the state machine, which consumes both the LUT^EF site type. By assigning to a layer, the resources used are recorded as a layer of time (4) = Μ 'which is recorded by all the layers for which it has resources to process the usage contributions, which in turn affects the use of such The force calculation of the layers of the prototype layer. The difference between the two is used for this layer. This congestion distribution is used to be the layer-to-layer, the distribution of congestion in its use and supply distribution. As in the previous FDP method, the various items on the calculation force. The force of the non-original, type j page is based on the weighted average of the resources from the resources of its resource layer or the local congestion based on the material resources: the weight applied to each layer can be - Uniform weighting or - depends on the weighting of the relative dispersion of the source of the source. Resource dispersion can be characterized as how far apart the resources are located, how sparse or distributed the resources are, etc. 133330.doc -37- 200915123 Resources are even or uneven. In a specific embodiment, similar to the case of a non-prototype example, the force is used for a component having one of a plurality of possible implementations. This force is additively weighted by weighting the forces of the layers from the resource layers of its implementation. The weighting of the resources she adds to the various embodiments may be a uniform weighting or a weighting depending on the probability that a given implementation will be selected. The advantage of the present invention is that the power of the example depends only on other instances of the same resource type and the provision of resources for that type. For example, if each of the items A and B has a resource of use. The force of the portion of the item a (or part of the use of the item C of the resource C) depends on the use of the part A of the case B of the resource C and also depends on the resource c available for resettlement. The items on different layers do not affect each other's spread. In the case, when the global placer is terminated, each item will be in or near an effective place of its type = so that the placement can be legalized with little improvement. This scheme compares the previous FDp with a new one, which previously required all models to be modeled as a -single type and combined all resource regions and then spread the instances on the combined region. In an exemplary embodiment, the architectural entity of the present invention can provide a modification to the body utilization problem. It is often the case that the wafer resources are beyond the circuit requirements: if the circuit to be implemented may be internal, or the chip or part has 256 LUTs, 15 LUTs are required. This / is called the source of education. In the case of a resource utilization problem, better results can be obtained by (4) (4) = cloth circuit examples, even if - Putian has different densities in the source of the poverty-stricken source - placement is 133330.doc _38· 200915123 now. The previous placer has ignored this issue or imposed an extra, "filler" exception. The filler case does not add (iv) additional items to the circuit for connectivity. The use of the ''filler'&quot; example is also problematic because the position must be determined for these items. In the exemplary embodiment, the present invention utilizes the _region removal method to solve the resource utilization problem. As with the production of 1, the various resource layers are considered separately. The method towel is removed in this area, and the material is: (4) based on its quality, while removing low quality resources. A quality metric is determined first, and then the lean supply is analyzed to determine one of the resources based on its quality. These low quality parts are then removed from the consideration by the placer as a place of placement. Since the placement changes affect the quality of these resources, the rating and removal can be performed multiple times during the placement process. The program is thus well suited to the repeated and incremental improvements of the present invention in the ten state. In a specific embodiment A, the quality metric used to form the rating is based on the distance between the resource and the usage. A method of calculating the force is a convolution of the density distribution of the byproduct layer with a Green function. The result of this convolution can be viewed as a topological map where a higher point indicates a demand for resources and a lower point indicates a lack of demand. Since the distribution consists of discrete squares, the squares can be selected based on the convolution result. The resources to be removed may then be determined by bypassing the supply and starting the removal of the lean source with the lowest value resource in the convolution selection order until the required requirements are removed. In one aspect, the method may leave sufficient resources to allow sufficient resources to satisfy the physical requirements on the layer and to cause the wafer to be routed. Alternatively, in other exemplary embodiments, the present invention utilizes a range of methods to address this resource utilization problem. In the force range method, the force on each of the 133330.doc -39· 200915123 terms is a weighted average of one of the forces from the plurality of force ranges. In one aspect, the 'short-range weighting factor system is closely related to the example in the short-range region. One of the more localized degrees causes a higher force. This proportionality thus increases the circumstance of the instances to reduce overlap. Using this force range method, the force applied to an item depends on the density of the items in the adjacent item. The general idea is that the spread of the case should depend on the area required to legalize the items in its adjacent area. In the most extreme case of congestion, where all of the instances overlap in a small adjacent area, the forces on each item are calculated based on the location of all instances and all resources. In the case of the most J congestion, where the instance has any other instance in its vicinity* and is directly on a resource, the instance will have no force. For the case between these two extremes, the force depends on the terms and resources within the area required for the legalization case. In one embodiment, the range of forces can be cut to local, medium, and long-range forces. In other embodiments, more or less force ranges may be used. In general, it is a compromise between computational and memory resources to determine the legalized area used for adjacent regions and the forces used for each legalization range. In one aspect, the forces are calculated by varying the magnitude of the Green's function. The long-range Green's function covers the entire placement area, and the smaller Green's function covers - a circular area with a radius of, for example, five times the average case area. The medium-range Green's function has, for example, 10 times the average case area. One of the radii. The force on the - item is the sum of the weights of the local, medium and long range forces of the example. The weight applied is determined by the density within the neighborhood of the example. If the money neighborhood is extremely dense, then the long-range force will have a very high weight of 133330.doc -40- 200915123 and the local weight will be zero. An item in a low density region will have a zero long range weight and a higher local weight. Another aspect of the method is the ability to determine important architectural decisions that determine the resources that should be used in implementing an architectural construct. At the architectural level, there are many decisions, such as whether a small RAM should be mapped to a 512-bit RAM resource or a 4k-bit RAM resource on an FPGA. Other examples include decision making by multiplier implementations and previously stated conditions, such as adder tree decomposition. However, the invention is not limited to these specific examples. Because of the availability of placement information, the present invention refines the important architectural implementation decisions that meet these design goals. An exemplary example is where a lk bit of memory can be assigned to two 512 bits as a source or a single 4k bit resource. This embodiment may be critical to a successful implementation when the logic to which the lk bit memory is connected is located close to a 512-bit or servant location. In the case where the connection logic of the financial memory is very close to the 512-bit resource and the source of the 4k-bit f is farther away, a non-optimal mapping to the 4k resource will result in a substantially lower performance path. It is important to use placement information to make this and other architectural decisions. In an exemplary embodiment, this embodiment refinement is handled by including a portion of the area of the elastic layer instance in use for each layer that the item may map. In the case of the (10) meta-example, the area of the entity will be partially included in both the 512 and 4k layers. The force on the example is determined by taking the potential layer to perform the weighting of the forces and the force with the least amount of values. The reason behind the ability to obtain the least amount of value is that the layer associated with this force should have a lower adjacent region density. In other exemplary embodiments, the resource implementation begins by including no instances of 133330.doc -41 - 200915123 having multiple possible resource implementations within the use of any of the layers. These two-in-one embodiment examples are considered after the region removal operation has been performed for all layers. For the Elastic Implementation example, consider the potential supply of each layer of its possible layers. The potential supply is the area that is removed from the entire supply by the area removal operation. The potential supply on each of the layers of the implementation layer is examined to determine which layer has removed the area that will be minimally fragmented when the instance is placed within this removal area. The instance is then assigned to the least splitting layer. f The assigned resource transform (operation 64) is responsible for deciding to assign an entry to its particular wafer resource. Various placement algorithms can be used for this operation, including force-guided placement of simulated annealing, Mongreh minimum slice placement, numerical optimization placement, evolution-based placement, and other detailed placement algorithms. Although it is intended that most of the specific embodiments of the present invention be applied to the rib [design synthetic software program], the present invention is not limited to such use. Although other languages and computer programs (eg, writable human-computer programs can be used to illustrate the hardware and thus are considered to be in the HDL-and can be compiled or in some embodiments), the present invention can be assigned or re-allocated Allocating a logical representation, an example of a circuit planning list, which is not used by the ancestor, but will be used in a ancestral synthesis system and in particular for such integrated circuits with a specific vendor technology/architecture Specific embodiments of the invention are described in the context of a user. As is well known, the target architecture is generally determined by a programmable deduction-supplier. An example of a target architecture is a programmable look-up table (LUT) and such integrated circuits (which are derived from San Jose, Calif.). The field can be programmed to gate the image of the vehicle. Logic. Target architecture / technology 133330.doc • 42- 200915123 Other examples include from Altera, Lucent Technology,

These well-known architectures in % programmable gate arrays and complex programmable logic devices from suppliers of Advanced Micro Devices and Lattice Semiconductor. For a particular embodiment, the invention may also be utilized with a particular application integrated circuit (ASIC).

One embodiment of the present invention may be a circuit design and a synthetic computer-aided design software implemented as a computer program stored in a machine readable medium such as a CD ROM or a magnetic hard disk. Or on a compact disc or a variety of other alternative storage devices. Moreover, many of the methods of the present invention can be implemented using a digital processing system, such as a conventional general purpose computer system. Special purpose computers can also be used, which are designed or programmed to perform only one function. Figure 17 shows a typical computer system, a model that can be used in conjunction with the present invention. The computer system is used to implement the logical synthesis of the design described in the _HDL code. It should be noted that although FIG. 17 illustrates various components of a computer system, it is not intended to represent any particular architecture or manner of interconnecting such components. Such details are not germane to the present invention. It should be noted that the architecture of Figure 17 is provided for illustrative purposes only and that a computer system or other digital processing system used in connection with the present invention is not limited to this feature architecture. It should also be understood that a network computer and other bedding processing systems having fewer components or components may be used with the present invention. The computer system in Figure i 7 may be, for example, an Apple Macintosh computer. The data processing system is lightly coupled as shown in FIG. 17, as a computer system including a form of one of the bus bars 1 - 2 - a microprocessor 103 and a 133330.doc - 43 · 200915123 ROM 107 and a volatile RAM 1〇5 with a non-volatile memory (10). Microprocessing JJ103 (possibly from (5) or M〇t(10)la, Inc or ugly) is coupled to the cache memory i. The busbars 1 〇2 interconnect the various components together and also interconnect the components 1〇3, 〇7, 1〇5, and (10) to a display (4) device and display device just to peripheral devices such as input/output (I/O) pirate 'may be a mouse, keyboard, modem, network interface, printer, scanner, video camera and other devices well known in the art. In general, the input/wheeling device n is coupled to the system via the input/output controller 109. The non-volatile RAM 1〇5 is generally implemented as a dynamic RAM (DrAM), which continuously requires power to renew or maintain the non-volatile memory in the memory as a magnetic hard disk drive or a magnetic device. Optical drives or optical actuators or a DVD RAM or even other types of memory systems that maintain data after power is removed from the system. In general. The non-volatile 5 memory will also be a random access memory, but this is not required. Although Figure 7 shows that the non-volatile memory system is directly coupled to a native device of the remainder of the components in the lean processing system, it should be understood that the present invention may utilize a non-volatile memory remote from the system. , such as a network storage device, coupled to the data processing system via a network interface, such as a data modem or an Ethernet interface. The busbar 2 can include one or more busbars connected to one another via various bridges, controllers and/or adapters, as is well known in the art. In one embodiment, the I/O controller 1〇9 includes a USB (Universal Serial Bus) adapter for controlling USB peripheral devices and/or an IEEE_1394 bus adapter for controlling IEEE-1394 peripheral devices. . 133330.doc -44- 200915123 It will be understood from this description that the aspects of the invention may be at least partially embodied in a software. That is, the techniques can be implemented in a computer system or other data processing system in response to a processor (such as a microprocessor) executing in a memory (such as ROM 1〇7, non-volatile) A sequence of instructions for RAM 1〇5, non-volatile memory 106, cache memory 4 or a remote storage device. In various embodiments, soft-wired circuitry can be used to implement the invention using hard-wired instructions. Thus, the techniques are not limited to any specific combination of hardware circuitry and software, nor to any source of such instructions for the data processing system (4). In addition, throughout this specification, various functions and operating systems are described as being implemented by software code or caused by a simplified description. However, it will be appreciated by those skilled in the art that such expression means that the operative power 6 is generated by a processor (such as microprocessor 1G3) executing the code. The software and the data can be stored using a machine readable medium that implements the various methods of the present invention in the context of "data processing". The executable software and data can be stored in various locations. And includes, for example, an exemplary ROM 107, a non-volatile Ram 〇 5, a non-volatile memory H) 6 and/or a cache memory 1G 4. The software and/or portions of the data may be stored in the storage devices In any of the '-machine-readable media, including any mechanism, which can be stolen by a computer (for example, a computer, a marriage, an electric chest, a personal digital assistant, a manufacturing Form: access to any form (or any device, etc.) access form = total (ie, store and / or send) information. For example, a machine readable medium including recordable / non-recordable media ", body (for example, read only memory (ROM), random hidden body (RAM), disk storage media, optical storage media, flash 133330.doc '45 200915123, acoustic or other forms of transmission, digital signals )Wait. Memory devices, etc.) and electrical and optical broadcast signals (eg, carrier 'infrared signals in the foregoing specifications, the present invention is described with reference to specific exemplary embodiments thereof. Obviously, it can be straightforward. Various modifications may be made without departing from the broader spirit and scope of the present invention as set forth in the accompanying claims. Accordingly, the specification and drawings are regarded as _ A restrictive meaning. ~ [Simple description of the schema]

The same reference numerals are used in the drawings to refer to the The present invention is illustrated by way of example, in which Figure 1 shows a prior art method for designing an integrated circuit. Figure 2 shows one prior art exemplary method of entity synthesis. Figure 3 is a flow chart showing one of the methods for designing an integrated circuit in accordance with the present invention. 4 is not in accordance with the present invention, and the specific embodiment is used to design an integrated body

One of the other methods of the road. Figures 5A and 5B show details of a method for designing an integrated circuit in accordance with a particular embodiment of the present invention. Figure 6 is a flow chart showing one of the methods for designing an integrated circuit in accordance with an embodiment of the present invention. Figure 7 shows an exemplary estimate of one of the shapes and resources. Figure 8 shows an exemplary mapping for one of the resource types. 9A and 9B are exemplary mappings of a memory resource. Figures 10A and 10B are exemplary resource sharing implementations. 133330.doc -46- 200915123 Figure 11 shows an example of an adder tree decomposition. Figure 12 shows an example of a brake tree decomposition. Figures 13A and 13B show an example of a slice optimization. Figure 14 shows an example of a replication optimization. Figure 15 shows an example of a one-way agricultural expansion. Figures 16A and 16B show examples of mux/pmux folding and timing driven decomposition. Figure 17 shows an example of a block diagram of one of the data processing systems that can be used with the present invention. [Main component symbol description] 101 Computer system 102 Busbar 103 Microprocessor 105 Volatile RAM 106 Non-volatile memory 107 ROM 108 Display device 109 Input/output controller 110 Input/output device 133330.doc

Claims (1)

200915123 X. Patent application scope: l - a kind of design-integrated circuit method, the method includes. In one of the integrated circuits, ^ ^ ^ 〇卩 6 ° and the meter is not in place, repeating and incrementally changing the edge ° What is the state. 2, such as clearing the item 1 eve f, +. Exhibition:, the method, wherein the repeated procedure toward the following at least - into the integrated circuit φ Yikou _ a piece of the table is not the level of abstraction - incremental reduction; _ + Circuit Planning List - incremental maturity; and one of the placement configurations to increase maturity. 3 · For example, the method of claim 1, wherein 哕; t; p is more than χη_ 4 士 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Day has - the implementation chooses for this component. Among them, the 3H repeat procedure is toward a required timing, each area is improved, and the power consumption is improved. 4. As in the method layer of claim 1, the congestion is reduced, and at least one progresses. i. The method of the requester' wherein the state of the integrated circuit design includes a circuit planning list having at least one of timing information, resource information, placement information, arrangement path information, and power data. 6. As in the method of the requester, the change program is at least one of a synthetic transformation and a placement transformation. A machine readable medium comprising a plurality of executable instructions which, when executed on a digital processing system, cause the digital processing system to perform a method of designing an integrated circuit (IC), the method Contains: In the high-order design representation of one of the integrated circuits, it is repeated and incrementally changed 133330.doc 200915123 The state of the design. 8. As requested in the media of the item 7, exhibition: T &quot; repeated spears of the order to at least - into the integrated circuit _ - RT two-level level - incremental reduction; one - one of the circuit planning list incremental maturity; One of the placement configurations is one-way maturity. 9· Hi: 7 media 'where the high-level design representation includes at least a set of component wafer prototypes that have not been available—the implementation option is selected for the 10. The medium of the item 7', wherein the repeated program is directed to a desired timing, each At least one of the layer-congestion reduction, the improvement in area utilization, and the improvement in power consumption. 11. The media of claim 7 wherein the state of the integrated circuit design comprises a circuit, the list comprising at least one of timing information, resource information, placement information, arrangement path information, and power data. 12. The medium of claim 7, wherein the change program is at least one of a composite transform and a placement transform. 13. A method of designing an integrated circuit, the method comprising: repeatedly selecting and performing at least one of a composite transform and a placement transform X incrementally changing a state of the design at a higher order representation of the integrated circuit. 14. The method of claim 13, wherein the high-order design representation comprises at least one set of components that have not been selected for use in the component in a wafer prototype. 133330.doc 200915123 wherein the repetitive procedure proceeds to at least one of the following: 15. The method of claim 13: The abstraction level of each of the || pieces in the unit circuit of the unit is incrementally reduced by the RTL circuit specification. Incremental maturity; and one of the placement configurations to increase maturity. One of the circuit planning lists is in the presence of the following 16. The method of claim 15, at least one of which is more mature, consisting of fewer high-order RTL instances and more gates; and it has fewer levels of abstraction . 17. The method of claim 15, wherein the placement configuration is more mature as it satisfies more rules governing the use of resources of the integrated circuit. 18. The method of claim 13, wherein the repetitive process progresses toward at least one of a desired timing, a per-layer-congestion reduction, an area utilization improvement, and a power consumption improvement. 19. The method of claim 13, wherein the state of the integrated circuit design comprises a circuit planning list having at least one of timing information, resource information, placement information, routing information of the arrangement, and power data. 20. A machine readable medium comprising a plurality of executable instructions which, when executed on a digital processing system, cause the digital processing system to perform a method of designing an integrated circuit (1C), the method comprising: At least one of a composite transform and a placement transform is repeatedly selected and implemented to incrementally change a state of the design at a higher order representation of the integrated circuit. 21. The medium of claim 20, wherein the high order design representation comprises at least one set of 133330.doc 200915123 for the item 'there is no in the on-wafer prototype' implementation option component. 22. The media exhibit of claim 20: wherein the repeating program is incrementally decreasing toward one of the following abstraction levels of each of the device representations in the integrated circuit; one of the RTL circuit planning lists is incremented in maturity; and a placement One of the configurations increments the maturity. 23. The medium of claim 22, wherein the __circuit planning list is more mature when at least one of the following is present: it consists of fewer "RTL instances and more gates; and it has fewer Abstraction level 24. In the medium of claim 22, one of the placement configurations is more mature as it satisfies more rules governing the use of resources of the integrated circuit. 25. The medium of claim 20, wherein the repetitive procedure - at least one of the required timing, per-layer-congestion reduction, - area utilization improvement, and - power consumption improvement. 26_ The medium of claim 20, wherein the state of the integrated circuit design includes a circuit planning list, It has at least one of timing information 'resource information, placement information, arrangement path information, and power data. 27. A method of designing an integrated circuit, the method comprising: generating an initial state of the design of the integrated circuit And repeatedly evaluating a cost function of the plurality of potential transformations; and performing a transformation of the optimal cost function; wherein each of the high-order design representations of the integrated circuit is repeated Handling tampering with 133330.doc 200915123 changes the state of one of the designs. 28. As requested in item 27, this is the item, which is in 丄, where the design of the order includes at least one and the prototype of the day. There is no -, component. 29_ as in the method of claim 27, 1 in . /, A-Tong 夂 私 私 朝 至少 至少 至少 至少 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 她 One of the abstract levels of the device representation in the integrated circuit represents one of the RTL circuit planning lists with increasing maturity; one of the placement configurations increments the maturity. The method of claim 29, wherein the at least one of the reduction of the abstraction level and the maturity of the circuit is early comprises a composite transformation. 31. The method of claim 29, wherein the maturity of the placement configuration comprises a second transformation of a placement transformation and a synthesis optimization. 32. The method of claim 29, wherein the circuit planning list is more mature in the presence of at least one of: consisting of fewer higher order RTL instances and more gate quasi-case items; and having less abstraction level. 33. As in the method of claim 29, one of the placement configurations is more mature as it meets more rules governing the use of resources of the integrated circuit. 34. The method of claim 29, wherein the global placement is for placing a less mature circuit planning list and a placement configuration. 35. The method of claim 34, wherein the global placement is directed to the placement method 0. 36. The method of claim 27, wherein the repetitive procedure is toward a desired timing, each 133330.doc 200915123 area utilization improvement and a power consumption One of the improved layers has less congestion and at least one progresses. 37. The method of claim 27, wherein the cost function comprises timing, at least one layer of congestion, area utilization, and power. 38. The method of claim 27, wherein the cost function is based on a state of the integrated circuit design. 39. The method of claim 27, wherein the cost function is based on a sensitivity criterion. 40. The method of claim 27, wherein the state of the integrated circuit design comprises a circuit planning list having at least one of timing information, resource information, placement information, routing information of the arrangement, and power data. • The method of claim 4, wherein the circuit planning list is optimized by a plurality of neutral optimizations based on a sequence. 42. The method of claim 41, wherein the neutral optimization comprises - a reversible area back! , - Adder tree decomposition, an obvious resource assignment, one of the circuit planning lists, and an electronic multiplexer decomposition. 4 The method of claim 4, wherein the step further comprises estimating the shape and resources for each 7° piece of the circuit planning list to obtain a substantially global placement. 44. The method of claim 27, wherein the potential transformation comprises at least one of: an undo/restore resource sharing, an additive tree decomposition, a and/or gate decomposition, a logical replication, a one-way agricultural deployment, a bit stack Connection, a m/x/pmu read stack and timing driven decomposition, a relocation removal, one assignment to each discrete source, factorization, and a placement. 45. As in the case of claim 27, the potential transformation includes at least one of the following: 133330.doc 200915123: “placement, an update placement, a 诂fanxian 1 placement optimization, a resource assignment, a resource utilization, a logic Preparation, class 'A, take advantage, a logical decomposition, a logical mapping and a logical synthesis. 46. The method of claim 45, wherein the 源 、, 盾 丨丨 和, and the ten a y y y y y y y y y y y y y y y y 47. The method of claim 45, wherein the mouth of the mouth is 曰 曰 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 罝 罝 罝. 48. The method of claim 45, wherein the resource utilization program includes a force calculated on each of the circuit instances, the force being weighted according to one of the equalities calculated by the plurality of ranges. 49. The method of claim 48, wherein the weight for a short-range force is proportional to the density of the item, and the weight for a long-range force is inversely proportional to the density of the item. 50. The method of claim 45, wherein the resource assignment comprises a heterogeneous resource assignment. 51. The method of claim 45, wherein the heterogeneous resource assignment comprises assigning a non-prototype item having a heterogeneous resource to all of the layers having the resource of the item, and the force on the item is from all layers One of these forces is weighted and summed. 52. The method of claim 45, wherein the heterogeneous resource assignment comprises assigning a non-prototype item having a heterogeneous resource to all of the layers having the resource, and the force on the instance is from all layers The force of the least amount of these forces. 53. The method of claim 45, wherein the heterogeneous resource assignment comprises: ~ ny 133330.doc 200915123 test (4) placement of the item resource - position calculation to place the item on the layer providing the least divergence, Then assign resources with non-prototype items of heterogeneous resources to this layer. 54. The method of claim 27, wherein the potential transformation comprises at least one of: - a composite map, a synthesis optimization, an abstraction level for each device representation in the integrated circuit design - a reduced one One of the maturity levels of synthesis and an RTL circuit planning list has increased. 55. The method of claim 27, wherein the potential transformation further comprises a second repetitive procedure. % - a machine readable medium comprising a plurality of executable instructions which, when executed on a digital processing system, cause the digital processing system to implement a design-integrated circuit (1C) method, the method comprising: generating the An initial state of the design of the integrated circuit; and a cost function that repeatedly evaluates a plurality of potential transformations; and performs a transformation that provides the optimal cost function; - each of which is incrementally changed at the high-order design representation of the integrated circuit One state of the design. 57. The medium of claim 56, wherein the high-order design representation comprises at least one set of components that have not had an embodiment selected for use in the on-wafer prototype. 58. The medium of claim 56, wherein the repetitive procedure is at least shown as follows: one of the abstraction levels of the representations of the devices in the system of intensive circuits is incrementally reduced; an RTL circuit planning list - incremental maturity; and 133330.doc 200915123 One of the reset configuration increases the maturity. 59. The medium of claim 58, wherein the at least one of the abstraction level reduction and the maturity of the circuit plan list comprises a composite transformation. 60. The medium of claim 58, wherein the maturity of the placement configuration comprises a second transformation of a placement transformation and a synthesis optimization. 61. As in the medium of claim 58, one of the circuit planning lists is more mature in the presence of at least one of: it consists of fewer higher order RTL instances and more gates; and 'its have more Less abstraction. 62. As in the medium of claim 58, one of the placement configurations is more mature as it meets more rules governing the use of resources of the integrated circuit. 63. As in the medium of claim 58, one of the global placements is used to place a less mature circuit planning list and placement configuration. 64. The media of claim 63, wherein the global placement is directed to the placement method. The media of claim 56, wherein the repetitive process progresses toward at least one of a desired timing, one of each layer of congestion reduction, an area utilization improvement, and a power consumption improvement. 66. The medium of claim 56, wherein the cost function comprises at least one of timing, congestion per layer, area utilization, and power. 67. The medium of claim 56, wherein the cost function is based on a state of the integrated circuit design. 68. The medium of claim 56, wherein the cost function is based on a convergence criterion 133330.doc 200915123 69. The medium of claim 56, wherein the state of the integrated circuit design includes a circuit planning list having timing information, At least one of resource information, resettlement information, route information of arrangements, and power information. 70. The medium of claim 69, wherein the circuit plan list is optimized by a plurality of neutral optimizations based on a sequence. 71. The medium of claim 70, wherein the neutral optimization comprises a reversible area response, an adder tree decomposition, an explicit resource assignment, a flattening of the circuit planning list, and an electronic multiplexer decomposition. At least one. 72. The medium of claim 69, further comprising estimating a shape and a resource for each component of the circuit planning list to obtain a substantially global placement. 73. The medium of claim 56, wherein the potential transformation comprises at least one of: undo/restore resource sharing, one addition tree decomposition, one and/or problem decomposition, one logical copy, one-way agricultural expansion, one-dimensional stack Connection, a mux/pmux folding and timing-driven decomposition, a round-trip removal, one assignment to each discrete resource, a factorization, and a placement. 74. The medium of claim 56, wherein the potential transformation comprises at least one of: a placement, an update placement, a placement optimization, a resource assignment, a resource utilization, a logic optimization, a logical decomposition, A logical mapping and a logical synthesis. 75. The medium of claim 74, wherein the resource utilization program includes rating and removing each low level resource based on a quality metric. 76. The medium of claim 74, wherein the quality metric comprises a distance from a resource. 77. The medium of claim 74, wherein the resource utilization program includes a force calculated on the 'J terms of each of the electrical powers 133330.doc -10- 200915123. The force is weighted according to one of the calculated forces of the plurality of ranges. 78. As in the media of request 77, ^ ^ ^ is used in the proportion of the short-private force to be proportional to the degree of the case, and is used for county-to-county comparison. The weight of the long-term private power is equal to the density of the item. The resource assignment includes a heterogeneous resource. 79. If the media item of claim 74 is 0, the T琢 Wu buy resource refers to 80. The media of claim 74 is followed by Danbai-heterogeneous resources—the non-prototype item to the item has all the sounds of the resource and the force on the item is from the force of all the layers—weighted and ° 丨. The media 'where the heterogeneous resource assignment includes assigning a non-prototype item having a heterogeneous resource to all of the layers having the resource of the item and the force on the item has the least of the forces from all layers The power of quantity. 82. The medium of claim 74, wherein the heterogeneous resource assignment comprises assigning a resource having a non-prototype item of a heterogeneous resource to a layer providing a minimum divisibility, if a position of the placement of the item resource is never considered Calculate to place the item in this layer. 83. The medium of claim 56, wherein the potential transform comprises at least one of: a composite map, a synthesis optimization, a synthesis for reducing one of an abstraction level of each device representation in the integrated circuit design And one of the maturity levels of an RTL circuit planning list has increased. 84. The medium of claim 56, wherein the potential transformation further comprises a second 133330.doc -11 - 200915123 repeated procedure. 85. A method of designing an integrated circuit, the method comprising: determining a sigma transformation of a design at a high-order circuit description; and determining that the synthesis from the high-order circuit description has not yet been completed. Determining each placement 86. The method of claim 85, wherein the high-order circuit description system, Table 1, includes at least one component that is not selected for use in a wafer prototype. The method of claim 85, further comprising: constituting a portion of the south-order circuit representation for the first-order synthesis.吸—5成变8 8. The method of claim 85, wherein the synthetic transformation is as follows: one adder tree decomposition; one and/or gate decomposition; one of the circuit planning lists is flattened and merged; Decomposition of a tool; a logical optimization; a logical decomposition; an undo/restore resource sharing; - logical replication; a logic factorization; a directional agricultural extension; a bit splicing; a mux/pmux folding and timing-driven decomposition; Remove it one time. The method of claim 85, wherein the composite transform combination is recorded by the high-order circuit for each rTL component compiled. For example, the method of claim 85, wherein the placement decisions are incremental. The method, wherein the placement decisions are placed for portions of several objects of the circuit designation. A method of designing an integrated circuit (1C), the method comprising: determining an incomplete placement information; and determining a composite portion of each of the synthetic transformations using the incomplete placement information at a higher order circuit representation, wherein Incomplete placement information includes decisions relative to the deduction. The method of month length item 92, wherein the high order circuit description system - representing at least - the component, has not been selected for use in the component in the wafer prototype. The method of claim 92, wherein the method further comprises: representing the portion I of the previously synthesized higher order circuit. The knives S complex-synthesis method of claim 92, further comprising: f determining, by the method of claim 92, the synthesis from the higher-order circuit description is still not completed, wherein the synthesis transformation is as follows - one adder Tree decomposition; one and/or gate decomposition; one of the circuit planning lists is flattened and merged; 133330.doc -13- 200915123 one electronic multiplexer decomposition; one logic optimization; one logic decomposition; one undo/restore resource sharing A logical copy; a logical factorization; a directional agricultural expansion; a one-dimensional splicing; a mux/pmux folding and timing-driven decomposition; and a round-trip removal. 97. The method of claim 92, wherein the composite transform combination is represented by the higher order circuit for each of the compiled RTL components. 98. The method of claim 92, wherein the synthetic transformation is incremental. 99. The method of claim 92, wherein the synthetic transformation is a composite of a plurality of objects for a portion of the circuit design. 133330.doc -14-