TW200913492A - Full digital soft-start circuit and power supply system applying the same - Google Patents

Abstract

A full-digital soft-start circuit, applied in a power supply system, includes a ring oscillator, a pulse generator, a counter and multiplexer. The ring oscillator generates a plurality of clock signals which have different phases but same duty cycle and the same frequency. The pulse generator generates pulse signals which have different duty cycles. The counter produces a multi-bit counting signal. The multiplexer decides whether to transfer the pulse signal generated from the pulse generator in order to produce the output pulse signal which is stable with time elapse.

Description

200913492 F2007-006-1W 23955twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a soft start circuit, and more particularly to a full digital position capable of operating at a low voltage source Soft start circuit. [Prior Art] In a power supply system that requires a pulse width modulation (pWM) signal, the 'receiving pressure' is required to utilize the large inductance "large capacitance" for energy storage and conversion. In order to prevent the power supply system from damaging components and internal circuits due to transient high current during the startup process, a soft-start circuit is currently added to the power supply system. In the soft-start circuit of a conventional power supply system, a resistor is added to the desired output surface (8) as a schematic diagram of a soft-start circuit of the prior art. As shown in Fig. 8 (8), the conventional soft start circuit includes: transistors 101 and 103, a resistor 1 〇 2, a capacitor 1 〇 4, and a comparator 105. The gate of the transistor 101 is connected to the enable signal ENB, the source terminal is connected to the voltage source, and the terminal is connected to the first end of the button 102. The gate terminal of the transistor 103 is connected to enable ENB, the source terminal is connected to the ground terminal, and is not connected to the second terminal of the resistor 102, the positive input terminal of the comparator 1〇5 and the first terminal of the capacitor 104. The first end of a resistor 102 is connected to the 汲 terminal of the transistor 101, and the first end is connected to the positive input terminal of the thief 1 〇 5, the non-extreme terminal of the transistor 1 〇 3, and the first end of the electrical connection 104. The positive input terminal of the comparator 1〇5 is connected to the first end of the capacitor 200913492 P2007-006-TW 23955^^^0/1, the first end of the resistor 102 and the end of the transistor 1〇3, which is also Node voltage VST. The negative input of comparator 105 receives the triangle k TRI. The first end of the capacitor 104 is connected to the positive terminal of the comparator 〇5, the second end of the resistor 102 and the 汲 terminal of the transistor 〇3, and the second terminal is connected to the ground. The comparison state 105 compares the triangular signal wave TRI with the node voltage VSt (a Γ ^ resistor 102 and capacitor 104 are charged). As shown in Fig. 1(b), when the three-corner signal waveform TRI is smaller than the node voltage VST, the comparator, (the wheel number EXJ of 〇5 will be the local potential; when the triangular signal waveform tri is greater than the node voltage VST, the comparison| | 1G5's output signal will be low

The time passes through the node and the VST will slowly (four), and the duty cycle of the output signal will be larger. W

In order to avoid the 'high current damage component circuit during the startup process, the voltage VST ί must be relatively slow, and the capacitance of the capacitor 104 must be good two: Second, the signal waveform generator and the comparator (10) are biased, which leads to The operating voltage of the soft-start circuit must be above lv to ensure that the circuit can work normally. A kind of soft start circuit is used, which can improve the conventional technology: this can be t:: work and does not need to use external electricity Metal Oxide Se * eight available CMos (Complementary -e'S__u* 'complementary The MOS process is implemented. [Summary of the Invention] 200913492 ^2υυ/-υυ〇-ι w 23955twf.doc/n This lx month is quite a kind of king-type digital soft start circuit, which can be applied to the supply system. This soft-start circuit does not need to use the external two; electric / ', process to achieve. The target example of the present invention is to provide a ring oscillator, a pulse generator, a counter and a multiplex; the generator generates a duty cycle with different duty cycles: the multiplexer determines whether or not the pulse is generated. The generated pulse age #b is generated to generate a power supply pulse for another example of the present invention. The digital soft start circuit operates on the reference power supply, and includes: a full start circuit for generating a responsibility for changing with time, the full digital soft circuit, the full digital soft start circuit is more responsive to the second enable pulse balance The generator is used to generate the pulse-balance width modulation pulse generating circuit to generate the round-off pulse balance transmission king digital soft start voltage conversion module according to the original 3 voltage conversion module 'the electric student's round out The voltage source is Leopard II'. * The voltage conversion module produces a 兮rr command from the above-mentioned "selection of the pulse" to generate the pulse, the financial t-modulation modulation signal is transmitted to the voltage conversion mode. A digital control type power conversion circuit is provided for operating in a system, comprising: a control type power conversion circuit for generating at any time;

L 200913492 ^υυ/-υυο-ι w 23955twf.doc/n output pulse; electric (four) change module, according to the output pulse generated by the circuit to generate output power supply power conversion, to select The digital control type electric power, the selected mode signal type; and the buffer are coupled between the digital control 1 +; the operating mode voltage conversion module of the circuit. The % source conversion circuit and the further example of the present invention propose a full-digital soft-start circuit that operates on a reference-regulated, %, 糸 system, including a soft-start circuit for generating changes over time, Digital rush; voltage conversion module; voltage regulation boundary, output pulse of /bee period produces offset modulating signal; and enable _:, power generation source, the full digital soft start circuit enable signal = . The a-state is used to generate the control when the stability is stabilized by the full-green type "such as the surface source has not been rushed, the electric_changing mode" circuit generates the pulse source. When the power is turned on, the voltage conversion module will be fully opened, and the green package [Tune (4) produces the bias voltage of the group, the electric conversion mode% will acupuncture to the card, (4) the electric waste Converting the modulo, 'converting the reference voltage source into the external 彳: Γ using the above-mentioned full-scale structure, so it can be improved by adding external capacitance and analogy = under the CMOS process. ^ The shortcomings of the source can make the above-mentioned features and advantages of the circuit in Xing Xing Li = this ^ month more obvious and easy to understand 'The following special cattle & ', with the accompanying drawings' are described in detail below.

[Embodiment] I In order to clarify the content of the present invention, the following specific example is taken as an example of the invention that can be implemented by the present invention as 200913492 rzuu/-uuo-i w 23955 twf.doc/n. In the embodiment of the present invention, in order to improve the conventional power supply co-generation system, the external capacitor and the operating voltage must be increased in excess of lv, so that the full digital module is used to achieve the soft start circuit.

Referring to Figure 2', there is shown a power supply system in accordance with a preferred embodiment of the present invention. The electrical system includes: a motor module 2), a selector 220, a soft start circuit 23A, a circuit, and an enable signal generator 242. When the power supply system is started, the output pulse generated by the selector 22 is transmitted to the voltage conversion module ^, and the conversion module 210 generates the output voltage source 2 (however, when the voltage conversion mode is used) , trending to the 'timer' selector 22. The pulse width modulation signal generated by _; Τέ ^ 241 is selected to be transmitted to the voltage conversion pull group 21 〇, with the # 厌 从 从 & & & & & 。 。 VDD. $Series change board, group 210 provides stable output electrode body LFig. 2 Electricity station is not in the body'2=Change module 210 includes: inductor 2n, two% solar body 213, capacitor 214 and anodes of resistors 215 and 216 VDD1, the second end of which is connected to one of the diode and the inductor to the output voltage source_2, the electric terminal, and the cathode of the cathode. The transistor; the 213, the brother h and the resistor 215 are connected to the inductor ^ ^, the output of the selector 22G, the end of the " brother and the anode end of the diode 212, 200913492 rzuu /.uuo-i w 23955twf.doc / n source terminal is coupled to the ground. Capacitor 214 One end is connected to the cathode end of the diode, the first end of the resistor 215 and the output voltage source VDr) 2, and the second is To the ground terminal. The first end of the resistor 215 is connected to the first end of the capacitor 214, the cathode of the diode 212 and the output voltage source VDD2, and the second end is connected to the first end of the resistor 216. The resistor is connected to the second end of the resistor 215 and the second end is connected to the ground. In the voltage conversion module training, the resistance of the resistor and the 216 can be used as the component pressure. The node voltage m after the voltage division is coupled to the negative input terminal of the enable signal and the PWM generates a cry 241 in the U mountain ^ seat The input terminal of the enable signal is input with a reference voltage VREF, and the output terminal generates an enable signal EN. The enable signal EN is transmitted to the soft start circuit 23, and the enable signal EN is available. The control soft-start circuit 230 is in a normal operation state or a shutdown state. The voltage conversion pole, the output voltage source VDD2 generated by the group 210 will be regarded as 1> the operating voltage source of the second and second generation generators 242 The pulse width modulation signal generated by the 241 is transmitted to the selected state 220. The 产生 σ φ At .. of the PWM generator 241 can be configured to be capable of generating a soft start circuit 230 operating at a voltage Under the source VDm, it is used to generate the pulse _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 232, counter 233 and multiplexer 234. 漱 ring oscillator 231 according to The signal is just the same, but the complex clock with the same phase but the same duty cycle is CK, cK丨,·.., CK2n+1 〇200913492 P2007-006-1W 23955twf.doc/n clock signal CK, CK1... .. CK2N+1 all have the same frequency. The pulse generator 232 is connected to the ring-shaped vibrator 231' and performs a digital logic operation according to the clock signal generated by the ring oscillator 231 with phase misalignment but the same duty cycle. The pulse signals PW1, PW2.....PW2n+1 having different duty cycles are generated. ο Counting 233 is lightly connected to the ring oscillator 231', which is counted according to the clock signal CK generated by the ring oscillator 231, to The N+1 bit signals S0~SN are generated. The counter 233 will affect the soft start of the soft start circuit 23A. The multiplexer 234 is coupled between the pulse generator 232 and the counter 233. The multiplexer 234 is based on the counter 233. The generated N+1 bit signal S0~SN 'the mosquito is a pulse signal with a different duty cycle generated by the feed pulse enchantment. Thus, an output pulse signal JPWJXJT which increases the duty cycle with time can be generated. Referring to FIG. 3A, the ring resonator 231 includes: a transistor victory, a eve Transmitter 3G5 'multiple delay unit 306, and delay unit 3〇7. Connected to ί: the second Z terminal is connected to the voltage source VDD1, and the idle terminal is connected to the No. 4 ENB (which is the opposite end of the enable signal EN) It is connected to the source terminal of the transistor 302. ^ The delay is connected to the idle terminal of the electric (4) and the extreme of the delay, and the terminal of the connection is connected to the source terminal of the bodies 303 and 304 of the reverse polarity. The wheel terminal of the 〇5" and the source terminal of the transistors 303 and 304 are connected to the enable signal. The transistors 303 and 304 are connected in parallel to the ground. Transistor 3〇4 200913492 P2UU/-UUb-iw 23955twf.doc/n ENB. The gate terminal of the transistor 303 is connected to the gate terminal of the transistor 3〇2 and the output signal terminal of the delay unit 307. The extremes of the transistors 3〇3 and 3〇4 are connected to the input of the reverse 305-1 and the transistor 302 is not extreme. The input of the inverter 305-1 is connected to the 汲 terminal of the transistors 3〇2, 3〇3 and 3〇4, and the output terminal is coupled to the wheel terminal of the delay unit 3〇6J. The output of the delay unit 306-1 outputs a clock signal CK1. The clock signal CK1 is out of phase with the clock signal CK. The waveforms of CK and CK1 are shown in Figure 5. And so on, the clock signals CK2.....CK2N+1 are outputted by the output terminals of the delay units 306 2 ..., 306 2n+1. At these times, the pulse signals are different from each other by one phase and have the same frequency. The inverter 2n+1 is connected to the delay unit 307 and the gate terminals of the transistors 3〇2, 3〇3, which output the clock L唬CK. The clock signals ck, CK1 ... CK2N+1 outputted by the ring oscillator 231 are as shown in FIG. In addition, transistors 301 through 304 describe how to perform the enabling action while also providing an inverted chirp. These series can be composed of inverters that reduce the delay effect. FIG. 3A shows another architectural diagram of the ring oscillator 231. In Fig. 3A, the sigma oscillator 231 includes a single-ended output inverter. However, in Fig. 3, the J J garment shape 231 includes a differential signal output inverter. The frequency of the ring oscillator 231 is controlled by the voltage VB. As shown in Fig. 3B, the ring oscillator 231 includes a plurality of differential signal turns, and the benefits 311-1 to 311-2n. The positive input terminal and the negative input terminal of the inverter 311" receive the clock signal CK and the clock signal ck2n. The positive output terminal and the negative output terminal of the inverter 311-1 respectively output clock signal cK1 and time 12 200913492 rzuu/-uuo-i w 23955twf.doc/n pulse signal CK2N+1. The internal architecture of the pulse generator 232 is shown in FIG. The clock signals CK and cki are mutually exclusive or logically operated (x〇R gateau to generate a pulse signal PW1. The clock signals CK and CK2 are mutually exclusive or logically operated via mutual exclusion or logic gates 401-2. The pulse signal pw2 is generated later, and the pulse signals pwi, PW2, . . . PW2N+1 as shown in FIG. 5 are generated. The 〇 counter 233 counts the clock signal CK generated by the ring oscillator 231, thereby The N+1 bit signal so~SN is generated. As shown in FIG. 计数器, the counter 233 includes a plurality of flip-flops 601, a plurality of flip-flops 6〇3, and an AND GATE 602. The counting period of the counter 233 will be affected, that is, the period width of the signals S0 SN SN will be affected. The flip flop 6 〇 3 is used to generate the N+1 bit signals S0 SN SN. The waveforms of the signals S0 SN SN are as shown in FIG. 7 . The input terminal of the gate 602 receives the N+丨 bit signal s〇~SN, and its output terminal is connected to the set terminal (SEL) of all the flip-flops 603. When all signals SO ' S1 ... SN are When it is logic high (L〇gic HIGH), the AND gate 602 maintains the signals S0, S1 ... SN in a logic high state, as shown in Fig. 7, the counter 233 stops the wave. The multiplexer 234 is composed of 2N+1 switches ^+丨 and Ν+ι inverters 801~0~801-N, as shown in Fig. 8. Each switch is composed of a plurality of transmission gates 803, for example. Of course, the embodiment is not limited thereto. The input terminals of the inverters 801 are connected to the signals s 〇 SN SN and then output s 〇 By S1B ... SNB. 13 200913492 rzuu/-uwo-i w 23955twf.doc/n The input end of the switch 802_1 receives the pulse signal PWl, and the signal S0~SN determines whether the pulse signal PW1 is output as pw_OUT. The input end of the switch 802_2 receives the pulse signal PW2, and the signal S0~SN determines whether to let The output of the pulse signal PW1 is PW_OUT, and so on, the output pulse signal PW__OUT is selected as the pulse signal PW1 or PW2 or ... PW2N+I as shown in the timing diagram of Fig. 9. For example, when SO, S1...SN are both logic low, The pulse signal PWJDUT is the pulse signal PW, and the last stable output pulse signal is PW2N+1. The duty cycle of the pulse signal needs to be between the upper limit DMAX < 100% and the lower limit DMIN = 〇〇 Figure 10 ~ Figure 12 shows the other of the present invention For example, those skilled in the art will recognize that the invention is not limited thereto. The power supply system 1000 includes: a voltage conversion module 1010, a selector 1020, a soft start circuit 1〇3〇, enable signal generator 1040, PWM generator and the enable signal generating 1〇41 1042 fast. The soft start circuit 1〇30 includes a counter 1〇31, a multiplexer 1032, a pulse generator 1〇33, and a ring oscillator 1〇34. An input of the voltage conversion module 1010 is coupled to an output of the selector 1020. Its voltage dividing point N1 is connected to the negative input of the enable signal generator 1〇4〇 and one of the inputs of the PWM generator. The selector 1〇2〇 selects the pulse signal output from the soft start circuit 1030 or the pulse width modulation signal generated by the pwM generator ι〇4ΐ. The signal selected by the selector 1 〇 2 ’ 'voltage conversion module 1010 converts the voltage source VDD1 to the output voltage source VDD2. The positive input terminal of the enable signal generator 1〇42 is connected to the reference voltage VREF, and the negative input terminal thereof is connected to the voltage dividing point of the voltage conversion module 1〇1〇 200913492 P2007-006-TW 23955twf.doc/n enable signal The output of the generator 1042 generates an enable signal EN and is transmitted to the input of one of the loop-opening & The input end of the pwM generating benefit 1041 is connected to the output % of the enable signal generator, and the other input is connected to the voltage dividing point N1 of the power conversion module, and the output end thereof is connected to the input end of the selector 1〇20. The voltage conversion module 1〇1〇 includes: a transistor 1011, an inductor 1〇12, a diode 1013, a capacitor 1014, and two resistors 〇15 and 1〇16. The source of the transistor 1011 is connected to the voltage source VDD1, the gate of the transistor ion is connected to the selector 1020, and the drain of the transistor ΐ〇π is connected to one end of the inductor 1〇12 and the cathode of the diode 1013. The anode of the diode 1013 is connected to the ground terminal, and the cathode is connected to the first end of the inductor 1012 and the anode terminal of the transistor 1〇11. The first end of the inductor 1〇12 is connected to the drain terminal of the transistor 1011 and the cathode of the diode 1〇13, and the first end is connected to the first end of the capacitor and the first end of the resistor 丨〇15. A first end of the capacitor 1014 is coupled to the first end of the resistor 1015 and the second end of the inductor 1012 and provides the output voltage source V]) D2. The second end of capacitor 1〇14 is connected to ground. The first end of the resistor 1015 is connected to the output voltage source VDD2, and the second end thereof is connected to the voltage dividing point N1. The first end of the resistor 1〇16 is connected to the voltage dividing point N1' and the second end is connected to the ground terminal. The soft start circuit 1030 receives the enable signal EN. The ring oscillator 1034 generates clock signals CK, CK1 ... CK2N+1. The clock signal CK is input to the counter 1031. The clock signals ck, CK1 ... CK2N+1 are input to the pulse generator 1033. The counter 1〇31 generates the signal s〇~SN, and the pulse product 15 200913492 23955twf.doc/nw takes the generator 1033 to generate the pulse signals PWl, PW2........PW2n+i and is selected by the multiplexer 1032. Let the pulse signal PW1 or PW2 or ... PW2N+1 be output to PW_OUT. Figure 11 is a circuit block diagram of a power supply system of another embodiment. The % source supply system 11 in this embodiment includes: a voltage conversion mode, a group mo, a soft start circuit 1120, an enable generator 1140, and a voltage regulation cry 1130. According to the pulse signal generated by the soft start circuit 1120 or the bias modulation signal generated by the voltage regulator 1130, the voltage conversion module m〇 converts the power source VDD1 into the required wheel voltage source VDD2. After the output power source VDD2 is stabilized, the voltage conversion module lu〇 internal ^ crystal = 1111 will be fully open. At this time, the voltage adjustment H 113G will adjust the closed circuit of the transistor (1) ^ to convert the source VDD1 into an output. Voltage source VDD2. The enable generator 1140 compares the reference voltage VREF2 = and compares the result as the enable signal EN to input to the soft node „30. Compare the reference power EF1 and the node voltage sub-comparison result as a bias modulation signal to input the internal 1110 The gate of the transistor 1112. The voltage conversion module U1G includes: the transistors 1111 and 1112, the resistors 1113 and 1114 and the Raymond 曰μ pressure 湄VDrn, pg package day 1111 source is connected to the electric =, force The extreme receiving soft-start circuit 1120 generates == the extreme is connected to the transistor output 2 = „, the day-to-day source is connected to the drain of the transistor 1111, and the open-end receiving regulator 113 is connected. To the tempo of the resistor 1113, _, the brother of the 汲 3, the voltage source VDD2 and the power 16 200913492 ^wv-υυο-ι w 23955twf.doc/n the first end of the capacity 1115. The first end of the resistor 1113 is connected to the 汲 terminal of the input 1112, and the second end is connected to the positive input terminal of the resistor (1) diode 2 = the second power 130 and the enabling terminal. The first end of the capacitor 1115 is smashed to the second side of the ground--the * 鸲 连接 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电* r The second end of the resistor 1114 (ie, the ground terminal). The brother-train is connected to the electrical soft start circuit 1120 including: a counter U2l, a multiplex pulse generator 1123 and a ring oscillator B 1124. 〇〇2, a replacement module Coffee, _ turn ^ double card system power conversion circuit 1230 = package i, ^ i24G ° digital control type power conversion circuit (four) and count ^; = 1231, pulse generation please 2, multiplexer (four) circuit 123G generated The pulse signal is pressed by the ratchet/buffer state 1220, and then transmitted to the electric module mo by the buffer 1220. The party controls the pulse signal #bPW-ουτ' voltage conversion VDD2. The electric dust source VDD1 is converted into the required The output voltage source includes a conversion mode! and the voltage dividing point N1 of 121〇 is connected to the selection mode 17 200913492 A ... 4 ” 23955 twf.d〇c/n signal generator 1240. Choose 掇 十产味女 "式(四)船μ式面生11 124Q controllable digits k-type power conversion circuit 123〇################ For example, select mode signal-and hold signal to control digital-controlled power conversion circuit贱

+曰=Conversion module coffee includes: inductor i2u, diode (10), coffee first-媸, = two resistors 1215 and 1216. Inductance == electric house source VDm, the second end of which connects the dangerous pole of the diode 1212 and the pole end of the transistor 1213. The anode of the Thunderbolt is connected to the terminal of the transistor 1213 and the I. terminal, and the cathode is connected to the first winding of the capacitor 1214 and the resistor 1215 and the output voltage source VDD2. The source of the 缕3ΐ3 is connected to the ground terminal, the gate terminal is connected to the mountain, the 6th terminal of the _, and the 汲 terminal is connected to the second end of the inductor 1211 and the anode terminal of the pole body 1212. The first end of the capacitor 1214 is connected to the first end of the resistor 1215, the output is the cathode end of the source VDD2 and the diode 1212, and the second end is connected to the ground. The first terminal of the resistor 1215 is connected to the first terminal of the capacitor 1214 and the cathode terminal of the diode 1212 and the output voltage source VDD2. The = terminal of the resistor 1215 is the voltage dividing point N1. The voltage dividing point N1 is connected to the input of the sample and hold circuit 1243 of the selection mode signal generator 1240. The first end of the resistor 1216 is also the voltage dividing point N1' and the second end is connected to the ground. 18 200913492 w 23955twf.doc/n / In the digitally controlled power conversion circuit 123〇, the counter! Say it can be counted up or down. When the output voltage source _2 is lower than the specification voltage value, the count is up to 1233, and the pulse width of the pulse signal PW_OUT increases with time (when there is an upper limit, the upper limit must be less than (10)%, such as , recommended value, 90%). When the output voltage source _2 is higher than the specification voltage value, the pulse width of the number of pulses 1233 down the pulse signal PW_OUT is decremented over time (of course, the lower limit thereof is, for example, the lower limit is 〇%). The counter 1233 is 往 the number of deaths or countdowns is controlled by the setting signal SEL. For example, when the setting signal SEL of the selected rake signal generator 1240 is logic low, the counter 1233 is counted down. When the setting signal SEL of the selection mode signal generator 124G is logic high, the counter 1233 is counted up. In addition, the hold signal h〇ld of the selection mode signal generator 1240 can determine the operating state of the count H 1233. #Select mode signal generation crying When the hold signal H0LD of the 1240 is logic low, the counter 1233 is in the normal operation mode. When the hold signal HOLD of the mode signal generator 124 is selected to be logic high, the counter is in a stopped state. Thus, the state of the count state 1233 is controlled, and the pulse signal PW_〇UT rotated by the multiplexer 1233 is controlled. The select mode signal generator 1240 includes comparators 1241, 1242, 1244, sample hold circuit 1243 and a mutex or gate 1245. The first input terminal of the sample and hold circuit 1243 is connected to the voltage dividing point N1 of the voltage conversion module 1210, and the input terminal receives the clock signal ck, and the output terminal thereof is connected to the negative input terminal of the comparator 1241 and the comparator 1242. The two positive inputs. The reference voltage VREF is connected to the positive input terminal of the car thief 1241, and the negative input terminal of the comparator 19 200913492 II lw 23955 twf.d〇c/n 1241 is connected to the wheel-out terminal of the sample-and-hold circuit 1243, and the output terminal outputs a set SEL signal. To counter 1234. n The positive input of the comparator 1242 and the input of the 1244 are both connected to the negative input of the comparator 1241 and the output of the sample and hold circuit 1243 and the negative input of the comparator 1242 are connected to the reference voltage vrefi. The negative input of the comparator 1244 is connected to the reference voltage VREF2. The two outputs of the comparator DC and 1244 are respectively connected to the two inputs of the mutually exclusive or closed 1245. The two inputs of the exclusive or gate I245 are connected to the outputs of the comparators m2 and (10), while the outputs thereof output the hold signal h〇ld to the count 1234. When the output voltage source v ship is close to the rated electric castle, the duty cycle of the pulse signal pw_(10) will be _ for the sake of simplicity. The detailed operation of the soft start circuit and the digital power conversion circuit of Fig. 10 to Fig. 12 The principle is the same or similar to the working principle of the first, and it is no longer Wei. However, the group is soft = the multiplexer in the bit-controlled power conversion circuit is produced: = need to be between ~ lag and lower limit = ^ through the architectural principle of Figure 2 and Figure 10 ~ Figure 12, and use - and use Soft-start circuit mechanism for external capacitors. In summary, the above-mentioned actual closing towel of the present invention can save external capacitive components and 2 = production because the raw pulse width modulation signal is not adjusted, because the starting circuit mechanism is a digital circuit, and the second and the second are lower. Below the voltage source (such as lv). Therefore, although the present invention has been disclosed above in several embodiments, it is not limited to 20 200913492 λ ι-\j\jkj-ι w 23955 twf.doc/n, and has any technical field in the art. In general, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 (a) and (b) are circuit diagrams of a conventional soft start circuit and f) generated duty cycle waveform diagrams. Figure 2 is a block diagram showing a power supply circuit in accordance with an embodiment of the present invention. 3A and 3B are schematic diagrams showing the architecture of a ring oscillator. Figure 4 shows a circuit diagram of the pulse generator. Figure 5 shows the clock and pulse signals generated by the ring oscillator and pulse generator. Figure 6 shows a circuit diagram of the counter. 〇 ® 7 displays the N+1 bit signal waveform generated by the counter. Figure 8 shows a schematic diagram of the interior of the multiplexer. Figure 9 shows the pulse signal waveform generated by the multiplexer. 10 to 12 show other embodiments of the present invention. 102: Resistor】〇5: Comparator 220=Selector [Main component symbol description] 101, 103: Transistor 104: Capacitor 210: Voltage conversion module 21 200913492 P2007-0U6-1W 23955twf.doc/n 241 : PWM generation 211: Inductor 213: transistor 215, 216: resistor 232: pulse generator 234: multiplexer 305: inverter 230: soft start circuit 242: enable signal generator 212: diode 214: capacitor

231: Ring oscillator 233: Counter 301-304: transistor 306, 307: delay unit 311 1 to 311 2N: differential signal output inverter 401 1 to 401 2N+1 : mutual exclusion or logic gate

60 603: flip-flop 801_0~801_N: inverter 803: transmission gate 1010: voltage conversion module 1030: soft-start circuit 1041: PWM generator 1011: transistor 1013: diode 1015, 1016: resistor 1032: Multiplexer 1034: Ring oscillator 1110: Voltage conversion module 1140: Enable generators 1111, 1112: Transistor 602: and Gates 802_1 to 802_2N+1: Switch 1000: Power supply system 1020: Selector 1040: Enable Signal generator 1042: Enable signal generator 1012: Inductance 1014: Capacitor 1031: Counter 1033: Pulse generator 1100: Power supply system 1120: Soft start circuit 1130: Voltage regulator 1113, 1114: Resistance 22 200913492 rzuu/-υυο -ι w 23955twf.doc/n 1115 : Capacitor 1121 Counter 1122 : Multiplexer 1123 Pulse Generator 1124 : Ring Oscillator 1200 Power Supply System 1210 : Voltage Conversion Module 1220 Buffer 1230 : Digitally Controlled Power Conversion Circuit 1240: Select mode signal generator 1211: Inductor 1212 Diode 1213: Transistor 1214 Capacitor 1215, 1216 · Resistor 1231 Ring oscillator 1232: Pulse generator 1233 multiplexer 12 34: Counter 1245 Mutex or Gate 1241, 1242, 1244: Comparator 1243: Sample and Hold Circuit ί. 23

Claims (1)

200913492 ...u,-卿-ϊν 23955twf.doc/n Ten, the scope of application for patents: a full range of soft-start electric 4 system, the full touch of Lai Wei material - power supply is a ring oscillator, according to consistent responsibility Multiple times with the same period and the same frequency: the signal; the phase is not monthly but a pulse generator is coupled to the ring Γ 所 产生 产生 产生 匕 匕 匕 匕 匕 责任 责任 责任Knowing that it is counted by generating a plurality of 0 tens of § 'supplied to one of the clock signals generated by the loop open 4 纟碁 L: when the soft start of the full-touch start circuit is generated, The device 'touches the pulse generator and the counter, and the multiplex = "4 counts the generated count signal to determine whether to transmit the pulse signals different in the duty cycle generated by the pulse ecology to generate the Ik time. Increasing one of the duty cycle of the output pulse. 2. The full-digital soft-start circuit as described in claim 1, wherein the ring oscillator comprises: - a first transistor, determining whether to conduct according to the enable signal ; —second transistor Determining whether to conduct according to the enable signal; - an inverter coupled to the first and second transistors, receiving and inverting one of the clock signals; 0 a plurality of serially connected inverting delay units, Receiving one of the output signals of the inverters' each of the inversion delay units outputs one of the clock signals. 24 200913492 r^w/-uw〇-iw 23955twf.doc/n 3. As claimed in the first item The full-digital soft start circuit includes: wherein the ring oscillator comprises: a plurality of serially connected differential signal output inverters, and the clock signals are generated according to the frequency of the enable signal and the frequency control voltage. A full-digital soft-start f-channel as described in claim 1, wherein the pulse generator includes a plurality of digital mutually exclusive or logic gates, and each of the mutually exclusive or logic gates is generated by the ring oscillator. The second bit of the clock signal is subjected to a digital logic operation to generate the pulse signal. [5] The full digital soft start circuit of claim 1, wherein the counter comprises a plurality of flip-flops, wherein Some of these flip-flops are used for - the counting period, the rest of the seam is used for the counting signal, when all the bits of the counting signal are logic high, the counter stops and all the bits of the money are maintained in logic High. 6. If you apply for the full-scale soft-start electric power as described in the article 专 丨 ===The toweler 11 includes 1 inverted H and multiple switches, each of which is used for reverse tt The number-bits _ are selected according to the pulse signals generated by the pulse generator according to the β-th bits of the counting signal and the inverted-bit bits thereof. The power supply system comprises: a full digital soft start circuit, operating under a reference voltage source, the king digital soft start circuit is used to generate an output pulse that changes its responsibility over time, the full digital soft start The circuit is back and operated; Huan 饴瓴 25 200913492 rzuu/-WD-lw 23955twf.d〇c/n a voltage conversion module; / a first pulse generator, operating under an output voltage source, the first A pulse generator for generating a pulse width modulation (PWM) signal ; And - a selector; wherein, when the power supply system starts, the selection would select P = Bian formula == fiber produced to the electrically conducting pulse. When the output voltage source of the controller is selected to be stable, the selection of the pulse width modulation signal generated by the voltage to the voltage converter is transmitted to the power supply system described in the entire item, wherein the rate is believed to be the phase The ones that are not aligned but have the same duty cycle and are generated by the frequency-time pulse detector are light. . The pulse signal of the Xiong-Hungarian duty cycle is different; - the - and the clock signals generated by the number oscillator - the multiplex-inhibition counting signal of a multi-bit; and how to conduct the reading A to find the counting money Determining the pulse signals generated by the output pulse street generator to produce the power supply system of the ring oscillator 8 wherein the first transistor determines whether to conduct according to the enable signal. 26 200913492 23955twf .doc/n a second transistor, determining whether to conduct according to the enable signal; ^ inverting, coupled to the first and second transistors, receiving and inverting one of the clock signals; The serially connected inverting delay unit receives an output signal of one of the inverters, and each of the inverting delay units outputs one of the clock signals. 10. The power supply system of item 8, wherein the sigma-type oscillator comprises: ^ φ connected differential signal input & inverting ^, according to the enable signal and a frequency control The voltage signals are generated by the voltage. U. The power supply system of the above-mentioned item, wherein the pulse generator comprises a plurality of mutual-mutation or sluice gates, and each of the digits is mutually responsive to the clock signals generated by the ring. Digital logic operations to generate the pulse signals. The power supply for the 8th item (4) is used for the remainder of the system, where; the counter is reversed; the part of the device is used for::; all the bits of the Γ counting signal are for the production = 4 The bits are all hidden from the logic high. Talk about the patent scope 帛8 of the power supply system, in which the second eve work includes multiple inverted H and multiple switches, each inverted cry for the ΐ-bit' The switches are selected according to the U of the counting signal i and the inverting contact f (four) two-pulse signal to form the output pulse. The two-K is as described in claim 7 of the power supply (four) system, wherein 27 200913492 --------23955twf.doc/n The voltage conversion module comprises: a step-down module. 15. The power supply system according to claim 7 of the patent application, further comprising a uniform energy signal generator, For generating the enable signal for controlling the full-digital soft start circuit. 16. A power supply system, comprising: a digitally controlled power conversion circuit, operating under a reference voltage source, the digitally controlled power conversion circuit Produce an output pulse that changes with time and has a duty cycle; mussel % t conversion The group converts the reference voltage source according to the digitally controlled power conversion circuit to convert the reference voltage source to generate a wheel-to-electric ink conversion to control the digitally controlled power conversion mode: surface-connected to digitally controlled power conversion The circuit and the voltage supply system as described in claim 4 of the patent specification No. 31, the re-hai digital control type power conversion circuit includes: /, the rate believes that the phase is not aligned but the duty cycle is the same, the messenger' According to the clocks b generated by the ring-shaped coffee, a plurality of pulse signals having different duty cycles are generated; the number of "1" is generated according to the simple illusion, and some of the clock signals have less til to generate a multi-bit Counting signal, the count: the idle mode, when the counter is in the operating mode 28 200913492 23955twf.doc/n, the duty cycle of the pulse signals generated by the pulse generator is increasing; when the counter When in another mode of operation, the duty cycle of the pulse signals generated by the pulse generator is gradually reduced; and a multiplexer is generated according to the counter The number signal determines how the pulse signals generated by the pulse generator are conducted to generate the round pulse. 18. The power supply system of claim 17, wherein the pulse generator comprises a plurality of digital mutually exclusive or logic gates, and the respective digits or logic gates generate the clocks generated by the ring oscillator The second signal is subjected to a digital logic operation to generate the pulse signals. The power supply system of claim 17, wherein the multiplexer comprises: a plurality of inverters and a plurality of switches, each of the inverters for inverting one of the count signals, The switches select the output pulse from the pulse signal generated by the pulse generator according to the bits of the counting signal and the inverted bit. 20. A power supply system comprising: a full digital soft start circuit operating under a reference voltage source, the full digital soft start circuit for generating a duty cycle over time ^ a voltage conversion mode a generating a bias-voltage regulator that operates on an output voltage source to modulate the signal; and a uniform energy signal for controlling the full-digital soft-start consistent signal generator circuit; 29 o The clocks generated by the signal are 200913492 1 ...w μ,23955twf.doc/n When the soft-start electric surface is not stable, the voltage conversion mode is based on the full digital type _: The voltage _ the replacement module will be fully open, the TO The bias voltage modulation signal is adjusted to adjust the group, and the group converts the reference voltage source into: the surface of the Laon number for her, the rate is the same as the sliver-reading and the frequency counter, according to the lion oscillation The number of clock signals generated by the series is counted. ,. To generate a multi-bit count signal; and - multiplex 2' to determine how to transmit the Wei complement generated by the secret genre based on the count signal generated by the count to generate the output pulse. 22. The power supply system of claim 21, wherein the ring oscillator comprises: a first transistor that determines whether to conduct according to a uniform energy signal; and a second transistor that is based on the enable signal Determining whether to conduct; a reverse phase, coupled to the first and second transistors, receiving and inverting one of the clock signals; a plurality of serially connected inverting delay units, receiving one of the inverters Output letter 30 200913492 23955twf.doc/n, each inverting delay unit outputs the clock signal in the clock signal, the == range, the 21st item, the plurality of serially connected differential signal output inverters, a frequency control Wei ― Produce a light clock signal. According to the H tiger and the 21 items, the 四 r r r 产生 = = = = = = = = = = = = = = 环形 环形 环形 环形 环形 环形 环形 环形 环形 环形 。 。 。 。 。 。 In the 25th, the power supply system of the Wei Wei F 21 item is used for the power supply system, and the detector includes a plurality of flip-flops, wherein the positive and negative components - part of the Si: counting period, the positive and negative The rest of the device is used to generate a count~' when all bits of the burst signal are logic high. High; ^ counts and all bits of the count signal are maintained in the logic with a plurality of inverters and a plurality of switches, the secret number of each inverted number == one bit, the switches are based on the count The balance is chosen to be the output pulse. Produced 31