200913492 F2007-006-1W 23955twf.doc/n 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種軟啟動的電路,且特別是有關於 一種能工作在低電壓源下的全數位式軟啟動電路。 【先前技術】 在需要脈衝寬度調變(pWM)信號之電源供應系統 〇 巾’因為升降壓的義’需要利用大電感《大電容作能量 儲存及轉換的動作。為使電源供應系統在啟動過程中,避 免因瞬間大電流傷害元件及内部電路,目前會加入軟啟動 (Soft-start)電路於電源供應系統。 在傳統電源供應系統之軟啟動電路中,會增加一電阻 電夺迴路在所需之輸出麵上丨⑻為—種習知技術之 軟啟動電路之示思圖。如圖丨⑻所示,此習知軟啟動電路 包含:電晶體101與103、電阻1〇2、電容1〇4以及比較器 105。 電晶體101之閘極端連接致能信號ENB,源極端連接 電壓源,没極端則連接纽102之第一端。電晶體103之 閘極端連接致能^號ENB,源極端連接至接地端,沒極端 連接至電阻102之第二端、比較器1〇5之正輸入端與電容 104之第一端。 一電阻102的第—端連接至電晶體101之汲極端,其第 了端連接至比較盗1〇5之正輸入端、電晶體1〇3之没極端 /、电合104之第一端。比較器1〇5之正輸入端連接電容 200913492 P2007-006-TW 23955^^^0/1, 的第一端、電阻102之第一端與電晶體1〇3之汲極端,此 點亦為節點電壓VST。比較器105之負輸入端則接收三角 k號TRI。電容104的第一端連接至比較器1〇5之正輪入 端、電阻102之第二端與電晶體1〇3之汲極端,其第二 連接至接地端。 比較态105比較三角信號波TRI與節點電壓VSt(a Γ ^電阻102與電容104所充電)。如圖1(b)所示,當三^角 信號波形TRI小於節點電壓VST時,比較器、(〇5的輪 號EXJ會為局電位;當三角信號波形tri大於節點電壓 VST時,比較|| 1G5的輸出信號咖會為低電位200913492 F2007-006-1W 23955twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a soft start circuit, and more particularly to a full digital position capable of operating at a low voltage source Soft start circuit. [Prior Art] In a power supply system that requires a pulse width modulation (pWM) signal, the 'receiving pressure' is required to utilize the large inductance "large capacitance" for energy storage and conversion. In order to prevent the power supply system from damaging components and internal circuits due to transient high current during the startup process, a soft-start circuit is currently added to the power supply system. In the soft-start circuit of a conventional power supply system, a resistor is added to the desired output surface (8) as a schematic diagram of a soft-start circuit of the prior art. As shown in Fig. 8 (8), the conventional soft start circuit includes: transistors 101 and 103, a resistor 1 〇 2, a capacitor 1 〇 4, and a comparator 105. The gate of the transistor 101 is connected to the enable signal ENB, the source terminal is connected to the voltage source, and the terminal is connected to the first end of the button 102. The gate terminal of the transistor 103 is connected to enable ENB, the source terminal is connected to the ground terminal, and is not connected to the second terminal of the resistor 102, the positive input terminal of the comparator 1〇5 and the first terminal of the capacitor 104. The first end of a resistor 102 is connected to the 汲 terminal of the transistor 101, and the first end is connected to the positive input terminal of the thief 1 〇 5, the non-extreme terminal of the transistor 1 〇 3, and the first end of the electrical connection 104. The positive input terminal of the comparator 1〇5 is connected to the first end of the capacitor 200913492 P2007-006-TW 23955^^^0/1, the first end of the resistor 102 and the end of the transistor 1〇3, which is also Node voltage VST. The negative input of comparator 105 receives the triangle k TRI. The first end of the capacitor 104 is connected to the positive terminal of the comparator 〇5, the second end of the resistor 102 and the 汲 terminal of the transistor 〇3, and the second terminal is connected to the ground. The comparison state 105 compares the triangular signal wave TRI with the node voltage VSt (a Γ ^ resistor 102 and capacitor 104 are charged). As shown in Fig. 1(b), when the three-corner signal waveform TRI is smaller than the node voltage VST, the comparator, (the wheel number EXJ of 〇5 will be the local potential; when the triangular signal waveform tri is greater than the node voltage VST, the comparison| | 1G5's output signal will be low
時間經過’節點· VST會慢慢㈣,輸出信號ΕΧΤ的 責任週期也會越大。 WThe time passes through the node and the VST will slowly (four), and the duty cycle of the output signal will be larger. W
為避免在啟動過程中’大電流傷害元件電路,電壓VST ί上Γ气度必須相對緩慢,電容104的電容值因此必須好 二:二,信號波形產生器與比較器⑽ 偏比Ϊ路,會導致軟啟動電路之工作電壓必須在lv以 上,以確保電路能正常工作。 用到種軟啟動電路,其可改良習知技術需使 容的此::可t數::工作且不需使用到外部電 Metal Oxide Se * 八可用 CMos(Complementary -e'S__u* ’互補式金氧半導體)製程來實現。 【發明内容】 200913492 ^2υυ/-υυ〇-ι w 23955twf.doc/n 本lx月挺供-種王數位式軟啟動電路,可應用於 供應系統中。此軟啟動電路不需使用外 二;电/'、 製程來實現。 本發明之靶例之-提出―種全數位 括環形振盪器、脈衝產生器、計數器與多工;動二^ 產生器產生責任周期不同的 Γ 生:斤產多工器決定是否傳導脈衝產 生杰所產生之脈齡#b,以產生隨時間 座 本發明之另一範例提出—種電源供應^ 3出脈衝。 數位式軟啟動電路,操作於參考電虔ϋ…,包括:全 啟動電路用於產生隨時間而改變里責任、,該全數位式軟 該全數位式軟啟動電路更回應於二致能脈衡, 生器用於產生脈衡寬度調變脈衝產 動電路所產生之該輪出脈衡傳封王數位式軟啟 壓轉換模組據以產原3電壓轉換模組’該電 生之該輪出電壓源足豹二二’、。*該電壓轉換模組所產 兮rr榛命由上 "擇00廷擇將該脈衝產生所吝斗々 該财t見度調變信號傳導至該電壓轉換模所產生之 發明之又一範例更提出一種湄供 數位控制式電源轉換電路,操作於系統,包括: 控制式電源轉換電路用於產生隨時; ΟIn order to avoid the 'high current damage component circuit during the startup process, the voltage VST ί must be relatively slow, and the capacitance of the capacitor 104 must be good two: Second, the signal waveform generator and the comparator (10) are biased, which leads to The operating voltage of the soft-start circuit must be above lv to ensure that the circuit can work normally. A kind of soft start circuit is used, which can improve the conventional technology: this can be t:: work and does not need to use external electricity Metal Oxide Se * eight available CMos (Complementary -e'S__u* 'complementary The MOS process is implemented. [Summary of the Invention] 200913492 ^2υυ/-υυ〇-ι w 23955twf.doc/n This lx month is quite a kind of king-type digital soft start circuit, which can be applied to the supply system. This soft-start circuit does not need to use the external two; electric / ', process to achieve. The target example of the present invention is to provide a ring oscillator, a pulse generator, a counter and a multiplex; the generator generates a duty cycle with different duty cycles: the multiplexer determines whether or not the pulse is generated. The generated pulse age #b is generated to generate a power supply pulse for another example of the present invention. The digital soft start circuit operates on the reference power supply, and includes: a full start circuit for generating a responsibility for changing with time, the full digital soft circuit, the full digital soft start circuit is more responsive to the second enable pulse balance The generator is used to generate the pulse-balance width modulation pulse generating circuit to generate the round-off pulse balance transmission king digital soft start voltage conversion module according to the original 3 voltage conversion module 'the electric student's round out The voltage source is Leopard II'. * The voltage conversion module produces a 兮rr command from the above-mentioned "selection of the pulse" to generate the pulse, the financial t-modulation modulation signal is transmitted to the voltage conversion mode. A digital control type power conversion circuit is provided for operating in a system, comprising: a control type power conversion circuit for generating at any time;
L 200913492 ^υυ/-υυο-ι w 23955twf.doc/n 輸出脈衝;電㈣換模組,根據該數 路所產生之該輸出脈衝以產生輸出電^刺式電源轉換電 產生益,用以選擇該數位控制式電鳇、選棒模式信號 式;以及緩衝器,耦接於該數位控制1 + ;電路之操作模 電壓轉換模組之間。 %源轉換電路與該 本發明之又-範例更提出—種 全數位式軟啟動電路,操作於參考严调、%、糸統,包括·· 軟啟動電路用於產生隨時間而改變,垓全數位式 衝;電壓轉換模組;電壓調節界,/貝壬周期之輸出脈 產生偏墨調變信號;以及致能_:,出電髮源下, 該全數位式軟啟動電路之致能信=。a态,用以產生控制 穩定時’根賴全綠式魏“如麵源尚未 衝,該電_換模”電路所產生之該輪出脈 源。當該輪出電二咖 ^^ 心曼該電壓轉換模組會全開,绿 包[调㈣所產生之該偏壓 該 組,該電麗轉換模%將兮灸去卡,㈣即該电廢轉換模 、、'將該參考電壓源轉換成該 外彳:Γ採用上述之全數化結構,因此可改進‘ 外增加外部電容與類比 =而額 CMOS製程下實現。^源的缺點亚可讓電路在 兴杏力=本^月之上述特徵和優點能更明顯易懂’下文特 牛貝& '、、配合所附圖式’作詳細說明如下。L 200913492 ^υυ/-υυο-ι w 23955twf.doc/n output pulse; electric (four) change module, according to the output pulse generated by the circuit to generate output power supply power conversion, to select The digital control type electric power, the selected mode signal type; and the buffer are coupled between the digital control 1 +; the operating mode voltage conversion module of the circuit. The % source conversion circuit and the further example of the present invention propose a full-digital soft-start circuit that operates on a reference-regulated, %, 糸 system, including a soft-start circuit for generating changes over time, Digital rush; voltage conversion module; voltage regulation boundary, output pulse of /bee period produces offset modulating signal; and enable _:, power generation source, the full digital soft start circuit enable signal = . The a-state is used to generate the control when the stability is stabilized by the full-green type "such as the surface source has not been rushed, the electric_changing mode" circuit generates the pulse source. When the power is turned on, the voltage conversion module will be fully opened, and the green package [Tune (4) produces the bias voltage of the group, the electric conversion mode% will acupuncture to the card, (4) the electric waste Converting the modulo, 'converting the reference voltage source into the external 彳: Γ using the above-mentioned full-scale structure, so it can be improved by adding external capacitance and analogy = under the CMOS process. ^ The shortcomings of the source can make the above-mentioned features and advantages of the circuit in Xing Xing Li = this ^ month more obvious and easy to understand 'The following special cattle & ', with the accompanying drawings' are described in detail below.
【實施方式;I 為了使本發明之内容更為明瞭,以下特舉實施例作為本 200913492 rzuu/-uuo-i w 23955twf.doc/n 發明確實能夠據以實施的範例。 在本發明實施例中,為改良習知電源共應系統中,額 外增加外部電容與工作電壓必須在lv以上的缺點,故利 用全數位化模組來達成軟啟動電路的功效。[Embodiment] I In order to clarify the content of the present invention, the following specific example is taken as an example of the invention that can be implemented by the present invention as 200913492 rzuu/-uuo-i w 23955 twf.doc/n. In the embodiment of the present invention, in order to improve the conventional power supply co-generation system, the external capacitor and the operating voltage must be increased in excess of lv, so that the full digital module is used to achieve the soft start circuit.
請參考圖2’其顯示根據本發明較佳實施例之電源供 應系統之方。此電祕應系統包括:電 模 組2Π)、選擇器220、軟啟動電路23〇、ρψΜ產;j 以及致能信號產生器242。 當電源供應系統啟動時’選擇器22〇合 ^ 230所產生的輸出脈衝傳導至電壓轉換模組^,由 1轉換模組210據以產生輸出電壓源娜2(不過,此時 當電壓轉換模, 趨向财時’選擇器22。會選擇由 _;Τέ^241所產生的脈衝寬度調變信號傳導至電壓 轉換拉組21 〇,以#带厭絲从 > 吁〒电麼 壓源VDD2。 $輯換板、組210提供穩定之輸出電 極體L圖2電所日不體’2=換模組210包括:電感2n、二 %日日體213、電容214與電阻215及216 之陽極源VDD1,其第二端連接二極體加 電感之一 至輸出電壓源_2、電端,其陰極輕接 端。電晶體;213之、之弟h與電阻215之第— 汲極端連接至電感^ ^連,選擇器22G之輸出端, " 之弟一端與二極體212之陽極端, 200913492 rzuu/.uuo-i w 23955twf.doc/n 源極端則耦接至接地端。電容214之第一端連接至二極體 之陰極端、電阻215之第一端及輸出電壓源VDr)2, 其第二,則耦接至接地端。電阻215之第一端連接至電容 214之第一端、二極體212之陰極及輸出電壓源VDD2, 其第二端則連接至電阻216之第一端。電阻—之第 連接至電阻215之第二端,其第二端則連接至接地端。 ”在電壓轉換模組训中,電阻犯與216可當成分壓 為。分壓後的節點電壓m則耦接至致能訊 之負輸入端與PWM產生哭241夕於U山^ 座之一輸入端。致能訊號產 态 之正輸入端則輸入一參考電壓VREF,其輸出端 生致能信號EN。致能信號EN會傳送至軟啟動電路23〇 形«器23卜致能信號EN可用於控制軟啟動電路 230疋否處於正常操作狀態或關閉狀態。 电壓轉換极、组210所產生之輸出電壓源VDD2會當成 1>二f生ί 241及致月^號產生器242之操作電壓源。 υ 生器241所產生之脈衝寬度調變信號會傳給選擇 态 220。PWM 產生器 241 之芊槿σ φ At .. 信料可。 構可不U、要能產生 軟啟動電路230操作於電壓源VDm下,用以產生會 =著時間而料責任週期的脈_號爾—㈤了。軟啟動電 fO之内。卩電路如圖2所示’其包括:環形振I器况、 脈衝產生器232、計數器233與多工器234。 漱環形振盪器231根據致能信號刚,而產生相位不對 4但責任周期相同的複數時脈錢CK、cK丨、·..、CK2n+1 〇 200913492 P2007-006-1W 23955twf.doc/n 時脈信號CK、CK1.....CK2N+1都具有相同頻率。脈衝 產生器232柄接至環形振烫器231’並根據環形振盈器231 所產生之相位不對齊但責任周期相同的時脈信號進行數位 邏輯運算’以產生責任周期不同的脈衝信號PW1、 PW2.....PW2n+1 ο 计數裔233輕接至環形振I器231 ’其根據環形振蘯 器231所產生的時脈信號CK來計數,以產生N+1位元信 號S0〜SN。計數器233將影響軟啟動電路23〇的軟啟動^ 間。多工器234耦接至脈衝產生器232與計數器233之間。 多工器234根據計數器233所產生的N+1位元信號 S0〜SN ’蚊是料導脈魅生^加所產生的責任周期° 不同之脈衝信號。如此,可以產生隨時間而增加責任周期 的輸出脈衝信號JPWJXJT。 凊參照圖3A,環形振盡器231包括:電晶體勝綱, 夕個反向器3G5 ’多個延遲單元306,以及延遲單元3〇7。 接至ί:二二Z端連接至電壓源VDD1,閑極端連 接至致4號ENB(其為致能信號EN之反 端則連接至電晶體302之源極端。 ^ 遲單連接至電㈣之閑極端與延 汲極端,其汲極端連接至反向考接f電日日體301之 體303及304之源極端。° 〇5」之輪入端以及電晶 電晶體303及304之源極 之閘極端連接至致能信號 電晶體303及304為並聯 端相連至接地端。電晶體3〇4 200913492 P2UU/-UUb-iw 23955twf.doc/n ENB。電晶體303之閘極端連接至電晶體3〇2之閘極端與 延遲單元307之輸出信號端。電晶體3〇3及3〇4之汲極端 則連接至反向裔305一 1之輸入端以及電晶體302之沒極端。 反向器305一 1之輸入端連接至電晶體3〇2、3〇3與3〇4 之汲極端,而輸出端耦接至延遲單元3〇6J之輪入端。延 遲單元306—1之輸出端會輸出時脈信號CK1。時脈信號 CK1與時脈信號CK相差一個相位。如圖5之CK與CK1 之波形所示。依此類推,由延遲單元306 2 ......、306 2n+1 之輸出端輸出時脈信號CK2........CK2N+1。這些時"脈信 號彼此均相差一個相位,且其頻率相同。反向器2n+1 連接至延遲單元307以及電晶體3〇2、3〇3之閘極端,其輸 出時脈L唬CK。環形振盪器231所輸出之時脈信號ck, CK1……CK2N+1如圖5所示。 此外,電晶體301〜304描述如何進行致能動作,同時 亦提供反相ϋ。這些輯單抑可由減延遲效果 的反相器組成。 圖3Β顯示環形振盪器231之另一種架構示意圖。在 圖3Α中,裱形振盪器231包括單端輸出反相器。但在圖 3Β、中J J衣形振靈器231則包括差動訊號輸出反相器。環形 振盪裔231之頻率由電壓VB所控制。 如圖3B所示,環形振盪器231包括多個差動訊號輪 出,相益311—1〜311—2n。反相器311」之正輸入端與負輸 入端为別接收時脈信號CK與時脈信號ck2n。反相器 311—1之正輸出端與負輸出端分別輸出時脈信號cK1與時 12 200913492 rzuu/-uuo-i w 23955twf.doc/n 脈信號CK2N+1。 脈衝產生器232之内部架構如圖4。時脈信號CK與 cki經由互斥或邏輯閘(x〇R gateau做互斥或邏輯 運算後產生脈衝信號PW1。時脈信號CK與CK2經由互斥 或邏輯閘401 一2做互斥或邏輯運算後產生脈衝信號pw2。 依此類推產生如圖5所示之脈衝信號pwi、PW2、....... PW2N+1。 〇 計數器233計數環形振盪器231所產生之時脈信號 CK,藉以生成N+1位元信號so〜SN。如圖ό所示,計數 器233包含多個正反器601、多個正反器6〇3與及閑(AND GATE)602。 正反盗601之數量將影響計數器233之計數週期,亦 即會影響信號S0〜SN之週期寬度。正反器6〇3用於產生 N+1位元信號S0〜SN。信號S0〜SN之波形圖如圖7所示。 及閘602之輸入端接收N+丨位元信號s〇〜SN,其輸出 端連接至全部正反器603之設定端(SEL)。當所有信號 SO ’ S1......SN都為邏輯高(L〇gic HIGH)時,及閘602將 信號S0,S1……SN都維持在邏輯高之狀態,如圖7所示 之計數器233停止之波形。 ’ 多工器234由2N+1個開關^+丨與Ν+ι個 反相器801 一0〜801 一N所組成,如圖8所示。各開關比如由 多個傳輸閘803組成,當然本實施例並不受限於此。該些 反相器801之輸入端連接信號s〇〜SN然後輸出s〇By S1B......SNB。 13 200913492 rzuu/-uwo-i w 23955twf.doc/n 開關802_1之輸入端接收脈衝信號PWl,並由信號 S0〜SN決定是否讓脈衝信號PW1輸出為pw_OUT。開關 802_2之輸入端接收脈衝信號PW2,並由信號S0〜SN決 定是否讓脈衝信號PW1輸出為PW_OUT。依此類推來選 擇輸出脈衝信號PW__OUT為脈衝信號PW1或PW2 或…PW2N+I。如圖9之時序圖所示。例如當SO,S1…SN 均為邏輯低時,脈衝信號PWJDUT為脈衝信號PW卜最 後達穩定之輸出脈衝信號為PW2N+1。其中脈衝信號之責任 周期需介於上限DMAX<100%與下限DMIN = 〇 〇 圖10〜圖12顯示本發明之其他實施例,熟習此項技藝 者當知本發明並不受限於此。圖10之電源供應系統1000 包括:電壓轉換模組1010、選擇器1020、軟啟動電路1〇3〇、 致能信號產生器1040、PWM產生器1〇41與致能信號產生 斋1042。軟啟動電路1〇30包括:計數器1〇31、多工器 1032、脈衝產生器1〇33與環形振盪器1〇34。 電壓轉換模組1010之輸入端與選擇器1020之輸出端 相連接。其分壓點N1連接至致能信號產生器1〇4〇之負輸 入端與PWM產生器之一輸入端。選擇器1〇2〇選擇軟啟動 電路1030所輸出之脈衝信號,或是pwM產生器ι〇4ΐ所 產生之脈衝寬度調變信號。受控於選擇器1〇2〇所選擇之信 號’電壓轉換模組1010將電壓源VDD1轉換為輸出電壓 源 VDD2。 致能信號產生器1〇42之正輸入端連接至參考電壓 VREF,其負輸入端連接電壓轉換模組1〇1〇之分壓點 14 200913492 P2007-006-TW 23955twf.doc/n 致能信號產生器1042之輸出端產生致能信號EN,並傳送 至環开> 振盡益1034與PWM產生器1〇41之一輸入端。pwM 產生益1041之一輸入端連接致能信號產生器之輸出 %,其另一輸入端連接至電愿轉換模組之分壓點 N1,其輸出端與選擇器1〇20之輸入端連接。 電壓轉換模組1〇1〇包括:電晶體1011、電感1〇12、 二極體1013、電容1014與兩個電阻ι〇15與1〇16。電晶體 1011之源極連接至電壓源VDD1,電晶體ion之閘極連 接至選擇器1020,電晶體ΐ〇π之汲極連接至電感1〇12之 一端與二極體1013之陰極。 二極體1013之陽極則連接至接地端,其陰極則連接 至電感1012之第一端與電晶體1〇11之汲極端。電感1〇12 之第一端連接電晶體1011之汲極端以及二極體1〇13之陰 極‘,其第一端則連接電容之第一端與電阻丨〇15之 第一端。 電容1014之第一端連接至電阻1015之第一端與電感 1012之第二端,並提供該輸出電壓源V])D2。電容1〇14之 第二端則連接至接地端。電阻1015之第一端連接至輸出電 壓源VDD2,其第二端連接至分壓點N1。電阻1〇16之第一 端連接至分壓點N1 ’其第二端則連接至接地端。 軟啟動電路1030接收致能信號EN。環形振盪器1034 產生時脈信號CK,CK1......CK2N+1。時脈信號CK輸入至 计數器1031。時脈信號ck , CK1......CK2N+1輸入至脈衝 產生器1033。計數器1〇31產生信號s〇〜SN,以及脈衝產 15 200913492 23955twf.doc/n w 取 或 生器1033產生脈衝信號PWl、PW2........PW2n+i 後由多工器1032選擇讓脈衝信號PW1或PW2或… PW2N+1 輸出至 PW_OUT。 圖11為另一實施例之電源供應系統的電路方塊圖。 此具施例中之%源供應系統11 〇〇包括:電壓轉換模、組 mo、軟啟動電路1120、致能產生器1140與電壓調節哭 1130。根據軟啟動電路1120所產生之脈衝信號或電壓調g 器1130所產生之偏壓調變信號,電壓轉換模組m〇將電 ,源VDD1轉換成所需要之輪出電壓源VDD2。當輸出電 愿源VDD2穩定之後,電壓轉換模組lu〇内部^電晶= 1111會全開,此時,電壓調節H 113G會調節電晶體⑴^ 之閉極電麗,以將源VDD1轉換成輸出電壓源VDD2。 致能產生器1140比較參考電壓VREF2 =並將比較結果當成致能信號EN以輸入至軟 節器„30比較參考電請EF1與節點電壓 亚將比較結果當成偏壓調變信號以輸人 組1110内部之電晶體1112之閘極。 果 電壓轉換模組U1G包括:電晶體1111及1112、電阻 1113及1114與雷完帝曰μ 壓湄VDrn,pg 包日日1111之源極端連接至電 = ,力極端接收軟啟動電路1120所產生 ==極端則連接至電晶體出2之= „ ,日日— 之源極端連接至電晶體1111之汲極踹, 開極端接收賴調節器113 ^糾 端則連接至電阻1113之笛之駄調、_,汲極 3之弟一鳊、輪出電壓源VDD2以及電 16 200913492 ^wv-υυο-ι w 23955twf.doc/n 容1115之第一端。 電阻1113之第-端連接至輸 1112之汲極端,其第二端則連接至電阻⑴二電晶體 =二電130之正輸入端與致能產 端。電容1115之第一端則诖垃於山弟—鸲都連接至接地 之第-端*電日體輸出電壓源跡電阻m3 日日體1112之汲極端,而1第-戚目丨丨、“* r 阻1114之第二端(亦即接地端)。、弟—训連接至電 軟啟動電路1120包括:計數器U2l,多工 脈衝產生器1123與環形振B 1124。 〇〇 2, 換模組咖、_轉 ^ 双证衩制式電源轉換電路1230 =包i,^生器i24G°數位控制式電源轉換電路 ㈣與計數^;=器1231,脈衝產生請2,多工器 ㈣電路123G所產生之脈衝信號 壓棘拖握/緩衝态1220,再由緩衝器1220傳送至電 模組mo且ϋ〇。党控於此脈衝信#bPW—ουτ’電壓轉換 VDD2。電塵源VDD1轉換成所需要之輸出電壓源 包乂轉換模!且121〇之分壓點N1輕接至選擇模式 17 200913492 A …4 ” 23955twf.d〇c/n 信號產生器1240。選擇掇十产味女 "式㈣舰μ 式麵生11 124Q可控制數位 k制式電源轉換電路123〇 號產生哭194η 您奋作杈式。比如,選擇模式信 號-與保持信號 可控制數位控制式電源轉換電路賤Referring to Figure 2', there is shown a power supply system in accordance with a preferred embodiment of the present invention. The electrical system includes: a motor module 2), a selector 220, a soft start circuit 23A, a circuit, and an enable signal generator 242. When the power supply system is started, the output pulse generated by the selector 22 is transmitted to the voltage conversion module ^, and the conversion module 210 generates the output voltage source 2 (however, when the voltage conversion mode is used) , trending to the 'timer' selector 22. The pulse width modulation signal generated by _; Τέ ^ 241 is selected to be transmitted to the voltage conversion pull group 21 〇, with the # 厌 从 从 & & & & & 。 。 VDD. $Series change board, group 210 provides stable output electrode body LFig. 2 Electricity station is not in the body'2=Change module 210 includes: inductor 2n, two% solar body 213, capacitor 214 and anodes of resistors 215 and 216 VDD1, the second end of which is connected to one of the diode and the inductor to the output voltage source_2, the electric terminal, and the cathode of the cathode. The transistor; the 213, the brother h and the resistor 215 are connected to the inductor ^ ^, the output of the selector 22G, the end of the " brother and the anode end of the diode 212, 200913492 rzuu /.uuo-i w 23955twf.doc / n source terminal is coupled to the ground. Capacitor 214 One end is connected to the cathode end of the diode, the first end of the resistor 215 and the output voltage source VDr) 2, and the second is To the ground terminal. The first end of the resistor 215 is connected to the first end of the capacitor 214, the cathode of the diode 212 and the output voltage source VDD2, and the second end is connected to the first end of the resistor 216. The resistor is connected to the second end of the resistor 215 and the second end is connected to the ground. In the voltage conversion module training, the resistance of the resistor and the 216 can be used as the component pressure. The node voltage m after the voltage division is coupled to the negative input terminal of the enable signal and the PWM generates a cry 241 in the U mountain ^ seat The input terminal of the enable signal is input with a reference voltage VREF, and the output terminal generates an enable signal EN. The enable signal EN is transmitted to the soft start circuit 23, and the enable signal EN is available. The control soft-start circuit 230 is in a normal operation state or a shutdown state. The voltage conversion pole, the output voltage source VDD2 generated by the group 210 will be regarded as 1> the operating voltage source of the second and second generation generators 242 The pulse width modulation signal generated by the 241 is transmitted to the selected state 220. The 产生 σ φ At .. of the PWM generator 241 can be configured to be capable of generating a soft start circuit 230 operating at a voltage Under the source VDm, it is used to generate the pulse _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 232, counter 233 and multiplexer 234. 漱 ring oscillator 231 according to The signal is just the same, but the complex clock with the same phase but the same duty cycle is CK, cK丨,·.., CK2n+1 〇200913492 P2007-006-1W 23955twf.doc/n clock signal CK, CK1... .. CK2N+1 all have the same frequency. The pulse generator 232 is connected to the ring-shaped vibrator 231' and performs a digital logic operation according to the clock signal generated by the ring oscillator 231 with phase misalignment but the same duty cycle. The pulse signals PW1, PW2.....PW2n+1 having different duty cycles are generated. ο Counting 233 is lightly connected to the ring oscillator 231', which is counted according to the clock signal CK generated by the ring oscillator 231, to The N+1 bit signals S0~SN are generated. The counter 233 will affect the soft start of the soft start circuit 23A. The multiplexer 234 is coupled between the pulse generator 232 and the counter 233. The multiplexer 234 is based on the counter 233. The generated N+1 bit signal S0~SN 'the mosquito is a pulse signal with a different duty cycle generated by the feed pulse enchantment. Thus, an output pulse signal JPWJXJT which increases the duty cycle with time can be generated. Referring to FIG. 3A, the ring resonator 231 includes: a transistor victory, a eve Transmitter 3G5 'multiple delay unit 306, and delay unit 3〇7. Connected to ί: the second Z terminal is connected to the voltage source VDD1, and the idle terminal is connected to the No. 4 ENB (which is the opposite end of the enable signal EN) It is connected to the source terminal of the transistor 302. ^ The delay is connected to the idle terminal of the electric (4) and the extreme of the delay, and the terminal of the connection is connected to the source terminal of the bodies 303 and 304 of the reverse polarity. The wheel terminal of the 〇5" and the source terminal of the transistors 303 and 304 are connected to the enable signal. The transistors 303 and 304 are connected in parallel to the ground. Transistor 3〇4 200913492 P2UU/-UUb-iw 23955twf.doc/n ENB. The gate terminal of the transistor 303 is connected to the gate terminal of the transistor 3〇2 and the output signal terminal of the delay unit 307. The extremes of the transistors 3〇3 and 3〇4 are connected to the input of the reverse 305-1 and the transistor 302 is not extreme. The input of the inverter 305-1 is connected to the 汲 terminal of the transistors 3〇2, 3〇3 and 3〇4, and the output terminal is coupled to the wheel terminal of the delay unit 3〇6J. The output of the delay unit 306-1 outputs a clock signal CK1. The clock signal CK1 is out of phase with the clock signal CK. The waveforms of CK and CK1 are shown in Figure 5. And so on, the clock signals CK2.....CK2N+1 are outputted by the output terminals of the delay units 306 2 ..., 306 2n+1. At these times, the pulse signals are different from each other by one phase and have the same frequency. The inverter 2n+1 is connected to the delay unit 307 and the gate terminals of the transistors 3〇2, 3〇3, which output the clock L唬CK. The clock signals ck, CK1 ... CK2N+1 outputted by the ring oscillator 231 are as shown in FIG. In addition, transistors 301 through 304 describe how to perform the enabling action while also providing an inverted chirp. These series can be composed of inverters that reduce the delay effect. FIG. 3A shows another architectural diagram of the ring oscillator 231. In Fig. 3A, the sigma oscillator 231 includes a single-ended output inverter. However, in Fig. 3, the J J garment shape 231 includes a differential signal output inverter. The frequency of the ring oscillator 231 is controlled by the voltage VB. As shown in Fig. 3B, the ring oscillator 231 includes a plurality of differential signal turns, and the benefits 311-1 to 311-2n. The positive input terminal and the negative input terminal of the inverter 311" receive the clock signal CK and the clock signal ck2n. The positive output terminal and the negative output terminal of the inverter 311-1 respectively output clock signal cK1 and time 12 200913492 rzuu/-uuo-i w 23955twf.doc/n pulse signal CK2N+1. The internal architecture of the pulse generator 232 is shown in FIG. The clock signals CK and cki are mutually exclusive or logically operated (x〇R gateau to generate a pulse signal PW1. The clock signals CK and CK2 are mutually exclusive or logically operated via mutual exclusion or logic gates 401-2. The pulse signal pw2 is generated later, and the pulse signals pwi, PW2, . . . PW2N+1 as shown in FIG. 5 are generated. The 〇 counter 233 counts the clock signal CK generated by the ring oscillator 231, thereby The N+1 bit signal so~SN is generated. As shown in FIG. 计数器, the counter 233 includes a plurality of flip-flops 601, a plurality of flip-flops 6〇3, and an AND GATE 602. The counting period of the counter 233 will be affected, that is, the period width of the signals S0 SN SN will be affected. The flip flop 6 〇 3 is used to generate the N+1 bit signals S0 SN SN. The waveforms of the signals S0 SN SN are as shown in FIG. 7 . The input terminal of the gate 602 receives the N+丨 bit signal s〇~SN, and its output terminal is connected to the set terminal (SEL) of all the flip-flops 603. When all signals SO ' S1 ... SN are When it is logic high (L〇gic HIGH), the AND gate 602 maintains the signals S0, S1 ... SN in a logic high state, as shown in Fig. 7, the counter 233 stops the wave. The multiplexer 234 is composed of 2N+1 switches ^+丨 and Ν+ι inverters 801~0~801-N, as shown in Fig. 8. Each switch is composed of a plurality of transmission gates 803, for example. Of course, the embodiment is not limited thereto. The input terminals of the inverters 801 are connected to the signals s 〇 SN SN and then output s 〇 By S1B ... SNB. 13 200913492 rzuu/-uwo-i w 23955twf.doc/n The input end of the switch 802_1 receives the pulse signal PWl, and the signal S0~SN determines whether the pulse signal PW1 is output as pw_OUT. The input end of the switch 802_2 receives the pulse signal PW2, and the signal S0~SN determines whether to let The output of the pulse signal PW1 is PW_OUT, and so on, the output pulse signal PW__OUT is selected as the pulse signal PW1 or PW2 or ... PW2N+I as shown in the timing diagram of Fig. 9. For example, when SO, S1...SN are both logic low, The pulse signal PWJDUT is the pulse signal PW, and the last stable output pulse signal is PW2N+1. The duty cycle of the pulse signal needs to be between the upper limit DMAX < 100% and the lower limit DMIN = 〇〇 Figure 10 ~ Figure 12 shows the other of the present invention For example, those skilled in the art will recognize that the invention is not limited thereto. The power supply system 1000 includes: a voltage conversion module 1010, a selector 1020, a soft start circuit 1〇3〇, enable signal generator 1040, PWM generator and the enable signal generating 1〇41 1042 fast. The soft start circuit 1〇30 includes a counter 1〇31, a multiplexer 1032, a pulse generator 1〇33, and a ring oscillator 1〇34. An input of the voltage conversion module 1010 is coupled to an output of the selector 1020. Its voltage dividing point N1 is connected to the negative input of the enable signal generator 1〇4〇 and one of the inputs of the PWM generator. The selector 1〇2〇 selects the pulse signal output from the soft start circuit 1030 or the pulse width modulation signal generated by the pwM generator ι〇4ΐ. The signal selected by the selector 1 〇 2 ’ 'voltage conversion module 1010 converts the voltage source VDD1 to the output voltage source VDD2. The positive input terminal of the enable signal generator 1〇42 is connected to the reference voltage VREF, and the negative input terminal thereof is connected to the voltage dividing point of the voltage conversion module 1〇1〇 200913492 P2007-006-TW 23955twf.doc/n enable signal The output of the generator 1042 generates an enable signal EN and is transmitted to the input of one of the loop-opening & The input end of the pwM generating benefit 1041 is connected to the output % of the enable signal generator, and the other input is connected to the voltage dividing point N1 of the power conversion module, and the output end thereof is connected to the input end of the selector 1〇20. The voltage conversion module 1〇1〇 includes: a transistor 1011, an inductor 1〇12, a diode 1013, a capacitor 1014, and two resistors 〇15 and 1〇16. The source of the transistor 1011 is connected to the voltage source VDD1, the gate of the transistor ion is connected to the selector 1020, and the drain of the transistor ΐ〇π is connected to one end of the inductor 1〇12 and the cathode of the diode 1013. The anode of the diode 1013 is connected to the ground terminal, and the cathode is connected to the first end of the inductor 1012 and the anode terminal of the transistor 1〇11. The first end of the inductor 1〇12 is connected to the drain terminal of the transistor 1011 and the cathode of the diode 1〇13, and the first end is connected to the first end of the capacitor and the first end of the resistor 丨〇15. A first end of the capacitor 1014 is coupled to the first end of the resistor 1015 and the second end of the inductor 1012 and provides the output voltage source V]) D2. The second end of capacitor 1〇14 is connected to ground. The first end of the resistor 1015 is connected to the output voltage source VDD2, and the second end thereof is connected to the voltage dividing point N1. The first end of the resistor 1〇16 is connected to the voltage dividing point N1' and the second end is connected to the ground terminal. The soft start circuit 1030 receives the enable signal EN. The ring oscillator 1034 generates clock signals CK, CK1 ... CK2N+1. The clock signal CK is input to the counter 1031. The clock signals ck, CK1 ... CK2N+1 are input to the pulse generator 1033. The counter 1〇31 generates the signal s〇~SN, and the pulse product 15 200913492 23955twf.doc/nw takes the generator 1033 to generate the pulse signals PWl, PW2........PW2n+i and is selected by the multiplexer 1032. Let the pulse signal PW1 or PW2 or ... PW2N+1 be output to PW_OUT. Figure 11 is a circuit block diagram of a power supply system of another embodiment. The % source supply system 11 in this embodiment includes: a voltage conversion mode, a group mo, a soft start circuit 1120, an enable generator 1140, and a voltage regulation cry 1130. According to the pulse signal generated by the soft start circuit 1120 or the bias modulation signal generated by the voltage regulator 1130, the voltage conversion module m〇 converts the power source VDD1 into the required wheel voltage source VDD2. After the output power source VDD2 is stabilized, the voltage conversion module lu〇 internal ^ crystal = 1111 will be fully open. At this time, the voltage adjustment H 113G will adjust the closed circuit of the transistor (1) ^ to convert the source VDD1 into an output. Voltage source VDD2. The enable generator 1140 compares the reference voltage VREF2 = and compares the result as the enable signal EN to input to the soft node „30. Compare the reference power EF1 and the node voltage sub-comparison result as a bias modulation signal to input the internal 1110 The gate of the transistor 1112. The voltage conversion module U1G includes: the transistors 1111 and 1112, the resistors 1113 and 1114 and the Raymond 曰μ pressure 湄VDrn, pg package day 1111 source is connected to the electric =, force The extreme receiving soft-start circuit 1120 generates == the extreme is connected to the transistor output 2 = „, the day-to-day source is connected to the drain of the transistor 1111, and the open-end receiving regulator 113 is connected. To the tempo of the resistor 1113, _, the brother of the 汲 3, the voltage source VDD2 and the power 16 200913492 ^wv-υυο-ι w 23955twf.doc/n the first end of the capacity 1115. The first end of the resistor 1113 is connected to the 汲 terminal of the input 1112, and the second end is connected to the positive input terminal of the resistor (1) diode 2 = the second power 130 and the enabling terminal. The first end of the capacitor 1115 is smashed to the second side of the ground--the * 鸲 连接 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电* r The second end of the resistor 1114 (ie, the ground terminal). The brother-train is connected to the electrical soft start circuit 1120 including: a counter U2l, a multiplex pulse generator 1123 and a ring oscillator B 1124. 〇〇2, a replacement module Coffee, _ turn ^ double card system power conversion circuit 1230 = package i, ^ i24G ° digital control type power conversion circuit (four) and count ^; = 1231, pulse generation please 2, multiplexer (four) circuit 123G generated The pulse signal is pressed by the ratchet/buffer state 1220, and then transmitted to the electric module mo by the buffer 1220. The party controls the pulse signal #bPW-ουτ' voltage conversion VDD2. The electric dust source VDD1 is converted into the required The output voltage source includes a conversion mode! and the voltage dividing point N1 of 121〇 is connected to the selection mode 17 200913492 A ... 4 ” 23955 twf.d〇c/n signal generator 1240. Choose 掇 十产味女 "式(四)船μ式面生11 124Q controllable digits k-type power conversion circuit 123〇################ For example, select mode signal-and hold signal to control digital-controlled power conversion circuit贱
+曰=轉換模組咖包括:電感i2u、二極體⑽、 咖之第-媸、= 兩個電阻1215及1216。電感 ==電屋源VDm,其第二端連接二極體 1212之險極與電晶體1213之汲極端。 雷咸之陽極連接至電晶體1213之没極端以及 I. —端,其陰極則連接至電容1214、電阻1215 之第一编與輸出電壓源VDD2。 缕衡ΐ?Π3之源極端連接至接地端,閘極端連接至 山、_ 之⑥出端,汲極端則連接至電感1211之第二 、以及一極體1212之陽極端。 電容1214之第—端連接至電阻1215之第—端、輸出 :要源VDD2與二極體1212之陰極端,其第二端連接至 接地端。 _電阻1215之第—端連接至電容1214之第一端與二極 體1212之陰極端以及輸出電壓源VDD2。電阻1215之第 =端即為分壓點N1。分壓點N1連接至選擇模式信號產生 器1240之取樣保持電路1243之輸入端。電阻1216之第一 端也為分壓點N1 ’其第二端則連接至接地端。 18 200913492 w 23955twf.doc/n /在數位控制式電源轉換電路123〇中,計數器!说可 在上數或往下數。當輪出電壓源_2比規範電壓值低時, 則计數$ 1233往上數,脈衝信號PW—OUT之脈衝寬度隨 ,間遞增(當,然有其上限,上限必須小於⑽%,比如,建 議值,90%)。當輸出電壓源_2比規範電壓值高時,則 汁數益1233往下數’脈衝信號PW—OUT之脈衝寬度隨時 間遞減(當然有其下限’比如下限為〇%)。計數器1233是 〇 往亡數或往下數乃是由設定信號SEL所控制。比如,當選 擇杈式信號產生器1240之設定信號SEL為邏輯低時,計 ^器1233為往下數。當選擇模式信號產生器124G之設定 信號SEL為邏輯高時,計數器1233為往上數。 、此外,選擇模式信號產生器1240之保持信號h〇ld 可決定計數H 1233之工作狀態。#選擇模式信號產生哭 1240之保持信號H0LD為邏輯低時,計數器1233處於^ 常工作模式。當選擇模式信號產生器124〇之保持信號 HOLD為邏輯高時’計數器咖為停止狀態。如此^ 制计數态1233之狀態,進而控制多工器1233所輪出之脈 衝信號PW_〇UT。 選擇模式信號產生器1240包括:比較器1241、1242、 1244,取樣保持電路1243與互斥或閘1245。取樣保持電 路1243之第一輸入端連接至電壓轉換模組1210之分壓點 N1,其弟—輸入端則接收時脈信號ck,其輸出端連接至 比較器1241之負輸入端與比較器1242之兩正輸入端。 比車父盗1241之正輸入端連接參考電壓VREF,比較器 19 200913492 I I l w 23955twf.d〇c/n 1241之負輸入端連接取樣保持電路1243之輪出端,其輸 出端會輸出設定SEL信號至計數器1234。 n 比較器1242之一正輸入端與1244之―輸入端皆連接 至比較器1241之負輸入端與取樣保持電路1243之輸出 端二比較器1242之負輸入端連接至參考電壓vrefi。4比 較器1244之負輸入端連接參考電壓VREF2。比較器DC 與1244之兩輸出端分別連接至互斥或閉1245之兩輸入端。 互斥或閘I245之兩輸入端連接至比較器m2與⑽ 之輸出端,而其輸出端則輸出保持信號h〇ld至計 1234。當輸出電壓源v舰接近額定電堡時,透過保: 之個,脈衝信號pw—⑽之責任週期將_ 為簡化起見’圖10〜圖12之軟啟動電路與數位 電源轉換電路之詳細操作原理相同或相似於第—實 之工作原理,在此不再魏。但是均组意軟 =位控制式電源轉換電路中之多工器其產俨: =需介於上〜賴與下限= ^ 透過圖2及圖10〜圖12之架構原理,產生出— 而使用外部電容之軟啟動電路機制。 綜上所述’本發明上述實關巾,由於未使 生脈衝寬度調變信號,可節省外部電容元件與2 =產 此外,因敕啟動電路機制乃是數位電路,是、二 在較低的電壓源(如lv)以下。 故疋以此夠工作 以 雖然本發明已以數個實施例揭露如上,然其並非用 20 200913492 λ ι-\j\jkj-ι w 23955twf.doc/n 限定本發明,任何所屬技術領域中具有通常知識者,在不 脫離本發明之精神和範圍内,當可作些許之更動與潤飾, 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 圖1(a)與(b)是習知之一種軟啟動電路的電路圖與其 f) 產生之責任週期波形圖。 ' 圖2是顯示根據本發明一實施例之電源供應 電 路方塊圖。 圖3A與圖3B顯示環形振盪器之架構示意圖。 圖4顯示脈衝產生器之電路圖。 圖5顯示環形振靈器與脈衝產生器所產生之時脈信號 與脈衝信號。 圖6顯示計數器之電路圖。 〇 ® 7顯示計數器所產生之N+1位元信號波形。 圖8顯示多工器内部之示意圖。 圖9顯示多工ϋ所產生之脈衝信號波形。 圖10~圖12顯示本發明之其他實施例。 102 :電阻 】〇5 :比較器 220 =選擇器 【主要元件符號說明】 101、103 :電晶體 104 :電容 210 :電壓轉換模組 21 200913492 P2007-0U6-1W 23955twf.doc/n 241 : PWM產生器 211 :電感 213 :電晶體 215、216 :電阻 232 :脈衝產生器 234 :多工器 305 :反向器 230 :軟啟動電路 242 :致能信號產生器 212 :二極體 214 :電容+曰=Conversion module coffee includes: inductor i2u, diode (10), coffee first-媸, = two resistors 1215 and 1216. Inductance == electric house source VDm, the second end of which connects the dangerous pole of the diode 1212 and the pole end of the transistor 1213. The anode of the Thunderbolt is connected to the terminal of the transistor 1213 and the I. terminal, and the cathode is connected to the first winding of the capacitor 1214 and the resistor 1215 and the output voltage source VDD2. The source of the 缕3ΐ3 is connected to the ground terminal, the gate terminal is connected to the mountain, the 6th terminal of the _, and the 汲 terminal is connected to the second end of the inductor 1211 and the anode terminal of the pole body 1212. The first end of the capacitor 1214 is connected to the first end of the resistor 1215, the output is the cathode end of the source VDD2 and the diode 1212, and the second end is connected to the ground. The first terminal of the resistor 1215 is connected to the first terminal of the capacitor 1214 and the cathode terminal of the diode 1212 and the output voltage source VDD2. The = terminal of the resistor 1215 is the voltage dividing point N1. The voltage dividing point N1 is connected to the input of the sample and hold circuit 1243 of the selection mode signal generator 1240. The first end of the resistor 1216 is also the voltage dividing point N1' and the second end is connected to the ground. 18 200913492 w 23955twf.doc/n / In the digitally controlled power conversion circuit 123〇, the counter! Say it can be counted up or down. When the output voltage source _2 is lower than the specification voltage value, the count is up to 1233, and the pulse width of the pulse signal PW_OUT increases with time (when there is an upper limit, the upper limit must be less than (10)%, such as , recommended value, 90%). When the output voltage source _2 is higher than the specification voltage value, the pulse width of the number of pulses 1233 down the pulse signal PW_OUT is decremented over time (of course, the lower limit thereof is, for example, the lower limit is 〇%). The counter 1233 is 往 the number of deaths or countdowns is controlled by the setting signal SEL. For example, when the setting signal SEL of the selected rake signal generator 1240 is logic low, the counter 1233 is counted down. When the setting signal SEL of the selection mode signal generator 124G is logic high, the counter 1233 is counted up. In addition, the hold signal h〇ld of the selection mode signal generator 1240 can determine the operating state of the count H 1233. #Select mode signal generation crying When the hold signal H0LD of the 1240 is logic low, the counter 1233 is in the normal operation mode. When the hold signal HOLD of the mode signal generator 124 is selected to be logic high, the counter is in a stopped state. Thus, the state of the count state 1233 is controlled, and the pulse signal PW_〇UT rotated by the multiplexer 1233 is controlled. The select mode signal generator 1240 includes comparators 1241, 1242, 1244, sample hold circuit 1243 and a mutex or gate 1245. The first input terminal of the sample and hold circuit 1243 is connected to the voltage dividing point N1 of the voltage conversion module 1210, and the input terminal receives the clock signal ck, and the output terminal thereof is connected to the negative input terminal of the comparator 1241 and the comparator 1242. The two positive inputs. The reference voltage VREF is connected to the positive input terminal of the car thief 1241, and the negative input terminal of the comparator 19 200913492 II lw 23955 twf.d〇c/n 1241 is connected to the wheel-out terminal of the sample-and-hold circuit 1243, and the output terminal outputs a set SEL signal. To counter 1234. n The positive input of the comparator 1242 and the input of the 1244 are both connected to the negative input of the comparator 1241 and the output of the sample and hold circuit 1243 and the negative input of the comparator 1242 are connected to the reference voltage vrefi. The negative input of the comparator 1244 is connected to the reference voltage VREF2. The two outputs of the comparator DC and 1244 are respectively connected to the two inputs of the mutually exclusive or closed 1245. The two inputs of the exclusive or gate I245 are connected to the outputs of the comparators m2 and (10), while the outputs thereof output the hold signal h〇ld to the count 1234. When the output voltage source v ship is close to the rated electric castle, the duty cycle of the pulse signal pw_(10) will be _ for the sake of simplicity. The detailed operation of the soft start circuit and the digital power conversion circuit of Fig. 10 to Fig. 12 The principle is the same or similar to the working principle of the first, and it is no longer Wei. However, the group is soft = the multiplexer in the bit-controlled power conversion circuit is produced: = need to be between ~ lag and lower limit = ^ through the architectural principle of Figure 2 and Figure 10 ~ Figure 12, and use - and use Soft-start circuit mechanism for external capacitors. In summary, the above-mentioned actual closing towel of the present invention can save external capacitive components and 2 = production because the raw pulse width modulation signal is not adjusted, because the starting circuit mechanism is a digital circuit, and the second and the second are lower. Below the voltage source (such as lv). Therefore, although the present invention has been disclosed above in several embodiments, it is not limited to 20 200913492 λ ι-\j\jkj-ι w 23955 twf.doc/n, and has any technical field in the art. In general, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 (a) and (b) are circuit diagrams of a conventional soft start circuit and f) generated duty cycle waveform diagrams. Figure 2 is a block diagram showing a power supply circuit in accordance with an embodiment of the present invention. 3A and 3B are schematic diagrams showing the architecture of a ring oscillator. Figure 4 shows a circuit diagram of the pulse generator. Figure 5 shows the clock and pulse signals generated by the ring oscillator and pulse generator. Figure 6 shows a circuit diagram of the counter. 〇 ® 7 displays the N+1 bit signal waveform generated by the counter. Figure 8 shows a schematic diagram of the interior of the multiplexer. Figure 9 shows the pulse signal waveform generated by the multiplexer. 10 to 12 show other embodiments of the present invention. 102: Resistor】〇5: Comparator 220=Selector [Main component symbol description] 101, 103: Transistor 104: Capacitor 210: Voltage conversion module 21 200913492 P2007-0U6-1W 23955twf.doc/n 241 : PWM generation 211: Inductor 213: transistor 215, 216: resistor 232: pulse generator 234: multiplexer 305: inverter 230: soft start circuit 242: enable signal generator 212: diode 214: capacitor
231 :環形振盪器 233 :計數器 301-304 :電晶體 306、307 :延遲單元 311 1〜311 2N :差動訊號輸出反相器 401 1〜401 2N+1 :互斥或邏輯閘231: Ring oscillator 233: Counter 301-304: transistor 306, 307: delay unit 311 1 to 311 2N: differential signal output inverter 401 1 to 401 2N+1 : mutual exclusion or logic gate
60卜603 :正反器 801_0〜801_N :反相器 803 :傳輸閘 1010 :電壓轉換模組 1030 :軟啟動電路 1041 : PWM產生器 1011 :電晶體 1013 :二極體 1015、1016 :電阻 1032 :多工器 1034 :環形振盪器 1110 :電壓轉換模組 1140 :致能產生器 1111、1112 :電晶體 602 :及閘 802_1 〜802_2N+1 :開關 1000 :電源供應系統 1020 :選擇器 1040 :致能信號產生器 1042 :致能信號產生器 1012 :電感 1014 :電容 1031 :計數器 1033 :脈衝產生器 1100 :電源供應系統 1120 :軟啟動電路 1130 :電壓調節器 1113、1114 :電阻 22 200913492 rzuu/-υυο-ι w 23955twf.doc/n 1115 :電容 1121 計數器 1122 :多工器 1123 脈衝產生器 1124 :環形振盪器 1200 電源供應糸統 1210 :電壓轉換模組 1220 缓衝器 1230 :數位控制式電源轉換電路 1240 :選擇模式信號產生器 1211 :電感 1212 二極體 1213 :電晶體 1214 電容 1215、1216 ··電阻 1231 環形振盪器 1232 :脈衝產生器 1233 多工器 1234 :計數器 1245 互斥或閘 1241、1242、1244 :比較器 1243 :取樣保持電路 ί. 2360 603: flip-flop 801_0~801_N: inverter 803: transmission gate 1010: voltage conversion module 1030: soft-start circuit 1041: PWM generator 1011: transistor 1013: diode 1015, 1016: resistor 1032: Multiplexer 1034: Ring oscillator 1110: Voltage conversion module 1140: Enable generators 1111, 1112: Transistor 602: and Gates 802_1 to 802_2N+1: Switch 1000: Power supply system 1020: Selector 1040: Enable Signal generator 1042: Enable signal generator 1012: Inductance 1014: Capacitor 1031: Counter 1033: Pulse generator 1100: Power supply system 1120: Soft start circuit 1130: Voltage regulator 1113, 1114: Resistance 22 200913492 rzuu/-υυο -ι w 23955twf.doc/n 1115 : Capacitor 1121 Counter 1122 : Multiplexer 1123 Pulse Generator 1124 : Ring Oscillator 1200 Power Supply System 1210 : Voltage Conversion Module 1220 Buffer 1230 : Digitally Controlled Power Conversion Circuit 1240: Select mode signal generator 1211: Inductor 1212 Diode 1213: Transistor 1214 Capacitor 1215, 1216 · Resistor 1231 Ring oscillator 1232: Pulse generator 1233 multiplexer 12 34: Counter 1245 Mutex or Gate 1241, 1242, 1244: Comparator 1243: Sample and Hold Circuit ί. 23