200913247 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種轉換光影像為電訊號之半導體裝置，尤其 係關於一種影像感測器。影像感測器大致被分類為電荷耦合裝置 (charge coupled device ; CCD)影像感測器或互補金屬氧化半導 體（complementary metal oxide semiconductor ; CMOS)影像感測 器（CMOS image sensor ; CIS )。 【先前技術】 衫像感測器中，發光一極體通常係使用離子植入形成於具有 電晶體電路之基板中。為了增加晝素數目且不增加晶片尺寸，發 光二極體之尺寸越來越減少，光接收部之區域也減少，從而影像 品質降低。 此外，因為堆疊高度未如同光接收部之區域減少的一樣多， 所以入射至光接收部之光子數也由於絲散而減少，稱為艾瑞盤 (airy disk )。 作為克服此限_—種選擇，#界已經_#試使用非晶石夕 (η ’ Si)形成發^二極體，或者形成讀出電路於々基板中， 以及使用例如晶_晶圓（讀⑽讀㈣接合加麵）方法 形成發光二極齡如電路上（稱為三維咖⑨―丨；則 影像感測ϋ )。發光二極體透過金屬線連接讀出電路。 ‘、而依照自知技術，制軸彳製程當溝槽獅成並且隔離 200913247 層被形成料彡鱗-單元麵之發光二極料，侧製程中發光 二極體表面可能產生缺陷，這樣導致暗電流 ’、間依照習知技術，當發光二極體之表面電壓由於入射光 ，降低時’縣感測部之表面霞也同時降低。此後，當轉移電 (nsfertransistor·) τχ被打職後被關閉時，轉移電晶體之 :極和祕之1壓變得彼此之電錄值透過驅動電晶 旦被放大。錢習知技術’因為轉移電晶體之雜和祕均被大 ’所以㈣電荷分享（eharge sharing)現象。當 ^何刀子現象出购’輪出影像之靈敏度降低並且可能產生影像 錯誤。 此外依照習知技術，因為光電荷並雜快地在發光二極體 和讀出電路之間移動’所以暗電流被產生，或者飽和度和靈敏度 被降低。 【發明内容】 本發明實施例提供—種影像制肢其製造方法，透過雜質 植入形成裝置隔離區域以隔離每—單元畫素之就二極體，可解 決暗電流雜，同時增加填充因子（謝輕）。 上實把例還提供-種影像感測器及其製造方法，可抑制電荷分 享現象之出現，同時增加填充因子。 實施例還提供—種影像❹in及其製造方法，透過提供發光 極體和4電路之’光電狀快辆動路徑而最小化暗電流 200913247 來源，並且可抑獅和度和$敏度之降低。 -個實施例中，影像感測器可包含：層間介電層，位於包含 項出電路之第-基板± ;紐層間介電層以連 =此線物爾—單咖崎：料刪，位於層 曰"電層上，發光二極體，位於晶狀半導體層内部，發光二極體 電連接線路之職線路；以及包含導電㈣之裝置隔離區域，此 f置隔離區顧提供於晶狀轉體勒部，這樣發光二極體依照 單元晝素被分離。 另-實施财，劍減·之製造方法包含：形 於第-基板上；形成賴介電層於包含讀出電路之第—基板上； 形成連接層間介電層之讀出電路之線路；準備包含晶狀半導體層 之第二基板；形成發光二極體於晶狀半導體層内部；植入導電^ 質至晶狀半導體層内，以形成裝麵離區域，這樣發光二極體依 照單元晝素被分離；接合第—基板和第二基板，這樣第一美板之 :: 電連接晶狀半導體層之發光二極體之對應發光二極體;以及 /月除弟一基板之一部分，這樣晶狀半導體層保持於 、 、步一暴板上。 一或多個實施例之細節在附圖和以下描述中加以蒽明 卜 域之技術人S從實施方式、圖式以及申請專·圍中軸 = 其他特徵。 … 【實施方式】 現在結合附圖依照實施例描述影像感測器之製造方、去 200913247 施例。 當術^之上、t上方或 層、區域、圖案或結構時，被理解為❹=本文中時，當指 直接地位於另—層或結構之上，或介人二二圖案或結構可 區域、圖案或結構時，1"或下方"用於本文中時，當指層、 地位於另目_構可直接 出現。^歲下’或介人層、區域、圖輯結構也可以 :第11圖」所示係為實施例之影像感測器之剖視圖。 月多考S 11圖」’影像感測器可包含：層間介電層160,位 於包含讀出電路120之第一基板勘上；線路15〇，通過層間介電 f⑽以連接讀出魏12〇，線路15〇係為每一單元晝素而形成； 曰曰狀半導體層20G’位於包含線路15()之層間介電層⑽上；發光 極體230 ’位於晶狀半導體層2〇〇内部，發光二極體2邓其中之 電連接線路150 ;以及’包含導電雜質之裝置隔離區域24〇，裝 置隔離區域形成於晶狀半導體層2〇〇内部，這樣發光二極體2如 依照单元晝素被分離。 第一基板100之讀出電路120可包含：電氣接面區域14〇,形 成於第一基板100中；以及第一導電類型連接區域147,連接電氣 接面區域140上之線路150。 包含第一雜質區域210 (η型）和第二雜質區域220 (p型） 200913247 之發光二極體230可形成於晶狀半導體層2〇〇内部。 裝置隔離區域240可被放置於發光二極體23〇 一侧。—個實 施例中’裝置隔離區域240可由高濃度p型雜質p+形成。 包含第一溝槽253之第一鈍化層250可被放置於發光二極體 230上。此外，連接發光二極體230之上部電極260可被玫置於發 光二極體230之上，並且透過第一溝槽接觸發光二極體。上部電 極260可透過發光二極體230邊緣處之第一溝槽253被提供於部 分發光二極體230上，這樣發光二極體之光接收區域可被確保盡 可能多。 第二鈍化層270可被放置於發光二極體230和上部電極260 上。彩色濾光片280可被放置於對應發光二極體230之部分第二 鈍化層上。 依照實施例，發光二極體230可被形成於晶狀半導體層2〇〇 中。因此，在發光二極體230在讀出電路120上之位置採用三維 影像感測器’填充因子可被增加。此外，因為發光二極體230形 成於晶狀半導體層200之内部，發光二極體230之缺陷可被減少。 此外’因為用於為每一單元畫素隔離發光二極體230之裝置 隔離區域240可透過植入p型雜質而被形成，發光二極體内部產 生的缺陷可被減少，從而暗電流可被抑制。 依照實施例，裝置被設計為轉移電晶體Tx之源極和汲極之間 存在電位差，這樣’光電荷（photocharge)可被完全傾印。因此， 10 200913247 當發光二極體產生的光電荷被傾印轉動擴散區鱗，輸出 的靈敏度可被增加。 就是說’電氣接面區域14G形成於第-基板觸中讀出電路 ⑽之形成處’以允許在轉移電晶體Τχ i2i 一側之源極和沒極之 間產生電位差，這樣光電荷可完全被傾印。一個實施例中，讀出 電路⑽可包含轉移電晶體Τχ⑵、麵電晶體办123、驅動電 晶體Dx 125以及選擇電晶體Sx 127。 詳細描述一實施例之光電荷之傾印結構。 電氣接面區域14G可包含形成於第二導電類型井⑷（或第二 導電類型蟲晶層（圖中未表示））上之第—導電類型離子植入層 143，以及形成於第—導電類型離子植人層143上之第二導電類^ 離子植入層145。例如，電氣接面區域⑽可為pN接面或脈 接面，但並非限制於此。 浮動擴散區域FD 131之節點係為N+接面，電氣接面區域 (PNP接φ ) 140與之不同’係為電氣接面區域14()並且應用電壓 未完全被傳送至此，電氣接面區域14〇在預定電壓時爽止。此電 壓被稱為釘插電廢（pinning v〇ltage)’取決於第二導電類型離子植 入層（P0 ϋ域）145和第-導電類型離子植人層143 特別地，發光二極體230產生之電子移動至電氣接面^域 140，並且被傳送至浮動擴散區域FD 131之節點，當轉移電晶體 Tx 121被打開時被轉換為電壓。 11 200913247 因為電氣接面區域140之最大電壓值變為釘插電壓，浮動擴 政區域FD 131之郎點之最大電壓值變為重設電晶體取123之閥 值電壓Vth，透過植入電位差於轉移電晶體丁乂 121之源極和汲極 之間aa片上部中發光一極體230產生的電子可完全被傾印至浮 動擴散區域FD 131之節點，沒有電荷被分享。 依照一實施例，就是說，於四電晶體主動畫素感測器（active pixel Sensor ; APS)重設作業期間，Ρ0/Ν_/ρ·井接面而非^^十/卜井 接面形成於第一基板1〇〇中，以允許+電壓被應用至ρ〇/Ν_/ρ_井接 面之第一導電類型離子植入層143,以及允許接地電壓被應用至第 二導電類型井141，這樣夾止在預定電壓時被產生於ρ〇/Ν_/ρ井雙 接面處或者更夕在雙載子接面電晶體（bipolar junction transistor ; BJT)結構中。這被稱為釘插電壓。因此，轉移電晶體Τχ⑵之 開/關作業期間，電位差產生於轉移電晶體Txm之源極和沒極 之間以抑制電荷分享現象。 因此，與習知技術中簡單使用Ν+接面連接發光二極體的例子 不同，可避免例如飽和度降低以及靈敏度降低等限制。 ±接下來，第一導電_連接區域147可形成於發光二極體和 Τ出電路之間以提供光電荷之快速運祕徑，這樣暗電流來源被 最小化，飽和度降低和靈敏度降低可被抑制。 為此目的’用於歐姆接觸之第—導電麵連接區域⑷可形 成；電氣接面區域M0上。其間，為了抑制第一導電類型連接區 12 200913247 戍7 路來源’第—導電類型連接區域w之寬度可被最BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for converting an optical image into an electrical signal, and more particularly to an image sensor. The image sensor is roughly classified into a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor (CIS). [Prior Art] In the shirt image sensor, the light-emitting body is usually formed in a substrate having a transistor circuit using ion implantation. In order to increase the number of halogens without increasing the size of the wafer, the size of the light-emitting diode is further reduced, and the area of the light receiving portion is also reduced, so that the image quality is lowered. Further, since the stack height is not as much as the area of the light receiving portion, the number of photons incident on the light receiving portion is also reduced due to the scattering, which is called an airy disk. As a way to overcome this limitation, #界的_# tries to use amorphous stellite (η 'Si) to form a diode, or to form a readout circuit in the germanium substrate, and to use, for example, a crystal wafer ( Read (10) read (four) joint plus face) method to form a light-emitting diode such as the circuit (called three-dimensional coffee 9 - 丨; then image sensing ϋ). The light emitting diode is connected to the readout circuit through a metal wire. 'In accordance with the self-knowledge technology, the shaft 彳 process is formed as a grooved lion and the 200913247 layer is formed into a scale-cell surface light-emitting diode. The surface of the light-emitting diode in the side process may be defective, which may result in darkness. According to the conventional technique, when the surface voltage of the light-emitting diode is lowered due to the incident light, the surface of the county sensing portion is simultaneously lowered. Thereafter, when the transfer power (nsfertransistor·) τχ is turned off after being employed, the transfer of the transistor: the polarity of the voltage and the voltage of each other becomes the ohmic value of each other through the drive electric crystal. The money-sharing technique 'because the heterogeneity and the secret of the transfer transistor are large', so (4) the phenomenon of charge sharing (eharge sharing). When the knives are purchased, the sensitivity of the rounded image is reduced and an image error may occur. Further, according to the conventional technique, a dark current is generated, or the saturation and sensitivity are lowered because light charges are moved and mixed between the light-emitting diode and the readout circuit. SUMMARY OF THE INVENTION Embodiments of the present invention provide a method for manufacturing an image limb, which is formed by isolating impurities to form a device isolation region to isolate a diode of each unit pixel, thereby solving dark current impurities and increasing a fill factor ( Thank you lightly). The above example also provides an image sensor and a method of manufacturing the same, which suppresses the occurrence of charge sharing and increases the fill factor. The embodiment also provides an image ❹in and a method of fabricating the same that minimizes the dark current 200913247 source by providing a 'photoelectric fast moving path of the illuminating body and the four circuits, and can reduce the lion and degree and the sensitivity. In an embodiment, the image sensor may comprise: an interlayer dielectric layer located on the first substrate of the item-containing circuit; the dielectric layer of the interlayer layer is connected to the line-- On the electrical layer, the light-emitting diode is located inside the crystalline semiconductor layer, the working line of the light-emitting diode electrical connection line; and the isolation region of the device containing the conductive (four), which is provided in the crystalline region The body is turned so that the light-emitting diodes are separated according to the unit element. In addition, the manufacturing method of the method of manufacturing, the method of manufacturing the method comprises: forming on the first substrate; forming a dielectric layer on the first substrate including the readout circuit; forming a circuit for connecting the readout circuit of the interlayer dielectric layer; preparing a second substrate comprising a crystalline semiconductor layer; forming a light emitting diode inside the crystalline semiconductor layer; implanting a conductive material into the crystalline semiconductor layer to form a surface away from the region, such that the light emitting diode is in accordance with the unit Separating; bonding the first substrate and the second substrate, such that the first beautiful plate:: the corresponding light emitting diode of the light emitting diode electrically connected to the crystalline semiconductor layer; and the portion of the substrate The semiconductor layer is held on the step board. The details of one or more embodiments are set forth in the accompanying drawings and the description below. [Embodiment] The manufacturer of the image sensor will now be described in accordance with an embodiment with reference to the accompanying drawings, and the example of 200913247 is applied. When it is above, above t, or layer, region, pattern or structure, it is understood as ❹=in this case, when the finger is directly on the other layer or structure, or the second or second pattern or structure can be , pattern or structure, when 1" or below" is used in this article, when the finger layer, the ground is located in another frame, it can appear directly. ^下下' or intervening layer, region, and map structure can also be: Figure 11 is a cross-sectional view of the image sensor of the embodiment. The monthly image may include: an interlayer dielectric layer 160 located on the first substrate including the readout circuit 120; and a line 15〇 connected by the interlayer dielectric f(10) to read the Wei 12〇 The line 15 is formed for each unit of the halogen; the braided semiconductor layer 20G' is located on the interlayer dielectric layer (10) including the line 15 (); the light emitting body 230' is located inside the crystalline semiconductor layer 2, The light-emitting diode 2 is electrically connected to the circuit 150; and the device isolation region 24〇 containing conductive impurities, and the device isolation region is formed inside the crystalline semiconductor layer 2, such that the light-emitting diode 2 is in accordance with the unit Is separated. The readout circuitry 120 of the first substrate 100 can include an electrical junction region 14A formed in the first substrate 100, and a first conductivity type connection region 147 connecting the circuitry 150 on the electrical junction region 140. The light emitting diode 230 including the first impurity region 210 (n-type) and the second impurity region 220 (p-type) 200913247 may be formed inside the crystalline semiconductor layer 2''. The device isolation region 240 can be placed on one side of the light-emitting diode 23A. In one embodiment, the device isolation region 240 may be formed of a high concentration p-type impurity p+. A first passivation layer 250 including a first trench 253 may be placed on the light emitting diode 230. In addition, the upper electrode 260 connected to the light-emitting diode 230 can be placed on the light-emitting diode 230 and contact the light-emitting diode through the first trench. The upper electrode 260 is provided on the partial light-emitting diode 230 through the first trench 253 at the edge of the light-emitting diode 230, so that the light-receiving area of the light-emitting diode can be ensured as much as possible. The second passivation layer 270 may be placed on the light emitting diode 230 and the upper electrode 260. The color filter 280 can be placed on a portion of the second passivation layer of the corresponding light emitting diode 230. According to an embodiment, the light emitting diode 230 may be formed in the crystalline semiconductor layer 2A. Therefore, a three-dimensional image sensor 'fill factor' can be increased at the position of the light-emitting diode 230 on the readout circuit 120. Further, since the light emitting diode 230 is formed inside the crystalline semiconductor layer 200, defects of the light emitting diode 230 can be reduced. In addition, because the device isolation region 240 for isolating the light-emitting diode 230 for each cell can be formed by implanting p-type impurities, defects generated inside the light-emitting diode can be reduced, so that dark current can be inhibition. According to an embodiment, the device is designed such that there is a potential difference between the source and the drain of the transfer transistor Tx such that the 'photocharge can be completely dumped. Therefore, 10 200913247 when the photocharge generated by the light-emitting diode is dumped and rotated, the sensitivity of the output can be increased. That is, the 'electrical junction region 14G is formed at the formation of the first substrate contact readout circuit (10)' to allow a potential difference between the source and the gate of the transfer transistor Τχ i2i side, so that the photocharge can be completely Dumping. In one embodiment, the readout circuitry (10) can include a transfer transistor (2), a face transistor 123, a drive transistor Dx 125, and a select transistor Sx 127. The photocharged dump structure of an embodiment is described in detail. The electrical junction region 14G may include a first conductivity type ion implantation layer 143 formed on the second conductivity type well (4) (or a second conductivity type insect layer (not shown)), and formed on the first conductivity type The second conductive ion implantation layer 145 on the ion implant layer 143. For example, the electrical junction area (10) may be a pN junction or a nip face, but is not limited thereto. The node of the floating diffusion region FD 131 is an N+ junction, and the electrical junction region (PNP is connected to φ) 140 is different from the electrical junction region 14 () and the applied voltage is not completely transmitted thereto, and the electrical junction region 14爽 Suppressed when the voltage is predetermined. This voltage is referred to as pinning v〇ltage' depending on the second conductivity type ion implantation layer (P0 domain) 145 and the first conductivity type ion implant layer 143, in particular, the light emitting diode 230 The generated electrons move to the electrical junction field 140 and are transferred to the node of the floating diffusion region FD 131, which is converted to a voltage when the transfer transistor Tx 121 is turned on. 11 200913247 Since the maximum voltage value of the electrical junction area 140 becomes the pin insertion voltage, the maximum voltage value of the floating point of the floating expansion area FD 131 becomes the threshold voltage Vth of the reset transistor taken 123, and the penetration potential difference is transferred. The electrons generated by the light-emitting body 230 in the upper portion of the aa sheet between the source and the drain of the transistor D can be completely dumped to the node of the floating diffusion region FD 131, and no charge is shared. According to an embodiment, that is, during the reset operation of the four-crystal active pixel sensor (APS), the Ρ0/Ν_/ρ· well junction is formed instead of the ^^10/b well junction. In the first substrate 1 ,, the first conductivity type ion implantation layer 143 is allowed to be applied to the ρ〇/Ν_/ρ_ well interface, and the ground voltage is allowed to be applied to the second conductivity type well 141. Thus, the pinch is generated at the predetermined voltage and is generated at the double junction of the ρ〇/Ν_/ρ well or even in the bipolar junction transistor (BJT) structure. This is called the pin insertion voltage. Therefore, during the on/off operation of the transfer transistor Τχ(2), a potential difference is generated between the source and the gate of the transfer transistor Txm to suppress the charge sharing phenomenon. Therefore, unlike the conventional example in which the light-emitting diode is simply connected using a Ν+ junction, restrictions such as a decrease in saturation and a decrease in sensitivity can be avoided. ± Next, a first conductive_connecting region 147 may be formed between the light emitting diode and the extraction circuit to provide a fast path of photocharge, such that the dark current source is minimized, the saturation is lowered, and the sensitivity is lowered. inhibition. For this purpose, the first conductive surface connection region (4) for ohmic contact can be formed; the electrical junction region M0. In the meantime, in order to suppress the first conductive type connection region 12 200913247 戍 7 way source 'the first conductive type connection region w width can be the most
Hb、透過如此使用，三維景彡佩測器之暗電流可被降低。 /就疋見’依照一實施例，用n型雜質僅僅局部且大量攙雜接 觸域。卩之相係便概姆_之軸，同時最小化暗訊號。在 大里攙雜i個轉移電晶體（Τχ來源）之例子中，暗訊號可透過石夕 表面搖擺接合而被增加。 第U圖」巾未被轉的參考標號在以下的製造方法中被解 釋。 /吉合「第1圖」、「第2圖」、「第3圖」、「第4圖」、「第5圖」、 「第6圖」、「第7圖」、「第8圖」、「第9圖」、「第ι〇圖」以及「第 11圖」描述影像感測器之製造方法。 請參考「第1圖」’讀出電路U0可形成於第一基板謂上。 定義主動區域和場區域之裳置隔離層110可形成於第一基板 100中。包含電晶體之讀出電路120可形成於第一基板觸之主動 區域上。例如，讀出電路12〇可包含轉移電晶體Τχ 121、重設電 晶體Rx 123、驅動電晶體Dx 125以及選擇電晶體Sx 127。形成電 晶體之閘極之後，包含浮動擴散區域FD 131和各電晶體之源極/ 汲極區域m、135及B7之離子植入區域13〇可被形成。 第-基板KK)上讀出雜m之形成可包含形成電氣接面區 域14〇於第-基板100巾以及形成連接線路ls〇之第一導電類型 連接區域147。 13 200913247 電氣接面區域mo可為PN接面，但並非限制於此。例如，電 氣接面區域140可包含形成於第二導電類型井141(或第二導電類 型遙晶層）上之第-導電類型離子植人層143，以及形成於第一導 電類型離子植入層⑷上之第二導電類型離子植入層145。因此， 電氣接面區域⑽可為「第丨圖」所示之pG (第二導電類型離子 植入層145)/N-(第一導電類型離子植入層143)/p_ (第三導電類型 井H1)接面，但並非限制於此。此外，第一基板1〇〇可為第二導 電類型基板，但並非限制於此。 依照-實施例’電氣接面區域刚可形成於第一基板⑽中 讀出電路120之形成位置’以允許轉移電晶體Txm之源極和汲 極之間產生電位差，這樣光電荷可完全被傾印。 就是說’依照-實施命j ’裝置被設計為轉移電晶體Τχ之源極 和汲極之間存在電位差’這樣綠射完全侧印。例如，透過 使得第-導賴型離子植人層143之攙雜濃度低於浮動擴散區域 FD131之攙雜濃度’裝置可被設計為轉移電晶體Τχ之源極和沒極 之間產生電位差。 接下來，依照-實施例’用於歐姆接觸之第一導電類型連接 區域147可被形成於電氣接面區域接面）14〇之表面上。 例如，用於歐姆接觸之第一導電類型連接區域（Ν+區域）147可 被形成於電氣接面區域（Ρ0/Ν-/Ρ-接面）ho之表面上。第一導電 類型連接區域（Ν+區域）147可被形成穿透第二導電類型離子植 14 200913247 入層145以接觸第—導電類型離子植入層143。 其間’為了抑制第一導電類型連接區域147變為泄露來源， 第-導電類型連接區域147之寬度可被最小化。為此目的，在為 第-金屬接觸151議刻—通孔之後，插检植人（plugimpiant)可 被完成。但是’實施例並非限制於此。例如，離子植入圖案（圖 中未表示）可开/成於第一基板應上，然後第一導電類型連接區 域147可使_子植人_作為離子植人遮罩被形成。 依照-實施例’第-導電類型連接區域147可形成於發光二 極體和4電路12〇之間，以最小化暗電流麵並且抑制飽和度 降低和靈敏度降低。 層間介電層160可形成於第一基板娜上，並且線路15〇可 被形成。線路可包含第—金屬接觸咖、第—金屬i5i、第二金 屬⑸、第三金屬153以及細金屬接觸154，但並非限制於此。 、'、路150彳為每-單元晝素形成以連接發光二極體23〇(將在 下文中描述）與讀出電路12〇，以及轉移發光二極體挪之光電 荷。當連接讀出電路120之線路15〇被形成時，連接周邊電路區 域用於訊號處理之線路17〇也可同時被形成。 線路⑼可由包含金屬、合金以及毅多種導電材料形成。 歹如線路150可由铭、銅、銘或鶴而形成。 、、；請參考「第2圖」，包含晶狀半導體層之第二基板2〇可 被準備。第二基板20可為單晶或多晶石夕基板，並且可為攙雜p型 15 200913247 雜質或η型雜質之基板。晶狀半導體層2〇〇可形成於第二美板 之上。例如，晶狀半導體層200可透過磊晶成長形成於第二基板 20 上。 一土 雖然圖中未表示，氫離子植入層可透過植入氫離子至第二基 板和晶狀轉縣之間的邊相娜成。氮料之植入甚至 可被完成於發光二極體之離子植入之後。 請參考「第3圖」，發光二極體230可形成於晶狀半導體層· 内部。發光二極體230可包含第一雜質區域21〇和第二雜質曰區域 220。 只知例中，弟一雜質區域21〇可透過植入η型雜質至晶狀 半導體層2GG之表面附近的晶狀半導體層之淺層區域内而形 成。第二雜質區域22〇可透職入ρ型雜質至晶狀半導體層· 之深層區域内而形成。-個實施例中，第二雜質區域220可首先 被升ν成’然後第_雜質區域21〇可形成於第二雜質區域上。 第一雜貝區域220和第一雜質區域21〇提供ρΝ接面結構。 明參考「第4圖」’歐姆接觸層2〇5可額外地形成於晶狀半導 體層200之表面處的第一雜質區域210上。歐姆接觸層205可透 過植入间/辰度η型雜質(η+)而形成。歐姆接觸層2〇5可降低發光二 極體230和線路15〇之間的歐姆電阻。下文中，使用發光二極體 230之下歐姆接觸層2〇5被省略的例子加以描述。 睛參考「第5圖」’裝置隔離區域240可形成於晶狀半導體層 16 200913247 200内部’以依照單^畫素分離發光二極體230。裝置隔離區域240 可透過形成軒植人遮罩（圖巾未表示）於晶狀半導體層細上 然後完成離子植人娜成。植人裝置隔祕域·之離子可為高 濃度P獅質。m為裝置齡區域雜騰子植人製程而形 成發光一極體230内產生的缺陷可被減少，因此暗電流特性可 被解決。 明參考「第6圖」，第一基板1〇〇和包含晶狀半導體層2㈨之 第二基板20可被彼此接合。尤其地，第-基才反100和第二基板20 可被彼此接合，這樣，針對單元晝素被分離之發光二極體咖分 別對應線路150其中之一。這樣，在第一基板卿和第二基板2〇 ，此接合之前，接合可透過增加賴催化所接合之表面的表面能 里而7L成。其Μ ’某些實施例中，接合可使用接合介面上放置的 介電層或金屬層而完成以改善接合力。 田第基板100和第二基板20接合時，第四金屬接觸1Ma 和發光二極體230之第一雜質區域210可彼此連接。因此，發光 -極體230產生的光電荷可透過線路⑼被轉移至讀出電路12〇。 尤’、地’透過裝置隔離區域240為每-單元晝素分離之發光 極體230可連接第一基板1〇〇巾為每—單元晝素放置之每一第 四金屬接觸154a。 ’軸圖巾未表示，對於結合氫離子植人層之實施例， 氫離子植入層可透過完成熱處理而被改變為氫氣層。 17 200913247 請參考「第7圖」，第二基板20可被清除，這樣晶狀半導體 層200保持在第一基板1〇〇上。就是說，使用氫氣層（圖中未表 示）作為參考，部分第二基板2〇可使用刀片被清除，發光二極體 230保持於第一基板1⑻上，這樣發光二極體230可被暴露。 因此，包含發光二極體230和裝置隔離區域240之晶狀半導 體層200可保留於第一基板1〇〇上。 請參考「第8圖」’暴露部115暴露周邊區域之部分層間介電 層160和線路170 ’暴露部115可透過清除部分晶狀半導體層2〇〇 而开y成此時，位於晶片外部區域之發光二極體之橫向側面 也可被暴露。Hb, through such use, the dark current of the three-dimensional finder can be reduced. / 疋 ’ ‘In accordance with an embodiment, the n-type impurity is only partially and heavily noisy to the contact domain. The phase of the 卩 is the axis of the _, while minimizing the dark signal. In the case of a large transfer transistor (Τχ source), the dark signal can be increased by the rocky surface of the stone. The reference numerals of the U-shaped "unturned" towel are explained in the following manufacturing methods. /Jihe "1st", "2nd", "3rd", "4th", "5th", "6th", "7th", "8th" , "9th figure", "1st figure" and "11th figure" describe the manufacturing method of an image sensor. Please refer to "Fig. 1". The readout circuit U0 can be formed on the first substrate. A skirt isolation layer 110 defining an active area and a field area may be formed in the first substrate 100. A readout circuit 120 including a transistor can be formed on the active area of the first substrate. For example, the readout circuit 12A may include a transfer transistor Τχ 121, a reset transistor Rx 123, a drive transistor Dx 125, and a selection transistor Sx 127. After the gate of the transistor is formed, the ion implantation region 13A including the floating diffusion region FD 131 and the source/drain regions m, 135 and B7 of the respective transistors can be formed. The formation of the read impurity m on the first substrate KK) may include forming the electrical junction region 14 on the first substrate 100 and forming the first conductive type connection region 147 of the connection line ls. 13 200913247 The electrical junction area mo can be a PN junction, but is not limited to this. For example, the electrical junction region 140 may include a first conductivity type ion implant layer 143 formed on the second conductivity type well 141 (or the second conductivity type telecrystal layer), and an ion implantation layer formed on the first conductivity type. (4) The second conductivity type ion implantation layer 145. Therefore, the electrical junction region (10) may be pG (second conductivity type ion implantation layer 145) / N - (first conductivity type ion implantation layer 143) / p_ (third conductivity type) shown in "Fig. Well H1) is but not limited to this. Further, the first substrate 1A may be a second conductivity type substrate, but is not limited thereto. According to the embodiment, the electrical junction region can be formed in the formation position of the readout circuit 120 in the first substrate (10) to allow a potential difference between the source and the drain of the transfer transistor Txm, so that the photocharge can be completely tilted. Printed. That is to say, the "in accordance with the implementation of the device" is designed such that there is a potential difference between the source and the drain of the transfer transistor, so that the green is completely printed. For example, the device can be designed such that the doping concentration of the first-lead-type ion implanted layer 143 is lower than that of the floating diffusion region FD131. The device can be designed to generate a potential difference between the source and the gate of the transfer transistor. Next, the first conductive type connection region 147 for ohmic contact according to the embodiment can be formed on the surface of the electrical junction region junction 14). For example, a first conductive type connection region (Ν+ region) 147 for ohmic contact may be formed on the surface of the electrical junction region (Ρ0/Ν-/Ρ-junction) ho. The first conductive type connection region (Ν+ region) 147 may be formed to penetrate the second conductive type ion implant 14 200913247 into the layer 145 to contact the first conductive type ion implantation layer 143. In order to suppress the first conductive type connection region 147 from becoming a leak source, the width of the first conductive type connection region 147 can be minimized. For this purpose, a plugimpiant can be completed after the through-hole is negotiated for the first-metal contact 151. However, the embodiment is not limited thereto. For example, an ion implantation pattern (not shown) may be opened/formed on the first substrate, and then the first conductivity type connection region 147 may be formed as an ion implant mask. The first conductive type connection region 147 may be formed between the light emitting diode and the 4 circuit 12A in accordance with the embodiment to minimize the dark current surface and suppress the decrease in saturation and the decrease in sensitivity. An interlayer dielectric layer 160 may be formed on the first substrate, and a line 15A may be formed. The line may include, but is not limited to, a first metal contact coffee, a first metal i5i, a second metal (5), a third metal 153, and a fine metal contact 154. ', the path 150 is formed for each unit cell to connect the light-emitting diode 23A (described later) with the readout circuit 12A, and to transfer the photo-electric charge of the light-emitting diode. When the line 15A connected to the readout circuit 120 is formed, the line 17 for connecting the peripheral circuit area for signal processing can also be formed at the same time. The line (9) may be formed of a metal, an alloy, and a plurality of conductive materials. For example, line 150 can be formed by Ming, Tong, Ming or Crane. Please refer to "Fig. 2", and the second substrate 2 including the crystalline semiconductor layer can be prepared. The second substrate 20 may be a single crystal or polycrystalline substrate, and may be a substrate doped with p-type 15 200913247 impurity or n-type impurity. The crystalline semiconductor layer 2 can be formed on the second beauty plate. For example, the crystalline semiconductor layer 200 can be formed on the second substrate 20 by epitaxial growth. A soil Although not shown in the figure, the hydrogen ion implantation layer can penetrate the side of the phase between the second substrate and the crystalline transition tube by implanting hydrogen ions. The implantation of the nitrogen material can even be completed after ion implantation of the light-emitting diode. Referring to "Fig. 3", the light-emitting diode 230 can be formed inside the crystalline semiconductor layer. The light emitting diode 230 may include a first impurity region 21A and a second impurity germanium region 220. In the case of the prior art, the impurity-type impurity region 21 can be formed by implanting an n-type impurity into a shallow region of the crystalline semiconductor layer near the surface of the crystalline semiconductor layer 2GG. The second impurity region 22 is formed by penetrating a p-type impurity into a deep region of the crystalline semiconductor layer. In one embodiment, the second impurity region 220 may be first raised to ' and then the first impurity region 21 may be formed on the second impurity region. The first mixed region 220 and the first impurity region 21 〇 provide a Ν junction structure. Referring to "Fig. 4", the ohmic contact layer 2?5 may be additionally formed on the first impurity region 210 at the surface of the crystalline semiconductor layer 200. The ohmic contact layer 205 can be formed by interposing an inter/implanted n-type impurity (η+). The ohmic contact layer 2〇5 reduces the ohmic resistance between the light-emitting diode 230 and the line 15〇. Hereinafter, an example in which the ohmic contact layer 2〇5 under the light-emitting diode 230 is omitted will be described. Referring to "Fig. 5", the device isolation region 240 may be formed inside the crystalline semiconductor layer 16 200913247 200 to separate the light-emitting diode 230 in accordance with the single pixel. The device isolation region 240 can be formed on the crystalline semiconductor layer by forming a mask (not shown) and then completing the ion implantation. The ion of the implanting device can be a high concentration of P lion. The m is a device in the device age region, and the defects generated in the light-emitting diode 230 can be reduced, so that dark current characteristics can be solved. Referring to "Fig. 6", the first substrate 1A and the second substrate 20 including the crystalline semiconductor layer 2 (9) may be bonded to each other. In particular, the first base 100 and the second substrate 20 may be joined to each other such that the light-emitting diodes for which the unit elements are separated correspond to one of the lines 150, respectively. Thus, in the first substrate and the second substrate 2, before the bonding, the bonding can be made by increasing the surface energy of the surface to which the bonding is catalyzed. In some embodiments, the bonding can be accomplished using a dielectric or metal layer placed on the bonding interface to improve bonding. When the Titanic substrate 100 and the second substrate 20 are joined, the fourth metal contact 1Ma and the first impurity regions 210 of the light emitting diode 230 may be connected to each other. Therefore, the photocharge generated by the light-emitting body 230 can be transferred to the readout circuit 12A through the line (9). The illuminating body 230 separated by the device isolation region 240 for each unit cell can be connected to the first substrate 1 for each fourth metal contact 154a placed per unit cell. The 'Axis Towel' does not indicate that for the embodiment in which the hydrogen ion implanted layer is bonded, the hydrogen ion implantation layer can be changed to a hydrogen gas layer by performing heat treatment. 17 200913247 Referring to "FIG. 7", the second substrate 20 can be removed, so that the crystalline semiconductor layer 200 is held on the first substrate 1A. That is, using a hydrogen gas layer (not shown) as a reference, part of the second substrate 2 can be removed using the blade, and the light-emitting diode 230 is held on the first substrate 1 (8), so that the light-emitting diode 230 can be exposed. Therefore, the crystalline semiconductor layer 200 including the light emitting diode 230 and the device isolation region 240 may remain on the first substrate 1A. Referring to FIG. 8 'the portion of the interlayer dielectric layer 160 and the wiring 170 exposed to the peripheral portion of the exposed portion 115, the exposed portion 115 can be opened by removing a portion of the crystalline semiconductor layer 2, at this time, in the outer region of the wafer. The lateral sides of the light-emitting diodes can also be exposed.
請參考「第9圖」，包含第一溝槽253之第一鈍化層25〇可形 成於其上形成有晶狀半導體層2〇〇和暴露部115之層間介電層WO 上。第-鈍化層250可透過沈積氧化層或氮化層於形 極體230之層間介電層16〇上而形成。 X 第一溝槽253可使用光刻製程和钱刻製程而形成於第一鈍化 層250中，以選擇性地暴露發光二極體230之表面。第一溝槽253 可形成於發光二極體23G之邊緣區域上，這樣不會遮蔽發光二極 之光編域。終帛：輸55可啊娜成以暴露 周邊電路區域之線路170，同時第-溝槽253被形成。 奸請參考「第U)圖」，上部電極可形成於包含第一溝槽攻 之弟-鈍化層250上。上部電極可形成於第—溝槽况中， 18 200913247 這樣上部電極260可電連接發光二極體23〇。 因為上部電極260透過第一溝槽253選擇性地連接部分發光 二極體230 ’上部電極細可被形成，這樣將不會遮蔽光線入射至 發光二極體230。此外’上部電極可透過第二溝槽255連接周 邊電路^域之線路17〇。另外，因為上部電極遮蔽發光二極體 230之橫向側面，可阻擋光線。某些實施例中，上部電極260可由 包含銘、銅、鈦和鎮之多種導電材料形成。 β月參考第11圖」’第二鈍化層270可形成於第一鈍化層25〇 和上部電極260上。例如，第二鈍化層270可為氮化層或氧化層。 此外，彩色濾光片280可形成於每一單元晝素之發光二極體 230之對應之部分第二鈍化層27〇上。 「第12圖」所示係為另一實施例之影像感測器之剖視圖。 請參考「第12圖」，影像感測器可包含：包含線路15〇和讀 出電路120之第一基板1〇〇;以及，晶狀半導體層2〇〇，包含讀出 電路120上形成的發光二極體和裝置隔離區域。第一基板1〇〇之 讀出電路12〇可包含：電氣接面區域140，形成於第一基板 中；以及第一導電類型連接區域148，連接電氣接面區域ho—側 之線路150。 「第12圖」所示之實施例可採用「第1圖」、「第2圖」、「第 3圖」、「第4圖」、「第5圖」、「第6圖」、「第7圖」、「第8圖」、「第 9圖」、「第10圖」以及「第11圖」所述實施例之技術特徵。 19 200913247 依照「第12圖」所示之實施例，裝設計為轉移電晶體 Tx之源極和汲極之間存在電减，這縣额可完全被傾印。因 此，當發光二極生的綠荷被傾印至浮動擴散區域時，輸出 影像之靈敏度可被增加。 此外，依照一實施例，電荷連接區域被形成於發光二極體和 讀出電路H提供光铺讀速移鱗徑，這樣暗電流來源 被最小化，飽和度降低和靈敏度降低可被抑制。 其間，與「第11圖」所述實施例不同，此實施例提供第一導 電類型連接區域148於電氣連接區域140 _侧之第一基板1〇〇中。 依照只靶例，用於歐姆接觸之第一導電類型連接區域（） ⑷可形成於電氣接面區域140上。此時，因為裝置作業於被應用 至電氣接面(1域14G之反向偏壓’第—導電類型連接區域（n+連 接區域）148和第-金屬接觸1Ma之形成製程提供泄露來源，因 此電場（electric field ; EF)可產生於石夕表面上。接觸形成製程期 間’電場内部產生的晶體缺陷作為泄露來源。 '此外，依照-實施例，在第-導電類型連接區域（N+連接區 域）M8形成於電氣接面區域⑽之表面上的實例中，電場係由於 第導電類型連接區域148/第二導電類獅子植入層⑷而被 增加。此電場也用作泄露來源。 因此’提供一種佈局’其中第一金屬接觸1Ma被形成於未攙 雜P0層但是包含第一導電類型連接區域（N+連接區域）之主 20 200913247 動區域中織，第-金屬接觸151a透過第—導電類型連接區域 (N+連接區域）148連接第—導電類型離子植入層⑷。 依照實施例，電場未產生於石夕表面上，可有助於降低三維積 體互補金屬氧化半導體影像感測器之暗電流。 本說明書中〃—個實施例〃、〃-實施例〃/實施例實例" 等表示聯繫本發明至少-個實施例中包含的該實施例所描述特別 特徵、結構或特點。說明書中不同位置出現的這種術語並非必須 全部指相_實_。此外，當特別㈣徵、結構或特點係結合 任意實施_料，在本賴技術人㈣麵範_結合其他實 施例會影響這些特徵、結構或特點。 雖然本發日肢前述之實施例揭露如上，然其並_以限定本 =恭在不脫離本發明之精神和範圍内，所為之更動與潤飾，均 屬本發明之專獅護顧之内。尤其地，各種更動與修正可能為 本發明揭露、圖式以及申請專利範圍之内主題組合排列之$且件部 和/或排列。除了組件部和/或排列之更動與修正 技術人員明顯還可看出其他使用方法。 本7貝域 【圖式簡單說明】 第1圖至第U騎示為實施例之影像感 視圖；以及 〈衣4方法之剖 第12圖所不為另一實施例之影像感測器之剖視圖。 【主要元件符號說明】 21 200913247 20 第二基板 100 第一基板 110 裝置隔離層 120 讀出電路 121 轉移電晶體Tx 123 重設電晶體Rx 125 驅動電晶體Dx 127 選擇電晶體Sx 130 離子植入區域 131 浮動擴散區域FD 133、135、137 源極/没極區域 140 電氣接面區域 141 第二導電類型井 143 第一導電類型離子植入層 145 第二導電類型離子植入層 147 第一導電類型連接區域 148 第一導電類型連接區域 150 線路 151 第一金屬 151a 第一金屬接觸 152 第二金屬 22 200913247 153 154a 160 170 200 205 210 220 230 240 250 253 255 260 270 280 第三金屬 第四金屬接觸 層間介電層 線路 晶狀半導體層 歐姆接觸層 第一雜質區域 第二雜質區域 發光二極體 裝置隔離區域 第一鈍化層 第一溝槽 第二溝槽 上部電機 第二鈍化層 彩色濾光片 23Referring to Fig. 9, a first passivation layer 25 including a first trench 253 may be formed on the interlayer dielectric layer WO on which the crystalline semiconductor layer 2 and the exposed portion 115 are formed. The first passivation layer 250 is formed by depositing an oxide layer or a nitride layer on the interlayer dielectric layer 16 of the body 230. The X first trench 253 may be formed in the first passivation layer 250 using a photolithography process and a credit engraving process to selectively expose the surface of the light emitting diode 230. The first trench 253 may be formed on an edge region of the light-emitting diode 23G so as not to shield the light-emitting region of the light-emitting diode. Finally, the input 55 can be formed to expose the line 170 of the peripheral circuit area while the first groove 253 is formed. Please refer to the "U" diagram. The upper electrode can be formed on the passivation layer 250 including the first trench. The upper electrode can be formed in the first trench state, 18 200913247 such that the upper electrode 260 can be electrically connected to the light emitting diode 23A. Since the upper electrode 260 is selectively connected to the partial light-emitting diode 230 through the first trench 253, the upper electrode can be formed so that light is not incident on the light-emitting diode 230. Further, the upper electrode can be connected to the line 17 of the peripheral circuit via the second trench 255. In addition, since the upper electrode shields the lateral sides of the light-emitting diode 230, light can be blocked. In some embodiments, the upper electrode 260 can be formed from a variety of electrically conductive materials including ingot, copper, titanium, and town. The second passivation layer 270 may be formed on the first passivation layer 25A and the upper electrode 260. For example, the second passivation layer 270 can be a nitride layer or an oxide layer. Further, a color filter 280 may be formed on a corresponding portion of the second passivation layer 27A of the light-emitting diode 230 of each unit. Fig. 12 is a cross-sectional view showing an image sensor of another embodiment. Referring to FIG. 12, the image sensor may include: a first substrate 1A including a line 15A and a readout circuit 120; and a crystalline semiconductor layer 2A including a readout circuit 120. Light-emitting diode and device isolation area. The readout circuit 12A of the first substrate 1b may include: an electrical junction region 140 formed in the first substrate; and a first conductivity type connection region 148 connecting the line 150 on the ho-side of the electrical junction region. The examples shown in Figure 12 can be used in "1st", "2nd", "3rd", "4th", "5th", "6th", " The technical features of the embodiments described in Fig. 7, "8th", "9th", "10th" and "11th". 19 200913247 According to the example shown in Figure 12, there is a charge reduction between the source and the drain of the transfer transistor Tx, which can be completely dumped. Therefore, when the green charge of the light-emitting diode is dumped to the floating diffusion region, the sensitivity of the output image can be increased. Further, according to an embodiment, the charge connection region is formed in the light emitting diode and the readout circuit H to provide a light-drawing speed scale, so that the dark current source is minimized, and the saturation reduction and sensitivity reduction can be suppressed. In the meantime, unlike the embodiment described in Fig. 11, this embodiment provides the first conductive type connection region 148 in the first substrate 1A on the side of the electrical connection region 140_. According to the target only example, the first conductive type connection region (4) for ohmic contact can be formed on the electrical junction region 140. At this time, since the device operates to provide a leak source by the formation process applied to the electrical junction (the reverse bias '1st conductive type connection region (n+ connection region) 148 and the first metal contact 1Ma of the 1 domain 14G, the electric field (electric field; EF) may be generated on the surface of the stone. The crystal defects generated inside the electric field during the contact forming process are used as a source of leakage. Further, in accordance with the embodiment, the first conductive type connection region (N+ connection region) M8 In the example formed on the surface of the electrical junction region (10), the electric field is increased by the first conductivity type connection region 148 / the second conductivity type lion implant layer (4). This electric field is also used as a source of leakage. 'The first metal contact 1Ma is formed in the undoped P0 layer but contains the first conductive type connection region (N+ connection region) in the main 20 200913247 moving region, and the first metal contact 151a is transmitted through the first conductive type connection region (N+ The connection region 148 is connected to the first conductivity type ion implantation layer (4). According to the embodiment, the electric field is not generated on the surface of the stone, which can help reduce the three-dimensional The dark current of the body-compensated metal oxide semiconductor image sensor. In the present specification, an embodiment, a 〃-embodiment 〃 / an example of an embodiment, and the like, are associated with the embodiment included in at least one embodiment of the present invention. The specific features, structures or characteristics described. The terminology appearing in different positions in the specification does not have to be all referring to the actual_. In addition, when the special (four) sign, structure or feature is combined with any implementation, in the technical person (4) </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; And the retouchings are all within the scope of the lion's care of the present invention. In particular, various changes and modifications may be the components and/or arrangements of the subject combinations within the scope of the disclosure, drawings, and claims. Other methods of use can be clearly seen by the component and/or alignment modifiers and corrections. This is a simple description of the drawings. FIG. 12 is a cross-sectional view of an image sensor of another embodiment. [Main element symbol description] 21 200913247 20 Second substrate 100 First substrate 110 Device isolation layer 120 Readout circuit 121 Transfer transistor Tx 123 Reset transistor Rx 125 Drive transistor Dx 127 Select transistor Sx 130 Ion implantation region 131 Floating diffusion region FD 133, 135, 137 Source/no-polar region 140 Electrical junction region 141 second conductivity type well 143 first conductivity type ion implantation layer 145 second conductivity type ion implantation layer 147 first conductivity type connection region 148 first conductivity type connection region 150 line 151 first metal 151a first metal contact 152 Second metal 22 200913247 153 154a 160 170 200 205 210 220 230 240 250 253 255 260 270 280 Third metal fourth metal contact interlayer dielectric layer line crystalline semiconductor layer ohmic contact layer first impurity region second impurity region light emitting two Polar body device isolation region first passivation layer first trench second trench upper motor second passivation layer color Ray 23