TW200910766A - PWM generating devices and methods - Google Patents

Abstract

A PWM generating device comprises a switch device and an integrated chip. The switch device is coupled to a power supply and a ground voltage, and configured to switch to output a driving signal according to a PWM signal. The integrated chip is configured to generate the PWM signal, detect the driving signal during a duty cycle of the PWM signal, and determine whether the voltage of the PWM signal is lower than a predetermined voltage. If the voltage of the PWM signal is lower than a predetermined voltage, the integrated chip stops outputting the PWM signal.

Description

200910766 IX. Description of the Invention: [Technical Field] The present invention relates to a pulse width modulation circuit and method, and more particularly to a voltage detection for testing whether an input voltage of a DC step-down circuit is normally supplied. Circuits and methods. [Prior Art] f: Fig. 1 shows a conventional DC buck converter 100. The control unit 102 is configured to generate a Pulse Width Modulation (PWM) signal to the switching device 1〇4. The switching device 1〇4 is coupled between the DC voltage source 106 and the grounding power source, and can output the driving signal according to the pulse width of the control unit 1〇2 for 5 weeks 4 δΚ. The driving signal is also a pulse modulation signal. The high voltage level is the supply voltage output from the supply voltage source 1〇6, and the low voltage level is the ground voltage. The DC step-down circuit 1〇8 is coupled to the switch device 104'. The low-pass filter t (L〇W_PaSS Filter, LPF) composed of an inductor and a capacitor can be driven according to the driving signal outputted by the switch device 104. The duty cycle (Duty Cyde) outputs DC voltage. If the duty cycle of the drive signal is larger, the DC voltage of the DC step-down circuit is larger, but it does not exceed the voltage of the supply voltage source 1〇6. The DC voltage output from the DC step-down circuit 1〇8 can be supplied to 110. ^ In practical applications, when the DC buck converter is to start supplying DC voltage to the load 110, the supply voltage source 106 is not necessarily ready for supply (for example, the supply voltage source 106 is still at 0 volts at this time).

Client's Docket No.: TT5s Docket No: Q975-A41242-TW/Final/LukeLee 5 200910766 causes the DC step-down circuit 108 to operate abnormally and cannot output a stable DC voltage. Therefore, the conventional solution is to experience a soft start time when the DC buck converter 100 begins to supply a DC voltage to the load 110. During the soft start time, the control unit 102 can output a short pulse during which the switching device 104 and the supply voltage source 106 are turned on, and the control unit 102 can detect the driving signal output by the switching device 104 at this time. Whether the normal supply voltage level is reached. However, this method must determine the pulse width of the short pulse in advance, and must first undergo a soft start-up time to test whether the supply voltage is ready when the DC voltage is initially supplied. Accordingly, the present invention is directed to the problems and deficiencies of the prior art which are not presented in the prior art, and the solutions are presented in the following embodiments in conjunction with the accompanying drawings. SUMMARY OF THE INVENTION The present invention provides an embodiment of a pulse width modulation device for driving a DC step-down circuit including a switching device and an integrated circuit chip. The switching device is coupled to a supply voltage source and a ground power source for outputting a driving signal at a connection point according to a pulse width modulation signal switching. The integrated circuit chip includes a pin, a pulse width modulator, and a voltage detector. The pin is coupled to the connection point for receiving the driving signal. The pulse width modulator is configured to output the pulse width modulation signal. The voltage detector is coupled to the pin, and detects the driving signal during one of the working cycles of the pulse width modulation signal, and determines whether a voltage of the driving signal reaches a predetermined voltage. Wherein the pulse width is above if the voltage is lower than the predetermined voltage level

Client's Docket No.: TT5s Docket No: 0975-A41242-TW/Final/LukeLee 6 200910766 . The modulator stops outputting the above pulse width modulation signal. The invention also provides an embodiment of a power history detecting method, which is applied to a DC-flow step-down control circuit, comprising: providing a pulse width modulation signal, and controlling a conduction state of a switching device according to the pulse width modulation signal to generate a driving Signal. Then, one of the driving signals is detected during one of the working periods of the pulse width modulation signal, and finally it is determined whether the voltage reaches a predetermined voltage. When the voltage is lower than the predetermined voltage, the pulse width modulation signal is stopped. [Embodiment] The present invention allows the control unit to directly send a pulse width modulation signal to the switching device, and detects whether the supply voltage is ready during the duty cycle of the pulse width modulation signal, that is, the pulse width modulation signal is at When the high level state is detected, it is detected whether the supply voltage is ready. Fig. 2A is a system embodiment of the present invention, which can detect whether the supply voltage has been prepared at the falling edge of the pulse width modulation signal < The DC buck converter 200 includes a control unit 202, a switching device 204, a supply voltage source 206, and a DC buck circuit 208. Switching device 204 includes two switches 212 and 214. The switch 212 and the switch 214 are connected to each other, and the switch 212 is coupled to the supply voltage source 206, and the switch 214 is coupled to the ground power source. In this embodiment, switches 212 and 214 are all N-type gold oxide half field effect transistors. The control unit 202 is coupled to the switching device 204, including a pulse width modulator 216, a voltage detector 218, a buffer 220, and an inverter 224. The pulse width modulator 216 can output a signal PWM. The signal PWM is a pulse width modulation signal and passes through the buffer 220 and the inverter 224, respectively.

Client's Docket No.: TT^ Docket No: 0975-A41242-TW/Final/LukeLee 7 200910766 Output signals UGATE and LGATE to switches 212 and 214, causing switches 214 and 214 to alternately conduct. For example, when the signal pWM is high, the switch 212 is turned on, and the switch 214 is non-conducting; otherwise, when the signal is low, the switch 212 is non-conducting. Note that since the switches 212 and 214 are high-power N-type CMOS transistors, the buffer 220 and the inverter 224 are required to have a driving capability 琢 and the signal PWM is converted to the signals UGATE and lgate for a time. If the supply voltage provided by the supply voltage source 2〇6 is ready, the drive signal PHASE is also the pulse width machine signal, and its high level is the supply voltage, and the low level is the ground voltage. The DC step-down circuit is connected to the device 204' for receiving the drive signal PHASE to output a DC voltage to the load 210. In addition, the DC voltage can also be fed back to the pulse width modulator 216 as a feedback signal fb to adjust the duty cycle of the pulse width modulation signal. For example, if the DC voltage is increased, the duty cycle of the pulse width modulation signal will decrease; if the DC voltage is decreased, the duty cycle of the pulse width modulation signal will increase to stabilize the voltage of the DC voltage output to the load 21〇. value. Signal timing diagrams for signal PWM, signal UGATE, and signal LGATE are shown in Figure 3. The signal UGATE and the signal LGATE are mutually opposite signals. Since the buffer 220 and the inverter 224 need to have the driving capability for the continuous application, the signal PWM is converted to the signals UGATE and LGATE for a period of time. Therefore, when the signal PWM is switched from the low level to the high level, the voltage of the driving signal PHASE is driven. Will be delayed - the time will be grounded

Client's Docket No.: TT^ Docket No:0975-A41242-TW/Final/LukeLee 200910766 . The voltage is switched to the supply voltage. On the contrary, in spring, the drive signal PiiAsE 唬ΡλνΜ is switched from the supply voltage to the ground power by the high level switch. The voltage will also be delayed for a period of time t, t2, and t3. The detector 2 i 8 can detect the high level of the first driving signal PHASE at the beginning or the first few falling edges, and the voltage of the HaSE is determined, and the voltage can be set as the supply voltage source 2〇6. Achieved - a predetermined voltage. If the predetermined power is voltage _ 21S = = pressure, the voltage of the obtained driving signal PHASE is low; the supply voltage of the voltage source 206 measured at the falling edge of the WM is good ~ voltage, indicating that the supply power W can be stopped The output signal PWMH is therefore pulse width modulator PWM ^ 1 ta slave & and then continue to output signal PHASE (four) h "detection drive signal PH == loss at the falling edge. If the measured drive signal PHASE voltage is still lower than the supply voltage, the voltage source 206 should be ready for supply voltage. ? & until the supply 'control list S 202 can be - integrated circuit chip, and wide _ (10) war duck signal ATE and 5 hole number LGATE. The voltage of the driving signal PHASE can be directly measured through the P H A S E pin of the integrated circuit chip without the need for additional pins. In another alternative embodiment, the rising edge of the signal PWM can also detect whether the voltage of the driving signal PHASE reaches a predetermined voltage, as shown in FIG. 2B. The difference between Fig. 2B and Fig. 2A is that the positions of the buffer 220 and the inverter 224 are mutually adjusted, and the waveform diagram is shown.

Client's Docket No.: TT’s Docket No: 0975-A41242-TW/Final/LukeLee 9 200910766 . As shown in Figure 3B. In Figure 3B, since the signal UGATE is generated by the signal PWM via the inverter 224, the signal UGATE and the PWM are inverted signals and delayed for a period of time. Therefore, in this embodiment, the voltage detector 218 can detect whether the signal PHASE reaches a predetermined voltage at the rising edge of the signal PWM, that is, also at times t1, t2, and t3. Figure 4A is another embodiment of the present invention in which it is detected whether the supply voltage is ready at the rising edge of the pulse width modulation signal. The pulse width modulator 416, the supply voltage source '406, and the DC step-down circuit 408 of the DC buck converter 400 in Fig. 4 are the same as those of the second figure, and will not be described again. Different from the 2A-B diagram, the switch 412 of the switching device 404 is a P-type MOS field effect transistor, so the signal PWM of the pulse width modulator 416 can be input to the switches 412 and 414 via the buffers 420 and 422, respectively. . Since switches 412 and 414 are high-power MOSFETs, buffers 420 and 422 also need to be driven, and signal PWM conversion to signals UGATE and LGATE is delayed for a period of time. In this embodiment, the voltage detector 418 can detect the voltage of the driving signal PHASE at the rising edge of the signal PWM, and determine whether the voltage of the driving signal PHASE has reached a predetermined voltage value. Figure 5A is a signal timing diagram of Figure 4A. The voltage detector 418 can detect the driving at the time points h, t2, and t3, that is, at the first or first rising edges of the signal PWM. The voltage of the signal PHASE, and determine whether the high level of the drive signal PHASE has reached a predetermined voltage value. If the voltage of the driving signal PHASE does not reach the predetermined voltage value, the pulse width modulator 216 can stop outputting the signal PWM and wait for a period of time.

Client’s Docket No.: TT5s Docket No:0975-A41242-TW/Final/LukeLee 10 200910766 . Continue to output the signal PWM. In another alternative embodiment, it is also possible to detect whether the voltage of the driving signal PHASE reaches a predetermined voltage at the falling edge of the signal PWM, as shown in FIG. 4B. The difference between Fig. 4B and Fig. 4A is that the signal PWM is output to the switches 412 and 414 via the inverters 424 and 426, respectively, and the waveform diagram is as shown in Fig. 5B. In Fig. 5B, since the signal UGATE is generated by the signal PWM via the inverter 424, the signal UGATE and the PWM are mutually inverted signals and delayed for a while. Therefore, in this embodiment, the voltage detector 218 can detect whether the signal PHASE reaches a predetermined voltage at the falling edge of the signal PWM, that is, at times t1, t2, and t3. Figure 6 is a method embodiment of the present invention, which can be applied to a DC-DC voltage control circuit to detect whether a supply voltage is ready during a duty cycle of a pulse width modulation signal. The method first provides a pulse width modulation signal having a duty cycle (step S602), and then uses the pulse width modulation signal to control the conduction state of an off device to generate a driving signal (step S604). For example, when the pulse width modulation signal is during the duty cycle, the switching device can switch to the supply voltage and output the driving signal as the supply voltage; otherwise, the switching device can switch to the ground voltage and output the driving signal to the ground voltage. Therefore, the driving signal is also a pulse width modulation signal, the high level is the supply voltage, and the low level is the ground voltage. However, if the supply voltage is not ready (for example, below the original supply voltage level), the output of the drive signal will not be able to maintain the desired high and low levels. Therefore, the test drive signal can be measured during the duty cycle of the pulse width modulation signal

The client's Docket No.: TT's Docket No: 0975-A41242-TW/Final/LukeLee 11 200910766 . The voltage value (step S606), and determines whether the voltage of the driving signal is lower than a predetermined voltage value (step S608). For example, the voltage value of the driving signal can be detected at the falling edge of the pulse width modulation signal, and the voltage value of the driving signal can be detected at the rising edge of the pulse width modulation signal. In one embodiment, the predetermined voltage value can be set to the supply voltage. If the voltage of the driving signal is lower than the predetermined voltage value, the pulse width modulation signal is stopped for a predetermined time (step S610), and the process returns to step 602. If the voltage of the driving signal is not lower than the predetermined voltage value, the driving signal is used to drive the 'buck circuit' to output the DC voltage to a load (step 612). This DC voltage is proportional to the duty cycle of the drive signal and is between the supply voltage and the ground voltage. In addition, the duty cycle of the pulse width modulation signal can also be adjusted according to the DC voltage. For example, if the DC voltage is increased, the duty cycle of the pulse width modulation signal is reduced; if the DC voltage is decreased, the pulse is pulsed. The duty cycle of the width modulation signal is increased to stabilize the voltage value of the DC voltage output to the load. While the present invention has been described above in terms of several embodiments, it is not intended to limit the invention, and it is to be understood that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional DC buck converter; FIG. 2A is a system embodiment of the present invention, which can detect whether a supply voltage is normally supplied at a falling edge of a pulse width modulation signal. 2B is a system embodiment of the present invention, which can be modulated in pulse width

Client's Docket No.: TT5s Docket No:0975-A41242-TW/Final/LukeLee 12 200910766 • The rising edge of the nickname detects whether the supply voltage is normally supplied; Figure 3A-B shows the 2nd and 8th graphs respectively. Signal timing diagram; FIG. 4A is a system embodiment of the present invention. It can detect whether the supply voltage is normally supplied on the rising edge of the pulse width modulation §fl number. FIG. 4B is a system embodiment of the present invention. Detecting whether the supply voltage is normally supplied at the falling edge of the pulse width modulation signal; FIG. 5A-B is a signal timing diagram of FIG. 4A and FIG. 4B respectively; and FIG. 6 is a method embodiment of the present description, Detect whether the supply voltage is normally supplied during the duty cycle of the pulse width modulation signal. [Description of main component symbols] 100, 200, 400 to DC buck converters 102, 202, 402 to control units 104, 204, 404 to switching devices 106, 206, 406 ~ supply voltage sources 108, 208, 408 ~ DC drop Voltage circuit 110, 210, 410~ load 212, 214, 412, 414~ transistor 216, 416~ pulse width modulator 218, 418~ voltage detector 220, 420, 422~ buffer 224, 424, 426~ Inverter

Client’s Docket No.: TT5s Docket No; 0975-A41242-TW/Final/LukeLee 13

Claims (1)

200910766 X. Patent application scope: 1. A pulse width modulation device for driving a DC current step-down circuit, wherein the pulse width modulation device comprises: a switching device coupled to a supply voltage source and a ground power source, And generating a driving signal according to a pulse width modulation signal switching; and an integrated circuit chip, comprising: a pin coupled to the connection point for receiving the driving signal f; a pulse width modulator for outputting the pulse width modulation signal; and a voltage detector coupled to the pin for detecting the driving during one of the duty cycles of the pulse width modulation signal a signal, and determining whether a voltage of one of the driving signals is lower than a predetermined voltage, wherein if the voltage is lower than the predetermined voltage level, the pulse width modulator stops outputting the pulse width modulation signal. 2. The pulse width modulation device of claim 1, wherein the switching device comprises: a first switch coupled to the supply voltage source and the connection point; and a second switch coupled And the grounding power source and the connection point, wherein the first and second switches are alternately turned on according to the pulse width modulation signal. 3. The pulse width modulation device described in claim 1 of the patent scope, Client's Docket No.: TT^ Docket No: 0975-A41242-TW/Final/LukeLee 14 200910766 Ί The above-mentioned electronic detector is more than the above pulse One of the falling edges of the width modulation signal detects the above voltage of the driving signal. The pulse width modulation device according to claim 3, wherein the first and second switches are Ν-type MOS field effect transistors. 5. The pulse width modulation device of claim 4, wherein the integrated circuit chip further comprises: a ^ buffer coupled to the first switch for delaying the pulse visibility modulation And an inverter coupled to the second switch for inverting the pulse width modulation signal. 6. The pulse width modulation device according to claim 3, wherein the first switch is a p-type MOS field effect transistor, and the second switch is a Ν-type MOS field effect transistor. 7. The pulse width modulation device of claim 6, wherein the integrated circuit chip further comprises: a first inverter coupled to the first switch for inverting the pulse width modulation And a second inverter coupled to the second switch for inverting the pulse width modulation signal. 8. The pulse width modulation device of claim 1, wherein the voltage detector detects the voltage of the driving signal at a rising edge of the pulse width modulation signal. 9. The pulse width modulation device according to claim 8, wherein the first switch is a Ρ-type MOS field effect transistor, and the above-mentioned Client's Docket No.: TT's Docket No: 〇975-A41242- TW/Final/LukeLee 15 200910766 • One switch is a gold oxide half field effect transistor. The pulse width modulation device of claim 9, wherein the integrated circuit chip further comprises: a first buffer coupled to the first switch to delay the pulse width modulation And a second buffer is coupled to the second switch for delaying the pulse width modulation signal. 11. The pulse width modulation device of claim 8, wherein the first and second switches are N-type MOS field effect transistors. 12. The pulse width modulation device of claim 2, wherein the integrated circuit chip further comprises: an inverter coupled to the first switch for reversing the pulse width modulation And a buffer coupled to the second switch for delaying the pulse modulation signal. 13. The pulse width modulation device according to claim 1, wherein when the driving signal is lower than the predetermined voltage level, the control unit stops outputting the pulse width modulation signal for a predetermined period of time and then re-outputs The above pulse width modulation signal. A pulse width modulation method for a DC-conversion control circuit, comprising: providing a pulse width modulation signal; controlling a conduction state of a switching device according to the pulse width modulation signal to generate a driving signal; Client's Docket No.: TT5s Docket No; 〇 975-A41242-TW/Final/LukeLee 200910766. detecting one of the driving signals in one of the working cycles of the pulse width modulation signal; determining whether the voltage reaches a predetermined voltage And when the voltage is lower than the predetermined voltage, the pulse width modulation signal is stopped. 15. The pulse width modulation method of claim 14, wherein the detecting the voltage of the driving signal further comprises detecting the voltage of the driving signal at a falling edge of the pulse width modulation signal. . 16. The pulse width modulation method of claim 14, wherein the detecting the voltage of the driving signal further comprises detecting the voltage of the driving signal at a rising edge of the beginning of the pulse width modulation signal. 17. The pulse width modulation method of claim 14, wherein stopping generating the pulse width modulation signal further comprises stopping a segment: after a predetermined time: t newly generating the pulse width modulation signal. 18. The pulse width modulation method of claim 14 further comprising driving the DC-DC circuit with the driving signal to generate a DC output voltage to a load. The pulse width modulation method as described in claim 18, further comprising adjusting the duty cycle of the pulse width modulation signal according to the DC output voltage. Client’s Docket No._ IT's Docket N〇:0975-A41242-TW/Final/LukeLee 17