TW200910195A - A device of using serial bits to determine instruction length at a multi-mode processor and the method thereof - Google Patents

A device of using serial bits to determine instruction length at a multi-mode processor and the method thereof Download PDF

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Publication number
TW200910195A
TW200910195A TW096130683A TW96130683A TW200910195A TW 200910195 A TW200910195 A TW 200910195A TW 096130683 A TW096130683 A TW 096130683A TW 96130683 A TW96130683 A TW 96130683A TW 200910195 A TW200910195 A TW 200910195A
Authority
TW
Taiwan
Prior art keywords
bit
instruction
bit data
data
length
Prior art date
Application number
TW096130683A
Other languages
English (en)
Chinese (zh)
Other versions
TWI337718B (enExample
Inventor
Li-An Song
Original Assignee
Sunplus Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sunplus Technology Co Ltd filed Critical Sunplus Technology Co Ltd
Priority to TW096130683A priority Critical patent/TW200910195A/zh
Priority to US12/222,887 priority patent/US7895414B2/en
Priority to GB0815165.6A priority patent/GB2452151B/en
Publication of TW200910195A publication Critical patent/TW200910195A/zh
Application granted granted Critical
Publication of TWI337718B publication Critical patent/TWI337718B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
TW096130683A 2007-08-20 2007-08-20 A device of using serial bits to determine instruction length at a multi-mode processor and the method thereof TW200910195A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW096130683A TW200910195A (en) 2007-08-20 2007-08-20 A device of using serial bits to determine instruction length at a multi-mode processor and the method thereof
US12/222,887 US7895414B2 (en) 2007-08-20 2008-08-19 Instruction length determination device and method using concatenate bits to determine an instruction length in a multi-mode processor
GB0815165.6A GB2452151B (en) 2007-08-20 2008-08-20 Instruction length determination device and method using concatenate bits to determine an instruction length in a multi-mode processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096130683A TW200910195A (en) 2007-08-20 2007-08-20 A device of using serial bits to determine instruction length at a multi-mode processor and the method thereof

Publications (2)

Publication Number Publication Date
TW200910195A true TW200910195A (en) 2009-03-01
TWI337718B TWI337718B (enExample) 2011-02-21

Family

ID=39812287

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096130683A TW200910195A (en) 2007-08-20 2007-08-20 A device of using serial bits to determine instruction length at a multi-mode processor and the method thereof

Country Status (3)

Country Link
US (1) US7895414B2 (enExample)
GB (1) GB2452151B (enExample)
TW (1) TW200910195A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9740484B2 (en) 2011-12-22 2017-08-22 Intel Corporation Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10956167B2 (en) * 2019-06-06 2021-03-23 International Business Machines Corporation Mechanism for instruction fusion using tags

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
US5295249A (en) * 1990-05-04 1994-03-15 International Business Machines Corporation Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
US5504932A (en) * 1990-05-04 1996-04-02 International Business Machines Corporation System for executing scalar instructions in parallel based on control bits appended by compounding decoder
EP0454985B1 (en) * 1990-05-04 1996-12-18 International Business Machines Corporation Scalable compound instruction set machine architecture
DE69424370T2 (de) * 1993-11-05 2001-02-15 Intergraph Corp., Huntsville Befehlscachespeicher mit Kreuzschienenschalter
GB2290395B (en) 1994-06-10 1997-05-28 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
JP3658101B2 (ja) 1996-09-13 2005-06-08 株式会社ルネサステクノロジ データ処理装置
US5881260A (en) * 1998-02-09 1999-03-09 Hewlett-Packard Company Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction
US6170050B1 (en) * 1998-04-22 2001-01-02 Sun Microsystems, Inc. Length decoder for variable length data
US6651160B1 (en) * 2000-09-01 2003-11-18 Mips Technologies, Inc. Register set extension for compressed instruction set
DE10120522A1 (de) * 2001-04-26 2002-11-07 Infineon Technologies Ag Verfahren zum Erkennen einer korrekten Befehls-Einsprung-Adresse bei Verwendung unterschiedlich langer Befehlsworte
JP3564445B2 (ja) * 2001-09-20 2004-09-08 松下電器産業株式会社 プロセッサ、コンパイル装置及びコンパイル方法
DE10204038B4 (de) * 2002-02-01 2005-03-03 Infineon Technologies Ag Verfahren zum Erkennen einer korrekten Befehls-Einsprung-Adresse bei Verwendung unterschiedlich langer Befehlsworte
US6944749B2 (en) * 2002-07-29 2005-09-13 Faraday Technology Corp. Method for quickly determining length of an execution package
TWI230899B (en) 2003-03-10 2005-04-11 Sunplus Technology Co Ltd Processor and method using parity check to proceed command mode switch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9740484B2 (en) 2011-12-22 2017-08-22 Intel Corporation Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage

Also Published As

Publication number Publication date
TWI337718B (enExample) 2011-02-21
GB2452151B (en) 2012-01-04
US7895414B2 (en) 2011-02-22
GB0815165D0 (en) 2008-09-24
GB2452151A (en) 2009-02-25
US20090055629A1 (en) 2009-02-26

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