200909963 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種薄膜電晶體基板、該薄膜電晶體基板 製造方法、採用該薄膜電晶體基板之液晶顯示裝置及該液晶 顯示裝置驅動方法。本發明尤其係關於一種基 : 之垂直配向型液晶顯示裝置。 羊較问 【先前技術】 液晶顯示裝置具有無輻射、輕薄及省電等優點，已廣泛 應用於各種資訊、通訊、消費性產品中。傳統液晶顯示裝置 通常存在視角窄及色偏問題，因此業界提出一種能較好解決 該問題之八域垂直配向型液晶顯示裝置。 請參閱圖1，其係一種先前技術八域垂直配向型液晶顯 示裝置之平面結構示意圖。該液晶顯示裝置10〇包括一第一 基底（圖未示）、一與該第一基底相對設置之第二基底（圖未示） 及一夾於該第一基底與該第二基底之間之液晶層（圖未示）。 該液晶層由介電常數為負且各向異性之液晶分子131構成。 該第一基底鄰近該液晶層一侧設置有一彩色濾光片（圖 未示）、一公共電極（圖未示）及複數第一突起119。該彩色滤 光片包括複數紅色濾光單元R(圖未示）、綠色濾光單元G(圖 未示）及藍色濾光單元B(圖未示）。該第一突起119呈開口向 右之“V”形，且相互平行間隔設置。 該第二基底鄰近該液晶層一側設置有複數公共電極線 121、複數掃描線122、複數第一資料線123、複數第二資料 線124、複數第一薄膜電晶體125、複數第二薄膜電晶體 200909963 126、複數第一晝素電極127、複數第二晝素電極128及複數 第二突起129。 該複數公共電極線121與該掃描線122相互平行交替間 隔設置，該第一資料線123、該第二資料線124相互平行交 替間隔設置，並與該掃描線122及公共電極線121垂直絕緣 相交。每一第一資料線123、一相鄰的第二資料線124及二 相鄰的公共電極線121交叉形成之區域定義為一晝素單元 10，一晝素單元10對應該彩色濾光片之一濾光單元R、G、 B。該掃描線122穿過該畫素單元10，並將該晝素單元10 劃分為一第一子晝素單元101及一第二子晝素單元102。 在每一晝素單元10内，該第一薄膜電晶體125設置於 該第一資料線123與該掃描線122之相交處，該第二薄膜電 晶體126設置於該第二資料線124與該掃描線122之相交 處，且該二薄膜電晶體125、126之閘極均連接至該掃描線 122，該第一薄膜電晶體125之源極連接至該第一資料線 123，該第二薄膜電晶體126之源極連接至該第二資料線 124。該第一晝素電極127設置於該第一子晝素單元101内， 並且電連接至該第一薄膜電晶體125之汲極。該第二晝素電 極128設置於該第二子畫素單元102内，並且電連接至該第 二薄膜電晶體126之汲極。至此，該第一晝素電極127可以 經由該第一資料線123及第一薄膜電晶體125加載第一灰階 電壓，該第二畫素電極128可以經由該第二資料線124及第 二薄膜電晶體126加載第二灰階電壓，使該二灰階電壓獨立 加載。 200909963 該第二突起129呈開口向右之“V”形，相互平行間隔 設置，且與該第一突起119交錯設置。 請一併參閱圖2,其係圖1所示第一子畫素單元内之液 晶分子之站向之俯視示意圖。當該第一晝素電極127與相對 之該公共電極分別加載第一灰階電壓及公共電壓時，二者之 間形成一電場。該電場使得夾於二電極、127之間之液晶分 子131均向著垂直於該電場方向扭轉。該液晶分子131受該 第一突起119與該第二突起129之作用，沿該二突起119、 129之斜面傾斜，該液晶分子131傾向於具有A、B、C、D 四個不同方向之站向。 同理，該第二晝素電極128與相對之公共電極加載電壓 時，其間之液晶分子131亦傾向於具有A、B、C、D四個不 同方向之站向。 請再一併參閱圖3,其係圖1所示二子晝素單元内之液 晶分子之站向之側視示意圖。當該二晝素電極127、128之 加載之灰階電壓不同時，該二子晝素單元101、102内之電 場不同，使該二子晝素單元101、102之液晶分子131之傾 斜角0 1、0 2不同。故，該二子畫素單元101、102之四個 站向互不相同，使該液晶顯示裝置100能夠實現八域顯示。 惟，由於該液晶顯示裝置100之一晝素單元10需二資 料線123、124驅動以獲得二不同之驅動電壓實現八域顯示， 又由於該二資料線123、124之平面式設計使其各自佔用一 定的基板面積，故該液晶顯示裝置100之基板利用率較低。 【發明内容】 200909963 有鑑於此，提供一種基板利用率較高之薄膜電晶體義 實為必需。 &枚 同時，提供上述薄膜電晶體基板之製造方法亦為必需。 同時，提供採用該薄膜電晶體基板之液晶顯示 必需。 且少# 同時，提供上述液晶顯示裝置之驅動方法亦為必需。 種薄膜電晶體基板，其包括一基底，設置於該基底之 複數掃描線，設置於該基底之複數資料線，複數第—開關元 件及複數第二開關元件及複數第一晝素電極及複數第二書 素電極’該資料線與該掃減交叉並絕緣且該資料線盘該 掃描線定舰數子晝素單元；每—子晝素單元對應—該第： 開關疋件及—該第二開關元件，每—子晝素單元内之第一薄 =開關元件及第二開關元件均由同—條該掃描線控制；每一 二素單元内設置有-第-畫素電極及—第二畫素電極，該第 :晝素電極經由該第-開關元件由該資料線獲取顯示訊 化’該第二畫素電極係經由該第二_元件及一分壓元件串 聯所形成之支路由同一資料線獲取顯示訊號。 -種液晶顯示裝置，其包括一對向基板，一與該對向基 ^相對設置薄膜電晶體基板及—位於該對向基板與該薄膜 ，晶體基板間之液晶層，其中，該薄膜電晶體基板包括一基 ^設置於該基底之複數掃描線，設置於該基底之複數資料 線，複數第-開關it件及複數第二開關元件及複數第一晝素 =極及複數第二晝素電極’該資料線與該掃描線交叉並絕 緣，且該資料線與該掃描線定義複數子畫素單元；每一子畫 11 200909963 素單元對應一該第一開關元件及一該第二開關元件，每一子 晝素單元内之第一薄膜開關元件及第二開關元件均由同一 條該掃描線控制；每一晝素單元内設置有一第一晝素電極及 一第二晝素電極，該第一畫素電極經由該第一開關元件由誃 貧料線獲取顯示訊號，該第二畫素電極係經由該第二開關元 件及一分壓元件串聯所形成之支路由同一資料線獲取顯示 訊號。 ‘"、不 一種薄膜電晶體基板製造方法，其包括如下步驟：提供 一基底；於該基底上形成複數掃描線、複數第一薄膜電晶體 之閘極及複數第二薄膜電晶體之閘極；於該基底、該掃:線 及該閘極上形成一閘極絕緣層；於該閘極絕緣層上形成半導 體圖案；於該閘極絕緣層及該半導體圖案上形成複數與該掃 描線交叉之資料線、複數第-薄膜電晶體之源極及沒極了複 數第二薄膜電晶體之源極及㈣：於該閘極絕緣層、該半導 體圖案、該資料線、該源極及魏極上形成—鈍化層；於談 鈍化層上形成賴第-軌、複㈣二㈣及複數第三= 孔；於該鈍化層上形成複數第一晝素電極、複數第二畫素電 極及複數偶合電極；其中，該複數掃描線與複數資料線交叉 形成複數畫素單元，每-晝素單元内設置—該第—薄膜電晶 體、-該第二薄膜電晶體、一該第一晝素電極、一該第二晝 素電極及至少-該偶合電極，在每—畫素單元内，該第一薄 膜電晶體之閘極及該第二薄膜電晶體之閘極均電連接至同 -掃描線，該第-畫素電極藉由該第—通孔電連接至該第一 薄膜電晶體之汲極，該第二晝素電極藉由該第二通孔電連接 12 200909963 至該第二薄臈電晶體之汲極，該 、BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate, a method of manufacturing the thin film transistor substrate, a liquid crystal display device using the same, and a liquid crystal display device driving method. More particularly, the present invention relates to a vertical alignment type liquid crystal display device. [Previous technology] The liquid crystal display device has the advantages of no radiation, light weight and power saving, and has been widely used in various information, communication, and consumer products. Conventional liquid crystal display devices generally have a narrow viewing angle and a color shift problem. Therefore, the industry has proposed an eight-domain vertical alignment type liquid crystal display device which can better solve the problem. Please refer to FIG. 1, which is a schematic diagram of a planar structure of a prior art eight-domain vertical alignment type liquid crystal display device. The liquid crystal display device 10 includes a first substrate (not shown), a second substrate (not shown) disposed opposite the first substrate, and a sandwich between the first substrate and the second substrate. Liquid crystal layer (not shown). The liquid crystal layer is composed of liquid crystal molecules 131 having a negative dielectric constant and anisotropy. A color filter (not shown), a common electrode (not shown), and a plurality of first protrusions 119 are disposed on a side of the first substrate adjacent to the liquid crystal layer. The color filter includes a plurality of red filter units R (not shown), a green filter unit G (not shown), and a blue filter unit B (not shown). The first projections 119 are in the shape of a "V" opening to the right and are spaced apart from each other in parallel. The second substrate is disposed adjacent to the liquid crystal layer with a plurality of common electrode lines 121, a plurality of scan lines 122, a plurality of first data lines 123, a plurality of second data lines 124, a plurality of first thin film transistors 125, and a plurality of second thin film electrodes. The crystal is 200909963 126, the plurality of first halogen electrodes 127, the plurality of second halogen electrodes 128, and the plurality of second protrusions 129. The plurality of common electrode lines 121 and the scan lines 122 are alternately arranged in parallel with each other. The first data lines 123 and the second data lines 124 are alternately spaced apart from each other and vertically insulated from the scan lines 122 and the common electrode lines 121. . A region in which each of the first data lines 123, an adjacent second data line 124, and two adjacent common electrode lines 121 are intersected is defined as a pixel unit 10, and a pixel unit 10 corresponds to a color filter. A filter unit R, G, B. The scan line 122 passes through the pixel unit 10 and divides the pixel unit 10 into a first sub-cell unit 101 and a second sub-cell unit 102. In each of the pixel units 10, the first thin film transistor 125 is disposed at the intersection of the first data line 123 and the scan line 122, and the second thin film transistor 126 is disposed on the second data line 124 and the The intersection of the scan lines 122, and the gates of the two thin film transistors 125, 126 are connected to the scan line 122, the source of the first thin film transistor 125 is connected to the first data line 123, the second film The source of the transistor 126 is coupled to the second data line 124. The first halogen electrode 127 is disposed in the first sub-cell unit 101 and electrically connected to the drain of the first thin film transistor 125. The second halogen electrode 128 is disposed in the second sub-pixel unit 102 and electrically connected to the drain of the second thin film transistor 126. At this point, the first pixel electrode 127 can be loaded with the first gray scale voltage via the first data line 123 and the first thin film transistor 125, and the second pixel electrode 128 can pass through the second data line 124 and the second film. The transistor 126 is loaded with a second gray scale voltage to load the two gray scale voltages independently. 200909963 The second protrusions 129 are formed in a "V" shape with an opening to the right, spaced apart from each other, and interlaced with the first protrusions 119. Please refer to FIG. 2 together, which is a schematic plan view of the liquid crystal molecules in the first sub-pixel unit shown in FIG. When the first halogen electrode 127 and the opposite common electrode are respectively loaded with the first gray scale voltage and the common voltage, an electric field is formed therebetween. This electric field causes the liquid crystal molecules 131 sandwiched between the two electrodes 127 to be twisted perpendicular to the direction of the electric field. The liquid crystal molecules 131 are affected by the first protrusions 119 and the second protrusions 129, and are inclined along the slopes of the two protrusions 119 and 129. The liquid crystal molecules 131 tend to have four different directions of A, B, C, and D. to. Similarly, when the second halogen electrode 128 and the opposite common electrode are loaded with voltage, the liquid crystal molecules 131 in between are also inclined to have four different directions of A, B, C, and D. Please refer to FIG. 3 again, which is a side view of the station of the liquid crystal molecules in the dicotocene unit shown in FIG. When the gray scale voltages of the two halogen elements 127 and 128 are different, the electric fields in the two sub-cell units 101 and 102 are different, so that the tilt angle of the liquid crystal molecules 131 of the two sub-cell units 101 and 102 is 0 1 . 0 2 is different. Therefore, the four stations of the two sub-pixel units 101 and 102 are different from each other, so that the liquid crystal display device 100 can realize eight-domain display. However, since one of the liquid crystal display devices 100 requires two data lines 123 and 124 to drive two different driving voltages to realize eight-domain display, and because of the planar design of the two data lines 123 and 124, Since the substrate area is occupied, the substrate utilization rate of the liquid crystal display device 100 is low. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a thin film transistor with a high substrate utilization rate. At the same time, it is also necessary to provide a method for producing the above-mentioned thin film transistor substrate. At the same time, it is necessary to provide a liquid crystal display using the thin film transistor substrate. At the same time, it is also necessary to provide a driving method of the above liquid crystal display device. A thin film transistor substrate comprising a substrate, a plurality of scan lines disposed on the substrate, a plurality of data lines disposed on the substrate, a plurality of first switching elements and a plurality of second switching elements, and a plurality of first halogen electrodes and a plurality of a second pixel electrode 'the data line intersects and is insulated from the sweeping line and the data line disk is the scanning line fixed number of sub-units; each of the sub-dielectric elements corresponds to the first: the switch element and the second The switching element, the first thin=switching element and the second switching element in each sub-cell unit are controlled by the same scanning line; each of the two elements is provided with a -first pixel electrode and a second a pixel electrode, wherein the pixel element is obtained from the data line via the first switching element, and the second pixel element is formed by a series connection of the second element and a voltage dividing element. The data line gets the display signal. a liquid crystal display device comprising a pair of substrates, a thin film transistor substrate disposed opposite to the opposite substrate, and a liquid crystal layer between the opposite substrate and the film and the crystal substrate, wherein the thin film transistor The substrate comprises a plurality of scan lines disposed on the substrate, a plurality of data lines disposed on the substrate, a plurality of first-switching members and a plurality of second switching elements, and a plurality of first and second halogen elements and a plurality of second halogen electrodes The data line intersects and is insulated from the scan line, and the data line and the scan line define a plurality of sub-pixel units; each sub-picture 11 200909963 element unit corresponds to the first switch element and the second switch element, The first thin film switching element and the second switching element in each sub-cell unit are controlled by the same scanning line; each of the pixel units is provided with a first halogen element and a second halogen element, the first a pixel element obtains a display signal from the lean line through the first switching element, and the second pixel electrode is routed through the same data line via a branch formed by the second switching element and a voltage dividing element Display signals. '", a method for fabricating a thin film transistor substrate, comprising the steps of: providing a substrate; forming a plurality of scan lines on the substrate; a gate of the plurality of first thin film transistors; and a gate of the plurality of second thin film transistors Forming a gate insulating layer on the substrate, the scan line and the gate; forming a semiconductor pattern on the gate insulating layer; forming a plurality of intersections with the scan line on the gate insulating layer and the semiconductor pattern a data line, a source of the plurality of thin film transistors, and a source of the plurality of second thin film transistors and (4): formed on the gate insulating layer, the semiconductor pattern, the data line, the source, and the Wei pole a passivation layer; forming a Lai-track, a complex (four) two (four), and a complex third = hole on the passivation layer; forming a plurality of first halogen electrodes, a plurality of second pixel electrodes, and a complex coupling electrode on the passivation layer; Wherein, the plurality of scan lines and the plurality of data lines intersect to form a plurality of pixel units, and each of the unit cells is provided with the first thin film transistor, the second thin film transistor, a first thin element electrode, and the like second a halogen electrode and at least the coupling electrode, in each of the pixel units, the gate of the first thin film transistor and the gate of the second thin film transistor are electrically connected to the same-scanning line, the first drawing The ferrite electrode is electrically connected to the drain of the first thin film transistor through the first via hole, and the second halogen electrode is electrically connected to the drain of the second thin germanium transistor through the second via hole 12200909963 , the,
至對應之資料線’該偶合電極藉由該第三通:電= J ==晶體之源極’且該偶合電極與該第-薄㈣晶 ，之:極所連接之資料線交疊以形成—偶合電容作為一分 澄元件。 續绍絲裝置，其包括複數掃描線、複數與該掃描 交之資料線及複數該掃描線與資料線相交構成之 液晶 =域„單元。每一晝素單元包括一第一子晝素 ::及-弟二子晝素單元，該第一子畫素單元包括一第一薄 =電晶體及-第—液晶電容，該第二子晝素單元包括一第二 薄：電晶體：一電阻及一第二液晶電容，其中，該第一液 電今、、$由該第—薄膜電晶體連接該掃描線及資料線，該第一 液晶電容經由該第二薄膜電晶體及該電阻連接該掃描線及 資料線。 種上述液晶顯示裝置之驅動方法，其包括如下步驟： a.施加第i次掃描訊號至該第n列掃描線，該資料線上之灰 階電壓經由該第一薄膜電晶體給該第一液晶電容充電，經由 ^第二薄膜電晶體及該電阻給該第二液晶電容充電；及b. 停止施加掃描訊號至該第n列掃描線，該第一及第二薄膜電 晶體關閉，使該第二液晶電容未完全充電。 相較於先前技術，由於本發明薄膜電晶體基板、薄膜電 曰曰體基板製造方法所製成的薄膜電晶體基板及液晶顯示裝 置採用了該分壓元件’使得本發明薄膜電晶體基板、薄膜電 曰曰體基板製造方法所製成的薄膜電晶體基板及液晶顯示裝 13 200909963 置在減少一半資料線的情況下亦可以實現同一子晝素單元 不同之電壓而實現八域顯示，進而使得薄膜電晶體基板、薄 膜電晶體基板製造方法所製成的薄膜電晶體基板及液晶顯 示裝置佈線簡單、成本較低。 【實施方式】 請參閱圖4，其係本發明液晶顯示裝置第一實施方式之 立體結構示意圖。該液晶顯示裝置200為一垂直配向型液晶 顯示裝置，其包括一彩色濾光片基板201、一與該彩色濾光 片基板201相對設置之薄膜電晶體基板202及一夾於該彩色 濾光片基板201與該薄膜電晶體基板202之間之液晶層 230。該液晶層230介電常數為負且各向異性，且包括複數 液晶分子231。 該彩色濾光片基板201包括一第一基底210，該第一基 底210鄰近該液晶層230 —側設置有一彩色濾光片213、一 公共電極215及複數突起219。該彩色濾光片213包括複數 紅色濾光單元R(圖未示）、綠色濾光單元G(圖未示）及藍色濾 光單元B(圖未示）。該突起219呈開口向左之“V”形，且相 互平行間隔設置。 請一併參閱圖5，其係圖4所示薄膜電晶體基板之平面 結構示意圖。該薄膜電晶體基板202包括一第二基底220。 該第二基底220鄰近該液晶層230 —側設置有複數相互平行 之掃描線221、複數相互平行且與該掃描線221垂直之資料 線222。該複數掃描線221及該複數資料線222均間隔設置， 使任意二相鄰掃描線221與任意二相鄰資料線222界定一矩 14 200909963 形之子晝素單元20,且每一子晝素單元20在位置上對應該 彩色濾光片213之一濾光單元R、G或者B。其中，每一條 掃描線221對應並控制一列該子晝素單元20,每一條資料線 222對應並控制一行子晝素單元20。 每一子晝素單元20内設置有相互絕緣之一第一晝素電 極225及一第二畫素電極226,每一子晝素單元20鄰近該掃 描線221與該資料線222相交處還設置有一第一薄膜電晶體 223及一第二薄膜電晶體224。每一薄膜電晶體223、224包 括一源極（未標示）、一閘極（未標示）及一汲極（未標示）。對於 每一子晝素單元20，該二薄膜電晶體223、224之閘極電連 接至該子畫素單元20所對應之掃描線221，該第一薄膜電晶 體223之汲極電連接至該第一晝素電極225，該第二薄膜電 晶體224之汲極電連接至該第二晝素電極226，該第一薄膜 電晶體223之源極電連接至該子畫素單元20所對應之資料 線222，該第二薄膜電晶體224之源極藉由一用於分壓之偶 合電容228偶接至該資料線222。 該第一晝素電極225及該第二晝素電極226均包括複數 溝槽227，該複數溝槽227呈開口向左之“V”形，且與該 突起219交錯設置。 請一併參閱圖6及圖7，圖6係圖5所示薄膜電晶體基 板沿VI-VI方向剖視示意圖，圖7係圖5所示薄膜電晶體基 板沿VII-VII方向剖視示意圖。該薄膜電晶體基板201還包 括一閘極絕緣層252、一半導體圖案250及一鈍化層255， 該偶合電容228包括一偶合電極229。 15 200909963 該二薄膜電晶體223、224之閘極251、261及該掃描線 222設置於該第二基底220上，該閘極絕緣層252設置於該 二閘極251、261、掃描線222及該第二基底220上，該半導 體圖案250對應該二閘極251、261設置於該閘極絕緣層252 上，該汲極253、263及源極254、264設置於該半導體圖案 250及該閘極絕緣層252上，該資料線222設置於該閘極絕 緣層252上，該鈍化層255設置於該資料線222、閘極絕緣 層252、汲極253、263及源極254、264上，該二晝素電極 225、226及一偶合電極229設置於該鈍化層255上。該第一 晝素電極225藉由一貫穿該鈍化層255之第一通孔291連接 該汲極253，該第二畫素電極226藉由一貫穿該鈍化層255 之第二通孔292連接該汲極263。該源極254延伸並連接至 該資料線222。該偶合電極229之兩端分別與該源極264及 該資料線222交疊，且該偶合電極229 —端藉由一貫穿該鈍 化層255之第三通孔293連接至該源極264，另一端與該資 料線222形成該偶合電容228。 該掃描線221、該閘極251、261由同一步驟形成的不透 光金屬製成，如鋁(A1)系金屬、鉬（Mo)、鉻(Cr)、钽(Ta)、或 銅（Cu)等。該汲極253、263、源極254、264及該資料線222 亦為同一步驟形成的不透光金屬製成。該二畫素電極227、 226及該偶合電極229由同一步驟形成的透明導電物製成， 如氧化銦錫（ITO)或氧化錮鋅（IZO)等。 描述至此，該薄膜電晶體基板201中一子晝素單元20 之等效電路圖可如圖8所示。 16 200909963 請一併參閱圖9，其係圖5所示子晝素單元内對應該第 一晝素電極之液晶分子之站向之俯視示意圖。當該第一晝素 電極225與相對之該公共電極215分別加載一灰階電壓及一 公共電壓時，二者之間形成一電場。該電場使得夾於二電極 215、225之間之液晶分子231均向著垂直於該電場方向扭 轉。該液晶分子231受該突起219與該溝槽227之作用，沿 該突起219之斜面傾斜，該液晶分子231傾向於具有A、B、 C、D四個不同方向之站向。 同理，該第二晝素電極226與相對之公共電極215加載 電壓時，其間之液晶分子231亦傾向於具有A、B、C、D四 個不同方向之站向。 請一併參閱圖10,其係圖5中二晝素電極所對應之液晶 分子之站向之側視示意圖。由於該第一薄膜電晶體223之源 極254係直接電連接至該資料線222上，該第二薄膜電晶體 224係藉由該偶合電容228偶接至該資料線222上，該偶合 電容228之分壓作用使得該二源極254、264自該資料線222 獲得之電壓不同，進而使該二晝素電極225、226所加載之 灰階電壓亦不相同，故該二晝素電極225、226所對應之液 晶分子231之傾斜角0 1、0 2不同。故，該二畫素電極225、 226所對應之液晶分子231之四個站向互不相同，使該液晶 顯示裝置200能夠實現八域顯示。 相較於先前技術，本發明液晶顯示裝置200由於在每一 子晝素單元20中，該第一薄膜電晶體223之源極254直接 電連接至該資料線222上，該第二薄膜電晶體264藉由該偶 17 200909963 合電容228偶接至該資料線222上，使該二晝素電極225、 226所加載之灰階電壓亦不相同，每一子晝素單元2〇僅利用 一條資料線222即實現了八域顯示，故液晶顯示裝置2〇〇基 板面積利用率較高。 該液晶顯示裝置200所採用之薄膜電晶體基板202之製 造方法包括如下步驟·· 步驟S1 :形成閘極金屬層； 於該第一基板220上依序形成一閘極金屬層及一第一光 阻層。 步驟S2 :形成閘極251、261及該掃描線221 ; 提供一第一光罩對該第一光阻層進行曝光顯影，從而形 成預疋之光阻圖案，對該閘極金屬層進行姓刻，進而形成 該閘極251、261及該掃描線221之圖案，移除第一光阻層。 步驟S3 :形成閘極絕緣層252及半導體層； 上形成該閘極絕 於該閘極251、261及該第二基板220 緣層252及該半導體層。 步驟S4:形成半導體圖案250 ; 提供一第二光罩對該第二光阻層進行曝光顯影，從而 成一預定之光阻圖案；對該半導體層進行蝕刻，進而形》 有該半導體圖案250,移除第二光阻層。 /战具 步驟S5 :形成源/汲極金屬層； 於該閘極絕緣層252及該半導體圖# 25〇均 汲極金屬層及一第三光阻層。 /原/ 步驟S6 .形成源極254、264、沒極253、2幻及 18 200909963 222 ； 提供一第三光罩對該第三光阻層進行曝光顯影，從而形 成一預定之光阻圖案；對該源/汲極金屬層進行蝕刻，進而 形成該源極254、264、汲極253、263及該資料線222。 步驟S7 :形成鈍化層薄膜； 於該閘極絕緣層252、源極254、264、汲極253、263 及該資料線222上依序沈積一鈍化層薄膜及一第四光阻層。 步驟S8:形成鈍化層255及第一通孔291、第二通孔292 及該第三通孔293 ; 提供一第四光罩對該第四光阻層進行曝光顯影，從而形 成一預定圖案；對該鈍化層薄膜及該閘極絕緣層252進行蝕 刻，進而定義出該鈍化層255及該第一通孔291、第二通孔 292及該第三通孔293，移除第四光阻層。 步驟S9 :形成一透明導體層； 於該鈍化層107上形成一透明導體層及一第五光阻層。 步驟S10:形成該二晝素電極225、226及偶合電極229; 提供一第五光罩對該第五光阻層進行曝光顯影，從而形 成一預定之光阻圖案；對該導體層進行蝕刻，進而定義出一 導體層圖案，即偶合電極229及具有溝槽227之該二晝素電 極225、226，移除第五光阻層。 請一併參閱圖11及圖12 ’圖11係本發明液晶顯示裝置 第二實施方式之薄膜電晶體基板之平面結構示意圖。圖12 係圖11所示薄膜電晶體基板沿XII-XII方向剖視示意圖。該 液晶顯示裝置300與該液晶顯示裝置200大體相同，其主要 19 200909963 區別在於：薄膜電晶體基板302之偶合電極329設置於該第 二基底320與該閘極絕緣層352之間。該偶合電極329之兩 端分別與該源極364及該資料線322交疊，且該偶合電極329 一端藉由一貫穿該閘極絕緣層352之第三通孔393連接至該 源極364，另一端與該資料線322形成該偶合電容328。該 掃描線321、該閘極351、361由同一步驟形成的不透光金屬 製成，如鋁系金屬、鉬、鉻、鈕、或銅等。 請一併參閱圖13及圖14’圖13係本發明液晶顯示裳置 第三實施方式之薄膜電晶體基板之平面結構示意圖。圖14 係圖13所示薄膜電晶體基板沿XIV-XIV方向剖視示意圖。 該液晶顯示裝置400與該液晶顯示裝置200大體相同，其主 要區別在於：該薄膜電晶體基板402進一步包括一偶合電極 430，該偶合電極430設置於該第二基底420與該閘極絕緣 層452之間。偶合電極429及s亥偶合電極430藉由一貫穿該 閘極絕緣層452及鈍化層455之第四通孔494電連接。該二 偶合電極429、430中之至少一個與該資料線422交疊形成 一偶合電容428。 相較於第一實施方式，由於該液晶顯示裝置4〇〇具有二 電連接之偶合電極429、430,可以藉由調整該二偶合電極 429、430與該資料線422父豐之總面積來調整第二晝素電極 426上灰階電壓之大小，故調節範圍較寬。 該液晶顯示裝置400所採用之薄膜電晶體基板4〇2之製 造方法與薄膜電晶體基板202之製造方法大體相同，其主要 區別在於： 20 200909963 形成閘極451、461、該掃描線421時一併形成該偶合電 極 430 ; 形成純化層455及第一通孔491、第二通孔492及該第 三通孔493時一併形成該第四通孔494。 請參閱圖15,其係本發明液晶顯示裝置第四實施方式之 一子晝素單元之等效電路圖。該液晶顯示裝置500與該液晶 顯示裝置200大體相同，其主要區別在於：第二畫素電極526 經由第二薄膜電晶體524及偶合電容528串聯形成之支路連 接至第一薄膜電晶體523之汲極。 請參閱圖16,其係本發明液晶顯示裝置第五實施方式之 一子晝素單元之等效電路圖。該液晶顯示裝置600與該液晶 顯示裝置200大體相同，其主要區別在於：第二畫素電極626 經由第二薄膜電晶體624及偶合電容628串聯形成之支路連 接至第一晝素電極625 上述第四、第五實施方式中同樣由於該第一薄膜電晶體 523、623與該第二薄膜電晶體524、624由同一條掃描線 521、621控制，使該第二薄膜電晶體524、624可以有效的 控制該第二畫素電極526、626在該掃描線521、621被掃描 時段經由該偶合電容528、628所在支路充電，在該掃描線 521、621未被掃描時段（即電壓維持時段）斷開該偶合電容 528、628所在支路以防止第一晝素電極525、625與第二晝 素電極526、626之間電壓重新分配。 請參閱圖17及圖18,圖17係本發明液晶顯示裝置第六 實施方式之等效電路圖，圖18係圖17所示液晶顯示裝置一 21 200909963 子晝素單元之等效電路圖。該液晶顯示裝置700與該液晶顯 示裝置600大體相同，其主要區別在於：該液晶顯示裝置700 將該液晶顯示裝置200之偶合電容228替換為一分壓電阻 728用於分壓。下面對該液晶顯示裝置700作進一步詳細描 述： 該液晶顯示裝置700包括複數相互平行之掃描線721及 複數相互平行且與該掃描線721垂直絕緣相交之資料線 722。該掃描線721與該資料線722相交構成之最小矩形區 域定義複數子晝素單元70。 每一子晝素單元70包括一第一子晝素區78及一第二子 晝素區79。該第一子晝素區78包括一第一薄膜電晶體723、 一第一晝素電極725、一公共電極707及一第一存儲電容 708。該第二子晝素區79包括一第二薄膜電晶體724、一分 壓電阻728、一第二晝素電極726、一公共電極707及一第 二存儲電容709。該分壓電阻728具較高阻抗，可由半導體 材質製成。 該第一薄膜電晶體723之閘極（未標示）連接該掃描線 721，源極（未標示）連接該資料線722，汲極（未標示）連接該 第一晝素電極725。該第二薄膜電晶體724之閘極（未標示) 連接該掃描線721，源極（未標示）連接該資料線722,汲極（未 標示）經由該電阻222連接該第二晝素電極726。 該公共電極707與該第一晝素電極725及位於其間之液 晶分子（圖未示）構成複數第一液晶電容718，亦與該第二晝 素電極726及位於其間之液晶分子（圖未示）構成複數第二液 22 200909963 晶電容719。該第一液晶電容718與該第一存儲電容708並 聯，該第二液晶電容719與該第二存儲電容709並聯。 該掃描線721用於控制該第一及第二薄膜電晶體723、 724之開啟及關閉。該資料線722用於在該第一及第二薄膜 電晶體723、724開啟時提供灰階電壓至該子晝素單元70以 實現顯示。該第一子晝素區78由該第一薄膜電晶體723驅 動，該第二子畫素區79由該第二薄膜電晶體724及該分壓 電阻728驅動。 該液晶顯示裝置700之工作原理如下： 當第η列掃描線721第i次被施加掃描訊號期間，該列 上之第一及第二薄膜電晶體723、724開啟，同時，該資料 線722上之灰階電壓經由該第一薄膜電晶體723之源極、汲 極至該第一畫素電極725，使該第一液晶電容718及第一存 儲電容708充電；亦經由該第二薄膜電晶體724之源極、汲 極及該分壓電阻728至該第二晝素電極726，使該第二液晶 電容719及第二存儲電容709充電。 由於該分壓電阻728之分壓作用，該灰階電壓經由該第 二薄膜電晶體724及該分壓電阻728給該第二液晶電容719 充電之充電電流較其經由該第一薄膜電晶體723給該第一液 晶電容718充電之充電電流小，從而該第二液晶電容719充 電較第一液晶電容718慢，控制該第一及第二薄膜電晶體 723、724之導通時間，使該第一液晶電容718完全充電及該 第二液晶電容719未完全充電，進而該第二液晶電容719與 第一液晶電容718具不同之電壓。同理，該第一存儲電容708 23 200909963 及第二存儲電容709亦具不同之電壓。 該η列掃描線721第i次掃描訊號關閉至第i+Ι次被施 加掃描訊號之前，該第一存儲電容708保持該第一液晶電容 718之電壓，該第二存儲電容709保持該第二液晶電719之 電壓，以維持該第一子晝素區78及第二子晝素區79之顯示。 相較於先前技術，本發明液晶顯示裝置700中，同一資 料線722上之灰階電壓經由該第一薄膜電晶體723給該第一 液晶電容718充電，經由該第二薄膜電晶體724及該電阻728 給該第二液晶電容719充電，從而該二液晶電容718、719 之充電電流不同，且使該第二液晶電容719未完全充電，進 而該第一液晶電容718及第二液晶電容719具不同之電壓而 實現八域顯示，由於該二子晝素區78、79僅需一資料線722 驅動，進而該液晶顯示裝置700佈線簡單、成本較低。 請參閱圖19，其係本發明液晶顯示裝置第七實施方式之 一子晝素單元之等效電路圖。該液晶顯示裝置800與第六實 施方式之液晶顯示裝置700大體相同，其主要區別在於：第 二薄膜電晶體824之源極（未標示）經由電阻828連接至該資 料線822，汲極（未標示）連接第二晝素電極826。 本發明液晶顯示裝置並不限於上述實施方式之所述，亦 可具其他多種變更設計，如： 一、第六實施方式中之該第二薄膜電晶體724可不連接 該資料線722，而連接第一薄膜電晶體723之汲極，該資料 線722上之灰階電壓經由該第一薄膜電晶體723、第二薄膜 電晶體724及分壓電阻728寫入該第二子晝素區79。 24 200909963 曰# i實施方式中之該偶合電容與該第二薄膜電 ttr路中，該偶合電容與該第二薄膜電晶體之 ^接^序W互換。即，第二畫素電極可以經由偶合電容連 s ^、,；—相電晶體之祕，該第二薄膜電晶體之源極連接 資料線$-薄膜電晶體之汲極及該第一晝素電極之一； 第^素電極可以連接至第二薄膜電晶體之没極，該第二薄 —— 〇 膜電晶體之源極經由分屢電阻連接至資料線、第—薄膜電晶 體之汲極及該第一晝素電極之 一在每一實施方式中，第一薄膜電晶體之通道寬長比 (W/L)與第二薄膜電晶體之通道寬長比可以相同，也可 同。 四、 在每一實施方式中，第一薄膜電晶體及第二薄膜電 晶體可以是底閘極型電晶體，也可以是頂閘極型電晶體丨第 一薄膜電晶體及第二薄膜電晶體可以是對稱式電晶體，也可 以是非對稱式電晶體。 五、 任何具有分壓功能之元件均可以作為分壓元件代替 上述實施方式中之偶合電容或分壓電阻。 綜上所述，本發明確已符合發明之要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之較佳實施方式，本發 明之範圍並不以上述實施方式為限，舉凡熟悉本案技藝之人 士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以 下申請專利範圍内。 【圖式簡單說明】 圖1係一種先前技術八域垂直配向型液晶顯示裝置之平 25 200909963 面結構示意圖。 圖2係圖1所示第一子晝素單元内之液晶分子之站向之 俯視示意圖。 圖3係圖1所示二子晝素單元内之液晶分子之站向之側 視不意圖。 圖4係本發明液晶顯示裝置第一實施方式之立體結構示 意圖。 圖5係圖4所示薄膜電晶體基板之平面結構示意圖。 圖6係圖5所示薄膜電晶體基板沿νΐ-νι方向剖視示意 圖7係圖5所示薄膜電晶體基板沿νπ_νπ方向剖視示 意圖。 圖8係圖5所示薄膜電晶體基板中一子晝素單元之等效 圖9係圖5所示薄膜電晶體基板中一子畫素單元内對應 該第一 圖 晝素電極之液晶分子之站向之俯視示意圖。To the corresponding data line 'the coupled electrode is formed by the third pass: electric=J==the source of the crystal' and the coupled electrode and the first-thin (tetra) crystal, the data lines connected to the pole are overlapped to form - The coupling capacitor acts as a separate component. The sequel device includes a plurality of scan lines, a plurality of data lines intersected with the scan lines, and a plurality of liquid crystal=domain units formed by the intersection of the scan lines and the data lines. Each of the pixel units includes a first sub-element: And a second sub-pixel unit, the first sub-pixel unit comprises a first thin = transistor and a - liquid crystal capacitor, the second sub-cell unit comprises a second thin: a transistor: a resistor and a a second liquid crystal capacitor, wherein the first liquid crystal is connected to the scan line and the data line by the first thin film transistor, and the first liquid crystal capacitor is connected to the scan line via the second thin film transistor and the resistor And a data line driving method of the above liquid crystal display device, comprising the steps of: a. applying an ith scan signal to the nth column scan line, wherein a gray scale voltage of the data line is given via the first thin film transistor Charging the first liquid crystal capacitor, charging the second liquid crystal capacitor via the second thin film transistor and the resistor; and b. stopping applying the scan signal to the nth column scan line, the first and second thin film transistors are turned off, Making the second liquid crystal Incompletely charged. Compared with the prior art, the thin film transistor substrate and the liquid crystal display device produced by the method for fabricating a thin film transistor substrate and a thin film electroconductive substrate of the present invention employ the voltage dividing element to make the thin film of the present invention A thin film transistor substrate and a liquid crystal display device 13 manufactured by a method for producing a crystal substrate or a thin film electro-dymium substrate can be realized by reducing voltages of half of the data lines to realize different voltages of the same sub-cell unit and realizing eight-domain display. Further, the thin film transistor substrate and the liquid crystal display device produced by the method of manufacturing the thin film transistor substrate and the thin film transistor substrate are simple in wiring and low in cost. [Embodiment] Please refer to FIG. 4, which is a liquid crystal display device of the present invention. A schematic diagram of a three-dimensional structure of the liquid crystal display device 200 is a vertical alignment type liquid crystal display device comprising a color filter substrate 201, a thin film transistor substrate 202 disposed opposite the color filter substrate 201, and a liquid crystal layer 230 sandwiched between the color filter substrate 201 and the thin film transistor substrate 202 The liquid crystal layer 230 has a dielectric constant that is negative and anisotropic, and includes a plurality of liquid crystal molecules 231. The color filter substrate 201 includes a first substrate 210, and the first substrate 210 is disposed adjacent to the liquid crystal layer 230. The color filter 213, a common electrode 215, and a plurality of protrusions 219. The color filter 213 includes a plurality of red filter units R (not shown), a green filter unit G (not shown), and a blue filter unit. B (not shown). The protrusions 219 are open to the left in a "V" shape and are arranged in parallel with each other. Please refer to FIG. 5 together, which is a schematic plan view of the thin film transistor substrate shown in FIG. The transistor substrate 202 includes a second substrate 220. The second substrate 220 is disposed adjacent to the liquid crystal layer 230 on the side of the plurality of parallel scan lines 221, and a plurality of data lines 222 parallel to each other and perpendicular to the scan lines 221 . The plurality of scan lines 221 and the plurality of data lines 222 are spaced apart to define any two adjacent scan lines 221 and any two adjacent data lines 222 to define a matrix 14 200909963-shaped sub-cell unit 20, and each sub-cell unit 20 corresponds in position to one of the color filter 213 filter units R, G or B. Each scan line 221 corresponds to and controls a column of the sub-cell units 20, and each data line 222 corresponds to and controls a row of sub-cell units 20. Each of the sub-cell units 20 is provided with a first halogen element 225 and a second pixel electrode 226 insulated from each other, and each sub-single unit 20 is disposed adjacent to the intersection of the scanning line 221 and the data line 222. There is a first thin film transistor 223 and a second thin film transistor 224. Each of the thin film transistors 223, 224 includes a source (not shown), a gate (not labeled), and a drain (not labeled). For each sub-cell unit 20, the gates of the two thin film transistors 223, 224 are electrically connected to the scan line 221 corresponding to the sub-pixel unit 20, and the drain of the first thin film transistor 223 is electrically connected to the The first pixel electrode 225, the drain of the second thin film transistor 224 is electrically connected to the second halogen electrode 226, and the source of the first thin film transistor 223 is electrically connected to the sub-pixel unit 20 The data line 222, the source of the second thin film transistor 224 is coupled to the data line 222 by a coupling capacitor 228 for voltage division. The first halogen electrode 225 and the second halogen electrode 226 each include a plurality of grooves 227 which are open to the left in a "V" shape and are interleaved with the protrusions 219. Referring to FIG. 6 and FIG. 7, FIG. 6 is a cross-sectional view of the thin film transistor substrate shown in FIG. 5 taken along line VI-VI, and FIG. 7 is a cross-sectional view of the thin film transistor substrate shown in FIG. 5 taken along the line VII-VII. The thin film transistor substrate 201 further includes a gate insulating layer 252, a semiconductor pattern 250 and a passivation layer 255. The coupling capacitor 228 includes a coupling electrode 229. 15 200909963 The gates 251 and 261 of the two thin film transistors 223 and 224 and the scan line 222 are disposed on the second substrate 220. The gate insulating layer 252 is disposed on the two gates 251 and 261 and the scan line 222. On the second substrate 220, the semiconductor patterns 250 are disposed on the gate insulating layer 252 corresponding to the two gates 251 and 261. The drain electrodes 253 and 263 and the source electrodes 254 and 264 are disposed on the semiconductor pattern 250 and the gate. The data line 222 is disposed on the gate insulating layer 252. The passivation layer 255 is disposed on the data line 222, the gate insulating layer 252, the drain electrodes 253 and 263, and the source electrodes 254 and 264. The dioxet electrodes 225, 226 and a coupling electrode 229 are disposed on the passivation layer 255. The first pixel electrode 225 is connected to the drain 253 via a first via 291 extending through the passivation layer 255. The second pixel electrode 226 is connected by a second via 292 extending through the passivation layer 255. Bungee 263. The source 254 extends and is coupled to the data line 222. The two ends of the coupling electrode 229 are respectively overlapped with the source 264 and the data line 222, and the end of the coupling electrode 229 is connected to the source 264 through a third through hole 293 penetrating the passivation layer 255. The coupling capacitor 228 is formed at one end and the data line 222. The scan line 221 and the gate electrodes 251 and 261 are made of an opaque metal formed by the same step, such as aluminum (A1) metal, molybdenum (Mo), chromium (Cr), tantalum (Ta), or copper (Cu). )Wait. The drains 253, 263, the sources 254, 264 and the data line 222 are also made of opaque metal formed in the same step. The two pixel electrodes 227 and 226 and the coupling electrode 229 are made of a transparent conductive material formed by the same step, such as indium tin oxide (ITO) or strontium zinc oxide (IZO). To this end, an equivalent circuit diagram of a sub-cell unit 20 in the thin film transistor substrate 201 can be as shown in FIG. 16 200909963 Please refer to FIG. 9 together, which is a schematic plan view of the liquid crystal molecules corresponding to the first halogen electrode in the sub-cell unit shown in FIG. 5 . When the first halogen electrode 225 and the opposite common electrode 215 are respectively loaded with a gray scale voltage and a common voltage, an electric field is formed therebetween. This electric field causes the liquid crystal molecules 231 sandwiched between the two electrodes 215, 225 to be twisted in a direction perpendicular to the electric field. The liquid crystal molecules 231 are inclined by the protrusions 219 and the grooves 227 along the slope of the protrusions 219, and the liquid crystal molecules 231 tend to have a standing direction of four different directions of A, B, C, and D. Similarly, when the second halogen electrode 226 and the opposite common electrode 215 are loaded with voltage, the liquid crystal molecules 231 therebetween tend to have four different directions of A, B, C, and D. Please refer to FIG. 10 together, which is a side view of the liquid crystal molecule corresponding to the dioxane electrode in FIG. Since the source 254 of the first thin film transistor 223 is directly electrically connected to the data line 222, the second thin film transistor 224 is coupled to the data line 222 via the coupling capacitor 228. The coupling capacitor 228 The voltage division causes the voltages obtained by the two source electrodes 254 and 264 from the data line 222 to be different, so that the gray scale voltages applied by the diode elements 225 and 226 are also different, so the dioxad electrode 225, The tilt angles 0 1 and 0 2 of the liquid crystal molecules 231 corresponding to 226 are different. Therefore, the four stations of the liquid crystal molecules 231 corresponding to the two pixel electrodes 225 and 226 are different from each other, so that the liquid crystal display device 200 can realize eight-domain display. Compared with the prior art, the liquid crystal display device 200 of the present invention has a source 254 of the first thin film transistor 223 directly connected to the data line 222 in each sub-single unit 20, the second thin film transistor. 264 is coupled to the data line 222 by the even 17 200909963 combined capacitor 228, so that the gray scale voltages of the diode elements 225 and 226 are also different, and each sub-unit unit 2 uses only one data. The line 222 realizes the eight-domain display, so that the liquid crystal display device 2 has a high substrate area utilization ratio. The manufacturing method of the thin film transistor substrate 202 used in the liquid crystal display device 200 includes the following steps: Step S1: forming a gate metal layer; sequentially forming a gate metal layer and a first light on the first substrate 220 Resistance layer. Step S2: forming gates 251, 261 and the scan line 221; providing a first mask to expose and develop the first photoresist layer, thereby forming a pre-tanned photoresist pattern, and surname the gate metal layer And forming a pattern of the gate electrodes 251, 261 and the scan line 221 to remove the first photoresist layer. Step S3: forming a gate insulating layer 252 and a semiconductor layer; forming the gate on the gate 251, 261 and the second substrate 220 edge layer 252 and the semiconductor layer. Step S4: forming a semiconductor pattern 250; providing a second mask to expose and develop the second photoresist layer to form a predetermined photoresist pattern; etching the semiconductor layer to form the semiconductor pattern 250, In addition to the second photoresist layer. /Sctor step S5: forming a source/drain metal layer; the gate insulating layer 252 and the semiconductor pattern #25〇 both a drain metal layer and a third photoresist layer. / original / step S6. Forming source 254, 264, stepless 253, 2 phantom and 18 200909963 222; providing a third mask to expose the third photoresist layer to form a predetermined photoresist pattern; The source/drain metal layer is etched to form the source 254, 264, the drains 253, 263, and the data line 222. Step S7: forming a passivation layer film; depositing a passivation layer film and a fourth photoresist layer on the gate insulating layer 252, the source 254, the 264, the drain electrodes 253 and 263, and the data line 222. Step S8: forming a passivation layer 255 and a first via 291, a second via 292 and the third via 293; providing a fourth mask to expose and develop the fourth photoresist layer to form a predetermined pattern; The passivation layer film and the gate insulating layer 252 are etched to define the passivation layer 255 and the first via 291, the second via 292 and the third via 293, and the fourth photoresist layer is removed. . Step S9: forming a transparent conductor layer; forming a transparent conductor layer and a fifth photoresist layer on the passivation layer 107. Step S10: forming the dioxad electrodes 225, 226 and the coupling electrode 229; providing a fifth mask to expose and develop the fifth photoresist layer to form a predetermined photoresist pattern; etching the conductor layer, Further, a conductor layer pattern is defined, that is, the coupling electrode 229 and the dioxadiene electrodes 225 and 226 having the trenches 227, and the fifth photoresist layer is removed. Referring to Fig. 11 and Fig. 12, Fig. 11 is a plan view showing the planar structure of a thin film transistor substrate according to a second embodiment of the liquid crystal display device of the present invention. Figure 12 is a cross-sectional view of the thin film transistor substrate shown in Figure 11 taken along the line XII-XII. The liquid crystal display device 300 is substantially the same as the liquid crystal display device 200. The main difference is that the coupling electrode 329 of the thin film transistor substrate 302 is disposed between the second substrate 320 and the gate insulating layer 352. The two ends of the coupling electrode 329 are respectively connected to the source 364 and the data line 322, and one end of the coupling electrode 329 is connected to the source 364 through a third through hole 393 extending through the gate insulating layer 352. The other end forms the coupling capacitor 328 with the data line 322. The scanning line 321 and the gate electrodes 351 and 361 are made of an opaque metal formed by the same step, such as an aluminum-based metal, molybdenum, chromium, a button, or copper. Referring to Fig. 13 and Fig. 14', Fig. 13 is a plan view showing the planar structure of the thin film transistor substrate of the third embodiment of the present invention. Figure 14 is a cross-sectional view of the thin film transistor substrate shown in Figure 13 taken along the line XIV-XIV. The liquid crystal display device 400 is substantially the same as the liquid crystal display device 200. The main difference is that the thin film transistor substrate 402 further includes a coupling electrode 430 disposed on the second substrate 420 and the gate insulating layer 452. between. The coupling electrode 429 and the sigma coupling electrode 430 are electrically connected by a fourth through hole 494 penetrating the gate insulating layer 452 and the passivation layer 455. At least one of the two coupling electrodes 429, 430 overlaps the data line 422 to form a coupling capacitor 428. Compared with the first embodiment, since the liquid crystal display device 4 has two electrically coupled coupling electrodes 429 and 430, it can be adjusted by adjusting the total area of the two coupling electrodes 429 and 430 and the data line 422. The magnitude of the gray scale voltage on the second halogen electrode 426 is wide. The manufacturing method of the thin film transistor substrate 4〇2 used in the liquid crystal display device 400 is substantially the same as the method of manufacturing the thin film transistor substrate 202, and the main difference is as follows: 20 200909963 When the gate electrodes 451 and 461 and the scanning line 421 are formed, The coupling electrode 430 is formed. The fourth through hole 494 is formed together when the purification layer 455 and the first through hole 491, the second through hole 492, and the third through hole 493 are formed. Referring to Fig. 15, there is shown an equivalent circuit diagram of a sub-cell unit of the fourth embodiment of the liquid crystal display device of the present invention. The liquid crystal display device 500 is substantially the same as the liquid crystal display device 200. The main difference is that the second pixel electrode 526 is connected to the first thin film transistor 523 via a branch formed by the second thin film transistor 524 and the coupling capacitor 528 connected in series. Bungee jumping. Referring to Fig. 16, there is shown an equivalent circuit diagram of a sub-cell unit of the fifth embodiment of the liquid crystal display device of the present invention. The liquid crystal display device 600 is substantially the same as the liquid crystal display device 200. The main difference is that the second pixel electrode 626 is connected to the first pixel electrode 625 via a branch formed by the second thin film transistor 624 and the coupling capacitor 628 in series. In the fourth and fifth embodiments, the first thin film transistors 523 and 623 and the second thin film transistors 524 and 624 are controlled by the same scanning lines 521 and 621, so that the second thin film transistors 524 and 624 can be used. Effectively controlling the second pixel electrodes 526, 626 to be charged through the branch of the coupling capacitors 528, 628 during the scanning period of the scan lines 521, 621, during which the scan lines 521, 621 are not scanned (ie, the voltage sustain period) Breaking the branch of the coupling capacitors 528, 628 to prevent voltage redistribution between the first halogen electrodes 525, 625 and the second halogen electrodes 526, 626. Referring to FIG. 17 and FIG. 18, FIG. 17 is an equivalent circuit diagram of a sixth embodiment of the liquid crystal display device of the present invention, and FIG. 18 is an equivalent circuit diagram of the liquid crystal display device of FIG. The liquid crystal display device 700 is substantially the same as the liquid crystal display device 600. The main difference is that the liquid crystal display device 700 replaces the coupling capacitor 228 of the liquid crystal display device 200 with a voltage dividing resistor 728 for voltage division. The liquid crystal display device 700 will be further described in detail below. The liquid crystal display device 700 includes a plurality of mutually parallel scanning lines 721 and a plurality of data lines 722 which are parallel to each other and which are vertically insulated from the scanning lines 721. The smallest rectangular area formed by the intersection of the scan line 721 and the data line 722 defines a complex sub-cell unit 70. Each sub-cell unit 70 includes a first sub-tend region 78 and a second sub-dize region 79. The first sub-quartz region 78 includes a first thin film transistor 723, a first halogen electrode 725, a common electrode 707, and a first storage capacitor 708. The second sub-tenon region 79 includes a second thin film transistor 724, a voltage dividing resistor 728, a second halogen electrode 726, a common electrode 707, and a second storage capacitor 709. The voltage dividing resistor 728 has a relatively high impedance and can be made of a semiconductor material. A gate (not labeled) of the first thin film transistor 723 is connected to the scan line 721, a source (not shown) is connected to the data line 722, and a drain (not labeled) is connected to the first halogen electrode 725. A gate (not labeled) of the second thin film transistor 724 is connected to the scan line 721, a source (not labeled) is connected to the data line 722, and a drain (not labeled) is connected to the second germane electrode 726 via the resistor 222. . The common electrode 707 and the first halogen electrode 725 and liquid crystal molecules (not shown) therebetween constitute a plurality of first liquid crystal capacitors 718, and the second halogen electrodes 726 and liquid crystal molecules therebetween (not shown) ) constitutes a plurality of second liquid 22 200909963 crystal capacitor 719. The first liquid crystal capacitor 718 is connected in parallel with the first storage capacitor 708, and the second liquid crystal capacitor 719 is connected in parallel with the second storage capacitor 709. The scan line 721 is used to control the opening and closing of the first and second thin film transistors 723, 724. The data line 722 is for providing a gray scale voltage to the sub-cell unit 70 for display when the first and second thin film transistors 723, 724 are turned on. The first sub-quartel region 78 is driven by the first thin film transistor 723, and the second sub-pixel region 79 is driven by the second thin film transistor 724 and the voltage dividing resistor 728. The working principle of the liquid crystal display device 700 is as follows: When the n-th scanning line 721 is applied with the scanning signal for the i-th time, the first and second thin-film transistors 723, 724 on the column are turned on, and at the same time, the data line 722 is on The gray scale voltage charges the first liquid crystal capacitor 718 and the first storage capacitor 708 via the source and the drain of the first thin film transistor 723 to the first pixel electrode 725; and also passes through the second thin film transistor The source, the drain of the 724 and the voltage dividing resistor 728 to the second halogen electrode 726 charge the second liquid crystal capacitor 719 and the second storage capacitor 709. Due to the voltage division of the voltage dividing resistor 728, the charging current of the gray level voltage charging the second liquid crystal capacitor 719 via the second thin film transistor 724 and the voltage dividing resistor 728 is higher than that of the first thin film transistor 723. The charging current for charging the first liquid crystal capacitor 718 is small, so that the second liquid crystal capacitor 719 is charged slower than the first liquid crystal capacitor 718, and the on-time of the first and second thin film transistors 723, 724 is controlled to make the first The liquid crystal capacitor 718 is fully charged and the second liquid crystal capacitor 719 is not fully charged, and the second liquid crystal capacitor 719 has a different voltage from the first liquid crystal capacitor 718. Similarly, the first storage capacitor 708 23 200909963 and the second storage capacitor 709 also have different voltages. The first storage capacitor 708 holds the voltage of the first liquid crystal capacitor 718, and the second storage capacitor 709 holds the second before the i-th scan signal 721 is turned off until the i-th scan is applied. The voltage of the liquid crystal 719 is maintained to maintain the display of the first sub-alloy region 78 and the second sub-tenon region 79. Compared with the prior art, in the liquid crystal display device 700 of the present invention, the gray scale voltage on the same data line 722 charges the first liquid crystal capacitor 718 via the first thin film transistor 723, via the second thin film transistor 724 and the The resistor 728 charges the second liquid crystal capacitor 719, so that the charging currents of the two liquid crystal capacitors 718 and 719 are different, and the second liquid crystal capacitor 719 is not fully charged, and the first liquid crystal capacitor 718 and the second liquid crystal capacitor 719 have The eight-domain display is realized by different voltages. Since the two sub-cell regions 78 and 79 only need to be driven by a data line 722, the liquid crystal display device 700 has simple wiring and low cost. Referring to Fig. 19, there is shown an equivalent circuit diagram of a sub-cell unit of the seventh embodiment of the liquid crystal display device of the present invention. The liquid crystal display device 800 is substantially the same as the liquid crystal display device 700 of the sixth embodiment, and the main difference is that the source (not labeled) of the second thin film transistor 824 is connected to the data line 822 via the resistor 828, and the drain is not Marked) connected to the second halogen electrode 826. The liquid crystal display device of the present invention is not limited to the above-described embodiments, and may have various other modifications, such as: 1. The second thin film transistor 724 in the sixth embodiment may not be connected to the data line 722, and the connection may be A drain of a thin film transistor 723, the gray scale voltage on the data line 722 is written into the second sub-tenon region 79 via the first thin film transistor 723, the second thin film transistor 724, and the voltage dividing resistor 728. In the coupling capacitor of the embodiment of the present invention, the coupling capacitor and the second thin film transistor are interchanged with the second thin film transistor. That is, the second pixel electrode may be connected to the s ^, , - the phase of the crystal through the coupling capacitor, the source of the second thin film transistor is connected to the drain of the data line $-film transistor and the first pixel One of the electrodes; the first electrode may be connected to the second electrode of the second thin film transistor, the second thin one of the source of the germanium transistor is connected to the data line, the drain of the first thin film transistor via a resistor And in one embodiment of the first halogen electrode, the channel width to length ratio (W/L) of the first thin film transistor and the channel width to length ratio of the second thin film transistor may be the same or the same. In each embodiment, the first thin film transistor and the second thin film transistor may be a bottom gate type transistor, or may be a top gate type transistor, a first thin film transistor, and a second thin film transistor. It may be a symmetrical transistor or an asymmetrical transistor. 5. Any component with a voltage dividing function can be used as a voltage dividing component instead of the coupling capacitor or voltage dividing resistor in the above embodiment. In summary, the present invention has indeed met the requirements of the invention, and the patent application is filed according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a prior art eight-domain vertical alignment type liquid crystal display device. Fig. 2 is a top plan view showing a station of liquid crystal molecules in the first sub-decene unit shown in Fig. 1. Fig. 3 is a view showing the station of liquid crystal molecules in the dicotomer unit shown in Fig. 1 to the side. Fig. 4 is a perspective view showing the configuration of a first embodiment of the liquid crystal display device of the present invention. FIG. 5 is a schematic plan view showing the planar structure of the thin film transistor substrate shown in FIG. 4. FIG. Figure 6 is a cross-sectional view of the thin film transistor substrate shown in Figure 5 taken along the line ν ΐ - ν 。 Figure 7 is a cross-sectional view of the thin film transistor substrate shown in Figure 5 taken along the νπ_νπ direction. 8 is an equivalent of a sub-halogen unit in the thin film transistor substrate shown in FIG. 5. FIG. 9 is a liquid crystal molecule corresponding to the first pixel electrode in a sub-pixel unit in the thin film transistor substrate shown in FIG. The station looks down to the schematic.
圖13係本發明液晶顯 體基板之平面結構示意圖。 示薄膜電晶體基板沿ΧΙΙ-Χ„方向剖視 良晶顯示裝置第三實施方式之薄膜電晶 26 200909963 圖14係圖13所示薄膜電晶體基板沿XIV-XIV方向剖視 示意圖。 圖15係本發明液晶顯示裝置第四實施方式之一子晝素 單元之等效電路圖。 圖16係本發明液晶顯示裝置第五實施方式之一子晝素 單元之等效電路圖。 圖17係本發明液晶顯示裝置第六實施方式之等效電路 圖。 圖18係圖17所示液晶顯示裝置一子晝素單元之等效電 路圖。 圖19本發明液晶顯示裝置第七實施方式之一子晝素單 元之等效電路圖。 【主要元件符號說明】 子晝素單元 20 ' 70 第一子晝素區 78 第二子晝素區 79 液晶顯示裝置 200、 300、400 ' 500、600、700、800 彩色濾光片基板 201 薄膜電晶體基板 202、302、402 第一基底 210 彩色濾光片 213 公共電極 215 突起 219 第二基底 220、320、420 掃描線 221 、 321 、 521 、 621 、 721 資料線 222、322、422、722、822 第一薄膜電晶體 223 、 523 、 623 、 723 27 200909963 第二薄膜電晶體 224 、 524 、 624 ' 724 、 824 第一晝素電極 225 、 625 、 725 第二晝素電極 226、 426 、 526 、 626 、 726 、 826 溝槽 227 偶合電容 228 、 328 、 528 、 628 ' 828 偶合電極 229 ' 329 、 429 、 430 液晶層 230 液晶分子 231 半導體圖案 250 閘極 251、 261 、 351 、 361 、 451 、 461 閘極絕緣層 252 、 352 、 452 没極 253 、 263 源極 254 ' 264 ' 364 鈍化層 255 、 455 第一通孔 291 、 491 第二通孔 292 、 492 第三通孔 293 、 393 、 493 第四通孔 494 > 494 公共電極 707 第一存儲電容 708 第二存儲電容 709 第一液晶電容 718 第二液晶電容 719 分壓電阻 728 28Figure 13 is a plan view showing the planar structure of a liquid crystal display substrate of the present invention. FIG. 14 is a cross-sectional view of the thin film transistor substrate shown in FIG. 13 taken along the XIV-XIV direction. FIG. 15 is a cross-sectional view of the thin film transistor substrate of the third embodiment of the present invention. Figure 16 is an equivalent circuit diagram of a sub-cell unit of a fifth embodiment of the liquid crystal display device of the present invention. Figure 17 is a liquid crystal display of the present invention. Figure 18 is an equivalent circuit diagram of a sub-cell unit of the liquid crystal display device of Figure 17. Figure 19 is equivalent to a sub-dielectric unit of a seventh embodiment of the liquid crystal display device of the present invention. Circuit diagram. [Main component symbol description] Sub-cell unit 20' 70 First sub-cell area 78 Second sub-cell area 79 Liquid crystal display device 200, 300, 400 '500, 600, 700, 800 color filter substrate 201 thin film transistor substrate 202, 302, 402 first substrate 210 color filter 213 common electrode 215 protrusion 219 second substrate 220, 320, 420 scan lines 221, 321 , 521 621, 721 data lines 222, 322, 422, 722, 822 first thin film transistors 223, 523, 623, 723 27 200909963 second thin film transistors 224, 524, 624 '724, 824 first halogen electrodes 225, 625 725 second halogen electrode 226, 426, 526, 626, 726, 826 trench 227 coupling capacitor 228, 328, 528, 628 '828 coupling electrode 229 '329, 429, 430 liquid crystal layer 230 liquid crystal molecule 231 semiconductor pattern 250 Gate 251, 261, 351, 361, 451, 461 gate insulating layer 252, 352, 452 electrodeless 253, 263 source 254 '264' 364 passivation layer 255, 455 first via 291, 491 second via 292, 492 third through hole 293, 393, 493 fourth through hole 494 > 494 common electrode 707 first storage capacitor 708 second storage capacitor 709 first liquid crystal capacitor 718 second liquid crystal capacitor 719 voltage dividing resistor 728 28