TW200908233A - Three dimensional NAND memory and method of making thereof - Google Patents

Abstract

A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

Description

200908233 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor devices and, more particularly, to three-dimensional anti-strings and other three-dimensional devices. [Prior Art] In IEDM Pr〇C (2〇01), pages 33 to 36, τ End〇h et al. titled "Novel Ultra High Density Memory With A Stacked-Smrounding Gate Transistor (S_SGT) structured CeU" In the early days, I did not reveal the two-dimensional vertical anti-string. However, this inverse string provides only 7 Gbits per cell. In addition, the area of action of the "reverse string" includes a relatively difficult and time consuming process of repetitive formation of sidewall spacers and portions of the substrate (4) which result in a generally conical shaped region shape. [Summary of the Invention]

According to an embodiment of the invention, a region of the semiconductor-active region of the bulk cell above the second memory cell is acted upon by the semiconductor semiconductor active region such that the active region and the second memory cell are at a boundary. The monomer, three-dimensional inverse and string comprise a first memory unit. Having a first memory formed between a semiconductor of a first memory cell of a second memory cell as a boundary between at least the first memory of the second memory cell according to another embodiment of the present invention The semi-second of the unit. The monomer, the three-dimensional inverse and the string comprise at least one first memory unit, wherein the conductor active region comprises a plurality of recrystallized according to another embodiment of the present invention, a single cell, a three-dimensional inverse and a string comprising 129933.doc 200908233 At least one first memory cell above the second memory cell, wherein at least one region of the inverted string is planarized. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following description is intended to describe the exemplary embodiments of the invention, and is not intended to limit the invention. Embodiments of the present invention provide a single, three-dimensional array of memory devices, such as arrays of vertical and vertical strings. In contrast, the strings are oriented vertically such that at least the memory cells are located above the other memory cells. The array allows vertical scaling of the device to provide a higher density of memory cells per unit area or other semiconductor material. Preferably, the non-volatile memory contains two charge collection memory cells (such as "SONOS cells" per 4F2 in each memory level. Therefore, the four memory cell level configuration will have an area of 〇.5F2 per cell. Or each cell has a binary bit of 〇5F2. The array ^ has two or more cell levels, such as two to eight levels. Therefore, the N memory cell level configuration will have 4f2/2n per cell. Area. If necessary, each of the counter-selected transistors may also be individually integrated into each of the opposite and/or below the memory cells. The monolithic three-dimensional memory array is in, for example, a semiconductor wafer. An array of a plurality of memory levels is formed above a single substrate (without an intervening substrate). The term "monomer" means that each layer of the array is deposited directly on the layer of each of the underlying layers of the array. The two dimensional arrays can be formed separately and then packaged to form a non-single memory device. For example, $, as in Leedy "Three Dimensional Structure Memory·· ^ ^ ^ 129933.doc 200908233, No. 5,915 '167, has been constructed by forming a memory level on a separate substrate and overlapping the memory levels on top of each other. Non-monomer stacked memory. The substrate can be thinned or removed from the memory level prior to bonding, but because the memory levels are initially formed over a separate substrate, such memory is not a true monolithic three dimensional memory array. The preferred stylization and erasure method for the inverse string is tunneling via F〇wier_N〇rdheimrTN"). Multiple % state types or mirror bit types are also used to reverse the string multi-level cell ("MLC") operation. Therefore, the array contains two bits per 叩2 in each memory level and further provides scaling by vertically integrating multiple memory levels. Each charge collection memory unit can provide a large margin And high-performance binary operation. Further efficiency is provided by the fact that the selection transistor can be vertically integrated and one or two selectable transistors can be completely omitted. Selecting the vertical integration of the transistor is eliminated for each device. Any break in the regular line and spatial pattern of the mask of the level. There is no rule of the entire memory array and the continuity of the line and space of the complete periodicity, thereby allowing small device features with narrow spacing formed by lithography. Contrary to prior art two-dimensional flat reversal devices, there is no need to create additional space for the end of the cross and the end of the space. The deuterated embodiment includes having The configuration of the selected gates in the trenches of Shixi wafers or other substrates does not have the configuration of selecting gates (ie, no gates are selected and no transistors are selected), and only has gates selected. The configuration of the pole 'only has the configuration of selecting the gate source and the configuration with two selected gates. Selecting the gate line with respect to the orientation of the source line, the bit line and the word line is 129933.doc 200908233 The orientation can vary in various configurations. As will be described below, even non-orthogonal orientations of the various lines with respect to each other are possible. In some embodiments, the source lines can be replaced by a common source region, which is on the substrate. The two dimensions of the plane extend and provide higher current draw capability at the expense of not being able to select individual source line voltages. The orientation of the memory levels relative to each other can also be changed. For example, each memory level can have Word lines oriented in the vertical direction with respect to the upper level and the lower level. Fig. 1A and Fig. 1B illustrate a first step in the method of fabricating the inverse and string according to the first embodiment of the present invention. Fig. 1A is a plan view and Fig. 1B for Figure ib illustrates a side view of a line A_A extending parallel to the word line. Figure ib illustrates a p-type germanium substrate 含有 containing an n-type germanium layer 3 adjacent to the surface. It should be noted that the inverted type and the n type can be reversed. A semiconductor material such as gallium arsenide other than germanium may be used in the region. The substrate 1 and layer 3 preferably comprise a single crystal germanium. The n-type layer may be grown by a blanket ion implantation or suspension on a germanium substrate. The layer 3 is formed. The active regions in the substrate 1 are separated from each other by the insulating isolation regions 7. Any suitable isolation regions 7, such as LOCOS yttrium oxide or STI oxide filled trenches may be used. Preferably, the substrate i The pn junction with layer 3 is above the bottom of isolation region 7 (such as above the bottom of the STI trench) to enable the voltage of each active device to be independent of the other devices. By patterning and etching standard STI channels Ditching, performing heat or radical inner wall isolation layer oxidation, depositing trench fill oxides and forming STI isolation by flattening the fill oxide with respect to the top of the germanium layer 3 by any suitable planarization method such as chemical mechanical polishing (CMP) Area 7. 2A and 9(9) illustrate a second step in the method of making the inverse string. Figure '29933.doc 200908233

2A is a top view and FIG. 2B is a side cross-sectional view along line A_A extending parallel to the word line in FIG. 2A. As shown in Fig. 2B, the ruthenium layer 9 is epitaxially grown on the active region 5 exposed between the isolation regions 7. The active region 5 acts as a seed for the epitaxial growth of the layer 9. Therefore, the grain boundary 丨丨 in the layer 9 is formed over the isolation region 7, and the single crystal germanium region in the layer 9 is formed above the active region 5. Layer 9 contains a p-type region 15 between n-type regions 13 and 17. Can you borrow during the growth period? The doped concentration in the precursor gas of the variator is used to dope the layer in situ. This 6-shape forms npn structures 13, 15, 17 which will later define the source/channel/drain regions of the vertical sidewall M?s selection transistor. Other forms of ion implantation or doping of the various layers 13 to 17 are also possible but result in a more complex process. The n-type region 13 is in electrical contact and the physical contact layer 3 is n-type active region 5. Figure 3 and Figure 3 illustrate the third (four) of the method of making the inverse and string. Figure 3 is a side elevational cross-sectional view of the top view and the line (4) extending along the line from the line parallel to the word line. % shown in Fig. 3, the layer 9 is planarized by a __ suitable planarization method such as cMp to provide a flat upper surface. Figure 4A and Figure 4 illustrate the fourth step in the method of making the inverse and string. Figure 4 is a top plan view and Figure 4A is a side cross-sectional view taken along line extending parallel to the word line in Figure 4A. The crystal layer 9 is patterned into strips _. As used herein, the term "strip" refers to a body having a length that is much greater than the thickness or width and that extends in one direction along the length. As will be described in more detail below, the stripes 19 along the bit in the first embodiment The line direction is extended by forming a mask over the layer 9 (such as a photoresist mask patterned by photolithography) and (4) the unmasked portion of the layer 9 (4) into a shackle. Figure 129933.doc As shown in 200908233 and Fig. 5, the patterning of the stripes is not necessarily automatically aligned with the active area 5 below. Preferably, but not necessarily, the strips 19 are not aligned with the active area 5 such that the strips 19 laterally pass over the active area 5 and The isolation region extends above (as shown in Figure 5B) 'and/or such that portions of the active region 5 are exposed below the stripes 19 (as shown in Figure 5A). Figures 5A and 5B illustrate the fabrication of the reverse and string The fifth step of the method. Fig. 5A is a plan view and Fig. 5B is a side cross-sectional view along line a_a extending parallel to the word line in Fig. 4A. As shown in Figs. 5A and 5B, insulation such as yttrium oxide is shown. Layer and/or another insulating layer 2 1 is deposited between the stripes The top surface of the stripe 9 is planarized. The insulating layer 21 can be planarized by CMP or other planarization methods such as etch back. Figures 6A through 6D illustrate the sixth step in the method of making the inverse and string. 6A is a plan view and FIG. 6B is a side cross-sectional view taken along line _a of FIG. 6A extending parallel to the word line. FIG. 6C is a line BB extending parallel to the bit line in FIG. 6A. Figure 6D is a three-dimensional view of the device shown in Figures 6A through 6C. The strips 19 and portions of the insulating layer 21 between the stripes 19 are flattened to the direction of the word line. And a stripe 23 extending perpendicular to the stripe 19. By forming a mask over the stripe 19 and the insulating layer 21 (such as a photoresist mask patterned by photolithography) and etching the strip 19 and the layer 21 The strips 23 are formed by portions of the mask. The strips 23 are composed of semiconductor pillars 25 spaced apart from adjacent pillars by portions of the insulating layer 21 in the word line direction. Each 129,933. Doc -12- 200908233 The pillars 25 are in the direction of the bit line by the trenches 27 between the pillars and the adjacent pillars Each of the pillars 25 has a p-type conductivity semiconductor region 丨5 between the n-type conductivity type semiconductor regions 13, 17 in the vertical direction (that is, with respect to the substrate 1, the region 15 is in the region) 13 is above and below the region 17.) Preferably, as shown in Figure 6A, each of the pillars 25 has a square or rectangular cross section when viewed from the top. Thus, each of the pillars 25 is preferably There are four vertical sides. Fig. 7A to Fig. 7C illustrate the seventh step in the method of making the reverse and the string. Fig. 7A is a top view and Fig. 7A is a side cross section of the line Α_Α extending along the line parallel to the word line in Fig. Figure. Figure 7C is a side cross-sectional view of the line Β-Β extending parallel to the bit line in Figure 7A. As shown in Fig. 7C, a gate insulating layer 29 is formed in the trench 27 between the pillars 25 and formed over the top surface of the pillar 25. The gate insulating layer 29 may comprise hafnium oxide, tantalum nitride or any other suitable gate insulating material. Layer 29 may contain two or more sub-layers having different compositions, if desired. A select gate layer is then deposited over the gate insulating layer 29. One or more of any suitable gate electrode materials may be used for the select gate layer, such as, for example, ruthenium, telluride (titanium telluride, etc.), tungsten, aluminum, or a combination of sublayers of such materials. The select gate layer is then planarized with respect to the top of the gate insulating layer 29 by any suitable planarization method such as CMP. As shown in Figure 7C, the planarization leaves a selection gate 129933.doc 200908233 pole 31 in the portion of the trench 27 above the gate insulating layer 29. 8A to 8C illustrate an eighth step in the method of making the inverse string. Figure 8A is a top plan view and is a side cross-sectional view of the line μ extending parallel to the word line in Figure 8A. This is a side cross-sectional view of line B - B extending parallel to the bit line in Figure 8-8. The tf' selection interpole 3i is partially returned as shown in Fig. 8C such that the top of the selected gate is located below the top of the pillar 25. A selective (iv) gate material may be selectively used above the material of the gate (four) edge layer 29 to circumscribe the remaining gate 3 1 . 9A to 9C illustrate the ninth step in the method of making the opposite. Figure 9A is a top plan view and is a side cross-sectional view of the line μ extending parallel to the word line in force diagram 9A. Figure 9C is a side cross-sectional view taken along line B-B of Figure 9 parallel to the bit line. An insulating top layer is deposited over the recessed select gate 3 i and over the gate insulating layer 29. Preferably, the cap layer comprises the same material as the gate insulating layer 29, such as hafnium oxide. The cap layer is then planarized (e.g., CMP planarized) to fill the trench above the select gate 31 and form an insulating cap 33 over each of the select gates 31. The top cover 33 electrically isolates the select gate from the reverse memory memory cell that will be formed above. During the planarization of the top layer, portions of the gate insulating layer 29 over the semiconductor pillars 25 are also removed to expose the top regions 17 of the pillars 25. As shown in Figure 9A, select gate 3 1 includes a portion of the select gate line that extends in the direction of the word line. Thus, the select gate line includes a striplined line located in the trench 27 (shown in Figure 6A). Each of the selection gates 3 is charged. 129933.doc -14- 200908233 When used for the gate electrodes of the two adjacent selection transistors 35 on the left and right sides of the gate 3! in Fig. 7C. Therefore, the ninth step is completed to select the transistor Μ for the bottom of the string. Each of the selected field effect transistors 35 includes a region of action of the pillars 25 (wherein region 15 acts as a channel and regions 13 and 17 act as "sources, and "dippoles, regions"), acting as gate electrodes for the transistors The gate 31 and the gate insulating layer 29 between the selection gate 31 and the pillar 25 are selected. Since each pillar is located between two different selection gates 31, each pillar 25 is The left and right sides can be viewed as acting on the same counter-and-string independent selection transistor 35 to be formed over the pillars 25. Figure 10A to Figure 10C illustrate the tenth step in the method of making the inverse and string. Figure 10A is a top view 1B is a side cross-sectional view along line AA extending parallel to the word line in FIG. 1A. FIG. 1〇c is a line BB extending parallel to the bit line in FIG. A side cross-sectional view. Figures 10A through 10C illustrate a first step of forming a memory cell 70 over a selective transistor 35. First, it is preferred to clean the exposed surface of the exposed pillar 25 after the CMP step in 圊9C. For example, the top surface of each column can be treated by thermal oxidation or free radical oxidation. (ie, to form a hafnium oxide layer on top of the pillars), followed by wetting, gentle oxide etching to remove the oxide layer along with damage that occurs during CMp and/or dry etching to surface Prepare for the growth of the next epitaxial layer. This damage can affect the quality of the subsequent epitaxial layer growth. Next, as shown in FIG. 10A to FIG. 1c, the growth is performed on the completed gate crystal 35. - epitaxial layer 109. Forming the first inverse memory block 129933.doc • 15· 200908233 The subsequent steps are similar to the method steps shown in Figures 2 to 9, except that instead of the gate insulating layer 29, charge storage is formed. Outside the region. As shown in Fig. 10B and Fig. 1c, the germanium layer 109 is epitaxially grown on the pillar action region 25 exposed between the isolation regions formed by the insulating layers 2, 29 and 33. In contrast, plasma assisted epitaxy (i.e., PECVD) can be used to grow the germanium layer 1 at lower temperatures (such as at 7 Torr < t & lower temperatures, e.g., at about 650 C). 〇 9. Although higher temperature growth treatment can be used, low temperature PECVD treatment It is permissible to use lower thermal budget metals and dielectric shells (ie, metals and dielectrics that are not compliant with the temperature of 〇〇.) and provide greater controlled joint depth and channel length. The exposed box-shaped upper surface of the object application region 25 serves as a seed crystal for the epitaxial growth layer 109. Therefore, the grain boundary ill in the layer 1〇9 is formed over the isolation region 7, and is formed over the active region 25. The single crystal germanium region in layer 1〇9. The grain growth of layer 109 rapidly increases from the underlying seed crystal 25 and forms a grain boundary 丨丨j where the grains meet each other during the epitaxial treatment. The position of the boundary Π 1 will be where the random grains meet and the grain boundaries 111 will generally not be as smooth and predictable as schematically illustrated in Figures 10A-10C. However, the grain boundaries are located in regions that will be etched away during subsequent steps. Therefore, high levels of smoothness and predictability are not required. Layer 109 contains a p-type region 115 between the bit-shaped regions 113 and 117 in the vertical direction. Layer 1〇9 may be doped in situ by varying the dopant concentration in the precursor gas during growth. In this case, the ηρη structures 113, 115, 117 of the source/channel/drain regions of the charge-collecting MOS memory device (i.e., opposite to the memory cells) will be defined. Ion implantation or doping of various types 129933.doc -16- 200908233 Other forms of layers 11 3 to 11 7 are also possible but result in a more complicated process stream %. The n-type region 113 is in electrical contact and physically contacts the n-type active region 17 in the pillar 25. Fig. 11A to Fig. 11C illustrate the eleventh step in the method of making the inverse and the string. Figure 11 is a plan view and Figure 11 is a side cross-sectional view of the line Α-Α extending parallel to the word line in Figure UA. Figure nc is a side cross-sectional view of the line Β-Β extending parallel to the bit line in Figure η. As shown in Figures 11A and 11C, the epitaxial layer 9 is planarized by any suitable planarization method, such as CMP, to provide a flat upper surface. Figures 12A through 12C illustrate the twelfth step in the method of making the inverse and string. Fig. 12A is a plan view and Fig. 12 is a side cross-sectional view taken along line A-A extending parallel to the word line in Fig. 12A. Figure 12C is a side cross-sectional view along line B-B extending parallel to the bit line in Figure 12A. The worm layer 109 is patterned into stripes 119. As used herein, the term "strip" refers to a body having a length that is much greater than the thickness or width and that extends in one direction along the length. As will be described in more detail below, the stripes 119 in the first embodiment are oriented along the bit line The stripe 119 is formed by forming a mask over the layer 109 (such as a photolithographic patterned photoresist layer) and etching the unmasked portion of the layer 109. As shown in Figures 12A-12C It is shown that the patterning of the stripes is not necessarily automatically aligned with the lower pillar action region 25. Preferably, but not necessarily the 'stripes 11 9 are not aligned with the active region 25' such that the stripes 119 laterally pass over the active region 25 and are surrounded by The isolation regions formed by layers 21, 29, and 33 of pillars 25 extend above (as shown in Figures 12B and 12C), and/or such that portions of 129933.doc • 17-200908233 of active region 25 are exposed below stripes 119. (shown in Figure 2a). Figures 13A through 13C illustrate a thirteenth step in the method of making the inverse and string. Figure 13A is a top view and Figure 3A is a line extending along parallel to the word line in Figure 13A. Side cross-sectional view. Figure] 3C A side view of the line BB extending parallel to the bit line in Fig. 3 A. As shown in Fig. 1 3 A to 1 3 B, an insulating layer such as an oxidized oxide layer and another insulating layer 121 Adjacent to the exposed lateral sides of the strips 119, deposited between the stripes 119. The layer stack 21 is then planarized with respect to the top surface of the strips 9. The insulating can be planarized by CMP or other planarization methods such as etch back. Layer 121 ° Figures 14A through 14C illustrate a fourteenth step in the method of making the inverse and string. Figure 14A is a top view and Figure 14 is a side cross-sectional view along line AA extending parallel to the word line in Figure 14A. Figure 14C is a side cross-sectional view taken along line BB extending parallel to the line 7L in Figure 14A. The portion of the insulating layer 12 1 between the stripes 11 9 and the stripes 11 9 is patterned parallel to the word line direction and A stripe 丨 23 extending perpendicular to the stripe 丨丨 9. A mask (such as a photolithographic patterned photoresist layer) is formed over the stripe 119 and the insulating layer 121 and the strip 119 and the layer 121 are etched. The unmasked portion forms a stripe 123. The stripe 123 is composed of a semiconductor pillar 1 25, half The body pillars 25 are spaced apart from the adjacent pillars by a portion of the insulating layer 121 in the direction of the word line. Each of the particles 12 5 is in the direction of the bit line by the trench m between the pillars and the adjacent pillar Each column 125 includes a p-type conductivity semiconductor 129933.doc -18-200908233 region 115 (ie, region 115) located between the n-type conductivity type semiconductor regions 113, 117 in the vertical direction. The substrate is above the region 113 and below the region 117). Preferably, as shown in Figure 14A, each of the pillars 125 has a square or rectangular cross section when viewed from the top. Therefore, each of the pillars 125 preferably has four vertical sides. /

The 'U diagram MA to Fig. 15C illustrates the fifteenth step in the method of making the inverse and the string. Fig. 15A is a plan view and Fig. 15B is a side cross-sectional view of the line Α·Α extending parallel to the word line in Fig. 15. Figure 15 (is a side cross-sectional view of the line B_B extending parallel to the bit line in Figure 15 VIII. As shown in Figures 15A to 15C, a charge storage region is formed between the stripes 123. Charge storage region A dielectrically isolated floating gate or dielectric charge storage material may be included. For example, to form a dielectric isolation floating, a polycrystalline layer is deposited between two insulating layers, such as an oxygen cut-through barrier layer. Shi Xi: In other words, 'the floating space formed by the sidewall spacers can be used. The extra space occupied by the spacer floating gate can be compensated by staging the two = early element (MLC) for these devices. a dielectric charge storage region that deposits a charge storage dielectric layer between the via and the barrier dielectric (also: two-edge) layer. For example, the electrical layer may comprise a gas-cut layer and the barrier layer may comprise oxidation The layer of the layer formed by the "S〇NOS" type device is thinner than the barrier dielectric layer. What is the storage area? The preferred example is the material other than the nitrogen (oxygen) oxygen cut. The device of this type is disclosed in the Wu Guo patent No. M5M99, which is incorporated by reference in its entirety. A high dielectric constant insulating material such as a material having a dielectric constant higher than 129933.doc •19-200908233 3.9 can be used in place of and in addition to the oxide layer. These materials include a metal oxide layer. 'such as oxidized, oxidized, oxidized, oxidized, oxidized or oxidized. The electrical storage medium may or may comprise a layer of nitrogen oxynitride, and the portion of nitrogen in the nitrided f layer is replaced by oxygen. Alternatively, a metal oxide layer such as an oxidation group, an oxidation oxidization or a ruthenium oxide may be used as the charge storage dielectric. In the following discussion, the 〇Ν〇 charge storage region 1 will be described, and it should be understood that a charge storage region or other combination of dielectric charge storage materials. As shown in FIG. 15C, the pass-through dielectric layer 128, the charge storage dielectric layer 129, and the barrier dielectric layer m are formed in the pillars in this order. (2) Between the trenches U7 (also V _ near the exposed side of the pillars) and the top of the pillars 125 and above the surface of the pillars _ _ _. The tunneling and blocking dielectric may contain yttrium oxide And the charge storage dielectric may comprise tantalum nitride. " a control gate layer is deposited over the electrical layers 128 to 130. One or more of any suitable gate electrode material may be used for the control gate layer, such as polycrystalline m (tetra) titanium, etc.) n or such material The combination of layers 0 then planarizes the control gate layer by any suitable planarization method, such as CMP, with respect to the top of the tunneling layer 128. The planarization leaves trenches 127 above the dielectric layers 128-130. Control gate i3i in the portion. Control gate 13 1 is partially etched back such that the top of the gate is below the top of pillar 125. The ground button can be selected above the germanium dielectric layers 128 to 130. The selective material of the polar material is engraved with a gate of 1 3 来回. 129933.doc -20· 200908233 Next, an insulating cap layer is deposited over the gate of the recessed control, the gate of the gate, and the top of the dielectric. Preferably, the tombstone layer comprises the same material as the material of the barrier dielectric 130, such as oxidized stone. The cap layer is then planarized (e.g., CMP planarization) to fill the trench above the control gate ΐ3ι and form an insulating cap 133 over each of the select gates ]3] t + π ^ & ^. The top cover 133 electrically isolates the control gate from the additional reverse string memory cells that will be formed above. During planarization of the cap layer, portions of the germanium dielectric layers 128-130 above the semiconductor pillars 125 are also removed to expose the top regions 11 7 of the pillars 125. As shown in Fig. 15A, the control gate 131 includes a portion of the word line extending below the cap 133 in the direction of the word line. Therefore, the word line includes a stripe line located in the groove 127. Each of the control gates 131 serves as a gate electrode for two adjacent memory cells 13 5 on the left and right sides of the gate 1 3 1 in FIG. This situation is used to complete the memory unit 丨35 at the bottom of the string. Each memory cell 135 includes a region of action of pillars 125 (where region 115 acts as a channel and regions 11 3 and 11 7 act as "source" and "dip" regions), a control gate that acts as a gate electrode for the transistor The pole/word line 13A and a charge storage region such as the germanium dielectric layers 128-130 between the control gate 13 1 and the pillars 125. Since each pillar 125 is located between two different control gates i3 i , the left and right sides of each pillar 125 can be considered as a memory unit. Figure 16 illustrates a side cross-sectional view of the direction of the bit line along the finished vertical and the string. The second level of the memory unit 235 which is identical to the first memory unit 135 is in the first memory unit by repeating the processing steps 129933.doc • 21 · 200908233 ρ described above with respect to FIGS. 10 to 15 . Formed on 135 to form a multi-level vertical inverse and =. If necessary, an additional level of memory cells (e.g., two or six levels of memory cells) can be formed over the first level of memory 7L 135 by repeating the processing steps described above. A plurality of bit lines 137 are then formed over the upper level of the memory cell. The bit line 137 contacts the pillar action area of the upper level of the memory unit 70. For example, the single bit line 137 shown in Figure 16 extends perpendicular to the word lines 131, 23 1 of the memory cell. However, as will be described in greater detail below, bit line 137 can extend in other directions. Further, if necessary, the same method as that of the lower selection gate transistor 35 is used. The upper selection transistor can be above the upper level of the memory cell below the bit line 137. An upper selection transistor is formed in addition to or instead of the lower selection gate transistor 35. Thus, Fig. 16 illustrates a vertical inverse of the string 100 formed vertically above the substrate. One memory unit 235 is located in the upper device level and the other memory unit 135 is located in the lower device level, the lower device level being located above the substrate and below the first device level 23 5 . Since the active regions 125 and 225 are grown in different insect growth steps, there is a defined boundary between the semiconductor active regions 125 and 225. The boundary may include dislocations, grain boundaries or lateral offsets with respect to the pillars 225 of the pillars 125 at the boundaries. In contrast, it is described in IEDM Pr〇c (2001) on pages 33 to 36. The title of T. Endoh et al. is "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell" The vertical and reverse series are formed by a plurality of etching steps 129933.doc-22.200908233 in the same region of the substrate. Further, when viewed from the top, the cylindrical action area of the vertical memory and the serial memory unit fabricated by the above method has a versatile or rectangular cross section. This situation is provided for each of the cells - each of the green faces and two bits per k configuration. The cylindrical action region is formed by patterning the active layer into stripes and patterning the stripes into pillars. On the contrary, when viewed from the top, the active area of E_h et al. has a circular (four) plane. The active area is surrounded by a gate around one of the bits for each unit configuration. The semiconductor active region 25 of the selected transistor 35 comprises a pillar. The semiconductor active region 125 of the lower memory cell includes pillars that are not aligned with the selected transistor Μ: semiconductor active region 25. In the non-limiting embodiment shown in Figure 16, the active region 125 extends laterally across the semiconductor active region 25 of the selective transistor 35 in at least the direction. Similarly, the column active region 225 extends laterally across the column active region 125 of the unit 135 in at least a direction such that the pillars 125 are not aligned with the posts 225. The semiconductor active region of the memory cell 135 is a pillar 125 comprising a first conductivity type semiconductor region 115 between the second conductivity type semiconductor regions 丨13, i17. The semiconductor active region of the memory cell 235 is a pillar 225 comprising a first conductivity type semiconductor region 215 between the second conductivity type semiconductor regions 213, 217. The second conductivity type semiconductor region 213 in the pillar 225 contacts the second conductivity type semiconductor region 11 7 in the pillar 125. As shown in FIG. 16, in the lower memory cell 135, the first charge 129933.doc -23- 200908233 stores the n-type 129A adjacent to a side of the first conductivity type semiconductor region (1) in the pillar i 25 And positioning, and the first control gate 131 is positioned adjacent to the first charge storage dielectric 129. The second charge storage dielectric is positioned adjacent the opposite side of the first conductivity type semiconductor region η? in the pillar 125, and the second control gate 13 is positioned adjacent to the second charge storage dielectric 129B. There are two similar charge storage dielectrics in the upper memory unit 235 and two opposite sides of the region 2 of the control gates located in the pillars 225. Figures 17A and 17B illustrate side cross-sectional views of portions of a counter transistor selected in accordance with the present invention in place of the second and third embodiments, respectively. The figure illustrates a side cross-sectional view along the word line direction of the second embodiment, in which the lower selection transistor 35 is omitted. In this case, the bottom memory cell level is formed on the substrate. A side cross-sectional view of the bit line direction of the second embodiment of Fig. 2, wherein the selection gate 31 of the selection transistor 35 is formed in a trench in the substrate i. In this embodiment, the p-type substrate i contains an n_p_n structure 13, Μ, 17, which is formed by implanting n (tetra) sub ions into the substrate to leave a substrate 15 between the implanted n-type regions 13 and 17. Formed as a P-type region. Alternatively, the regions ΐ3 to 17 may be formed by the growth of the stray layer and the length of the d and the in-situ replacement during the growth. Then, the channel is formed by photolithography of the substrate type portion via the npn structure. The trench is filled with an insulating material such as oxygen cut. The insulating material is then patterned by photolithography and (iv) to form additional trenches in the material 2〇. These additional trenches are filled with a select gate material which is then planarized to form the select gate 31. If the selection of the transistor 129933.doc -24· 200908233 35 ' is omitted, the lowermost memory unit us can alternatively be formed in the trench.

In the alternative fourth embodiment, the pillar action regions 25, 125, etc. of the selected transistor and/or memory cell are formed by polycrystalline semiconductor material 9, 1 〇 9, etc., in the underlying pillar. An amorphous, microcrystalline or polycrystalline semiconductor layer such as a rare layer is formed thereon instead of forming an epitaxial semiconductor layer 9, 1G9 or the like on the underlying pillar. The amorphous, microcrystalline or polycrystalline semiconductor layer is then recrystallized to form a large grain polycrystalline semiconductor material layer such as a large grain polycrystalline germanium layer. Recrystallization can be carried out by any suitable annealing method such as thermal annealing in a furnace, laser annealing, and/or flash lamp annealing. As described above, this recrystallized layer is then patterned into pillar action regions 25, 125, and the like. The use of cryogenically deposited and recrystallized polycrystals allows the formation of active regions over metal wires or electrodes that cannot withstand high temperatures. Therefore, the semiconductor active region of the upper memory cell can be epitaxially formed on the semiconductor active region of the underlying memory cell, or the semiconductor of the first memory cell can be formed in the recrystallized polycrystalline spine Make two domains. The action region of the lowermost level of the memory cell is formed subtly, or the refinement of the lowermost level of the memory cell is formed by recrystallization on the semiconductor active region of the selected transistor. The active region of the selective crystal is formed in a staggered manner, or the active region of the selective crystal is formed by recrystallization over the substrate. The memory array is in the horizontal dimension. The upper limit is the RC time of the word line, the selection gate, the source line and the bit line. When the roar p is 丨 J1 J, the enemy is restricted. In contrast, the string is oriented vertically, and the channel region (showing p-region seven, non-domain 115, NMOS memory instance) is not grounded. Therefore, it is necessary to note the total body potential of the phone. The inversion layer on the (unselected) side of 129933.doc 200908233 can be established and used to facilitate anchoring the potential of the floating p-type body during various operations such as reading, programming, and/or erasing. . It is also possible to use highly doped and p-regions with steep junctions so that the floating bodies can be more strongly coupled to each other via thinner depletion regions. Another way to indicate the potential of the floating body is to leak current through its junction. In addition, the program suppression boost (b〇〇St) should be more efficient. However, it is possible to drive the columnar action area as opposed to boosting, thereby allowing a steeper junction. Each memory cell and selected transistor level is automatically aligned with itself. In other words, no separate alignment steps are required between device levels. In addition, each device level requires only two lithography steps... a first step of forming a first stripe and a second step of forming strips 123. The remaining features in each device level are formed by layer deposition and planarization. Thus, at least one region or layer of the string 100 and preferably a plurality of regions or layers are planarized by CMP and/or other methods. For example, for the cell 5, when the semiconductor active region 丨25 is in the form of the epitaxial layer 1〇9, it is planarized as shown in FIGS. 11B and 11C, so that the inverse string 1〇〇 and at least one The other insulating layer 121 adjacent to the m insulation is planarized as shown in FIG. 13B, and the charge storage dielectric 129' control gate 131 and the cap layer 133 are planarized as shown in FIGS. 15B and 15C. Therefore, in each of the cells 135, 235 and the like, at least five layers (the tunneling and the blocking dielectric are not calculated) are planarized by CMP. If necessary, the wafer substrate 丨 can be rotated 45 in all lithography steps. Take 129933.doc -26· 200908233. In this case, it is further provided that the wafer notch is not at the 12 o'clock position, and at the 1:3 〇 position, then the vertical sidewall channel will be on the [1〇〇] crystal plane, the same channel mobility. Each device level is not automatically aligned with the level below it. However, the phase-like region is deliberately expected to be the source-polar region for the material of the chain, so this situation has almost no consequences. Based on the thermal budget of the annealing associated with the various levels, the vertical dimension of each level and the position of the (9) junction in each layer can be different from the other levels. Semiconductor epitaxial growth and plasma oxygenation, such as low temperature growth of pecvd (such as temperatures below 700), can be used to minimize gradation to gradation. This situation also allows for a single high temperature anneal after all memory is formed and the gate level is selected. However, separate layer-by-layer annealing or multiple annealing steps for the memory/selection level can also be used. Annealing in a hydrogen atmosphere may also be performed as necessary. As described above, the pillars are preferably rectangular or square when viewed from the side. However, when the side walls of the trench are not vertical, the active layer such as the selective crystal column active region portion 5 will be in the form of a truncated pyramid having a rectangular or square bottom greater than the top. Therefore, a certain amount of misalignment will not result in a change in the contact area of the top of the - (iv) pillar with the bottom of the dream pillar of the layer above it. Figure 18A illustrates a circuit schematic of an array of inverse rates as described above. Figure (10) illustrates a portion of the circuit diagram of Figure 18A, but with the source lines, select lines, and word lines removed for clarity. 8A and 8B illustrate at least two levels of the selective transistor 35 on the substrate or in the trench in the substrate and the § memory element located vertically above the selected electrical anode 35. Each inverse string 129933.doc -27· 200908233 is depicted as a single row in which each level of the memory cell is above the overlay level below the memory cell. For example, the intermediate vertical inverse string 1 控制 controlled by the bit line 237 in the row includes the selection transistor 35 and four memory cells 135, 235, 345, and 445 located in the four levels. The electrification crystal 35 is connected to the source line SL in the column Ν + 1/2. The selection transistor 35 is controlled by the selected gate line 3丨 of the columns Ν and Ν+1. The lowermost memory cell 丨3$ is represented by a column of lines N and N+1 in vertical level 1 (shown as WL (N+X columns, z-level) in Figure 18A, such as for column N, The word line in level i is controlled by wl(n, 1)). The other memory cells 235, 335 and 445 are controlled by word lines 231, 331 and 441 in columns N and N+1 of levels 2, 3 and 4, respectively. The upper s-resonance unit 445 is electrically connected to the bit line 23 7 in the bit line row M. Therefore, each of the vertical inverse strings includes the selection transistor 35 and is vertically arranged. The hidden cells tl 1 35 to 445 'the memory cells are overlapped. The word lines 13丨 to 43丨 are not parallel to the bit line 237. For example, the word line extends perpendicular to bit line 237. However, word lines 131 through 431 extend parallel to at least one of source line 239 and select gate line 31, such as parallel to the source line and select gate line 31. In an alternate embodiment, the word lines in different vertical levels may extend in different directions from each other. For example, the word in memory cell level one may extend in a different direction (e.g., in the vertical direction) than the direction of word line 231 in memory cell level two. The word line side alternates between the body unit levels. For example, in the mother. 5, the lines in the first and third levels extend in the direction and extend at the sound level -u. The word line of the word (five) is in different directions. The line directions may differ from each other - to ninety degrees. This configuration can be used by 129933.doc -28- 200908233 to place the electrical storage location adjacent to different faces of the column active region adjacent to the memory cell level to reduce coupling between device levels (eg, 'charge Stored in layers 1 and 3 adjacent to the north and south of the column and stored adjacent to the east and west in levels 2 and 4 and stored in another alternative embodiment shown in FIG. The line, word line and source line are not parallel to each other. In other words, the bit line 237 is not parallel to the word line j 3 to 431, the word lines 131 to 431 are not parallel to the source line 239, and the source line 239 is not parallel to the bit line. For example, as shown in FIG. 19, word lines 13 j to 43 1 may extend perpendicular to source line 239, while bit line 237 is diagonally opposite to word line and source line (ie, Extending at an angle of 1 to 89 degrees, such as 3 to 6 degrees, such as 45 degrees. This situation allows various effective programs to be provided by increasing the source and bit lines of each of the inverted strings. Simultaneously program different multi-state VT levels to one of the same word lines Body unit. The current from each bit line is drawn to the individually selected source line, thus reducing the amount of current supplied to a particular source line. The diagonal position line of Figure 2 can have a ratio compared to Figures 18A and I8B. A narrow spacing between the bit lines shown. If necessary, the configuration is changed such that the word lines and the bit lines are perpendicular to each other and the source lines are diagonal. A source line can be formed at the top and a bit can be formed at the bottom. Element. This situation allows the formation of metal and/or diced rather than semiconductor source lines' which results in reduced current crowding due to lower resistivity source line material. Where necessary, 'all three types of lines can be They are not perpendicular to each other and extend diagonally with respect to each other. Preferably, the selection line is parallel to the word line. As shown in Figure 19, each memory cell has all of its memory cells in the array with its 129933.doc -29-200908233 Different related 胄 word lines, bit lines 纟 source line group σ, for example, s, parallel to the word line direction—all memory cells in the column are controlled by different bit lines and different source lines. Configuration allows even two fields in the field Each memory cell in the array is still individually programmed (alternatively stylized with each pair of adjacent cells) when the same word line is shared, because these 4 a I connections are different from each other. The group of line and source lines δ is exemplified by 5, and two adjacent units in the same row parallel to one source line are controlled by different bit lines. Because &, two adjacent units in the same line The same word line and source line but different bit lines are associated. If necessary, due to the use of bit-wise line control for the stylized unit, the ability to individually program each-memory unit is shown in Figure 19 In the configuration, the selection of the electrical body 3 1 may be omitted as appropriate. However, it is preferable to programmatically in each of the reversed strings 2 逐, where 'sequentially stylize alternate levels. In another alternative embodiment, the source line 239 may be replaced by a common source region (source plane) extending in two dimensions of the plane of the substrate (i.e., in the x-y plane). The common source region may comprise a common conductive plate in electrical contact with the pillar active regions 25 of all of the select transistors 35 of the array, such as highly doped monocrystalline or polycrystalline semiconductors, germanium and/or metal plates. If the selection of the transistor is omitted, the source plate contacts the pillar 25 of the lowest memory unit 135 level. The common source plate provides higher current draw capability at the expense of the ability to relax the selection of individual source line voltages. An alternate embodiment for MLC operation has source lines and bit lines extending in the same direction to provide for changing the entire anti-chain voltage on a bit-by-bit basis so that the programmatic ratio is being programmed to a lower Vt The unit of state is being faster programmed by 129933.doc -30· 200908233 to a higher ντ state unit. The source line and bit line voltages of the unit being programmed to a lower ντ state will be increased to delay the stylization of these single πs so that less stylized pulses will be used to program the 2D or 3D configuration The state of the entire collection. The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. The embodiments were chosen and described in order to explain the principles of the invention and the embodiments of the invention in the It is intended that the scope of the invention be defined by the scope of the claims BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2, 3Α, 4Α, 5Α, 6Α, 7Α, 8Α, 9Α, 10Α, 11Α, 12Α, 13Α, 14Α and 15Λ are steps for fabricating a device according to a first embodiment of the present invention. Top view. Figure IB, 2Β, 3Β, 4Β, 5Β, 6Β, 6C, 7Β, 7C, 8Β, . / 8C, 9B, 9C, 10Β, 10C, 11Β, 11C, 12Β, 12C, 13Β, 13C, 14Β, 14C, 15Β And 15C are side cross-sectional views of the steps of making the apparatus according to the first embodiment of the present invention. Figure 6D is a three dimensional view of the device being fabricated as shown in Figure 6. Figure 16 is a side cross-sectional view showing the direction of the bit line of the completed vertical reverse and string along the first embodiment of the present invention. 17A and 17B are side cross-sectional views showing portions of an anti-string access transistor according to a second embodiment and a third embodiment of the present invention. 129933.doc • 31 · 200908233 FIGS. 1 8 A and FIG. 1 9 illustrate circuit diagrams of the inverse and string of the embodiment of the present invention. Figure 1 8B illustrates a portion of the circuit diagram of Figure 18A, but with the source lines, select lines, and word lines removed for clarity. [Main component symbol description] I p-type germanium substrate 3 n-type fragment layer 5 active region 7 insulating isolation region / STI isolation region 9 germanium layer II grain boundary 13 n-type region / ηρ η structure 15 p-type region / ηρη structure 17 N-type region / ηρη structure 19 stripe 20 insulating material 21 insulating layer 23 stripe 25 semiconductor pillar 27 trench 29 gate insulating layer 3 1 select gate 33 insulating cap 35 select transistor 100 reverse string 129933.doc - 32- 200908233 109 worm layer 111 grain boundary 113 n-type region / npn structure 115 p-type region / npn structure 117 n-type region / ηρη structure 119 stripe 121 insulating layer 123 stripe / 125 semiconductor pillar / semiconductor active region 127 Channel 128 Tunneling Dielectric Layer 129 Charge Storage Dielectric Layer 129A First Charge Storage Dielectric 129B Second Charge Storage Dielectric 130 Barrier Dielectric Layer 131 Control Gate/Word Line K / 131A First Control Gate 131B second control gate 133 top cover layer/insulating cap 135 first memory unit 200 opposite string 213 second conductivity type semiconductor region 215 first conductivity type semiconductor region 217 Second Conductive Type Semiconductor Region 129933.doc -33- 200908233 225 Semiconductor Active Region/Column 231 Word Line 235 Memory Cell 237 Bit Line 239 Source Line 331 Word Line 335 Memory Unit 431 Word Line 129933. Doc -34-

Claims (1)

200908233 X. Patent application scope: 1. A single-body, three-dimensional anti-string and a string comprising at least one first memory unit above a second memory unit, wherein the first memory unit has a semiconductor active area Forming a crystal on one of the semiconductor active regions of the second memory cell such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell . 2. The reverse string of claim 1, wherein: the reverse string is formed vertically above a substrate; the first memory unit is located in a first device level; and the second memory unit is located at a location Above the substrate and in the second device level below the level of the first device. 3. The reverse string of claim 1 further comprising a selection transistor underlying the second memory unit. 4. The reverse of the request item 3, where: The selection transistor is located on the substrate or in a trench in the substrate; and the semiconductor active region of the second memory cell is staggeredly formed on one of the semiconductor active regions of the selected transistor. 5. The reverse string of claim 4, wherein: the semiconductor-using region of the selected transistor comprises a pillar having a square or rectangular cross-section viewed from above; and The tomb of the memory unit has a square-shaped view from the m-square; the area contains - the pillar of the semiconductor from which the transistor is selected; the pillar is not aligned with the region It extends laterally across the semiconductor active region of the selected transistor of 129933.doc 200908233. 6. The inverse of the string of claim 1, wherein: the semiconductor active region of the first § memory unit comprises a first pillar, the first pillar comprising a second conductivity type semiconductor region a first conductivity type semiconductor region; the semiconductor active region of the second memory cell includes a second pillar, and the second pillar includes a second region between the second conductivity type semiconductor regions a conductive type semiconductor region; a second conductivity type semiconductor region of the first pillar contacting one of the second pillar type second conductivity type semiconductor regions; and the first pillar is not aligned with the second pillar Extending the first pillar laterally across the second pillar. 7. The reverse string of claim 6, further comprising: an upper-first charge storage dielectric positioned adjacent to the first conductivity type semiconductor region in the first pillar; - (d) a gate adjacent to the first charge storage dielectric: a second charge storage dielectric positioned adjacent to the second conductivity type semiconductor region of the second pillar; a second control gate adjacent to the second charge storage dielectric: a two-cell, a three-dimensional inverse and a string 'containing at least ___. ^ ... - memory - memory located above a second memory unit The unit 'in which at least the first memory is early—the semiconductor active region comprises recrystallized polycrystalline lit. 129933.doc 200908233 9. The reverse string of claim 8, wherein: the reverse string is formed vertically above a substrate; the first memory unit is located in a first device level; and the first memory The body unit is located in a second level of the device above the substrate and below the level of the first device. 1 〇. For example, the inverse of the string of 8 is further included in the wiring and a selection transistor under the second memory unit. 11. The inverse of the string of claim 1 wherein: 忒 the selected transistor is located on a substrate or in a trench in the substrate; and the semiconductor active region of the β 第 § 体 体 unit includes recrystallization Polycrystalline seconds. 12. The inverse of the claim 11 wherein: the semiconductor active region of the 涫k electrification crystal comprises a pillar having a guarded / squared or rectangular cross section viewed from above; (4) The semiconductor active region of the two memory sheets s includes a pillar having a square or a rectangular cross-face when viewed from above, which is not adjacent to the semiconductor active region of the selected transistor and laterally crossed The semiconductor active region of the selected transistor extends. 13_, as in the reverse of the request item 8, wherein: the coin-memory single--I r zq----------------------------------------------- a first conductivity type semiconductor region between the regions. One of the semiconductor memory regions of the second memory cell includes an H-shaped object. The second pillar includes - a second conductive crack-like semi-conductive semiconductor 129933.doc 200908233 a first conductivity type semiconductor region between the regions; the first pillar ♦ one of the second conductivity type semiconductor regions contacting one of the second pillars of the second conductivity type semiconductor region; and the first The pillars are not aligned with the second pillar such that the first pillar extends transversely across the second pillar. 1 . The reverse string of claim 13 further comprising: a first charge storage dielectric positioned adjacent to the first conductivity type semiconductor region in the first pillar; a control gate positioned adjacent to the first charge storage dielectric; a second charge storage dielectric positioned adjacent to the first conductivity type semiconductor region in the second pillar; And a second control gate positioned adjacent to the second charge storage dielectric. 15. A monomer, three-dimensional inverse and string comprising at least one first memory cell located above a second memory cell, wherein at least the region of the inverse string is planarized. 16. The reverse string of claim 15 wherein: the inverse string is formed vertically above a substrate; 5 a memory unit is located in a first device level; and the second memory unit is located at Located in the second device level above the substrate and below the level of the device. 1 7 - The inverse of the string of claim 1 5 further includes a selection transistor located below the second memory unit. 129933.doc -4- 200908233 18. The reverse of the request item 7 and the string of the selected transistor are located on the substrate or in the substrate - in the trench, the semiconductor active region of the transistor A pillar having a square or rectangular cross section when viewed from above, and: the semiconductor active region of the first § memory unit comprises a column having a square or rectangular cross section from above And which does not extend in alignment with the semiconductor active region of the X-selective transistor and laterally across the semiconductor active region of the 4k electret. 19. The inverse of the claim 15 wherein: one of the first suffix unit semiconductor active regions comprises a first pillar 4 and the first pillar comprises a second conductivity type semiconductor region a first conductivity type semiconductor region between; a semiconductor active region of one of the first memory cells includes a second pillar '4 the second pillar includes - between the second conductivity type semiconductor regions a first conductivity type semiconductor region; one of the first pillars of the first conductivity type 35 semiconductor region contacts the first pillar of the 5H - the second conductivity type semiconductor region; the first pillar Not aligned with the second pillar such that the first pillar extends laterally across the second pillar; and the first pillar comprises recrystallized polysilicon or in the second The stone is grown on the column. 20. The inverse of the claim 19, further comprising: a first charge storage dielectric positioned adjacent to the first conductivity type semiconductor region in the first pillar; 129933.doc 200908233 a first control gate adjacent to the first charge storage dielectric; a second charge storage dielectric adjacent to the first conductivity type semiconductor region of the second pillar Positioning; and - the second control gate is positioned adjacent to the second charge storage dielectric. 21. The inverse of the claim 15 wherein the at least one region of the inverse of the flattened region comprises a semiconductor active region of the first memory cell. 22. In the case of the inverse of the string, the inverse of the string, wherein the inverse of the string to the ', the regional progress includes the first s-resonant unit - the control gate. 23. The reverse string of the item 22, wherein the at least one region of the inverted pixel and the string further comprises: one semiconductor active region of the second memory cell; one of the second memory cells Controlling the gate; and - an insulating layer that causes the opposing string to intersect at least the other adjacent edges. 24. A method for making a single, three-dimensional, and a string of squares, wherein the inverse string comprises a first portion above a second memory unit, and the method comprises: growing a semiconductor active region of the second memory cell; and in a growth step different from the step of growing the semi-solid X-conductor region of the second memory cell, 'in the second memory of the second hidden body The first semiconductor device is epitaxially grown on the semiconductor active region. 129933.doc 200908233 25. The method of claim 24, further comprising: forming the second memory unit over a substrate; X first. Forming a first-semiconductor layer on the semiconductor active region of the memory cell; planarizing the first semiconductor layer; patterning the first semiconductor layer into a first semiconductor strip extending in a first direction Forming a first insulating layer adjacent to the exposed lateral side of the first semiconductor stripe; patterning the first semiconductor stripe to form a first semiconductor pillar; forming a first charge storage dielectric, Positioning adjacent to a first exposed side of the first semiconductor pillar; forming a first control gate adjacent to the first charge storage dielectric; forming a second charge storage dielectric, Positioning adjacent to a second exposed side of the first semiconductor pillar; and forming a second control gate adjacent to the second charge storage dielectric. The method of claim 25, wherein: a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell, the first semiconductor pillar The body includes the semi-conductive region of the first memory unit 129933.doc 200908233; and the second conductivity type semi-conductive region. The first semiconductor pillar includes a first conductivity type semiconductor between the first body regions. The method of the first semiconductor pillar is further included: depositing over the first semiconductor pillar. a film and a control gate layer; the charge storage dielectric thinly planarizes the charge storage dielectric film and the control gate layer to expose the first semiconductor pillar and form the first charge storage dielectric and a second charge storage dielectric and the first control gate and the second control gate; partially etching the first control gate and the second control gate; and the first partially etched control gate and Forming a second insulating layer over the second partially etched control gate; and planarizing the third insulating layer to expose the first semiconductor pillar. 28. The method of claim 24, further comprising forming a selective transistor on a substrate or in a trench in the plate. The method of claim 28, further comprising: epitaxially growing on a semiconductor active region of the selective transistor - a second semiconductor layer; planarizing the second semiconductor layer; Patterning a second semiconductor strip extending in a first direction; forming a third insulating layer adjacent to the exposed lateral side of the second semiconductor strip; 129933.doc 200908233 Patterning the second semiconductor导体 a conductor columnar stripe to form a second half; f forming a third charge storage, one of the pillars being exposed to the side: adjacent to the second semiconductor power to form a third control room a fourth charge storage dielectric adjacent to the third charge storage dielectric, positioned adjacent to the second exposed side of the second semiconductor pillar; and forming a fourth control gate, The method of claim 29, wherein: the second semiconductor pillar comprises the second memory active region; The inclusions include - (4) a first conductivity type semiconductor region located in the second conductivity type body region. </ RTI> The method of claim 30, wherein the second semiconductor pillar is not aligned with the semiconductor active region of the first memory cell. 32. The method of claim 29, wherein the step of forming the selective transistor comprises: layering: crystallizing a third semiconductor on the substrate or in a substrate to planarize the third semiconductor layer; The third semiconductor layer is patterned into a third semiconductor stripe in a first direction; 129933.doc 200908233 forms a fourth insulating layer adjacent to the exposed lateral side of the third semiconductor stripe; patterning the third semiconductor Striping to form a third semiconductor pillar; forming a first gate dielectric positioned adjacent to the first exposed side of the third semiconductor pillar; forming a first selected gate, Adjacent to the first gate dielectric; forming a second gate dielectric positioned adjacent to the exposed side of the third semiconductor pillar; and opening/forming a second selected gate It is adjacent to the second gate dielectric. The method of claim 3, wherein: the third semiconductor pillar comprises the semiconductor active region of the selective transistor; and the second semiconductor pillar comprises a second conductivity type semiconductor region A first conductivity type semiconductor region between. The method of claim 33, wherein the third semiconductor pillar is not aligned with the second semiconductor pillar. 35. A method of making a single, three-dimensional, and string, which is included in a second. A first memory cell unit is formed over the hidden body unit, wherein at least one of the semiconductor functional regions of the first memory cell unit comprises a recrystallized polycrystalline stone. 36. The method of claim 35, further comprising: forming an amorphous germanium or polysilicon semiconductor active region of the first memory cell over the second memory cell; and 129933.doc -10· 200908233 The amorphous germanium or polycrystalline germanium semiconductor active region of a memory cell is recrystallized to form a multi-small semiconductor active region in which one of the first memory cells is recrystallized. 37. The method of claim 36, further comprising: forming a selection transistor on a substrate or a trench in the substrate; forming a second memory cell over the selected transistor An amorphous or a polycrystalline germanium semiconductor active region; and recrystallizing the amorphous or polycrystalline semiconductor active region of the hexa-implex unit to form one of the second memory cells to recrystallize The spar semiconductor operating area. 3. The method of claim 37, wherein: the semiconductor active region of the ^5 丨 丨 body unit comprises a first pillar, the first pillar comprising a semiconductor region of the second conductivity type a first conductive type semiconductor region; the semiconductor active region of the second memory cell includes a second pillar, and the second pillar includes a second region between the second conductivity type semiconductor regions a conductive type semiconductor region; a one of the first pillars of the second conductive type semiconductor region contacting one of the second conductive type semiconductor regions; and the first conductive material is not Aligned with the second pillar. 39. The method of claim 38, further comprising: forming a charge storage dielectric positioned adjacent to the first conductivity type semiconductor region of the first pillar; 129933.doc 200908233 forming - - controlling the gate 'position adjacent to the mass; the electrical storage dielectric forms a second charge storage dielectric positioned adjacent to the first conductivity type semiconductor region in the second pillar And forming a second control gate positioned adjacent to the second charge storage dielectric. 40. A method of making a single 'three-dimensional inverse and string, which includes: Forming a first memory cell over a second memory cell; and planarizing at least one region of the inverse string. The method of claim 40, further comprising: forming the second memory unit over a substrate; epitaxially growing a first semiconductor layer on a semiconductor active region of the second memory unit; Forming the first semiconductor layer; patterning the first semiconductor layer into a first semiconductor strip extending in a first direction; forming a first insulating layer adjacent to the exposed lateral side of the first semiconductor stripe Patterning the first semiconductor strip to form a first semiconductor pillar; forming a first charge storage dielectric positioned adjacent to a first exposed side of the first semiconductor pillar; forming a a first control gate adjacent to the first charge storage dielectric; 129933.doc -12- 200908233 forming a second charge storage dielectric adjacent to a second exposure of the first semiconductor pillar Positioning on the side; and forming a control gate that is adjacent to the first electrical storage medium. 42. The method of claim 41, wherein: the first semiconductor pillar comprises a semiconductor active region of the first memory cell; and the first semiconductor pillar comprises a second conductivity type semiconductor region A first conductivity type semiconductor region between. 43. The method of claim 42, further comprising: depositing a charge storage dielectric film and a control gate layer over the first semiconductor pillar; planarizing the charge storage dielectric film and the control gate a pole layer for exposing the first semiconductor pillar and forming the first charge storage dielectric and the second charge storage dielectric and the first control gate and the second control gate; partially etching The first control gate and the second control gate; forming a second insulating layer over the first partially etched control gate and the second partially etched control gate, and planarizing the first Two insulating layers to expose the first semiconductor pillar. 44. The method of claim 4, wherein the step of planarizing comprises planarizing by chemical mechanical polishing. A method of fabricating a semiconductor memory device, comprising: 129933.doc -13- 200908233 forming a selective transistor in a first device level using only two photolithography steps An array; and an array of memory cells formed in a second device level different from the first device level using only two additional photolithography steps. The method of claim 45, further comprising: forming a first photoresist layer over a first semiconductor layer; exposing the first photoresist layer via a first photolithographic mask; The semiconductor layer is patterned into a plurality of first stripes; a second photoresist layer is formed over the plurality of first stripes; and the second photoresist layer is exposed through a second photolithographic mask; a stripe patterning is selected to select a plurality of semiconductor pillar active regions of the array of transistors; a second semiconductor layer is formed over the array of selected transistors; and a third photoresist layer is formed over the second semiconductor layer Exposing the third photoresist layer via a third photolithography mask; patterning the second semiconductor layer into a plurality of second stripes; forming a fourth photoresist layer over the plurality of second stripes; Exposing the fourth photoresist layer via a fourth photolithography mask; and patterning the plurality of second stripes into a plurality of semiconductor pillars of the array of memory cells in the second device level region. 47. The method of claim 46, further comprising: forming a third semiconductor layer over the array of memory cells in the second device level; forming a fifth photoresist layer over the third semiconductor layer; 129933.doc 14 200908233 exposing the fifth photoresist layer via a fifth photolithography mask; patterning the third semiconductor layer into a plurality of third stripes; forming a sixth over the plurality of third stripes a photoresist layer; exposing the sixth photoresist layer via a sixth photolithography mask; patterning the plurality of third stripes into a plurality of semiconductor pillars of the array of memory cells in a third device level The area of action. 48. The method of claim 45, wherein the array package 3 of the semiconductor memory device is perpendicular to the array of strings. f 49. A monomer, three-dimensional inverse and string, comprising: a fifth memory unit located above a second memory unit; a selection transistor; a first word line of the first memory unit; a second word line of the second memory unit; a bit line; a source line; and one of the selection transistors selects a gate line; wherein: the first sub-line and the second word line are not parallel to The bit line; and the first word line and the second word line extend parallel to at least one of the source line and the select gate line. 50. The reverse string of claim 49, wherein: the reverse string is formed vertically above a substrate; the selection transistor is located on a substrate or in a trench in the substrate; the first memory unit is located In a first device level; and 129933.doc _ 15· 200908233 "- H single 70 is located in the second device hierarchy on the selected transistor and below the first device level. 51. And a string, wherein · X is a single body - the semiconductor action region is formed on the semiconductor active region of the second memory cell; "first. The semiconductor active region of the hidden body is epitaxially formed on one of the semiconductor active regions of the selective transistor; the first charge storage is located in the semiconductor active region of the first memory cell and the first word Between the lines; and - the second charge storage &quot; is located between the semiconductor active region of the second memory cell and the second word line. 52. The reverse string of claim 51, wherein: the semiconductor core region of the first memory cell comprises a first pillar, and the first pillar of the fifth core comprises a second conductivity type semiconductor region a semiconductor region between the first conductivity type; the semiconductor region of the second memory cell includes a second pillar; the second pillar includes a semiconductor region between the second conductivity type a first conductive type semiconductor region; the semiconductor active region of the selective transistor includes a third pillar; wherein one of the second conductive type semiconductor regions contacts the second pillar a second conductivity type semiconductor region; 'the first pillar is not aligned with the second pillar such that the first pillar extends laterally across the second pillar; and 129933. Doc -16- 200908233 The first weir is not aligned with the third pillar such that the second pillar extends transversely across the third pillar. 53. The reverse string of claim 49, wherein: the first word line and the second word line extend perpendicular to the bit line; and the first sub-line and the fifth second word line are parallel to the The source line and the selected gate line extend. 54. The reverse string of claim 49, wherein: the first word line and the second word line extend perpendicular to the bit line; and the first word line and the second word line are parallel to the source Extend the line. 55. The reverse string of claim 49, wherein: the first word line and the second word line extend perpendicular to the bit line; and the first word line and the second word line are parallel to the select gate Extends the polar line. 56. — A monomer, a three-dimensional inverse and a string, comprising: a first memory unit located above a second memory unit. a first word line of the first memory unit; and a second word line of the second memory unit; wherein: the word The line extends in a first direction; and the second word line is in a second direction different from the first direction. 5 7. As in the inverse of the request item 56, wherein: the inverse string is formed vertically in one Above the substrate; a selective transistor is located on a substrate or in a trench in the substrate 129933.doc -17· 200908233 the first, the memory unit is located in the first seismic level; and is first. The body is located in the second device level on the selected transistor and below the level of the first device. 58. The reverse string of claim 57, wherein: a semiconductor active region of the first memory cell is silly formed on the semiconductor active region of the first memory cell; X&quot; % of the semiconductor active region is crystallized on one of the semiconductor active regions of the selective transistor; a first charge storage dielectric f is located between the semiconductor active region of the (four)-memory cell and the first word line And a second charge storage dielectric is between the semiconductor active region of the second memory cell and the second word line. 59. The inverse of the claim 58 wherein: the semiconductor of the first memory cell comprises a long domain - the first pillar of the first pillar comprises a region between the second conductivity type semiconductor domains a first conductivity type semiconductor region; 亥 第一 第一 m m m 早 早 早 早 早 早 + + + + + + + + + + + + + + + + + m m m m m m m m m m m m m m a first conductivity type semiconductor region, the object; the 4 + conductor action region includes a third columnar distal first pillar - the first pillar is - the first pillar is not Contacting the second conductivity type semiconductor region with the second conductivity type semiconductor region; the first pillar is aligned such that the first 129933.doc -18-200908233 pillar laterally crosses the second pillar Extending; and the second pillar is not aligned with the third pillar such that the second pillar extends transversely across the third pillar. 6. The inverse of the request item 56, wherein the first word line extends perpendicular to the second word line. 61 _ - an inverse array, comprising: an array of vertical inverses and strings; a plurality of word lines; a plurality of bit lines; and a plurality of source lines; wherein: the bit lines are not parallel to the words Lines; the word lines are not parallel to the source lines; and the source lines are not parallel to the bit lines. 62. The array of claim 61, wherein: the word lines extend perpendicular to the source lines; and the bit lines extend diagonally about the word lines and the source lines. 63. The array of claim 61, wherein: the word lines extend perpendicular to the bit lines; and the source lines extend diagonally about the word lines and the bit lines. 6 4 - The array of claim 6 1 wherein: each of the vertical inverse strings comprises at least two vertically arranged memory sheets 129933.doc 200908233; and each vertical inverse string of each memory unit Each has a different combination of word lines, bit lines, and source lines than all other memory cells in the array. 65. An array of claim 64, wherein each memory cell in the array is adapted to be individually programmed. 66. An anti-array comprising: an array of vertical inverses and strings; a plurality of word lines; a plurality of bit lines; and a common source plane electrically coupled to the array of the vertical and the columns of the string, wherein the common source plane comprises an array of conductive ΰ f Wherein each of the guide plates in the lead string is electrically contacted with the vertical opposition 69. an actuating region of the selected transistor. a method of body, three-dimensional inverse and string, comprising: forming-selecting a transistor; a first word line of the first memory cell; a word line of the second memory; forming over the second memory cell - forming - for the first Forming a memory cell - for forming a second memory cell - a bit line; forming a source line; and selecting a polarity line for the selected transistor; 129933.doc -20- 200908233 wherein: The first word line and the second word line are not parallel to the bit line; and the first word line and the second word line extend parallel to at least one of the source line and the select gate line. 70. The method of claim 69, wherein: the reverse string is formed vertically above a substrate; &quot; the selection transistor is located on a substrate or in a trench in the substrate; The body unit is located at a first device level; and the 1-5 unit is located in a second device level on the selection transistor and below the device level. 71. The method of claim 7, wherein: a = a semiconductor functional region of the first memory cell is epitaxially formed on a semiconductor active region of the first 5th memory cell; The 丨 conductor function of the body unit is formed on a semiconductor active region of the 5 Hz selective transistor; a first charge storage dielectric is located in the semiconductor active region of the first memory unit and the first Between the word lines; and the second charge storage dielectric is between the second memory conductor active region and the second word line. The method of claim 71, wherein: the semiconductor active region of the memory cell comprises a first pillar, the first pillar comprising a semiconductor region of the second conductivity type The first conductive type semiconductor region; the semiconductor active region of the DH first memory cell includes - the second pillar 129933.doc -21 - 200908233, the '5 haidi-column contains 'one-way Booklet i » ^ ^ ^ 〇5 W 孓 a first conductivity type semiconductor region between the conductive type semiconductor regions; the semiconductor active region of the selective transistor includes a third pillar; the first pillar One of the second conductivity type semiconductor regions contacts one of the second pillars of the second conductivity type semiconductor region; the first pillar is not aligned with the second pillar such that the first a pillar extends laterally across the second pillar; and the second pillar is not aligned with the third pillar such that the second pillar laterally crosses the third pillar Extending like a substance. 73. The method of claim 69, wherein: the first word line and the second word line extend perpendicular to the bit line; and the first word line and the second word line are parallel to the source line and The gate line is selected to extend. 74. The method of claim 69, wherein: f the first word line and the second word line extend perpendicular to the bit line; and the first word line and the second word line are parallel to the source line And extended. The method of claim 69, wherein: the first word line and the second word line extend perpendicular to the bit line; and the first word line and the second word line are parallel to the select gate line And extended. 76. A method of fabricating a single cell, a three-dimensional inverse, and a string, comprising: forming a first memory cell over the second memory cell; forming a first word line for the first memory cell 129933.doc -22· 200908233 / is used for the second word line of the second memory unit; forming a bit line; and forming a source line; wherein: the first word line extends in the first direction And the 5th second word line extends in a second direction different from the first direction. 77. The method of claim 76, wherein: the inverse is formed vertically above a substrate; the selective transistor is located on a substrate or in a trench in the substrate; / the fifth memory element is located in a In a device level; and the first upper suffix unit is located in a second device level on the select transistor and below the first device level. 78. The method of claim 77, wherein: ^ „海第—a semiconductor functional region of one of the memory cells is epitaxially formed on a semiconductor active region of the first memory cell; the first δ hexamor cell The semiconductor active region is epitaxially formed on the semiconductor active region of the 5H selection transistor; the charge storage dielectric is located in the semiconductor active region of the first memory cell. #&#; And a method of claim 78, wherein: ___^ a charge storage medium is located between the semiconductor active region of the second memory cell and the second word line. The semiconductor active region of the β海第C memory unit includes a first 枉129933.doc -23- 200908233 ′′ the first pillar includes a conductivity type of a 々, 罘, 罘a first conductivity type semiconductor region between the semiconductor regions; the semiconductor active region of the second memory cell includes a second pillar, the second pillar being located in the second conductivity type semiconductor region a first conductivity type semiconductor region; the semiconductor active region of the selective transistor includes a third pillar; the electrical conductivity type + conductor region of the first pillar contacts the second pillar a second conductivity type semiconductor region; the first pillar is not aligned with the second pillar such that the first pillar extends laterally across the second pillar; and the second The pillar is not aligned with the third pillar such that the second pillar extends laterally across the third pillar. 80. The method of claim 76, wherein the first word line is vertical Extending the second word line. 81. A method for fabricating an inverse array, comprising: forming an array of vertical inverses and strings; forming a plurality of word lines; forming a plurality of bit lines; and forming a plurality of a source line; wherein: the bit lines are not parallel to the word lines; the word lines are not parallel to the source lines; and the source lines are not parallel to the bit lines. J29933,doc -24- 200908233 82. The method of claim 81, wherein: The line extends perpendicular to the source lines; and the 5 haith bit line extends diagonally with respect to the word lines and the source lines. 83. The method of claim 8 1 wherein: The line extends perpendicular to the bit line; and the source line such as 5 hai extends diagonally with respect to the word line and the bit line. 84. The method of claim 81, wherein: The strings each include at least two vertically arranged memory cells; and each of the vertical and reverse memory cells has an associated word line, bit line different from all other memory cells in the array And source line combination. 85. The method of claim 84, wherein each of the memory cells in the array is adapted to be individually programmed. 86. A method of fabricating an inverse array, comprising: forming an array of vertical inverses and strings; forming a plurality of word lines; forming a plurality of bit lines; and forming a common source plane, electrically connecting the lines Vertically reverses each of the strings. 87. The method of claim 86, wherein the common source plane comprises a conductive plate 0 129933.doc • 25- 200908233 8 8. If the request item, &lt; 10,000, wherein the conductive plate is in the _ _ string Each of the electric plates is electrically contacted with the vertical opposition and 89. - a selective region of the transistor. Above the element: the third dimension and the string, which contains - located in the second memory - the memory unit, where: Party:! a semiconductor unit-semiconductor active region comprising - a first pillar from a first &quot;sub-rectangular rank cross section, the third layer comprising a second conductivity between the second conductivity type semiconductor regions Type semiconductor region; one of the square memory cells comprising a second pillar having a square or rectangular cross section, the pillar being located below the first pillar, the second pillar The first conductivity type semiconductor region between the second conductivity type semiconductor regions; and one of the second conductivity type semiconductor regions of the first pillar contacts the second pillar A two-conductivity type semiconductor region. 9. In the case of the inverse of the claim 89, the further step comprises - selecting the transistor below the second memory unit. 91. The reverse string of claim 90, wherein: the reverse string is formed vertically above a substrate; the selection transistor is located on a substrate or in a trench in the substrate; the first memory unit is located In a first device level; and the second memory unit is located in a second device level on the selection transistor and below the first device level. 92. The inverse of the claim 90, wherein: 129933.doc -26- 200908233 The semiconductor active region of the first memory cell of the hexa-helium is epitaxially formed on the semiconductor-active region of the memory cell The semiconductor active region of the second memory device is formed on the semiconductor active region of the selective transistor; a first charge storage dielectric is located in the semiconductor active region of the first memory cell Between a first word line and a second charge storage dielectric between the semiconductor active region of the second memory cell and a second word line. 93. The reverse string of claim 9 wherein: the semiconductor active region of the selective transistor comprises a third pillar; and the second pillar is not aligned with the third pillar The pillars are caused to extend laterally across the third pillar. 94. The reverse of the claim 90, wherein the string further comprises: a bit line; a source line; and one of the selected transistors selects the gate line. a second memory unit 95. - a monomer, a three-dimensional inverse and a string, comprising a first memory unit above a unit, wherein: a semiconductor active region of the first memory unit comprises a first pillar 'The first pillar comprises a first conductivity type semiconductor region between the second conductivity type semiconductor regions; one of the second memory cells + conductor acts 1 earth or contains _ is 1 columnar a second pillar under the object 'the second pillar comprises two first conductivity type semiconductor regions between the second conductivity type semiconductor regions; 129933.doc -27-200908233; a second conductivity type semiconductor region contacts one of the first conductive type semiconductor regions of the first pillar; and the semiconductor active region of the first s-resonant cell or one of the semiconductor functions of the selective transistor At least one of the regions is located in a trench in a substrate. 96. The inverse of claim 95, further comprising the select transistor, the selectable B body comprising the semiconductor active region in the trench in the substrate. 97. The reverse string of claim 96, wherein: the reverse string is formed vertically above a substrate; the selective transistor is located on a substrate or in a trench in the substrate; the first delta memory The unit is located in a first device level; and the first first δ memory unit is located in a second device level on the selection transistor and below the first device level. 98. The inverse of the claim 97, wherein: the material conductor of the first memory cell acts or is telecrystallized on a semiconductor active region of the first sth memory unit; the second memory The semiconductor active region of the bulk cell is formed on the semiconductor active region of the selective transistor; a first charge storage dielectric is located in the semiconductor active region of the first memory cell and a first word line And a second charge storage dielectric is located between the conductor 119933.doc -28-200908233 conductor active region and a second word line of the second memory unit. 99. The reverse string of claim 96, wherein: the semiconductor active region of the columnar δ ray select transistor comprises; and the second pillar is not aligned with the third pillar to cause the knuckle The pillar extends transversely across the third pillar. 100. The reverse string of claim 95, wherein the second semiconductor active region is located in the trench in the substrate. 101. A monomer, a three-dimensional inverse and a string, comprising a first memory unit above a one-L _, a first memory unit, wherein: a semiconductor active region of the first memory unit includes a a first pillar comprising a first conductivity type semiconductor region between the second conductor, and the like semiconductor region; the semiconductor active region of the second memory unit a second pillar under the first pillar, the second dome comprising a first conductivity type body region between the second conductivity type semiconductor regions; the first pillar a second conductivity type semiconductor region contacting one of the second pillars of the second conductivity type; and the first pillar is not aligned with the second pillar such that the first The pillar extends transversely across the second pillar. The reverse of the request item 101 and the string 'which further includes a selection transistor located below the second memory unit. 103. The reverse string of claim 1 〇 2, wherein: 129933.doc -29- 200908233 the reverse string is formed vertically above a substrate; the selection transistor is located on a substrate or the substrate is a trench The first memory unit is located in a first device level, and the second memory unit is located at a second device level located on the selection transistor and below the first device level. 104. The reverse string of claim 103, wherein: the semiconductor active region of the first memory cell is crystallized on a semiconductor active region of the second memory cell; the second memory cell The semiconductor active region is remotely formed on one of the semiconductor active regions of the selected transistor; a first charge storage dielectric is located between the semiconductor active region of the first memory cell and a first word line; a second charge storage medium ff is located between the semiconductor active region of the second memory cell and a second word line. 105. The reverse string of claim 102, wherein: the semiconductor active region of the selected transistor comprises a third pillar; and / the first pillar is not aligned with the third pillar such that The second pillar extends transversely across the third pillar. 106. The reverse of the claim 104, wherein the string further comprises: a bit line; a source line; and 之一 selecting one of the transistors to select the gate line. 107. The inverse of the request item 106, wherein: 129933.doc -30· 200908233 ^ the sub-line and the second word line extend perpendicular to the bit line and/the second sub-line and the second word line are parallel Extending in at least one of the source line and the select gate line. 108. The reverse of the string of claim 1 〇 4 wherein: the first word line extends in a first direction; and the second word line extends in a second direction that is different from the first direction. 109. A method of making a single-dimensional two-dimensional inverse and string, which is included in a second. Forming a semiconductor active region of a first memory cell above one of the semiconductor active regions, wherein: the semiconductor active region of the first sth memory cell includes a B-inch view from above a first dove of a square or rectangular cross-sectional surface, the first pillar comprising a first conductivity type semiconductor region between the ith conductive 纟 type 丨 conductor regions; The semiconductor active region contains a second weir having a square or rectangular cross section when viewed from the side, the second pillar being located under the first pillar, the second pillar comprising a region between the first conductivity type semiconductor regions a first conductivity type semiconductor region; and the second conductivity type semiconductor region of the first pillar contacts one of the second pillars of the second pillar-shaped semiconductor region. 110. If the request item 1 〇 9 is in the form of a palm, the method of forming a selective transistor is formed under the second memory unit. 111. The method of claim 11, wherein: 129933.doc • 31 - 200908233 the reverse string is formed vertically above a substrate; the selection transistor is located on a substrate or in a trench in the substrate; The first memory unit is located in a first device level; and the second memory unit is located in a second device level on the selection transistor and below the first device level. The method of claim 111, wherein: the semiconductor active region of the first memory cell is epitaxially formed on a semiconductor active region of the second memory cell; the semiconductor function of the second memory cell a region is epitaxially formed on one of the semiconductor active regions of the selected transistor; a first charge storage dielectric is between the semiconductor active region of the first memory cell and a first word line; and the first The storage medium is located between the semiconductor active region of the second memory cell and a second word line. 113. Such as Gu Jiejie 1 1 Λ &gt; bucket *, l - And the region includes a third column, the second column is not aligned with the third column, and the column lateral soil is also extended with the third column (four) to make the second 114. The method of claim 109, further comprising forming the second memory unit over a substrate; the semiconductor effect in the second memory unit; the second memory unit being a first semiconductor layer; Flattening the first semiconductor layer; 129933.doc -32- 200908233 - patterning the first semiconductor layer into a first semiconductor strip extending in a - direction - a coffee-forming insulating layer adjacent to a lateral side of the first semiconductor stripe; - patterning the first semiconductor strip to form the first pillar; forming a first charge storage dielectric adjacent to the first pillar Positioning on an exposed side; forming a first control gate adjacent to the first charge storage dielectric; forming a second charge storage dielectric adjacent to one of the first pillars Positioning on the side of the second exposure Forming a second control gate adjacent to the second charge storage dielectric, depositing a charge storage dielectric film and a control gate layer over the first pillar; planarizing the charge storage medium And the control gate layer to expose the first pillar and form the first charge storage dielectric and the second charge storage dielectric and the first control gate and the second Controlling the gate; partially engraving the first (four) gate A of the second control gate; forming a second insulating layer over the first partially etched control gate and the second partially etched control gate Flattening the first insulating layer to expose the first pillar; forming a selective crystal on the substrate or in a trench in the substrate 129933.doc -33· 200908233 in the selected transistor-semiconductor Forming a second semiconductor layer on the Q domain &lt;^ crystallizes; planarizing the second semiconductor layer; patterning the second semiconductor layer into a second semiconductor strip extending in the first direction; forming a first a third insulating layer adjacent to the a lateral side of the exposed portion of the semiconductor stripe; patterning the second semiconductor stripe to form a δ 弟 二 二 pillar; forming a second charge storage dielectric adjacent to the first exposure of the second pillar Positioning on a side surface; forming a second control gate adjacent to the third charge storage dielectric to form a fourth charge storage dielectric positioned adjacent to a second exposed side of the second pillar ; and quality. 115, a method of fabricating a single cell to form a fourth control gate adjacent to the fourth charge storage dielectric, two-dimensional inverse and string The semiconductor active region of the second memory cell includes a second pillar of the second type of electrically conductive semiconductor conductivity type semiconductor region; 129933.doc -34· 200908233 a second pillar comprising a first conductivity type body region between the first conductivity type semiconductor regions; and a second conductivity type semiconductor region in the f-column contact a second conductivity type semiconductor region in the two pillars; and at least one of the semiconductor active regions of the first sigma cell or the selected transistor of the selected transistor is located in a substrate — in the trench. 116. The method of claim 115, which further comprises forming the selected electro-optic. The electret transistor comprises a region of the semiconductor that is located in the trench in the substrate. 117. The method of claim 116, further comprising forming a selection transistor under the second memory unit. 118. The method of claim 117, wherein: the reverse string is formed vertically above a substrate The selection transistor is located on a substrate or in a trench in the substrate; the first memory unit is located in a first device level; and the second memory unit is located on the selection transistor 119. The method of claim 118, wherein: the method of claim 118, wherein: the semiconductor active region of the first memory cell is epitaxially formed in one of the second memory cells In the active region, the semiconductor active region of the second memory cell is epitaxially formed on one of the semiconductor active regions of the selected transistor; 129933.doc •35· 200908233 A first conductor acts on the electric prayer storage dielectric Qualitatively located between the first region and the first word line; and the half-charge storage dielectric of the memory cell is located in the conductor active region of the second memory cell 120. The method of claim 115, wherein the body-acting region of the second memory unit is located in the trench in the substrate. a three-dimensional anti-string method, comprising: forming a semiconductor active region of a first memory cell above a semiconductor active region of the second hidden body 7L, wherein: the semiconductor of the first memory cell The active region includes a first pillar - the pillar comprises a first conductivity type semiconductor region between the second conductivity type semiconductor regions; the semiconductor active region of the second memory cell includes a a second pillar located below the first column of the crucible, the second column comprising a bit 2 Between the second conductivity type semiconductor regions (4) - a conductive genus body region; a body region contact region; and one of the first pillars of the second conductivity type is a second one of the pillars The first type of pillars of the conductivity type semiconductor are not aligned with the second pillar such that the first pillar extends laterally across the second pillar. The method of claim 121, further comprising forming a selection transistor under the element. 123. The method of claim 122, wherein: the reverse string is formed vertically above a substrate; 129933.doc -36. 200908233 1 Hai selects the transistor on the substrate or in the trench in the substrate; The first S memory unit is located in a first device level; and the δ first memory unit is located in a second device level on the selected transistor and below the first device level. 124. The method of claim 123, wherein: the semiconductor active region of the first s memory cell is epitaxially formed on a semiconductor active region of the second memory cell; The semiconductor active region of the cell is epitaxially formed on one of the semiconductor active regions of the select transistor; a first charge storage dielectric is between the semiconductor active region of the first memory cell and a first word line And the first electrical storage medium is located between the semiconductor active region of the second memory unit and a second word line. 125. The method of claim 122, wherein: the semiconductor active region of the select transistor comprises a third pillar; and the first pillar is not aligned with the third pillar such that The second pillar extends transversely across the third pillar. 126. The method of claim 121, further comprising: forming the second memory unit over a substrate; depositing a first semiconductor layer on the semiconductor active region of the second memory unit; planarizing The first semiconductor layer is visualized as a J29933.doc-37·200908233 first semiconductor strip extending in a first direction; a first insulating layer is formed adjacent to the first semiconductor layer a lateral side of the exposed semiconductor stripe; patterning the first semiconductor strip to form the first pillar; forming a first charge storage dielectric adjacent to a first exposed side of the first pillar Positioning; forming a first control gate adjacent to the first charge storage dielectric; Forming a second charge storage dielectric positioned adjacent to a second exposed side of the first pillar; and forming a second control gate adjacent to the second charge storage medium. 127. The method of claim 26, further comprising: depositing a charge storage dielectric thin layer and a control interpole layer over the first pillar; planarizing the charge storage dielectric film and the control a gate layer to expose the first pillar and form the first charge storage dielectric and the second charge storage dielectric and the first control gate and the second control electrode; partially etching the a first control gate and the second control gate; forming a second insulating layer over the first partially etched control gate and the second partially etched control gate; and planarizing the second insulation A layer to expose the first pillar. 128. The method of claim 12, further comprising: 129933.doc • 38-200908233 forming a selective transistor on the substrate or in a trench in the substrate; in the semiconductor-active region of the selected transistor Forming a second semiconductor layer epitaxially; planarizing the second semiconductor layer; patterning the second semiconductor layer into a second semiconductor strip extending in the first direction; forming a third insulating layer Adjacent to the exposed lateral side of the second semiconductor stripe; patterning the second semiconductor stripe to form the second pillar; forming a second charge storage dielectric adjacent to one of the second pillars Positioning on a side of the first exposure; forming a second control gate adjacent to the third charge storage dielectric; forming a fourth charge storage dielectric adjacent to one of the second pillars Positioning on an exposed side; and forming a fourth control gate adjacent to the fourth charge storage dielectric. 129. A method of fabricating a single, three-dimensional array of a semiconductor device, comprising: forming a plurality of second semiconductor pillar active regions in a second device level, wherein the second semiconductor pillar active regions Intersecting the regions of the insulating material from each other; growing the -th semiconductor layer on the second semiconductor pillar active region and the insulating material regions 129933.doc • 39-200908233 to make the first semiconductor layer a grain boundary region is located above the regions of insulating material; and patterning the first semiconductor layer to remove the boundary region of the 晶粒 · · 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且A substantial beibei on the early day of a semiconductor pillar role area. 130. The method of claim 129, further comprising: planarizing the first semiconductor layer; patterning the first semiconductor layer pattern into a plurality of first-stripes, and extending in the direction of the first plurality of first stripes Forming a first-first insulating layer; patterning the plurality of first strips of the first insulating layer to form the plurality of regions of the semiconductor pillar; in the first semiconductor pillar Forming a dielectric film in a space between or between the materials; and filling the first groove with a first word line; and storing a drain in the dielectric film in the dielectric film (1) μ, " </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; 132. The method of claim 131, wherein the method further comprises: planarizing the first charge storage electricity purchase film and the skirt Chu ^ 1 green green · 4 Etching the first-word line Forming a first insulating top 129933.doc -40. 200908233 a cap layer over the partially etched first sub-line; planarizing the first insulating cap layer to expose the first semiconductor pillar active regions; And forming a bit line in contact with the active regions of the first semiconductor pillars. 133. The method of claim 1 30, further comprising: forming a plurality of selectable powers on a substrate or in a trench in the substrate a crystal, wherein the plurality of selective transistors comprise a plurality of third semiconductor pillar active regions spaced apart by an insulating material region; epitaxially growing on the third semiconductor pillar active regions and the insulating material regions a second semiconductor layer such that a grain boundary region in the second semiconductor layer is over the insulating material regions; and patterning the second semiconductor layer to remove the grain boundary regions and at a second device level Having the plurality of stages: a semiconductor pillar active region. 134. The method of claim 133, wherein the step further comprises: planarizing the second semiconductor layer; a plurality of second stripes extending in a first direction of the shai; a second insulating layer is formed between the plurality of second stripes; the plurality of second stripes and the (four) two insulating layers are Forming the second semiconductor pillar active region, wherein the mothers in the second half V pillar active region include - first conductivity between the second conductive type semiconductor regions Type semiconductor region; 129933.doc -41 · 200908233 forming a first electrical storage dielectric film in a space between the second semi-flute-ray-like active regions; filling the first-line — 沟; #—Electrical storage of the dielectric film in the channel flattening the second charge storage left volt, the electrolyte film and the second word line; the second word line is etched by the part/knife; Forming a second word cap layer that is partially inscribed in the 荨 ;; and planarizing the second insulating cap layer to circumscribe the second semiconductor pillars of the region of the specific insulating material region. &lt; 129933.doc 42-