200908070 九、發明說明： L發明所屬之技術領域】 本發明係提供一種半導體剪#太 性亍守版衣：^方法，特別是 機電結構製造方法，其不猶成難W 種牛導^ 魏結構之_，更能有效避 免側蝕，降低微機電結構曝露在外、 1又到彳貝傷的機率，並減少封 裝成本。 【先前技術】 按’現今半導體微機電系統包含各種不同的半導體微結構， :如：不可動的探針'流道、孔穴結構，或是—些可動的彈菩、 連才干、齒輪（剛體運動或是撓性形變）等結構。 將上述不同的結構和相_半導體電路相互整合，即可構成 各種不_半導體_。故如何勤製造方法提昇微機械結構各 種不同的魏’是未來半導體微機電系統_鍵指標，也是未來 進—步研究晶料的嚴峻挑戰；若能研發改進習知的技術，未來 的發展性實無法預估。 目則衣作微機電感測II及啟動器纽經常需要在％基底上製 式結構。前述製程必麵用了絲的半導體技術，例如： 衣見比乾姓刻和犧牲層（sacrificiaHayer)去除等專用的微 機電作業(MEMS : Micro-ElectiO-Mechanical Systems)。 200908070 習用技術如美國專利6，458，6聰，前述技術皆是於一石夕基 底上表面形絲少—内具微機電結構的絕緣電路層，觀接著從 上表面逐層钱刻’並且經過微機電結構側緣後，趣^等向性 (脱t_ic etching⑽基底乾餘刻，達祕機電^懸浮； 前述第-種習用技術雖然能夠製作懸浮微機電結構，但是卻 會產生下側幾項缺陷·· 其一，其採用非等向性化學钱刻（㈣输opicdry chemical 獅观)方式化學反應的方絲除絕緣層，但是由於經過 微機電結構舰後’仍要再進行#向性化學勤】將雜底大量飯 刻，故此種技術會發生嚴重的側侧象(under⑽）； 其二’此種習馳術的製程中，該微機電結構一開始就曝露 在製程之巾’糾㈣程之後’鱗會有微機魏構受到污 ¥、相傷’造成良率過低； 其三，此種製程技術在綱健完成之後，該微機電結構已 能懸洋運作’但是卻又__具將該微機f結構表面封裝阻 絕空氣，但是由於該微機電結構必須確保懸浮狀態，以往是利用 特殊模具罩設於產品表面，再精密製作不碰觸懸浮微機電結構的 封裝賴，献後製技術的表面封裝較為複敎高成本，且無法 與一般積體電路1C的封袭整合。 前述技術的發展十分迅速，為了改進其諸多問題，美國專利 200908070 6,712/ 983B2專利則提出了使用離子侧（Reactivei〇n油呢， 以下簡献IE)的技術，此種技術雖然能大幅降低側賊象（牆『 cut) ’但是由於其同樣是由上而下逐層進行侧，且最後一次的 石夕基底大量侧工作必須獅橫向侧技術方能達成，故此改進 :習用技術仍然過於麻煩複雜，且仍然通過該微機電結構進行大 量敍刻及橫向_仍會有纖縣(under eut)，且前賴機電結 構曝露、不紐製封I的問題姆;未獲得改善。 有4α於4本案發明人乃經詳思細索，並積多年從事各種 V體U機電產品輯與半導體研究生顏經驗，開發出—種能有 效避免側钱、降低微機電結構曝露、降低損傷機率及減少封裝成 本的半導贿型結構製造方法，而且可藉由此種方式自由的調整 微機电結構的厚度，以達成原先設計的微結構重量。 【發明内容】 本發明之首要目的在於提供一種半導體微型結構製造方法， 其能有效避免側蝕。 本發明為達成前述目的，其於-石夕基底上表面形成至少一内 =微:電結構的絕緣電路層，並且於絕緣電路層上表面㈣而外 依序製作—犧牲層及—阻絕層，接著於絲底之下背面製作 =刻ρ且絕層’域祕紅Tf面騎深反絲子糊亦或者: 慶餘刻形成相應該微機電結構之空間，再依序進行絕緣電路層： 200908070 犧牲層的蝕刻，達成微機電結構之懸浮； 藉此，本發明彻從㈣底之下f面進躲反應離子钱刻的 技術，可讓㈣鋪電結翻侧製程時㈤齡、繼的侧量 降低，配合乾式的深活性離子飯刻咖⑽咖加_她咏— 簡稱_及乾式的離子_ (_tlve lGn謹㈣稱_ 技術，有效避免微機電結構部位出現側姓。 本毛月目的之—在於提供—種半導體微型結構製造方法，其 降低微機物繼、㈣瓣，蝴嫌封裝成本Γ m為達讀述目的，其献絕緣電路層上表面由内而外 離子牲層及1絕層，並财基底之下背面進行深反應 層、犧牲層糊㈣㈣峨行絕緣電路 面的阻絕層；錢_電之懸料仍财絕緣電路層上表 獨特技術，用從矽基底之下背面進行深反應離子蝕刻的 皆保有絕緣;=層内的微機電結構從製程開始到懸浮時， 構曝露在外、面的阻絕層’故本發明有效避免微機電結 '降低受到損傷的機率； 機電社構糾❻由於絕緣電路層上表面的阻絕層可以直接作為微 製二故本發明能夠直接去除以往複雜、高成本的後 200908070 本發轉目的疋提供一種半導體微型結構製造方法，其能 夠隨意調控微機電結構的厚重或製作導體阻絕層，有效增加本發 明產品微機電結構賴式，降低成本。 :達月以目的，由於犧牲層是最後#刻的部位，本發明可以 利用若干儲置層配合犧牲層進行微機電結構的厚重㈣；此外， 由於該阻絕層將會絲巾空難，若是採料體崎層就能電性 共同連接阻導體阻絕層的微機電結構； 前述導體阻絕層的#料可以妓、銀、錄、銅或金等高導通 性金屬材料，並且直接與微機電結構電性通連。 值付-提的是’乾式的深活性離子侧③卿r㈣^⑹ ⑽啊卩下__)，_是近年來相當受難視的非等向 性體_技術’其利祕_過程中所形成的髓層，來防止側 壁被_ ’以達到非輪域刻的目的，因此侧的結構形狀， 不會受到晶格面的影響城有凸肖底_特性，耻可以钮刻出 ，开姻孔洞或凸塊；科，__延細E lag)的特性， 還可以在基材表面製造多重高度。 旦疋過去由於石夕晶片的乾式深钱刻技術沒有凸角底切效應， 因此製造财的《電結構十分_，但是本糾顧反向㈣ 的特殊技術，就能夠降低製造懸浮微機電結構的困難度。 200908070 & =關本案_為達成上述目的、所_之高度技術思想、手 I又狄列舉幸又佳可實施例並配合圖式詳細說明如後，相信本案 發明之目的、特徵及其他優點’當可由之得-深人而具體之瞭解。 【實施方式】 、/月參閱第1至5圖之實施例’本發料導體微型結構製造方法 之詳細說明如下； /第1圖所不’首先於一喊底1〇上表面U形成至少一内具微 機電結的絕緣電路，並且於絕緣電路獅上表面由内而 外依序製作—齡細及-阻絕層4〇 ; 如第2圖所不’接著於石夕基底】〇之下背面i 2製作一層侧阻絕 層5〇 ’且蝕刻阻絕層50的開口51相應該微機電結構21 ; 如第3圖所示，並财基細之下背面财概反應離子飯刻 圯)亦或者漫侧，且於石夕基底1〇定向形成相應該微機電結構 之二間101，該空間101到達該絕緣電路層2〇 ; ”如第4圖所示，自石夕基底10之空間101利用離子钱刻（RIE) 進行、，、巴緣f路層20的定向侧，到達預設的微機電結構21，並 且形成到達犧牲層30的空間201 ; 如第5圖所示，自絕緣電路層2〇的空間2〇1進行該犧牲層3〇 的非等向性蝕刻（etching)，並且形成犧牲層3〇相應微機電結構 200908070 21的空間301，達成微機電結構2i之縣浮 再心心，予且微機電結構21上 方皆保有阻絕層40之密封。 藉前述半導麵造方法；其錢_果在於： 1.其能有效避免纖，_從德底1G之下背面12進行深 反應離子似⑽圆亦或絲刻的技彳^可讓經過曝紐機電結 構21的細減少、_餅低，且配合乾式轉子_ (咖)技 術’有效避免微機電結構21部位出現侧蝕。 2·其降低微機電曝露、降低難機率，並能有效減少封裝成 本，由於糊财基底1Q之下f面12依騎行深反應離子侧 (DRIE)、奸關_)及非等向性關（etehing)，該絕緣電 路層20内的微機電結構21從製程開始到懸浮時，上方皆保有阻 絕層4G，有效聽微機魏構21曝露在外、降低受到損傷的機 率；更因絕緣電路層21上的阻絕層4〇可以直接作為封裝，故本 發明能夠直接去除以往複雜、高成本的後製封裝作業。 本發明另一實施例，請參閱第6至12圖之實施例，本發明半導 體微型結構製造方法之詳細說明如下； 如第6圖所示，首先於一矽基底1〇上表面u形成至少一内具微 機電結構21的絕緣電路層2〇，並且於絕緣電路層2〇上表面由内而 外依序製作一儲置層60、一犧牲層3〇 ; 200908070 如第7圖所示，於犧牲層3〇上製作_阻絕層4〇 ; 如第8圖所示，接著於矽基底丨〇之下背面丨2製作一層蝕刻阻絕 層50 ’且敍刻阻絕層50的開口51相應該微機電結構21 ; 如第9圖所示，並從矽基底1〇之下背面12進行深反應離子蝕刻 (DRIE)亦或溼蝕刻，且於矽基底1〇定向形成相應該微機電結構 之空間101，該空間1〇1到達該絕緣電路層2〇 ; 如第ίο圖所示，自矽基底10之空間101利用離子蝕刻 進行絕緣電路層20的定向蝴，賴達預設的賴電結構21，並 且形成到達儲置層6〇的空間; , 如第11圖所示，自絕緣電路層20的空間2〇1利用深反應離 子餘刻⑽IE)或離子蝴⑽）進行儲置層6()的定向侧，且通 過預設的微機電結構21形成到達犧牲層3㈣空間6〇1 ; ★如第12圖所示’自儲置層6〇的空間進行該犧牲層3〇的 專向性侧（is〇trcpic etching)，並且形成犧牲層3q相應微機 電結構21的挪3G1 ’達成微機電結抑之懸浮，此時，該懸浮 微機電結構2卜側的有預設厚度的儲置層⑼，可供使用者需求 =控懸浮微機電結構21的重量、扭力料物理特性，錢機電結 構21上方皆保有阻絕層4〇之密封。 藉前述半導體微型結構製造方法實施例；其產生的效果在於： 1. 其能有效避免側姓(如前述）。 2. 其降低錢祕露、損傷_，錢有錢少難成本(如 12 200908070 前述）。 3 ·其志夠思調控微機曾么士德>/ rg 钱包結構的厚重，利用若干儲置層60 配合犧牲層30就能進行微機電結構21的厚重保留，供使用者依 照需求調控懸浮微機電結構21的重量、扭力等等物理特性。 本發明再-實施例’請參閱第13至18圖之阻絕層封裝實施 例’本發财導體微魏戦造紐之詳細朗如下；、 如第13圖所示’魏於—絲綱上表面⑽成至少一内具 微機電結構21的絕緣電路層2G，並且於絕緣電路層2()上表面由内 而外依序製作-儲置層60、—犧牲層3Q，且於犧牲層別上製作一 倒蓋狀阻絕層40，且倒蓋狀阻絕層4〇外側與儲置層6〇接觸； 如第14圖所示，接著於矽基底1〇之下背面12製作一層蝕刻阻 絕層50，且蝕刻阻絕層50的開口51相應該微機電結構21 ; 如第15圖所示，並從矽基底1〇之下背面12進行深反應離子蝕 刻（DRIE)，且於矽基底1〇定向形成相應該微機電結構21之空間 1〇1 ’該空間101到達該絕緣電路層2〇 ; 如第16圖所示，自矽基底10之空間101利用離子蝕刻（RIE) 進订絕緣電路層2〇的定向蝕刻，且到達預設的微機電結構21，並 且形成到達儲置層60的空間201 ; 如弟17圖所示，自絕緣電路層20的空間201利用深反應離 子钱刻（DRIE)或離子蝕刻（rIE)進行儲置層60的定向蝕刻，且通 13 200908070 過預設的微機電結構21形成到達犧牲層30的空間，而空間 601位於該倒蓋狀阻絕層4〇無置層6〇接觸位置之内； ”如第18圖所示，自儲置層6〇的空間6〇1進行該犧牲層％的 寺向性_ (1SQtn)pie etehing)，並且將犧牲㈣全部消除， 達成韻電結構21之懸浮，此時，該懸浮微機電結構2丨一側尚 留有預設厚度的層6G，可供使用者需求·财微機電結構 21的重量、扭力等等物理特性，且微機電結構？！上方皆保有倒蓋 狀阻絕層40之密封。 藉前料導II微型結構製造方法實施例；其產生的效果在於： 1.其能有效避免側飯（如前述）。 一 2.其降低微機電曝露、損傷機率，並能有效減少封裝_⑷ 前述）。 3.其旎夠隨意調控微機電結構的厚重（如前述）。 : 4.其在微機電結構21上方皆保有倒蓋狀阻絕層之密封， 不僅能提昇密封效果，且能運關蓋狀崎層Μ材料之選用，令 倒蓋狀阻絕層40直接作為微機電結構21的封裝，讓本發明關 直接去除以在複雜、尚成本的後製封裝作業。 本發明另-實施例，請參閱第19至25圖之石夕基底調變實施 例，本發明半導體微型結構製造方法之詳細說明如下； 如第19圖所示，首先於—錄細上表面⑽成至少—内具 14 200908070 微機電結構21的絕緣電闕20，並且於縣電路獅上表面由内 而外依序製作-儲置層60 —犧牲層3〇，且於犧牲層3()上製作一 倒蓋狀阻絕層40，且倒蓋狀阻絕層術卜側與儲置細接觸，接著 於石夕基底1G之下背面12製作-祕難絕侧，且_阻絕層5〇 的開口 51相應該微機電結構21 ; 如第20®所示’並财基細之下背面12_深反應離子兹 刻（DRIE)或離子姓刻⑽)進行預設高度的定向姓刻，且於石夕基底 1〇定向形成相應該微機電結構21之空_2，該空卿2未到達該 絕緣電路層20 ; 如第21圖所示，剝離阻絕層50後，在祕底1G之下背面12及 空間102内製作底阻絕層7〇 ; 如第22圖所不’藉由底阻絕層7〇在石夕基底1〇進行該深反應離 子^M(DRIE) ’ ^向勤〗形餘應該微機電結構a之空間皿， 該空間101到達該絕緣電路層2〇; …如第23圖所不’自石夕基底1〇之空間仙利用離子钮刻⑽) 進仃、、、巴緣電路層20的定向侧，且到達預設的微機電結構，並 且形成到達儲置層60的空間2〇1 . 第24圖所不’自絕緣電路層的空間測利用深反應離 子姓刻咖)或離子綱（_進彳讚置層6G的定向侧，且適 、。預又的微機也結構21形成到達犧牲層3〇的空間謝，而空間 601位於_盖狀阻絕層4〇與儲置層⑼接觸位置之内； 15 200908070 斤如第25圖所示，自儲置層6〇的空間601進行該犧牲層3〇的 等向性賴（iSQtrQpic etGhing)，並且將犧牲層全部消除，達 成微機電結構21之财，此時，巾央縣微機電結構21 一側尚 留有預設厚度的儲置層6G、另―側也形成作鱗重基礎的懸浮石夕 基底10，可供使用者需求調控懸浮微機電結構21的重量、扭力等 等物理特f生且微機電結構21上方皆保有倒蓋狀阻絕層之密 封。 藉則述半導體微型結構製造方法實施例；其產生的效果在於： 1. 其能有效避免側蝕(如前述）。 2. 其降低微機電曝露、損傷機率，並能有效減少封裝成本(如 前述）。 3. 其能夠隨意縱微機電結構21的厚重，並且讓魏底ι〇 也成為微機電結構21厚重的基礎，並且令微機電結構21厚重的 調變範圍增加，更有效令產品設計變化更多樣。 4·其此k幵密封效果（如前述）。 再請參閲第期至第35圖，本翻微機電結_控有無厚重 之實施例’本發明半導體微型結構製造方法之詳細說明如下； 如第26圖所示’首先於-錄細上表仙形歧少一内具 微機電結構21的絕緣電路層2〇 ’並且於絕緣電路㈣上表面製作 -儲置層6G ’該儲置層60具有孔洞61，且該孔洞61相應預設的微 16 200908070 機電結構21 ; 如第27圖所示，於儲置層60上製作一犧牲層30，且犧牲層30 充填於該儲置層60的孔洞61内； 如第28圖所示，於犧牲層3〇上製作一倒蓋狀阻絕層4〇，且倒 蓋狀阻絕層40外側與儲置層60接觸； 如第29圖所示，接著於矽基底10之下背面丨2製作一層蝕刻阻 絕層50，且姓刻阻絕層5〇的開口 51相應該微機電結構μ ; 如第30圖所示，並從矽基底1〇之下背面12利用深反應離子蝕 刻（DRIE)或離子蝕刻（RIE)進行預設高度的定向蝕刻，且於矽基底 ίο定向形成相應該微機電結構21之空間1〇2，該空間1〇2未到達該 絕緣電路層2〇 ; 如第31圖所示，剝離阻絕層5〇後，在矽基底1〇之下背面12及 空間102内製作底阻絕層; 如第32圖所不’藉由底闕㈣在雜進行該深反應離 f蝕刻（DRIE)，且定向蝕刻形成相應該微機電結構21之空間1〇1， 忒二間1 〇 1到達該絕緣電路層2〇 ·， 、二第33圖所示’自石夕基底10之空間101利用離子姓刻⑽) 、:巴緣電路層2G蚊向侧，且到達預設的微機電結構21，並 且幵^成到達儲置層60的空間2〇1 ; 子飾2 34圖所示’自絕緣電路層2〇的空間謝利用深反應離 HE)或離子飯刻⑽)進行儲置層6〇的定向敍刻，且通 17 200908070 過預設的微機電結構21形成到達犧牲層3〇的空間则，而空間 601位於該倒蓋狀阻絕層4〇與儲置層6〇接觸位置之内，並且到達 充填於該儲置層60的孔洞61内的犧牲層3〇 ; 斤如第35圖所示，自儲置層6〇的空間謝進行該犧牲層加的 等向性侧（iSQtrc)pie etching)，並且將犧牲層及域於該儲 置層60的孔洞内的犧牲層全部消除，達成微機電結構2ι之懸浮， 此時，中央懸浮微機電結構21 —側尚留有預設厚度的儲置層即、 另-側也形成作為厚重基礎的财絲底1G，且微機電結曰構Μ 上方皆保有倒蓋狀阻絕層40之密封，另於原本相應該儲置層6〇 孔洞的彳政機電結構21上方則沒有保留之厚重。 藉前述半導體微型結構製造方法實施例；其產生的效果在於： L其能有效避免側钕(如前述）。 2.其降低賴電曝露、損傷解，魏有效減少封裝成本(如 前述）。 3·其能夠隨意雜微機電結構21的厚重，不但縣基底1〇 也成為微機電結構21厚重的基礎，並且令微機電結構21可以選 擇部份厚重>肖除'部份厚重的增加，更有效令產品設計變化更多 樣。 4.其能提昇密封效果(如前述）。 最後，再請參閱第36圖至第42圖，本發明微機電結構製作導 18 200908070 肢阻、％層之方法步驟’本發明半導體微型結構製造方法之詳細說 明如下； 如第36圖所不’首先於—⑦基細上表面11形成至少-内具 微機電結構21的絕緣電路，並且於絕緣電路上表面開設 若干孔洞22，該孔職減預設的微機電結構21 ; 如第37圖所示，於絕緣電路層20上製作一犧牲層30，且犧牲 層30未覆蓋於該絕緣電路層2〇的孔洞22 ; 如第38圖所示，於犧牲層3〇上製作一倒蓋狀導體阻絕層8〇， 且倒蓋狀導體阻絕層_側與絕緣電路層20接觸，且導體阻絕層 80進入m %路層go的孔洞22内與微機電結構21電性通連，前 述V體阻、％層80的材料可以是!s、鎳、銀、滅金等高導通性金 屬材料； ”如第39圖所示，接著於石夕基細之下背面12製作-層侧择 '巴層50且姓刻阻絕層5〇的開口51相應該微機電結構a ; 如第40圖所示，並從石夕基_之下背抓利用深反應離子食 刻（DRIE)進行定向_，且於絲細定向形成到達該絕緣辆 層20的空間1〇1 ; 、如第41圖所示，自石夕基底10之空間101利用離子_⑽) 進行絕緣電路層2〇的定向_，且到達預設的微機電結㈣，並 且形成到達犧牲層3〇的空間2〇1 ; 如第42圖所示，自絕緣電路層2〇的空間2〇ι利用餘刻技術 19 200908070 將犧牲層全部消除，達成微機電結構2 沿序，此時，該導體阻 絕層80可以進行預設至少二微機電 。偁Zi电性通連， 微機電結構21上方。 、、且 汽施例；其產生的效果在於： ，並能有欵減少封裝成本(如 藉前述半導體微型結構製造方法 1. 其能有效避免側钱（如前述）。 2. 其降低微機電曝露、損傷機率 前述）。 3. 其能夠隨意雛微機電結構的厚重（如前述) 4. 其能提昇密封效果（如前述）。 5.其能利用導體阻絕層8〇進行 μ ^ 、°又至少〜微機電結構21電 1·生通連’而且完全不會影響原本微機電結構的設計。 造方法新^係1全新的半導體微型結構製 :方法，其先㈣緣電路層上表面㈣科依賴作—犧牲層2 阻絕層，接著於矽基底之下背面 基底fF A ifr、# 、 θ餘刻阻絕層，並從矽 丞原之下月面進仃深反應離子餘 間，”成相應該微機電結構之空 门冉依序進仃絕緣電路層、儀 糾的_’達賴機電之懸浮； 糟此，有鋪免触，而且 率低，更能減少最後封裝成本；_路在外'受到損傷的機 所以本發明之『具有產業 > AL 矛用十生』應已毋庸置疑，降士卜 之外，在本案貫施例所揭露 矛、此 特徵技術，於申請之前並未曾見 20 200908070 於諸刊物，亦未曾被公開使用，不但具有如上所述功效增進之事 實，更具有不可輕忽的附加功效，是故，本發明的『新穎性』以 及『進步性』都已符合專利法規，爰依法提出發明專利之申請， 祈請惠予審查並早曰賜准專利，實感德便。 21 200908070 【圖式簡單說明】 第1圖至苐5圖 第6圖至第ϊ2圖 圖， 本發明實施例之方法步驟示意圖. 本發明厚度調變實施例之方法步驟示意 第13圖至第18圖 意圖； 本發明阻絕顧轉施攸方法步驟示 第19圖至第25圖 意圖； 本發明石夕基底調變實施例之方法步驟示 第26圖至第35圖 之方法步驟示意圖； 本發明微機電結翻控有無厚重實施例 以及 第36圖至第42圖 法步驟示意圖。 本發明微機電結構製作導體阻絕層之方 【主要元件符號說明】 矽基底10 上表面11 下背面12 空間101 空間102 絕緣電路層2〇 空間201 微機電結構21 孔洞22 22 200908070 犧牲層30 空間301 阻絕層40 钱刻阻絕層50 開口 51 儲置層60 孔洞61 空間601 底阻絕層70 導體阻絕層80 23200908070 IX. INSTRUCTIONS: The technical field to which the invention belongs is: The present invention provides a semiconductor shearing method: a method for making a sturdy slogan: a method, in particular, an electromechanical structure manufacturing method, which is not difficult to form a bovine guide _, can effectively avoid side erosion, reduce the exposure of micro-electromechanical structure, 1 to mussel injury, and reduce packaging costs. [Prior Art] According to the 'current semiconductor MEMS system contains a variety of different semiconductor microstructures, such as: non-movable probes' flow path, hole structure, or - some movable missiles, contingent, gears (rigid body motion) Or flexible deformation) and other structures. By integrating the above different structures and phase-semiconductor circuits with each other, various types of semiconductors can be constructed. Therefore, how to improve the micro-mechanical structure of Wei's is a future semiconductor MEMS key, and it is also a serious challenge for the future research of crystal materials. If we can develop and improve the technology, the future development Unpredictable. It is often necessary to make a structure on a % substrate for the purpose of measuring the machine inductance II and the starter. The above-mentioned processes must use silk semiconductor technology, for example: MEMS: Micro-ElectiO-Mechanical Systems, etc., which is more than a dry name and sacrificiaHayer removal. 200908070 Conventional technology, such as U.S. Patent No. 6,458,6, the above-mentioned techniques are all on the surface of a stone substrate with a small amount of surface-insulating circuit layer with micro-electromechanical structure, and then the layer is carved from the upper surface and passes through the micro-electromechanical structure. After the side edge of the electromechanical structure, the interesting isotropic (de- t_ic etching (10) base dry remnant, the secret electromechanical ^ suspension; the above-mentioned first-used technology can make suspended micro-electromechanical structure, but it will produce several defects on the lower side · · First, it uses non-isotropic chemical money engraving ((4) opicdry chemical lion view) chemical reaction of the square wire in addition to the insulation layer, but due to the micro-electromechanical structure after the ship 'still to carry out #向性化学勤】 A large amount of rice is engraved on the miscellaneous bottom, so this technique will have a serious side image (under (10)); in the second process of this kind, the microelectromechanical structure is exposed to the process of the process after the correction (four) process 'The scale will have the micro-machine Wei structure contaminated ¥, the phase injury' caused the yield is too low; Third, after the completion of the process technology, the micro-electromechanical structure can be suspended for operation 'but yet __ The microcomputer f structure table The package blocks air, but since the micro-electromechanical structure must ensure the suspension state, it has been used to cover the surface of the product with a special mold, and then precision-prepared the package that does not touch the suspended micro-electromechanical structure. The surface package of the post-production technology is more complicated. High cost, and can not be integrated with the generalized circuit 1C. The development of the above technology is very rapid, in order to improve its many problems, the US patent 200908070 6,712/ 983B2 patent proposed the use of the ion side (Reactivei〇n oil, below Jane IE) technology, although this technology can greatly reduce the side thief (wall "cut" 'but because it is also from the top to the bottom layer by side, and the last time the Shi Xi base a large amount of side work must be lion landscape The side technology can be achieved, so the improvement: the conventional technology is still too cumbersome and complicated, and still carry out a lot of narration and lateral direction through the MEMS structure. There will still be an under eut, and the front and the back of the electromechanical structure are exposed. The problem of sealing I; no improvement. There are 4α in 4 cases, the inventor has carefully studied and accumulated many years of experience in various V body U mechanical and electrical products. The experience of semiconductor graduates has developed a semi-conductive bridging structure manufacturing method that can effectively avoid side money, reduce micro-electromechanical structure exposure, reduce the probability of damage and reduce packaging costs, and can freely adjust the micro-electromechanical structure by this way. The thickness of the invention is to achieve the weight of the micro-structure originally designed. SUMMARY OF THE INVENTION The primary object of the present invention is to provide a method for fabricating a semiconductor microstructure which can effectively avoid side etching. The present invention achieves the aforementioned object, and Forming at least one inner/micro: electrical structure of the insulating circuit layer on the upper surface, and sequentially forming the sacrificial layer and the barrier layer on the upper surface (4) of the insulating circuit layer, and then making the bottom surface under the silk bottom Layer 'domain secret red Tf surface riding deep anti-filament paste or: Celebrate the space to form the corresponding micro-electromechanical structure, and then insulate the circuit layer: 200908070 Sacrificial layer etching, to achieve the suspension of micro-electromechanical structure; Therefore, the present invention completely removes the reactive ion engraving technique from the bottom surface of (4), and can reduce the (five) age and the subsequent side quantity when the (four) electric junction is turned over. With a dry deep reactive ion engraved coffee meal plus coffee _ her ⑽ Yong - and referred to the dry ion _ _ (_tlve lGn wish _ (iv) said technology to effectively prevent occurrence microelectromechanical structure portion side name. The purpose of this month is to provide a semiconductor micro-structure manufacturing method, which reduces the micro-computer, (four) lobes, and the packaging cost Γ m is for reading purposes, and the upper surface of the insulating circuit layer is composed of internal and external ions. Layer and 1 layer, and the bottom side of the bottom layer is deep reaction layer, sacrificial layer paste (4) (4) the insulating layer of the insulating circuit surface; the money _ electric suspension material is still a unique circuit on the insulating circuit layer The bottom side of the deep reactive ion etching retains insulation; = the microelectromechanical structure in the layer is exposed to the outer and surface barrier layers from the beginning of the process to the suspension. Therefore, the present invention effectively avoids the micro-electromechanical junction' reducing the probability of damage. The electromechanical structure is entangled. Since the barrier layer on the upper surface of the insulating circuit layer can be directly used as the micro-fabrication, the present invention can directly remove the complicated and high-cost post-200908070, and provide a semiconductor micro-structure manufacturing method capable of The thickness of the microelectromechanical structure can be arbitrarily regulated or the conductor barrier layer can be formed, which effectively increases the microelectromechanical structure of the product of the invention and reduces the cost. : For the purpose of reaching the moon, since the sacrificial layer is the last part of the engraving, the present invention can utilize a plurality of storage layers in combination with the sacrificial layer to carry out the thickness of the microelectromechanical structure (four); in addition, since the barrier layer will be difficult for the scarf, if the material is collected The body layer can electrically connect the microelectromechanical structure of the resistance conductor barrier layer; the material of the conductor barrier layer can be high conductivity metal materials such as germanium, silver, magnet, copper or gold, and directly with the microelectromechanical structure. Connected. The value of pay- mention is 'dry type of deep active ion side 3 Qing r (four) ^ (6) (10) 卩 _ _ _), _ is a relatively unsightly anisotropic body in recent years _ technology 'its secret _ formed in the process The marrow layer, to prevent the side wall from being _ 'to achieve the purpose of non-wheel engraving, so the side structure shape, will not be affected by the lattice surface, the city has a convex bottom _ characteristics, shame can be carved out, open marriage hole Or the characteristics of the bump; section, __ 延 细 E lag), it is also possible to create multiple heights on the surface of the substrate. In the past, due to the dry deep-cutting technique of Shixi wafer, there is no embossing effect. Therefore, the electrical structure of manufacturing wealth is very _, but this special technique of reversing the reverse (4) can reduce the manufacturing of suspended micro-electromechanical structures. Difficulty. 200908070 &=Close the case _ In order to achieve the above objectives, the high technical thinking, the hand I and Di, and the detailed description of the case, with the details of the following, I believe the purpose, characteristics and other advantages of the invention When you can get it - deep people and understand. [Embodiment] </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; An insulated circuit with a micro-electromechanical junction, and the upper surface of the insulated circuit lion is made in order from the inside to the outside - the age is fine and the barrier layer is 4 〇; as shown in Fig. 2, it is not followed by the back of the stone 基底 substrate. i 2 produces a layer of side barrier layer 5 〇 ' and the opening 51 of the etch stop layer 50 corresponds to the MEMS structure 21; as shown in Figure 3, and the bottom of the financial accounting Side, and in the Shixi substrate 1 〇 oriented to form a corresponding 101 of the microelectromechanical structure, the space 101 reaches the insulating circuit layer 2;" as shown in Fig. 4, the space 101 from the Shishi base 10 utilizes ions The engraving (RIE) proceeds, and the directional side of the slab layer 20 reaches the predetermined microelectromechanical structure 21 and forms a space 201 reaching the sacrificial layer 30; as shown in Fig. 5, the self-insulating circuit layer 2 The space of the crucible 2〇1 performs an anisotropic etching of the sacrificial layer 3〇, and forms The 301 of the corresponding micro-electromechanical structure 200908070 21 of the livestock layer reaches the county of the micro-electromechanical structure 2i, and the sealing of the barrier layer 40 is maintained above the micro-electromechanical structure 21. The method of manufacturing the semi-conductive surface; _The fruit is: 1. It can effectively avoid the fiber, _ from the bottom of the bottom 1G under the back of the 12 deep reaction ions like (10) round or silk engraved technology ^ can be reduced through the exposure of the electromechanical structure 21, _ cake Low, and with the dry rotor _ (coffee) technology 'effectively avoid the side erosion of the microelectromechanical structure 21 parts. 2 · It reduces the micro-electromechanical exposure, reduces the difficulty rate, and can effectively reduce the packaging cost, because the paste base 1Q f The surface 12 is immersed in the deep reactive ion side (DRIE), the traits _) and the non-isotropic (etehing). The microelectromechanical structure 21 in the insulating circuit layer 20 has a barrier layer 4G from the beginning of the process to the suspension. The effective listening micro-machine is exposed to the outside and reduces the probability of damage; and the barrier layer 4 on the insulating circuit layer 21 can be directly used as a package, so the invention can directly remove the complicated and high-cost post-packaging operation. Another aspect of the invention For example, referring to the embodiments of FIGS. 6 to 12, the detailed description of the method for fabricating the semiconductor micro-structure of the present invention is as follows; as shown in FIG. 6, first, at least one micro-electromechanical device is formed on the upper surface u of the substrate 1 The insulating circuit layer 2 of the structure 21 is formed, and a storage layer 60 and a sacrificial layer 3 are sequentially formed on the upper surface of the insulating circuit layer 2 from the inside to the outside; 200908070, as shown in FIG. 7, on the sacrificial layer 3〇 Forming a barrier layer 4; as shown in FIG. 8, then forming an etch stop layer 50' on the backside 丨2 under the 矽 substrate 且 and the opening 51 of the barrier layer 50 corresponds to the MEMS 21; As shown in Fig. 9, the deep back reactive ion etching (DRIE) or wet etching is performed from the back surface 12 of the germanium substrate 1 , and the space 101 is formed on the germanium substrate 1 to form a space 101 corresponding to the microelectromechanical structure. 1 arrives at the insulating circuit layer 2; as shown in Fig. 00, the space 101 of the self-lying substrate 10 is subjected to ionization etching to perform the orientation of the insulating circuit layer 20, and the predetermined electrical structure 21 is formed, and the formation is reached. a space of 6 〇; , as shown in FIG. 11 , from the insulating circuit layer 20 The space 2〇1 uses the deep reactive ion residual (10) IE) or the ion butterfly (10) to perform the oriented side of the storage layer 6(), and is formed by the predetermined microelectromechanical structure 21 to reach the sacrificial layer 3 (4) space 6〇1; 12 shows the space of the sacrificial layer 3〇 from the space of the storage layer 6〇, and the formation of the sacrificial layer 3q corresponding to the microelectromechanical structure 21 of the 3G1 'to achieve micro-electromechanical suppression Suspension, at this time, the storage layer (9) of the suspension microelectromechanical structure 2 has a predetermined thickness, which can be used by the user to control the weight of the suspension microelectromechanical structure 21, the physical properties of the torsion material, and the upper surface of the electromechanical structure 21 All have a seal that blocks the layer 4 。. The foregoing embodiment of the semiconductor micro-structure manufacturing method has the following effects: 1. It can effectively avoid the side surname (as described above). 2. It reduces the cost of money, damage _, money has money and less difficult costs (such as 12 200908070 mentioned above). 3 · Its ambition is to control the thickness of the micro-machine Zengshide>/rg wallet structure, and the thickness of the micro-electromechanical structure 21 can be preserved by using a plurality of storage layers 60 with the sacrificial layer 30, so that the user can control the suspension micro-micro according to the demand. Physical properties of the electromechanical structure 21 such as weight, torsion, and the like. Further embodiments of the present invention, please refer to the resistive layer package embodiment of FIGS. 13 to 18, the details of the present invention are as follows: , as shown in Fig. 13, the surface of the Wei Wei-Sifang (10) forming at least one insulating circuit layer 2G having the microelectromechanical structure 21, and sequentially forming the upper surface of the insulating circuit layer 2 (from the inside and the outside - the storage layer 60, the sacrificial layer 3Q, and on the sacrificial layer) A flip-shaped barrier layer 40 is formed, and the outer side of the flip-shaped barrier layer 4 is in contact with the storage layer 6?; as shown in FIG. 14, an etch stop layer 50 is then formed on the back surface 12 of the germanium substrate 1? And the opening 51 of the etch stop layer 50 corresponds to the microelectromechanical structure 21; as shown in Fig. 15, and performs deep reactive ion etching (DRIE) from the back surface 12 of the 矽 substrate 1〇, and forms a phase on the 矽 substrate 1〇 The space of the microelectromechanical structure 21 should be 1 〇 1 'the space 101 reaches the insulating circuit layer 2 〇; as shown in Fig. 16, the space 101 of the germanium substrate 10 is bonded by the ion etching (RIE) to the insulating circuit layer 2 Directionally etching, and reaching the preset microelectromechanical structure 21, and forming a space 201 reaching the storage layer 60; As shown in FIG. 17, the space 201 of the insulating circuit layer 20 is subjected to directional etching of the storage layer 60 by deep reactive ion etching (DRIE) or ion etching (rIE), and the pass-through microelectromechanical structure is passed through 13 200908070. 21 forms a space reaching the sacrificial layer 30, and the space 601 is located within the contact position of the inverted capping barrier layer 4 without the layer 6〇;" as shown in Fig. 18, the space 6自 from the storage layer 6〇 The temple tropism of the sacrificial layer is performed _ (1SQtn) pie etehing), and the sacrificial (four) is completely eliminated, and the suspension of the rhythmic structure 21 is achieved. At this time, the floating MEMS structure has a predetermined thickness on the side of the 微2 The layer 6G can be used for the user's demand, the physical characteristics of the weight, torque and the like of the micro-electromechanical structure 21, and the micro-electromechanical structure?! The upper part is sealed with the inverted cap-shaped barrier layer 40. Method embodiment; the effect thereof is: 1. It can effectively avoid side meals (as mentioned above). 1. It reduces the micro-electromechanical exposure, damage probability, and can effectively reduce the package _ (4) the aforementioned). Feel free to regulate the thickness of the MEMS structure (as mentioned above) : 4 The upper part of the micro-electromechanical structure 21 is sealed with a flip-shaped barrier layer, which not only improves the sealing effect, but also can transport the cover-like layer material, so that the inverted cover layer 40 directly functions as the micro-electromechanical structure 21 The package allows the present invention to be directly removed for complex and costly post-packaging operations. In another embodiment of the present invention, please refer to the embodiment of the present invention, the semiconductor microstructure fabrication of the present invention. The detailed description of the method is as follows; as shown in Fig. 19, firstly, the upper surface (10) is recorded to at least the insulating electric cymbal 20 of the 14200908070 MEMS structure 21, and the upper surface of the county circuit lion is internally and externally The fabrication-storage layer 60 - the sacrificial layer 3 〇, and a flip-shaped barrier layer 40 is formed on the sacrificial layer 3 (), and the inverted cap-shaped barrier layer is in fine contact with the storage, followed by the Shi Xi substrate. Under the 1G, the back surface 12 is made to the side, and the opening 51 of the barrier layer 5 corresponds to the microelectromechanical structure 21; as shown in the 20th®, the back surface 12_ deep reaction ion is engraved ( DRIE) or ion surname (10)) to perform a preset height of the preset height, and The Shixi substrate 1〇 is oriented to form an empty space corresponding to the microelectromechanical structure 21, and the hollow 2 does not reach the insulating circuit layer 20; as shown in Fig. 21, after the barrier layer 50 is peeled off, the back surface is under the secret 1G. 12 and the space 102 to make the bottom layer 7 〇; as shown in Fig. 22, the deep reaction ion ^M (DRIE) should be carried out by the bottom layer 7 〇 at the base of the stone ' ^ ^ ^ The space plate of the micro-electromechanical structure a, the space 101 reaches the insulating circuit layer 2; ... as shown in Fig. 23, the space is not used by the space stalks (10)) The directional side of the layer 20, and reaches a predetermined microelectromechanical structure, and forms a space 2 〇1 that reaches the storage layer 60. Figure 24 does not 'spatial measurement of the self-insulating circuit layer using the deep reaction ion name) or The ion class (_ 彳 彳 彳 置 layer 6G orientation side, and appropriate. The pre-computer structure 21 also forms a space to reach the sacrificial layer 3〇, and the space 601 is located within the contact position of the cover-like barrier layer 4〇 and the storage layer (9); 15 200908070 kg as shown in Fig. 25, self-storage The space 601 of the layer 6 进行 performs the isotropic lag (iSQtrQpic etGhing) of the sacrificial layer 3〇, and completely eliminates the sacrificial layer, and achieves the MEMS 21 profit. At this time, the side of the micro-electromechanical structure 21 of the towel county The storage layer 6G with a predetermined thickness is left, and the other side also forms a suspended stone base 10 which serves as a basis for the scale. The user can control the weight, torque and the like of the suspended microelectromechanical structure 21. The MEMS structure 21 is sealed with a flip-shaped barrier layer. Embodiments of the semiconductor microstructure manufacturing method are described; the effects thereof are as follows: 1. It can effectively avoid side etching (as described above). 2. It reduces the probability of micro-electromechanical exposure and damage, and can effectively reduce the cost of packaging (as mentioned above). 3. It is capable of arbitrarily arranging the thickness of the micro-electromechanical structure 21, and making Weidi 〇 成为 also the basis of the thick MEMS structure 21, and increasing the thick modulation range of the MEMS structure 21, more effectively making the product design change more kind. 4. The sealing effect of this k幵 (as mentioned above). Please refer to the first to the 35th, the embodiment of the micro-electromechanical junction _ control whether there is no heavy weight. The detailed description of the manufacturing method of the semiconductor micro-structure of the present invention is as follows; as shown in the figure 26, the first--recording table The insulative circuit layer 2 of the microelectromechanical structure 21 is formed and the storage layer 6G is formed on the upper surface of the insulating circuit (4). The storage layer 60 has a hole 61, and the hole 61 corresponds to a preset micro 16 200908070 Electromechanical structure 21; as shown in Fig. 27, a sacrificial layer 30 is formed on the storage layer 60, and the sacrificial layer 30 is filled in the hole 61 of the storage layer 60; as shown in Fig. 28, at the expense A flip-shaped barrier layer 4 is formed on the layer 3, and the outer side of the flip-shaped barrier layer 40 is in contact with the storage layer 60; as shown in FIG. 29, an etch stop is formed on the back surface of the germanium substrate 10 The layer 50, and the opening 51 of the last name of the barrier layer 5 corresponds to the microelectromechanical structure μ; as shown in Fig. 30, and from the back surface 12 of the germanium substrate 1 by deep reactive ion etching (DRIE) or ion etching (RIE) Performing a directional etch of a predetermined height, and aligning the ί substrate ίο to form the corresponding MEMS The space of the structure 21 is 1〇2, and the space 1〇2 does not reach the insulating circuit layer 2〇; as shown in FIG. 31, after the barrier layer 5 is peeled off, the back surface 12 and the space 102 are fabricated under the germanium substrate 1〇. The bottom barrier layer; as shown in Fig. 32, the deep reaction etch (DRIE) is performed by the bottom 阙 (4), and the directional etching forms a space corresponding to the MEMS 21, 1 〇1, 忒1 11 1 Arrives at the insulating circuit layer 2〇, , and 2, as shown in Fig. 33, 'from the space 101 of the Shishi base 10, using the ion surname (10)), the edge of the palm-edge circuit layer 2G, and reaching the preset micro-electromechanical Structure 21, and 成 ^ into the space 2 〇 1 of the storage layer 60; sub-decoration 2 34 shown in the 'self-insulating circuit layer 2 〇 space thanks to deep reaction from HE) or ion rice (10) for storage Directional characterization of layer 6〇, and through 17 200908070 through the preset microelectromechanical structure 21 to form a space reaching the sacrificial layer 3〇, and space 601 is located in the contact position of the inverted capping barrier layer 4〇 and the storage layer 6〇 Within the reach of the sacrificial layer 3 filled in the hole 61 of the storage layer 60; as shown in Fig. 35, the space from the storage layer 6〇 The sacrificial layer is added to the isotropic side (iSQtrc) pie etching), and the sacrificial layer and the sacrificial layer in the hole of the storage layer 60 are all eliminated, thereby achieving suspension of the microelectromechanical structure 2, at this time, the center Suspended MEMS structure 21 - the storage layer with a preset thickness on the side, that is, the other side also forms the bottom 1G as a thick foundation, and the MEMS structure is maintained above the MEMS structure. The seal is not retained above the 机电 机电 electromechanical structure 21 which originally corresponds to the 层 hole of the storage layer 6 . The foregoing embodiment of the semiconductor micro-structure manufacturing method has the following effects: L can effectively avoid side turns (as described above). 2. It reduces the exposure and damage of the electricity, and effectively reduces the packaging cost (as mentioned above). 3. The thickness of the micro-electromechanical structure 21 can be arbitrarily increased, and not only the base of the county but also the basis of the thickness of the micro-electromechanical structure 21, and the micro-electromechanical structure 21 can select a part of the thickness > More effective to make product design changes more varied. 4. It can improve the sealing effect (as mentioned above). Finally, please refer to FIG. 36 to FIG. 42 again, the microelectromechanical structure fabrication guide 18 of the present invention. 200908070 Method of limb resistance, % layer method The detailed description of the method for manufacturing the semiconductor micro structure of the present invention is as follows; Firstly, an insulating circuit having at least a microelectromechanical structure 21 is formed on the upper surface 11 of the substrate, and a plurality of holes 22 are formed in the upper surface of the insulating circuit, and the hole reduces the preset microelectromechanical structure 21; as shown in FIG. A sacrificial layer 30 is formed on the insulating circuit layer 20, and the sacrificial layer 30 does not cover the hole 22 of the insulating circuit layer 2; as shown in FIG. 38, a flip-shaped conductor is formed on the sacrificial layer 3? The barrier layer 8 is blocked, and the inverted cap conductor barrier layer_ is in contact with the insulating circuit layer 20, and the conductor barrier layer 80 is electrically connected to the microelectromechanical structure 21 in the hole 22 of the m% channel layer go, the V body resistance The material of the % layer 80 may be a high-conductivity metal material such as !s, nickel, silver or gold; "as shown in Fig. 39, followed by the back surface 12 of the Shi Xiji fine-layered side layer 50 and the opening 51 of the surname blocking layer 5 corresponds to the microelectromechanical structure a; such as the 40th As shown in the figure, and using the deep reactive ion food engraving (DRIE) for orientation _ from the Shi Xiji _ lower back, and forming a space 1 〇 1 reaching the insulating layer 20 in the fine orientation of the wire; As shown, the space 101 from the base of the Shishi base 10 utilizes ions _(10) to perform the orientation _ of the insulating circuit layer 2, and reaches the preset microelectromechanical junction (4), and forms a space 2〇1 reaching the sacrificial layer 3〇; As shown in Fig. 42, the space 2〇 from the insulating circuit layer 2〇 is completely eliminated by the residual technique 19 200908070, and the microelectromechanical structure 2 is achieved. At this time, the conductor blocking layer 80 can be preset at least. The second micro-electromechanical. 偁Zi electrical connection, the micro-electromechanical structure 21 above, and the steam application; the effect is: and can reduce the packaging cost (such as by the aforementioned semiconductor micro-structure manufacturing method 1. Can effectively avoid side money (as mentioned above) 2. It reduces the micro-electromechanical exposure, damage probability mentioned above. 3. It can freely climb the thickness of the micro-electromechanical structure (as mentioned above) 4. It can improve the sealing effect (as mentioned above). 5. It can use the conductor blocking layer 8〇 for μ ^ ° At least ~ micro-electromechanical structure 21 electricity 1 · raw communication 'and does not affect the original micro-electromechanical structure design. Manufacturing method new ^ 1 new semiconductor micro-structure system: method, its first (four) edge circuit layer upper surface (4) The dependence of the section—the sacrificial layer 2, the barrier layer, and then the underlying substrate fF A ifr, # , θ, the barrier layer under the 矽 base, and the deep reaction ion space from the moon surface under the 矽丞原, Correspondingly, the empty gate of the micro-electromechanical structure is sequentially inserted into the insulating circuit layer, and the instrument is corrected by the suspension of the Dalai electromechanical device; otherwise, there is a touch-free, and the rate is low, which can reduce the final packaging cost; Therefore, the invention has the industry > AL spears for ten students. It should be no doubt that in addition to the sect of the sect, the spears in this case are exposed, and this feature technique has not seen 20 200908070 before the application. The publications have not been used publicly, not only have the fact that the effects are improved as described above, but also have additional functions that cannot be neglected. Therefore, the "novelty" and "progressiveness" of the present invention have met the patent regulations. The proposed method patented invention, said prayers vouchsafed to review and give early patent-pending, will be a real sense of ethics. 21 200908070 [Simplified Schematic] FIG. 1 to FIG. 5 to FIG. 6 to FIG. 2 are schematic diagrams showing the steps of the method of the embodiment of the present invention. Steps of the method of the thickness modulation embodiment of the present invention are shown in FIGS. 13 to 18 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 19 to FIG. 25 are intended to be used in the steps of the present invention; the method steps of the embodiment of the present invention are shown in FIGS. 26 to 35; The electromechanical junction reversal control has a thick embodiment and a schematic diagram of the steps of the 36th to 42nd steps. The microelectromechanical structure of the present invention is used to form a conductor barrier layer. [Main component symbol description] 矽 substrate 10 upper surface 11 lower back surface 12 space 101 space 102 insulating circuit layer 2 〇 space 201 MEMS structure 21 hole 22 22 200908070 sacrificial layer 30 space 301 Blocking layer 40 money blocking layer 50 opening 51 storage layer 60 hole 61 space 601 bottom resistance layer 70 conductor barrier layer 80 23