TW200907727A - Method for adapting schematics for different manufacturing processes and different operating specifications - Google Patents

Abstract

A system 1 for providing a plurality of sized schematics 2 for respective analogue electronic circuits each having one or more electronic components. System 1 includes memory in the form of a structured database 3 for storing sized schematics 2 and a structured database 4 for storing a plurality of design objects 5. Each of objects 5 contains first data 6 in the form of a plurality of data records 7 that are indicative of respective specifications for the components. The design objects also include second data 8 in the form of a plurality of data records 9 that are indicative of respective specifications for the electronic circuit. Third data 10 includes an optimization script 11 that is indicative of further specifications for the components. An interface, in the form of a computer terminal 13, allows a user, in the form of a circuit designer 14, to selectively define all of the data. A processor, in the form of a central server 15, executes script 11 and provides a respective sized schematic 2.

Description

200907727 IX. Description of the Invention: [Technical Field] The present invention relates to a system for providing a circuit diagram of a circuit, an electronic circuit, and a method for providing - including at least - an electronic component A system and method for a circuit diagram of a lightning circuit. The main purpose of the present invention is to determine the specifications of electronic components for radio frequency (radio freqUency) and analog power (4), and the present invention will be described hereinafter. "It should be understood that the present invention is not limited to the field of application, but is also used for the use of other electronic circuits and for the determination and optimization of parameters in addition to specifications. [Prior Art] Finding (4) The discussion of cutting techniques in the article should in no way be regarded as an endorsement of the fact that such prior art is well known or constitutes a common knowledge in the field.

The design of an electronic circuit typically involves the formation of a series of circuit traces that are tailored to one or more of the specifications, the range of operating conditions, and the process. - The conventional circuit diagram of a circuit consists of a series of circuit components defined by the user (usually a circuit designer) that includes the component type, the connectivity between the components, and the components. Other layout information, so other layout information includes specification information that is directly provided by the circuit designer or calculated by a simple formula. Then, based on this circuit diagram, the simulation software is used to simulate the performance of the circuit, for example, using the simulation software "spicE (Simulation Program with Integrated Circuit Emphasis)" which is known by the trademark. This analog software replicates the performance of the circuit and the operating point of the circuit, and then provides the results of the modulo 200907727. The designer should modify the component type, the nature of each component, and other layouts of each component as well as the results. Repeat the simulation and modification until the designer has provided the best circuit. Especially for complex circuits, the number of repetitions will be (4) large, and the designer will spend a lot of time. Although the above iterative simulation and modification process can be finally obtained - the best circuit and the components with the best specifications, it has been found that the circuit diagram will vary depending on the specific operating conditions and process, and if it is desired to make the line suitable for other specific conditions or processes It usually needs to be done - a separate simulation and modification process to customize the wiring diagram accordingly. SUMMARY OF THE INVENTION It is an object of the present invention to overcome or at least ameliorate at least one of the disadvantages of the prior art or to provide a suitable alternative. In general, in the aspect, the present specification describes a method for providing an I-like circuit diagram in which an analog-like electrical power includes a first data and a second data, and the analog electronic circuit has - or more Electronic components. The method includes the following steps: providing a design target, the design target third data and a fourth data, the first tribute is used to indicate component type and connectivity information of the components, and the second data is used to indicate the One or more specifications of the electronic circuit; the third data is used to define a second-line CinSt-) (script) '' and the step-by-step specification' is used to indicate the electronic circuit - or more Manufacturing specifications and - or operating specifications of the electronic circuit. The method allows the user to selectively ◎ all of the data; and to process the design goal to provide the fifth material from the + normalized line. The normalization line (4) includes (4) dimensions and connectivity of the material of the electronic circuit. Wei's secret map can be used for production. 7 200907727 5. It is a type of net meter that can be used to simulate the circuit performance of the electronic circuit and the layout of the layout. In a particular embodiment, the method allows for the change of the fourth lean material of the design goals and subsequent processing of the design goals to obtain a new normalized circuit diagram that is suitable for the fourth material. . The fourth document contains the following manufacturing specifications: the manufacturer and manufacturing location of the clothing and the component of the electric device, the statistical information on the matching characteristics and changes of the manufactured device, and all such devices that can be manufactured by the process. The model number of the device and the accuracy of the device type. The fourth data can also be as follows: the specification of the supply voltage specification, the operating temperature range, and the higher-level design goals that are part of the other design goals. In the design goal, the second data indicates the desired performance or specification of the normalized circuit diagram to be generated by the design target, and the reference to the design target: data or other design goals; The three f-materials consist of a series of instructions or only seven batches of long-term indicators. The series of instructions or instructions broadcast instructions on how to determine the specifications of the components, including the first, second and fourth data. The third data contains a series of instructions or instruction batches that specify the performance of the simulation of a single component or a collection of components, and the desired analog characteristics of the component or components. - The method comprises the steps of: determining the specification of the component, matching the simulated characteristic with the specification in the third data, thereby deriving the normalized circuit diagram. In the specific embodiment, the third data specifies DC operating point parameters and voltages and matching characteristics of the transistors to determine their specifications. In another embodiment, the fifth information of the design goal is also composed of at least 200907727 a performance parameter of the circuit, and is the _th of the design goal. Set the second or third data of the tree to use. The other group: the current group, the current consumption, the noise index, the gain 'number system, the self-including the force, the bandwidth, the third-order load with the input of the input, the output drive breakpoint, and the round For reference, the third-order intercept point, the second-order third-order spectral distortion, the second harmonic distortion, the second-order intercept point, the corner, the over-excitation, the bias current, and the trembling noise density, phase = Offset: tremor noise power supply rejection and substrate noise suppression. Sfl, timing jitter, overall, in another aspect, this specification describes the method for the normalized circuit diagram of the analog electronic circuit: "species for the proposal and the ancient - bucket -2, 'light' s Hai Temple analog electronic ray 个 electronic components 'where the system contains the provision - design of the goal, the design objectives include: a first data to indicate the components of the components;; type and connectivity information; -Second: #料的,和零件类规格.-n Use 4 or not the electronic circuit - or multiple specifications, H material 'to define a series of instructions or instruction batch mark to refer to - Or a step-by-step specification of a plurality of components; and - a fourth data indicating - or a plurality of manufacturing specifications of the _ sub-circuit and the electronic circuit - or a plurality of operating specifications Define all such information; and process the design objective 'to provide a fifth-form composed of - normalized circuit diagrams. The normalized circuit diagram contains the physical scale of the electronic circuit. The normalized circuit diagram can also be used to generate or be a netlist that can be used to simulate the circuit performance of the electronic circuit and to construct the layout. The system includes: - an interface 'for the user to selectively define all of the bedding' and a processor adapted to handle the design goal to provide a fifth of the - normalized 200907727 circuit diagram data. . The normalized circuit diagram generated by the Hai's first generation includes the real-inch and connection of the components of the circuit diagram and can be used to generate a network table, which can be used for the circuit performance of the electronic circuit. Simulation and layout construction. In a particular embodiment, the system allows for the change of the fourth data of the design goals and subsequent processing of the design goals to obtain a new normalized circuit map adapted to the new data in the fourth material. The fourth document includes the following manufacturing rules: the manufacturer of the electronic circuit, the manufacturer of the components, and the manufacturing location, statistics on the matching characteristics and changes of the manufactured device, and all such agricultural products that can be manufactured by the process. The U model and the accuracy of these device models. The fourth data may also be as follows: the specifications of the power supply specification, the operating temperature specification, and the higher-level design goals. H; in the system, 'the third data consists of a series of instructions or instruction batch files, (10) the list of instructions or instructions for the batch broadcast instructions how to determine the first, second and fourth data. :t Specifications for these components. The third data is used to specify the performance of the simulation of the "single-component" or a collection of components, and to specify the desired simulated characteristics of the component or components. The system includes the following steps: The specification of the component is determined such that the simulated characteristic matches the specification in the third data. In the implementation of sorrows, the simulation type can include static analysis; DC simulation; transient simulation; harmonic balance simulation; periodic steady-state simulation; quasi-periodic steady-state simulation; S/parameter simulation; AC simulation; Function simulation; pole-zero analog simulation and phase noise simulation. - The intended design The embodiment of the present invention includes one or more of the following advantages: 200907727, which can be used for different standardized circuit diagrams according to different processes, performance parameters, operating ranges, and the like. Designers initially did not pay more attention to component specifications, but: Pay more attention to the actual functionality of each component in the overall performance environment of the circuit. Design: Effectively obtain the designer's intentions and considerations. ^ ^ Unless otherwise expressly required by the above T, the measures used in this specification and the claims include: (_咖和comprising) and similar terms shall be deemed to have a meaning of 'inclusive' rather than exclusive or exhaustive. Meaning; in other words, has the meaning of being limited. [Embodiment] Referring to FIG. 1 and FIG. 2, a method for providing a plurality of normalized circuits for each analog electronic circuit having one or more electronic components is shown in FIG. The body 'heart recall body' is used to store the structured lean material of the normalized circuit diagram 2, 3 and - for storing a plurality of structural objects 4 of the design target 5. As best shown in Figure 2, each design objective 5 contains a first data first data 6 is a plurality of data records 7 indicating the specifications of the respective components. The design goals also include a second material 8, which is a data record 9 indicating the various specifications of the electronic circuit. The third document 1 contains the -instruction directive: Talent Field 11' is used to refer to further specifications for such components. An interface as a computer terminal 13 allows a user (i.e., a circuit designer 14) to selectively define all of the data. - The processor (i.e., used as the central server 15) executes the command batch file 11 and provides a respective normalized circuit diagram 2. The designer 14 can selectively define the data, that is, all of the data can be defined by the designer, or some of the data can be defined by the designer, or all the data can not be designed. 2009 20092727 πa +丨 and 1:1, the library 4 contains a number of template design goals (not shown), which is selected in it#. Even if the template matches the exact requirements of the designer, then the first, second or second: The younger brother - Beca white does not need further definition. However, the stone is only available for the usual or simple Thunder Road. Generally, the first, second, and third data are at least in the middle - Yishan' is selectively defined by the s, and more generally, the secondary P is defined selectively by the 4f4. In some cases, the first, second, and third materials are all defined by the designer. In the present embodiment, the 'mth-m data is all accessible by the designer and is: 'in other embodiments, the access to the material of the material is based on, for example. also. The ten questions or experiences are selectively provided and managed by the designer's login privileges. In some implementations, only the third (four) is accessible to the designer. It should be understood that each of the normalized circuit diagrams 2 is for a circuit having a plurality of components, and each of the design goals includes information 6 and data 10 for defining parameters for each component, and data 8 and information of the circuit. 1〇. In other embodiments, there are circuit diagrams for circuits having hundreds or thousands of components or fewer than ten components. In some cases... the circuit will have only one component. • I and. The electronic circuit not shown in Fig. 3 is implemented in one of the design objectives 5. ', the official figure 1 only exemplifies three normalized circuit diagrams 2 and three design goals. However, it should be understood that 'this is only for the sake of clarity and the database 3 and 4 respectively contain hundreds of normalizations. Road map and design goals. The system I includes a further progressive structured database 16 for storing the fourth data 孑5's 'Beet 17' indicating the specification of the 2009 20092727 road that is to be manufactured with the route map provided by the target 5. The material specification is referred to as the global parameter, which represents the electronic component or the proposed circuit/in the case of the selected operating conditions (eg, operating temperature range, power supply fluctuations, or other operating conditions) of the selected system. These global parameters also include: the device's electrical diode, bipolar junction transistor (step), field effect transistor, tolerance: inductance, varactor, diode, etc. Model; component system—...statistics of matching characteristics of components; and model accuracy. In the case of repeated applications, the amount of ice + material 1 is used. Bay 1 uses external or alternative global parameters to provide design goals

In the present embodiment, the data 17 (i.e., the global parameter) indicates both the manufacturing process of the electronic circuit and the woodwork specification. The data 17 is provided by the command batch slot n batch file u. In the context of this specification, it should be understood that the term "normalized circuit diagram" is used to replace a circuit circuit diagram or a radar technology. "Sub...the consistent example of layout" has been made by system 1 or -similar = It is privateized or otherwise processed. In the embodiment shown in Figure ,, the specification of the circuit diagram will include the definition of the layout of each circuit and the information of the specification and other information. In other words, the normalized line _ = The 相 phase table can be used to simulate a circuit with a suitable circuit simulator. In some embodiments, the normalization line will be stepped into the net list. The schematic diagram of the circuit diagram "circuit diagram" is different from the "circuit" or "where the circuit and circuit diagram are common, "circuit" or "use package" 3 The conventional symbols of the electronic components in the circuit are connected to the components of the circuit diagrams in Table 13 Γ, i 200907727. The circuit is not practical except that it is clearly indicated in the context. Real body electrophoresis The "design target" described in the preferred embodiment is as follows: the specification of the J-channel two-way circuit diagram (ie, the first data 6), the +, · σ • electricity, and the electronic circuit (ie, the second data 8) And a batch of batches (ie, the third asset contains electronic Thunder, π,). In some embodiments, the design goals are also & specifications and/or operational specifications (i.e., fourth material 17). Autumn and more generally, the design goals will involve the recording of relevant uses and parameters. I... "Which of these design goals are used to define a data set, the data set is fine and the input data is scheduled and processed by the system to perform the most for = ^, the performance parameters of the material path, the operating range of the circuit, etc. The advantages of these 4 cases are that 'there is no need for the designer to directly normalize the components. More precisely, the $7 meter can be designed in other aspects than the component specifications before forming the _roadmap. The goal defines at least a third data 10. This makes it possible for: • The designer initially determines the actual specification of the components in the overall performance of the circuit (defined by Data 8) (by data 6 and Script 11 is defined.) • Center 5: The target can be used to form a standardized circuit diagram according to different conditions of the process, performance parameters, operating range, etc. Ό10 mesh can effectively obtain the designer's Intentions and considerations. For example, when designing a circuit, the parameters of a certain transistor can be used to define the specification of the transistor and how the 4-parameter is derived. 14 200907727 During or after the formation of each normalized circuit diagram 2, the processor μ also generates a fifth: material 18, and the package 3 indicates the "or multiple performance parameters" of the circuit with w! 9 of a plurality of: After forming the circuit diagram 2, the feeder 15 extracts the layout that has been optimized according to the first data 6, the second data szhe-1, the 8' second tribute, and the fourth data 丨7. The performance parameter of the specific circuit of the component specification. The parameter b can then be used to hold the H-characterized circuit diagram or the circuit set containing the normalized circuit diagram, and the class 1 (4) 'for example: static analysis, wave balance Analog state simulation, quasi-periodic activity, 'heart' simulation, S-parameter simulation, AC simulation, transfer function simulation, pole-zero analysis, miscellaneous, noise analysis and phase noise analysis simulation, and 苴 other simulation By extracting the equivalent energy parameter 19 · Rainy sputum is enough, and further evaluating the effect of the proposed chaotic path, using the equivalent energy to establish the number of giant 隹 P彳 does not establish a macro 杈 type, It is mathematically replaced with the normalized circuit diagram....a, a . ^ U and materials used Recorded as other regulations of mosquito Γ π - section. Do as much as 2 (2) two performances, however, it should be understood that in other embodiments and other settings "" the number of performance parameters. In the eyes of the system, you can use different numbers in the present embodiment, the performance parameters, etc., or the circuit. One or the following parameters: the Hongsheng, the heart-breaking turbulence, the noise index, and the output driver. Ability, Lai Gong,, & wheel load, old U, third-order truncation point with input as reference, output as

Sr, eight for reference, breakpoint, to lose = ohm r), Μ input offset, output offset, tremor noise Μ (contact erlin IT (_dnve) must, w (four) thoroughly test se power spectral d It ), white hybrid, force rate, gold density (whitendsep〇wer 15 200907727 spectral density), first harmonic distortion (sec〇nd harm〇nic shirt such as 丨 (10)), third harmonic distortion (thud harm0nic distorti〇n), Total harmonic distortion (shirt), phase noise, phase jitter (u shegj) (four), power supply rejection (power supply rejecti〇n), and substrate noise suppression (pure coffee) e(10) 脱reject). In other real hoods, the plucking factor is used. The performance parameter 19 is stored as part of each normalized circuit diagram in the database 3. In other embodiments, the equivalent energy parameter Then stored in the database 16 or other location.

Each design goal 5 includes a third material 10, and the third data 10 is in the form of an -optimized instruction batch file 11 or - to _ the following instruction batch label link form: the finger ^ batch number contains multiple Executable instructions for selectively optimizing specifications of one or more components or combinations of components within the design target. Performing the instruction batch reading in the following manner: determining each component line: performing a related conversion for each component or group of _ and determining the group specification m in a manner based on the results of the simulations The characteristics are exactly as defined in the material instructions. In this example, the instruction read also produces a performance parameter 19. In the current implementation, the k-command batch file u is stored as part of the associated design target 5, respectively. In other embodiments, the instruction batches n, although associated with the respective leaf target 5, are stored in, for example, the database 丨6. ❼ In addition to the specifications provided by Data 6, the command batch U can also define -10 = 14 to selectively define the specifications of such components. For example, the % of the circuit 规定 specifies that the base of the -dipolar transistor is connected to the emitter of the second bipolar electrode and the first The emitter of the crystal is connected to the 〆16 200907727 resistor, and the other end of the resistor is connected to the earth rail. The designer 14 can thereby further define the relationship between the two transistors by, for example, defining the emitter current of the first transistor (and thus the base current of the second transistor) to a predetermined size. The instructions in the batch of instructions are written in a design language that allows for the determination of a MOS transistor when providing a suitable combination of MOS device model specifications, device type specifications, area specifications, gain specifications, and voltage specifications. Specifications of the order. One of the area specifications of a MOS transistor is defined as a specification that is primarily or negatively correlated with the product of the channel width and channel length and the number of fingers over a wide range of operating conditions. The area specification is usually selected from the group consisting of: gate capacitance, source capacitance, gate-source capacitance, gate area, threshold voltage mismatch, current mismatch, and dithering noise corners. , channel width, and channel length. However, in other embodiments, there may be additional or alternative area specifications. The gain parameter is defined as a parameter that is primarily or negatively correlated with the transconductance of the MOS transistor over a wide range of operating conditions. A gain parameter of the MOS transistor is typically selected from the group consisting of overdrive voltage, bias current, transconductance, output impedance, channel length, channel width, and white noise current. However, in other embodiments, there may be additional or alternative area specifications. Examples of valid sets of MOS transistor voltage specifications used in determining MOS transistor specifications include: • Specifying gate, drain, and substrate voltages, and source voltage optimization; • Specifying source, drain, and substrate voltages And the gate voltage should be optimized; 17 200907727 • The gate and drain voltages are specified, and the source and substrate voltages are equal and optimized; • The source and substrate voltages are specified, and the gate and drain voltages are equal. And optimized; • The source and substrate voltages are specified, and the gate and drain voltages are related to each other and optimized by a well-defined relationship; and • all of these voltages are specified. The design language used to program the instructions in the batch file also allows a command to determine the bipolar junction transistor specification to be made when providing the appropriate combination of specifications: bipolar junction transistor device type, device type, area Parameters, gain parameters and effective voltage specifications. For a bipolar junction transistor, the area parameter is defined as a parameter that is related or negatively related to the product of the total emitter area over a wide range of operating conditions. This includes, but is not limited to, current density, cutoff frequency, base-to-collector gain ratio, base junction capacitance, collector junction capacitance, and transistor mismatch. For a bipolar junction transistor, the gain parameter is defined as a parameter that is primarily or negatively correlated with the transconductance of the transistor over a wide range of operating conditions. Examples of gain parameters include, but are not limited to, collector current, base current, emitter current, and transconductance. Examples of effective sets of bipolar junction transistor voltage specifications used in determining a bipolar junction transistor specification with a gain parameter and an area parameter include, but are not limited to: • specifying the base, collector, and substrate voltages, and transmitting The pole voltage is optimized; • The emitter, collector and substrate voltages are specified and the base voltage is optimized; • The base and collector voltages are specified and the emitter and substrate voltages are equal and optimized; 18 200907727; The emitter and substrate voltages are specified, and the base and collector voltages are equal and optimal. • The emitter and substrate voltages are specified, and the base-to-one, zeta potential squeezing is related to each other by a clear relationship. Optimize; and • specify all such voltages. Execution of the specification determination command (ie, running the instruction batch, ^田1 to form the circuit diagram 2) will result in a fixed-known specification f-wide body, and the previous "unknown" voltage will also be calculated and Included in Figure 2 of the respective line. When the specifications of the respective circuit components have been determined, all of the DC poles of the 1-day-inch Japanese body are made in the relevant circuit diagram 2 and can be supplied to the designer 14 via the terminal η. In the embodiment, the D pieces are stored in the body line record 25 in the respective line drawing 2, and in the bean 眚 ^ ^ " in other examples, the item records are Stored in a separate file in Figure 2 separated by a line. /, line into the ^, for the hall hall M1, the designer can access the idle pole by running -I: I, such as Μ,), 疋义贝科1〇. In this embodiment,

J t' 5 and the juicer 14 uses the characteristics of the sentence · A R m line. 3. In BSIM version 33m〇

Version 4.0 MOS model and FKV 婼 士 bIM Guide 所有 All capacitances, trans-bias, over-excitation voltage, mismatch, device size, cut-off frequency of the Cong device in the EKVfe type. In addition, the designer can also provide the designer with additional or alternative features. In the other-instance, for - has been marked as "strong or "m.gpi" • by the body, can use the life", the second bad is stored in the existing literature commonly used nomenclature 19 200907727 Base-emitter capacitance and conductance. In this embodiment, the characteristics of the bipolar transistor stored in circuit diagram 2 and available to the designer 丨4 include: all junction capacitances and junction conductance, transconductance described in the Gummel-Poon model. Output impedance, bias current, mismatch, device size, cutoff frequency, and noise performance. In other embodiments, there may be additional or alternative features of other models. When System 1 is used in large circuits, it contains and utilizes equation solving capabilities. It is because the large circuit 'more often defines the data 10 of a given transistor - and in particular the command batch 11 - with reference to the command batch 11 of the other transistor. In other embodiments, the design goals first reference the data 17 - the global parameter one - to estimate the minimum expected routing parasitics of the proposed circuit. Since this is done before the layout is completed, it is able to more accurately estimate the performance parameters of the components and circuits that are sensitive to parasitic phenomena. Examples of such parameters include bandwidth and Q factor. Since this was done early in the design phase and prior to the layout, it has been found to reduce the number of iterations required by the designer to achieve a final normalized circuit diagram 2. In other embodiments, the determination of component specifications is made using other analog forms. For example, in one embodiment, the result of executing the instruction batch file 11 is to invoke another simulator to simulate the performance of the circuit, a portion of the circuit, or another associated circuit. The information obtained from the simulation is then used to aid in the formation of a normalized circuit diagram. Examples of such simulations include, but are not limited to, AC simulation, noise simulation, harmonic balance simulation, transient simulation, periodic steady state simulation (periodic) Steady state simulation ), cyclostationary noise simulation, phase noise simulations, transfer function simulation 20 200907727 (transfer ftmction simulation ), pole-zero analysis (p〇ie zer〇 And quasi-static periodic steady state simulati (10). In embodiments in which one of the first design goals includes a further design goal and each of the design goals includes an optimized instruction batch file, the further step can be initiated by the instruction batch file of the first design goal. Optimization of design goals. More specifically, &, 6 Xuan first design target instruction batch mark will also execute the second $ leaf target instruction batch slot when executed. When executing the instruction batch file 11, reference the data 6, 8 and 1 in the design objective 5, together with the data 17' in the data 4 16 to form a normalized circuit diagram 2, which is not only in the normalized circuit diagram 2 - At the component level, and also at the circuit level, and at the global parameter level, as described above, at least in some cases, other design goals or circuit diagrams are referenced. In addition to the data 丨8, the circuit diagram 2 also includes a plurality of records in the form of h. The specification determines the poor material 1 in this implementation. The records not only indicate connectivity and component information, but also indicate all that is required to define a netlist. Specification determines information.

Record 7 relates to the various components in the circuit, and therefore, there is a plaque component-like record 7 in the target 5. In other embodiments, when more than one component is specified in a single record, each record indicates that all of the specifications of the small pieces are indicated by the poor material 6 and are in detail printed by the meat. The specifications of the seven systems are related to the individual groups to be used in the circuit, the type and type, and the connectivity between the components used to define the edge circuits. , § Shi and the day to keep 'this is enough to stipulate these components. And the specification and network plus f ^ ^ ^ ^ ^ ^ will be 睑纮 (10) ^ for reference. If you are familiar with this technology, you will understand that the difference between record 7 and the conventional circuit diagram is that the record 7 21 200907727 is irregular; t component type and / or - or multiple component size, and in the formation of their respective Specification Material® 2 _ It is the purest. In other words, although the designer μ may define - or a plurality of specifications of the components - or at least - the size of the components, it is preferred to leave at least the at least 'components - the size of the specification is undefined. More generally; all specifications of all devices are not sized by the designer 14 because the undefined characteristics of the components are optimized by the processor 15. As mentioned above, Data 8 and Record 9 are specifications for the circuit. This typically includes one or more of the lowest performance parameters of the circuit, regardless of bandwidth, input impedance, wheel-out impedance, current capacity, (d) m-line range, trembling: linearity requirements, or other performance parameters. These specifications relate to the overall functionality of the circuit and not to the functions of the individual components used in the circuit. 'However, it should be understood that the first-order material 6 can be added according to the data 8, because the designer 14 can define one or more specifications of a given component according to the body: body specification. For example, if the data 8 = an overall gain performance 'and the component is - the bipolar transistor used to bias the other transistor M, - DC, then the base of the bipolar transistor can be used. The pole voltage and bias current are specified to be related to the overall gain. It should also be understood that the cautiousness of a circuit s % — 峪 峪 # # August is enough for the other - design target information 8 and, or data 18 derived. For example, the production of walls ^ one case and 5 in a younger-circuit 'hope to make the output impedance 盥 a brother - the circuit is called to match, the power transmission of the miscellaneous power is better. Correspondingly, when the instruction batch is executed, the design of the first circuit is to refer to the material 8 of the second circuit from the database 4 when the respective normalized circuit diagram 2 is generated. In some cases, the instruction batch η does not reference the material 8 or the data 18 from the design target of the second circuit, but refers to the circuit diagram generated by the design target 5 using 22 200907727 the same fourth data 7 2. Another example is a circuit such as a power supply dust regulator - a second circuit (such as - RF amplifier) ... ten for the package / original / voltage). The second data 8 of the lightning supply with two % μ refers to the amplifier W house (four) #得产干料心心5 or normalized circuit diagram 2, in order to supply power to the enlarged state # ω 4 Ζ Voltage and output current data. Tongshu, the data of the power supply voltage regulator, 之一 one of the circuit diagrams of the alpha-amplified state, or one of the performance parameters 19.

In other embodiments, the server 15 utilizes input that is passed through the terminal device designer. In the power supply voltage regulator design target example given above, the servo 15 requests the designer to specify a "power supply" or a design target for the circuit to be powered by the _ device. " Referring now to Fig. 3, it is a circuit diagram of a 〇-type M〇s (NM〇s) transistor sharing interpole amplifier 23. The circuit circuit diagram is a schematic circuit - the graphic form is not in the form of the circuit diagram. The circuit circuit diagram includes the marking symbols of various components and the connection information for making the components related to each other and, for example, the terminal, the power supply rail, the grounding k And other reference points. In some embodiments, the designer has the right to change the circuit diagram, i.e., the side circuit diagram is part of the data 6 and is stored in a plurality of records 7. However, in other embodiments, the circuit designer has no right to change the circuit diagram. The designer 14 is able to define the data 10 for each component in the amplifier 23. This is accomplished by setting or changing the command batch number 11 for one or more of the components in terminal block 3. In this embodiment, the 'instruction batch file' is written in a language (such as 6 & described above), which allows the designer 14 to selectively define or not define the data to be stored at all. 8 or the following variable parameters in the data 1 :: 23 200907727 • The processing type of each device, that is, the relevant device model is selected from the list of available models defined by the global parameters. • The supply voltage is expressed as VDDA. • Input impedance one is expressed as Rin. Via the terminal 13, the designer 14 defines the instructions for determining the M1 specification in accordance with, for example, the variable parameters or relationships shown below, which are stored in the command batch file 11:

Size[Ml=NMOS,substrate=0,source=VDDA*0.2,gate?, Γ · · drain=VDDAx〇.4 , GmPlusGmbs=l/RiN , length=minimum , widthclOu] not by the designer 14 The parameters defined by the variable parameters are left to be optimized after executing the command batch file 11. Once the command batch file 11 is executed, it will form a specific specification of the transistor M1 and a known gate voltage. Those skilled in the art will appreciate that the above variable parameters require that the input impedance referenced to the source node of the transistor be equal to the impedance of Rin to achieve a good match and thus provide better power transfer. In order to bias the gate voltage of Μ1, it is necessary to define the transistor M2 accordingly. To provide this bias, the designer 14 adjusts or inputs the variable parameters of M2 via the terminal 13. The variable parameters are included in the same design target as the variable parameters of M1. In detail, the designer 14 defines the following variable parameters for M2: Specification [M2=NMOS,substrate=0,source^O,gate=Ml.gate,drain= Ml. gate 1 current=Ml .current/4 » length ^minimum] Once the design target batch file 11 is executed, the specification of M2 will be determined 24 200907727. When a current equal to 1/4 of the current of the transistor M1 is applied to the bias current of M2, M2 will be The gate of transistor M1 produces the correct bias. The bias current IB2 is expressed as: Ib2, M2. current is a bias current applied to the transistor ’2, and the designer 14 forms a current mirror Μ3/Μ4 at the source of the Μ1. It is desirable to have the current mirror have a suitable overdrive voltage and a mismatch of less than 1%. Accordingly, designer 14 defines the following variable parameters:

Size[M3=NMOS 'substrate = 0 > source = 0 , gate?, drain=M 1 .source > overdrive=VDDA/l0 j mismatch <1 Pt)] Recalculate[M4=M3,drain two M3,gate The next step in current designer 14 defines one or more variable parameters for resistor R1 at the output of M1. This is achieved by including/changing the variable parameter of R1 in Design Objective 5 (Material 10): R] = VDDA/2/M1 .current Thereafter, Designer 14 provides the following variable parameters for capacitor Cl:

C1 = 10*M1.CGG Once the designer 14 has defined all the required user-defined variable parameters, ie the data 10, the design target 5 is submitted to the server 15 in order to be able to execute the command batch file. 11. The server 15 runs an optimization command batch number 11, wherein the command batch level is particularly responsive to the variable parameter, i.e., the third item, used to form a circuit diagram 2. As described above, after the server 15 runs the command batch file 11, the resulting circuit diagram 2 contains all of the required specifications for a given circuit and all components of the circuit. The line _(4) is stored in the f-bank 3 and contains records 21 indicating the specification information, circuit diagrams, connectivity information, device or component type, process, etc. Circuit diagram 2 is an example of an optimized circuit based on a number of inputs, including: • any requirements for individual components; • overall circuit performance; • global parameters; and • requirements for surrounding circuits. The final layout and fabrication of the circuit design is then achieved using the circuit diagram 2 4+ B S* M h π for the specific 1 and the end-of-life application. It is desirable to make w - π η Y, different $L process (such as smaller minimum feature size) to make the same circuit, or ant ant - right to ~ different application (such as wider operating temperature range) m can use the same - design The goal is to design another example of the circuit. In particular, the server 15 runs the blood of the blood + ρ, ,, π α? 7 batches - the person U, the Aynthesis data 8, 8 and 10 (all of which remain unchanged) and for the new 劐鼗; Covered as a new global parameter of the database μ6 for the conditions of μ ', Ding ah and #. Thus, another circuit diagram 2 is provided which implements one of the design goals of the optimization example' but is implemented by the server 15 in response to a unique input. Accordingly, a single design goal can be reused to achieve an optimized specification, rather than having to be caged by the designer and then optimized by the stack. In this embodiment, the designer can also modify the variable parameters and re-execute the command-in-time file to provide another normalized circuit diagram. The command batch file U is fine--the design language is edited, and the New York language is based on the specification of the rainway (ie, data 8) and according to the expected process and operating conditions (ie, data (7) electricity 26 200907727: 〇:, and the specifications of the parts. One of the roles of the command batch file 11 is a combination of expression data. The noon and the sixteenth person define the function of the component and one or more surrounding components, and the global parameters. In the following, the transistor is And a bipolar transistor to provide an example of the characteristics of the language. However, it should be understood that the language is also applicable to other components included in the integrated circuit. The end user 13 4 provides a graphic use Interface ((10))%. The 2 is the line diagram input interface, which can be viewed graphically in each t to make it easy to identify its type and its connectivity to the component. The seven components, the GUI will turn down the man „ _ _ > — enough six ', brother - and third information, and enable the designer to 夂 ": change the reference point of the data or just manually redefine certain resources Once the designer is on a given component or on the whole The specification of the circuit is changed, and it is set to: Renew the update to recalculate any voltage or current fixed before the execution of the instruction batch slot 11. The electrician understands that as the designer gradually provides separate components or integration _ _ _, 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Design goals • After the formation-design goal, the most κ pre-conditions or process recipes can be executed multiple times. Accordingly, the designer needs to “start from the beginning” in the fabric process.对—新27 200907727 • Provides a design language for the setters to indicate certain parameter specifications of the device on the basis that, when these parameters are specified, the language can achieve the specification of the component. Provides a design rumor that captures the designer's design intent and key design ideas, including the order in which the component specifications are determined and which parameters are used to determine the component. The 仏 仏 ' 々 々 々 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 够 • • • • • • • • • • • , for example, overall and noise performance, so that the circuit's frequency response, bandwidth, gain, IIP3, and other parameters can be used to build a macro model of the circuit. Or "electronic components." The individual components of an electronic circuit are generally referred to as " It will be understood by those skilled in the art that other terms may be used as equivalent terms, such as "devices" or "electronic devices" or "components" or "electronic components" unless explicitly stated otherwise in the following description. Understand, in this book

Any device or any portion of a device and/or device can be used to process electronic data, such as from an electronic device n of the memory device to convert the electronic material into other electronic musical articles. Other electronic materials may be stored, for example, in a register and/or memory. "Computer" or "computer" (_师师职仙〇) or "叶曾平台(C〇mputlngpIatf〇rm)" may contain one or more processors. - An example is a form of computer readable body that carries a set of instructions for execution on - or a plurality of processors, such as a computer program. For example, a processor in the form of a server 15 is - a system for providing electronic materials. (d), skilled in the art, embodiments of the invention may be implemented as a method, a device - for example, a special f such as a bedding processing system equipment, Or a computer readable carrier medium, for example, a "brain product. The electric material read carrier carries a computer code". The electric material reading code includes - group age, if the instruction is executed at - one place, The method may be performed by a plurality of processors. Accordingly, aspects of the invention may be embodied as a method, a fully hardware embodiment, a fully software embodiment, or a combination of a soft body and a hard body. Embodiment I In addition, the present invention can also be carried as a carrier medium (for example - A computer program product on a readable storage medium, in the form of a computer readable program code embodied in the medium. It should be understood that the steps of the methods described in the 'in the embodiment' are performed by a processing system - ie - Execution of one of the computer systems (ie, computer readable code) stored in the memory - or a plurality of appropriate processors. It should also be understood that the invention is not limited to any particular embodiment or stylization technique. And the present invention may be difficult to use using any of the techniques described herein. The present invention is not limited to any localized programming language or operating system. 29 200907727 "One embodiment" (referred to throughout the specification) _ _ 〇 〇 ) ) 」 」 」 」 embo 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Therefore, the phrase "in one embodiment ((1) Team_〇细咖)" or "in the case of (inanemb〇diment)" does not necessarily mean the same as in the embodiment. example. In addition, in the case of the ❹彳 实 实 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , As such, it will be appreciated that in the foregoing description of the exemplary embodiments of the invention, Combinations are made in a single embodiment or are described. However, such a method disclosed should not be construed as requiring that the features of the invention are more than that required. However, it should be explained that, as reflected in the main patent scope of the following claims, each invention can be found in only a part of the features of the single disclosed embodiment. Therefore, the "patent application scope" following the "% of the practice method" is clearly defined by the "implementation method, the implementation method, the electric power * τ 兵 母 mother - 4 item itself represents a separate embodiment of this 。 。 。. Some of the embodiments described above contain certain features and do not include the features contained in the embodiments. The examples are less, and the person skilled in the art will understand that different implementations are also considered to be included in the present invention. Within the scope of the invention, and the formation of the difference between the two: 'This article will implement the Hunan-Finance A-M--T-, the four methods of the various, and &,; can be - computer system 1 (four) or by 'm ±. m,, ~ he The device of the function of the Bianbian function, the processor having the instructions for implementing the method or method, or the element of the method = set. Further, the device or system described herein实,, 70仵 is used to implement the present invention In the description provided herein, numerous specific details are set forth. However, the library understands that the implementation of the present invention may be implemented without the specific details. In order to avoid the understanding of this description, 4 well-known methods, structures and techniques have not been shown in detail. ΜIn addition to mosquitoes, this article describes the sequential adjectives -", "first", "Third" and the like merely refer to different instances of the object (5), rather than implying that the objects so described must be in a given order - regardless of order, spatial order, hierarchical order, or any other manner. In the scope of the patent application below and the description herein, any term "comprising (_,_)", "consisting of (_ρ(10)"〇" or "including (comp.)" is an open term. It is intended to include at least the elements/features that follow, but does not exclude other elements/features. Therefore, when the term "including (c(10)pdsing)" is used in the scope of the patent application, it should not be construed as limited to The device or component or step listed thereafter. For example, the expression "a device containing A and B (&amp; deVlce comprismg A and B)" should not be limited to a device consisting only of components A and B. Any of the terms used in this article "including (mc丨uding)" or "which includes" or "including indudes" is also 31 200907727 - open language, which also means - From the elements/features that follow the 匕3, do not exclude other pieces/features. Therefore, 仁 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ~ item ==7 is said to be preferred for the present invention </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The formulas are only representative of the programs that can be used. 4 Add or remove functions from this section, and interchange the functions of each function block. 1This method adds or removes steps from the method. A specific implementation of the present month, however, those skilled in the art will understand that 'it is also possible to carry out many other forms of riding. [Simplified illustration of the drawings] The above description is by way of example only with reference to the accompanying drawings In the drawings, the /1 diagram is an unintentional illustration of a system for providing a plurality of normalized circuit diagrams for each electronic circuit having one or more electronic components according to a design goal; The data is included in the design target and the data of the normalized line $Fig. shown in the figure; and the third figure is the circuit diagram of a common gate amplifier, the design target of which is provided by the system shown in Figure 1. Main component symbol description]: System: Structured Database 2: normalizing circuit 4: Structured Database 32200907727

5: Design goal 7: data record 9 · tribute record 11 : optimization instruction batch file 14 : circuit designer 16 : structured database 1 8 · · fifth data 21 : record 23 : N type MOS ( NMOS 25: Data record Ml: MOS transistor R1: Resistor 6: First data 8: Second data 10: Third data 13: Computer terminal 15: Central server 17: Data 19: Performance parameter transistor common gate Pole amplifier 26: Graphical user interface M2: Transistor C1: Capacitor 33

Claims (1)

200907727 X. Patent application scope: h: A method for providing a standardized circuit diagram for providing an electronic circuit having - or a plurality of electronic components, the method comprising the steps of: a) providing a design target having : i. the first information to indicate the component type and connectivity information of the electronic components; U. the first bedding material 'to indicate at least one specification of the electronic circuit; m. the second tribute' to define - a series of instructions or instruction batch slots (scnpt) to indicate the further step specifications of the one or more electronic components; and iv. fourth information for use as a specification; showing the manufacturing specifications and operational objectives of the electronic circuit All of the funds b. enable a user to selectively define the design material; and one of the graph components C• handle the design goal to provide the fifth material from the normalized line. 2. 3. In the method described in the claim 苴, the 甲 ” 格 格 线路 包含 包含 包含 包含 包含 包含 包含 甲 甲 甲 甲 甲 甲 甲 甲 ” ” 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The normalized circuit diagram can be used to generate or be a netlist for "the simulation of the circuit performance of the sub-circuit and the construction of the horror." According to the method described in claim 1, Α ^ , 宁文殳6海弟四肓, and processing the s juice targets to obtain a suitable road map. (4) New normalization of the reading towel 34 4. 200907727 5. The method of claim 4, wherein the manufacturing specification comprises one or the following: a process of the electronic circuit; b, the components Manufacturer and manufacturing location; c. Statistics on the matching characteristics and changes of the manufactured devices; the type of device that is sufficient for all such devices manufactured by the process; and e• the accuracy of the device models. The method described in the 'description' includes one or more of the following: a power supply voltage specification, an operating temperature range, and a specification of a design target that is one of the other design goals. 7. The method of claim 4, wherein the electronic circuit (4) - analog or mixed signal circuit is or - part thereof, the analog or mixed signal circuit comprising a function of processing an analog voltage or analog current signal or both . Or information on other design goals. The instruction batch file consists of 'the series of instructions or the command batch file. The second data is determined by a series of instructions or batch files to indicate how to use the first, second and fourth data considerations of 35 200907727. The specifications of the components. 12. The method of claim n, wherein the third data consists of a series of instructions or batches of instructions comprising a specified pair of ', and a component or a component The performance of the simulation of the collection, and the desired analog characteristics of the component or components. 13. The method of claim 1 wherein the process of deriving the normalized circuit diagram from the design objective involves determining a specification of the component such that its simulated characteristic or static characteristic is consistent with the specification in the third material. . 14. The method of claim 12, wherein the simulation type may include static analysis, Dc simulation 'transient simulation, harmonic balance money, occupational (four) simulation, quasi-periodic «state simulation, S-parameter simulation, AC simulation , transfer function simulation, pole-zero (pole-zero) simulation, noise simulation, and phase noise simulation. The method of claim 12, wherein the series of instructions or instruction batches refers to a plurality of specifications of a non-MOS transistor, a field effect transistor or a carbon nanotube transistor: device type, device type , area specification, increase the standard voltage specification. P 16. The method of claim 15 wherein the area specification is within a wide operating condition range is primarily related to or negatively correlated with a product of a channel width of the transistor and a number of channels and fingers. Specification. The method of claim 15, wherein the area specification is - a specification of a group comprising: a gate device - a limited state, a source, and a gate - Source capacitance, gate and pole capacitance, power r 1 &quot;&quot; gate area, threshold lightning mismatch, current mismatch, dithering noise angle, and channel 36 200907727 length. 18. A method as claimed in claim 15 wherein the gain specification is within a range of conditions and is primarily related to transconductance of the transistor. 19. The method of claim 5, wherein the gain specification is a specification selected from the group consisting of, but not limited to, overdrive voltage, partial production, electrical &amp; eccentricity, transconductance, output impedance, Channel length, channel visibility, and white noise current. 2 〇 如 如 如 如 如 如 如 如 1 1 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 铭 有效 有效 有效 有效 有效 有效 有效 有效 有效, the drain voltage is extremely high and the source voltage is optimally 4 匕, and the gate is required to be b. wherein the source, drain and substrate voltages are optimized; and the source and the substrate voltage are c. The gate and the immersion voltage are specified and optimized; d. The source and substrate voltages are specified, and the interpole and the pole are equalized and optimized; " e. The polarity of the pole and the substrate, and the polarity of the pole and the voltage of the pole are related to each other by a well-defined relationship, and are optimized; and f· which specifies all of the voltages. 21. As described in claim 2G The method, wherein if a node voltage is specified, the value is directly specified by the user or derived from the node voltage of the other component. ', the method of claim 12, wherein the series of instructions or instruction batch slots Means 37 22. 200907727 shows a plurality of specifications for a bipolar junction transistor, the The specifications of the crystal include: device type, device type, area parameter, benefit parameter, and node voltage specification. 23. 24. 25. 26. 27. The method of claim 22, wherein the area specification is one A parameter that is related or negatively related to the product of the total emitter area within a wide range of operating conditions. As recited in claim 22, wherein (4) the product _ is selected from the following parameters: current density, cutoff, Base-to-collector gain ratio, base junction capacitance, collector junction capacitance, and transistor mismatch. The method is broadly described in the method of claim 22, wherein the gain regulation is Within the conditional range, 'mainly related to the transconductance or negative phase of the transistor. As claimed in claim 22, the sequel to the molybdenum and the molybdenum, and the armor. The invention is limited to the following specifications: collector current, base current, emitter current, and transconductance. The method of claim 22, wherein the voltage specification is effective in one of the packages: 3 ° a. wherein the base is specified, The electrode and the substrate voltage are to be optimized; and the emitter voltage b. wherein the emitter, collector and substrate voltage voltages are optimized; and the base electrode is c. The base and collector M are specified in the afternoon. And the emitter disk voltage is equal and optimized; /, earth anti-electricity d, wherein (iv) the emitter and the substrate voltage, and the base is equal to the collector 38 200907727 and optimized; e. The emitter and substrate voltages are specified, and the base and collector voltages are related to each other and optimized by a well-defined relationship; and f. wherein all of the voltages are specified. 28. 29. 30. 31. The method of claim 27, wherein if -node_ is specified, the value is directly specified by the user or derived from the node voltage of the other component. The branch of claim 12, wherein the (four) instruction or instruction batch configuration indicates a plurality of instructions from the components of the self-list, the list including capacitors, inductors, resistors, diodes, varactors, and others Design goals. The method of claim 1, wherein the (4) instruction or instruction batch references other materials of the design goal or other design goals. The method of claim 12, wherein the third f-system indicates a device for generating at least one performance parameter to be included in the fifth material, and the parameter is indicative of the performance of the circuit. 32. The method of claim 31, wherein the fifth data is referenced by the second tribute of the design target or the third data or the first data or the third data of another design target reference. 33. The method of claim 31, wherein the equivalent energy parameter is selected from the group consisting of: current consumption, noise index, gain, input load, output drive capability, bandwidth, reference to input Third-order truncation point, second-order truncation point with input as reference, third-order intercept point with reference to output, second-order truncation point with reference to output, third harmonic distortion, second harmonic distortion, input offset, output Offset, trembling noise corners, overexcited, biased, and trembling 39 200907727 Phase noise, timing jitter, power supply rejection, and substrate noise suppression. 34. C. An execution-method system for providing a standardized circuit diagram of an electronic circuit having - or a plurality of electronic components, the system comprising: a. a design target having: i. The information 'is used to indicate the component type and connectivity information of the components; the second information is used to indicate one or more of the electronic circuits, in the third data, to define a series of instructions or Command batch file to indicate further specification of the one or more components; and iv. fourth material 'to indicate the manufacturing specifications and operating specifications of the electronic circuit; b · - interface for making - making (four) selective Defining all such information for the design objective; and a processor that is adapted to process the summary objectives to provide a fifth material consisting of a normalized circuit diagram. 35 々. The system of claim 34, wherein the normalized circuit diagram includes physical dimensions and connectivity of the components of the electronic circuit. The system of claim 34, wherein the normalized circuit diagram can be used to generate a netlist&apos; that can be used for the simulation of the circuit performance of the electronic circuit and the construction of the layout. 37. The system of claim 34, wherein the fourth material is changed, and the system processes the design goals to obtain (iv) the new specification in the fourth (four) 40 200907727 new Normalized circuit diagram. 38. The system of claim 37, wherein the manufacturing specifications comprise one or more of the following: a. a process of the electronic circuit; b. a manufacturer and a manufacturing location of the components; c. The statistical characteristics of the matching characteristics and changes of the device; d. The device model of all such devices that can be manufactured by the process; and e. the accuracy of the device models. 39. The system of claim 37, wherein the operational specifications include one or more of the following: a supply voltage specification, an operating temperature range, and a specification of a higher level design goal as part of other design goals. 40. The system of claim 37, wherein the system is implemented as a computing server, a computer, a computing processor, or generally a software program, a software program set, or a computer-aided design on a computing machine. (CAD) system. 41. The system of claim 37, wherein the electronic circuit is an analog or mixed signal circuit or a portion thereof, the analog or mixed signal circuit comprising a function of processing an analog voltage or analog current signal or both. . 42. The system of claim 41, wherein the component types can comprise: an N-type MOS transistor, a P-type MOS transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, a resistor , capacitors, inductors, varactors, diodes, relays, design targets, or symbolic links to other electronic circuits or components. 41. The system of claim 41, wherein the second data is indicative of a desired performance or specification of the normalized circuit diagram to be generated by the design objective. 44. The system of claim 43, wherein it references other materials of the design objective or other design objectives. 45. The system of claim 41, wherein the third data consists of a series of instructions or a batch of instructions, the s series command or the instruction batch indicates how the first and second The fourth data considerations determine the specifications of these components. The system of claim 4, wherein the third data consists of a series of instructions or instruction batch files, the series of instructions or instruction batch files including performance requirements for simulating a single component or a collection of components. And the desired analog characteristics of the component or components. 47. 48. 49. The line of claim 46, wherein the process of deriving the normalized circuit diagram from the design target relates to the specification of the jersey assembly such that its simulated or static characteristics are associated with the third data. These specifications are consistent. The system of claim 46, wherein the simulation type may include static analysis, DC simulation, load balancing simulation, steady state simulation, quasi-periodic handle pseudo S-parameter plate simulation, AC simulation, transfer function simulation, pole _ zero Analog, noise simulation, and phase noise simulation. The system described in claim 46 is a non-MOS transistor, field effect transistor: device model; device type voltage specification. Wherein the series of instructions or instruction batch files refers to a plurality of gauges of a crystal or carbon nanotube transistor; an area specification; a gain specification; and a system according to claim 49, wherein the area specification is - A specification that is related or negatively related to the product of the channel width and channel length of the transistor and the number of fingers within a wide range of operating conditions of 4207707727. The system of claim 49, wherein the area specification is selected from the group consisting of, but not limited to, a gate capacitance, a source; an electrical junction, a gate-source capacitance, Gate-drain capacitance, gate area of the transistor, threshold voltage mismatch, current mismatch, dithering noise corner, channel width, and channel length. 52. The system of claim 49, wherein the gain specification is a correlation or a negative correlation with a transconductance of the transistor over a wide range of conditions: a specification. 5 3. The system of claim 4, wherein the series of instructions or instruction batch marks a plurality of specifications of a bipolar junction transistor, the specifications of the transistor comprising: device model , device type, area specification, gain specification, and node voltage specification. 54. The system of claim 53, wherein the area specification is a &gt; specification that is related or negatively related to the product of the total emitter area over a wide range of operating conditions. 55. The system of claim 53, wherein the increase in the range of operating conditions is primarily related to a correlation or a negative correlation of the transconductance of the transistor. 56. The line of claim 46, wherein the series of instructions or instruction batch files are indicative of a plurality of instructions from a component of the list, the list comprising capacitors, inductors, resistors, diodes, varactors, And other design goals. 57. The system of claim 46, wherein the series of instructions or instruction batch files reference 43 200907727 other materials of the design goal or other design goals. 58. The system of claim 46, wherein the third data is indicative of means for generating at least one performance parameter to be included in the fifth data, the at least one performance tea number indicating performance of the circuit . The system of claim 58, wherein the fifth data is referenced by the second or third data of the design target or referenced by another design target. The system of n 60, wherein the equivalent energy parameter is selected from the group consisting of a current consumption, a noise index, a gain, a negative driving force, a bandwidth, a third-order intercept point with an input as a reference, The second-order wear breakpoint of the test, the third-order cut-off point with the output as the reference, the second-order cut-off point, the third-order wave distortion, the second wave misalignment, the /-parameter output offset, Dithering corners, over-excitation, bias and shunting, phase noise, timing jitter, power supply rejection, and substrate density, 44