200905646 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種主動式矩陣液晶顯示器之晝素驅 動電路；特別是有關於一種主動式矩陣液晶顯示器之倍壓 晝素驅動電路。 【先前技術】 目前大多的顯示器其晝素所需的驅動電壓多大於資 料驅動電路的操做電壓。如果在晝素内有一個倍壓晝素電 路可提供兩倍以上的輸入資料電壓，便可降低f ;所=，，而將此倍壓電路應用在高= 中的广虎提出—種應用於顯示器畫素 口&旦素驅動電路1〇〇，如第一 驅動電路100係用以驅動±圖所不，該倍壓晝素 的一個佥音1Λ/ _主動式矩陣液晶顯示H(AMLCD) 成。”板雷」 S電極之間的液晶材料112所構 做Ί：極111係耦合至一共同參考 的畫素顯示電壓Vpi丨係相等於 c〇m。該旦素1〇6 電極111之f板電極11G與該前板 電容器104及電晶體102、107及二電 電匯流排Γ及其源極係麵接於該儲存 电^ 104的局電壓端及該背板電極 1〇2的閘極係耦接至一第一㈣ 以及該電曰曰體 VA传姆帛㈣竣匯流排101。訊號電壓 vcs?;=;;電墨匯流排103送出，而第-控制訊號 係线該第一控制訊號匯流排ΗΠ送出。電晶體1〇7 5 200905646 ^ ?i〇7-^ VrS2孫铖山兮结—制矾號匯流排1〇5。第二控制訊號 的、原搞H弟一控制訊號匯流排1〇5送出。電晶體108 的源極健接至該儲麵容ϋ HM的低電壓端及該電晶體 07的源極’及其及極係接地，而該電晶體⑽的間極係 經由連線109輕接至該第—控制訊號匯流排ΐ(π。’、 r %200905646 IX. Description of the Invention: [Technical Field] The present invention relates to a pixel drive circuit for an active matrix liquid crystal display; and more particularly to a voltage doubled pixel drive circuit for an active matrix liquid crystal display. [Prior Art] At present, most of the displays require more driving voltages than the operating voltage of the data driving circuit. If there is a voltage doubled voltage circuit in the element that can provide more than twice the input data voltage, it can reduce f; =, and apply this voltage doubler circuit to the high = medium In the display pixel port & drive circuit 1 〇〇, such as the first drive circuit 100 is used to drive the ± picture, the octave 1 Λ / _ active matrix liquid crystal display H (AMLCD) ) to make. The "liquid crystal material 112" between the S electrodes is constructed such that the pixel 111 is coupled to a common reference pixel display voltage Vpi, which is equal to c〇m. The f-plate electrode 11G of the denier 1〇6 electrode 111 and the front plate capacitor 104 and the transistors 102, 107 and the two electric bus bars and their source lines are connected to the local voltage terminal of the storage device 104 and The gate of the back plate electrode 1〇2 is coupled to a first (four) and the electric body VA 帛 帛 (4) 竣 bus bar 101. The signal voltage vcs?;=;; the ink bus bar 103 is sent out, and the first control signal line sends the first control signal bus bar. Transistor 1〇7 5 200905646 ^ ?i〇7-^ VrS2 Sun Yishan 兮 — 矾 矾 矾 矾 矾 矾 矾 矾 矾 矾 。 。 。 。 。 。 。 。 。 。 The second control signal, the original H brother, a control signal bus, 1〇5 is sent out. The source of the transistor 108 is connected to the low voltage end of the reservoir surface HM and the source of the transistor 07 and its poles are grounded, and the interpole of the transistor (10) is connected via the connection 109. To the first - control signal bus ΐ (π.', r %
^ η該第一控制訊號匯流排101先傳送一高電位的第一控 制訊號VSC1 ’以開啟該等電晶體102及108，此時該第二 控制訊號VSC2為—低電位訊號，以關閉該電晶體107， 進而使知跨於該儲存電容器刚❸電壓充電至該訊號電壓 VA’而使得該儲存電容器ι〇4的高電壓端電壓vb相等於 ，訊號電壓VA。接著該第-控制訊號VSC1為-低電位訊 破’以關閉該等電晶體102及1〇8，而該第二控制訊號VSC2 ，為一高電位訊號，以開啟該電晶體1〇7，使得該訊號電 壓VA搞合於該儲存電容器1〇4的低電壓端。如此一來， 該儲存電容器104的高電壓端電壓VB即被提昇至2VA， 進而提供兩倍該訊號電壓的電壓予該晝素106的該背板電 極 110。 如上述’該電晶體107以該訊號電壓VA為資料輸入 源’需要一直處於開啟狀態並維持一個畫面期間（fraine time)，而增加晝素驅動電路的功率消耗。若在一個晝面期 間’該訊號電壓VA改變，該晝素106的晝素電壓也將跟 著改變。若在一個晝面期間將該電晶體107關閉，那麼支 持電荷泵(charge pump)的電壓(VA)將會消失，VB點會回到 未電荷泵之前的電壓，此兩個改變都會影響到顯示色彩的 表現’使該美國專利第5,903,248號僅能適用於單色面板， 6 200905646^ η The first control signal bus 101 first transmits a high-potential first control signal VSC1 ' to turn on the transistors 102 and 108, and the second control signal VSC2 is a low-potential signal to turn off the power. The crystal 107, in turn, is charged to the signal voltage VA' across the storage capacitor voltage so that the high voltage terminal voltage vb of the storage capacitor ι4 is equal to the signal voltage VA. Then, the first control signal VSC1 is - low potential signal breaking to turn off the transistors 102 and 1 〇 8 , and the second control signal VSC2 is a high potential signal to turn on the transistor 1 〇 7 The signal voltage VA is applied to the low voltage terminal of the storage capacitor 1〇4. As a result, the high voltage terminal voltage VB of the storage capacitor 104 is boosted to 2 VA, thereby providing twice the voltage of the signal voltage to the backplane electrode 110 of the halogen 106. As described above, the transistor 107 uses the signal voltage VA as a data input source to be kept on and maintains a frine time, thereby increasing the power consumption of the pixel drive circuit. If the signal voltage VA changes during a kneading period, the pixel voltage of the halogen 106 will also change. If the transistor 107 is turned off during a facet, the voltage (VA) supporting the charge pump will disappear and the VB point will return to the voltage before the uncharged pump. Both changes will affect the display. The performance of color' makes this U.S. Patent No. 5,903,248 only applicable to monochrome panels, 6 200905646
而不能符合曰此B 路100需多^顯示器的需求。再者’該倍髮晝素驅動電 持該電晶題^—條控制訊號線以開啟該電晶體,並保 與掃描驅動雷:—直處於開啟狀態’而需要兩倍的掃描線 據此，龟路，使得掃描驅動電路的製作成本增加。 以克服上地=寺提供—種改良的倍壓晝素驅動電i設計， 义“知技術之缺失。 【發明内容】 r 晝素供:種倍壓晝素驅動電路’係可提供-對應 的電屢料電壓’以降低資料驅動電路所需提； 另—方而即令電路製作成本及達到省電功能。 用—儲存電本發明提供一種倍壓畫素驅動電路，係利 並藉由該錯存—資料電壓直至整個畫面期間結束， 素的—晝素器儲存的前述資料電壓以括升該對應晝 結束，進愿至兩倍的資料電壓直至整個畫面期間 據上诚^夕電晶體開啟時間，以延長電路壽命。 —儲存電_本發明提供的倍壓晝素鶴f路係包括-第 二電晶體二第二儲存電容器、-第-電晶體、-第 容器具有一第一:電晶體及一第四電晶體。該第-儲存電 儲存電容^ 一第二端，該第二端係接地。該第二 畫素;二第有"？—端及一第二端，該第-端蝴- 該源極係二有一源極、一汲極及-間極， 第二電晶體ί具;二;:間極係耦接至-掃描叫 接至該資料電壓線' 汲極及一閘極，該源極係耦 第-端，及該f雜係至該第二儲存電容器的 ’、 掃插電壓線。該第三電晶體 7 200905646 、：汲極及-閘極，該源極係耦接該第二儲 ^^r,；〇 „ 該源極係轉接兮第:六係具有原極、一汲極及-閘極， 該第二儲存ΐ:;:ΓΓ二端，該汲極係姻 問_接至：=二端及該第三電晶體的源極，及該 電壓以開啟該第電？體線、^^^ 體，以使該第一儲存以—_電日日體及該第三電晶 線電壓，當掃描=ΐ 該第三電晶該第二電晶體ϊ 將儲存於該第一儲啟該第四電晶體’以 存電容器之第轉移至該第， 升至該，電第一健存電容器之第 體。= = 通道電晶體或—。通道電曰 波形在掃晦時間晶體時，調整掃描“ 電路製作成本。以供做該訊號轉移線，以減 本發明提供的另一脉厂 1存電容n、—s 素驅動電路係包括 二電晶释；》 ^ 电仔电容器、一筮—雨。 乐 一端及笛—第三電晶體。讀第一儲亡^電曰曰體、一第 有-第，S畫:;極，二 極係_至1料，、-汲極及—間極， 5亥沒極係輪接該第1存電ί 8 200905646 器之第-端，及該閘極係 有—源極、1極及ι:Γ電摩線。該第二電 枓电壓線，該汲極耦接 ，極，碡源極係耗 ^ 二儲存電容器之第—嫂弟1存電容轉接该貧 該第三電晶體係且右讀閑極係耦接I 端及該第 第-2:電=核、1極及二：虎轉移線。 -端’該二，第4:¾ ==電壓線。讀第二端，= 日三電晶體，電壓以 入零電壓，關閉該第―電：；’待儲存完畢後， 剩餘之掃描時間内，該訊號該第三電晶體， Ϊ第Si晶體’以將該資料電壓線入掃描電壓開啟 器’進而將該第-鍺壓儲存至該 至"亥負料电壓的兩倍電壓。 电令器的第一端抬升 本發明前述倍壓晝素叙 p儲存該資料電壓，—進而將該第一^用該第二儲存電 極括升至該資料電塵的:二子^器，：· 功率的消耗，而延長晝素電路的壽^啟’可降低晝素電路 【資施方式】 本發明提供的倍壓晝素驅動電路 電容器組成的電荷泵(eharge pump)電路，、電晶體及 的控制訊號來完成電荷泵的動作。、σ上適當時序 ，藉由以下具體實施例配合所附圖 200905646 第一A圖係本發明倍 例的電路示意圖，其包括一駆動電路的第一具體實施 二N通道電晶體2〇2匕—^二―N通道電晶體201、_第 N通道電晶體2〇4、一 f二N通道電晶體203、一第四 電容器206。該第―N容ϋ 205及一第二儲存 f 極及一閘極，該源極係耦接:次2〇1具有一源極、一汲 係輕接該第1存電容器2。=電壓線208，該及極 容器205的第二端係接地。嗲端，而該第一儲存電 極係耗接至一掃描電壓線2的=通道電晶體2 01的閘 具有一源極、—沒極及-閘極，^、、了 Ν通逼電晶體202 壓線2 0 8，該汲極耦接至該第二儲i係耦接至該資料電 該第二儲存電容器2〇6的媳=電容器206的第一端， 畫素電極’而另一晝素電極係至:對，晝素Clc 如接地。該第二N通道電曰許9fn、接至一低電壓源，例 電壓線209。該第三N通； =極係耦接至該掃描 二 趣及-閘極，該源極係體，具有—源極、-沒 端，該汲極係接地，而該閘極堵存電容器206的第_ 讀第四N通道電晶體：至該掃描電壓線21 接該第-N通道電晶體^的、^ =及1極’ :器=一端，極輕接該第第:儲存 知及«二N通道電晶體2():子電各器206 至—訊號轉移線210。 極’該閘極輕接 虽進行整個畫面掃描時（其中 ^ :掃描時間，而tF為整個晝面：、c掃插電壓線 先傳送-掃描電壓以開啟該第丄道=插電壓緩209 2通道電晶體搬及該第三N通體加、該第 貝料電壓、線208傳送的一資料電壓儲存至H3,以使該 〜儲存電容 200905646 器205及該第二儲六a 容器205的第二端接^: 06 °此時由於該第一儲存電 造成該第二儲存電= 通道電晶體2〇3被開啟 存電容器2〇5的第地，因此該第-儲 皆具有相等於該資料= = 施的第-端 行掃描時’該第—N通道電晶體2〇;-條== 2〇2及第三N通道電晶體2〇3呈關閉狀:? 電容器205的第—端及該第二儲存電容^ 存It can't meet the needs of this B road 100 need more than the display. Furthermore, 'the hairpin drive power holds the electro-crystal title ^-bar control signal line to turn on the transistor, and the scan-driven lightning: - is in the open state' and requires twice the scan line accordingly. The turtle road increases the manufacturing cost of the scan driving circuit. In order to overcome the improvement of the double-pressure element-driven electric i design provided by Shangdi = Temple, the meaning of "the lack of knowledge technology." [Abstract] r 昼素供: 倍倍压素素驱动电路' can provide - corresponding The voltage of the electric material is used to reduce the data driving circuit; the other is to make the circuit manufacturing cost and achieve the power saving function. The present invention provides a voltage doubling pixel driving circuit, which is beneficial and uses the error. Save-data voltage until the end of the whole picture period, the voltage of the above-mentioned data stored in the prime-salt device ends with the corresponding 昼, and the data voltage is doubled until the entire screen period is based on the opening time of the transistor. To extend the life of the circuit. - Storage of electricity - The present invention provides a voltage doubler, the second circuit capacitor, the second transistor, the -the first transistor, the first container has a first: transistor And a fourth transistor, the first storage electrical storage capacitor ^ a second end, the second end is grounded. The second pixel; the second has a "?-end and a second end, the first - End butterfly - the source system has a source, a bungee and - The interpole, the second transistor; the second; the interpole is coupled to - the scan is connected to the data voltage line 'the drain and the gate, the source is coupled to the first end, and the f is To the second storage capacitor', the sweep voltage line. The third transistor 7 200905646, the drain and the gate, the source is coupled to the second reservoir, 〇„ the source System transfer: The sixth system has the original pole, a drain pole and a gate pole, the second storage pole::: the second end of the pole The source of the crystal, and the voltage to turn on the first? a body line, a ^^^ body, such that the first storage is -_ electricity day body and the third transistor line voltage, when scanning = ΐ the third transistor, the second transistor ϊ will be stored in the first And storing the fourth transistor 'to the first of the capacitors to the first, and rising to the first body of the first first storage capacitor. = = channel transistor or —. When the channel power waveform is in the broom time crystal, adjust the scan "circuit fabrication cost. For the signal transfer line, to reduce the other circuit provided by the invention, the storage capacitor n, the -s drive circuit includes two Crystallized release;" ^ Electric capacitor, a 筮-rain. Le end and flute - the third transistor. Read the first deposit and death ^ electric corpus, one has - the first, S painting:; pole, two poles _ to 1 material, , - bungee and - interpole, 5 Hai Wuji system to connect the first storage ί 8 200905646 The first end of the device, and the gate system has - source, 1 pole and ι:第二Electric motor wire. The second electric 枓 voltage line, the 汲 pole is coupled, the pole, the 碡 source is consumed by the second storage capacitor - the first 1 1 storage capacitor is transferred to the third electro-crystalline system and right The read idle pole is coupled to the I terminal and the second -2: electrical = core, 1 pole and 2: tiger transfer line. - terminal 'the second, 4:3⁄4 == voltage line. Read the second end, = day Three transistors, the voltage is zero voltage, the first power is turned off:; 'After the storage is completed, the remaining third time, the signal is the third transistor, and the first Si crystal' is used to scan the data voltage line. The pressure opener 'further stores the first voltage to the voltage twice the voltage of the negative voltage. The first end of the electric actuator is raised, and the voltage voltage of the present invention is stored, and further The first storage electrode is lifted to the data storage dust: two sub-devices, :· power consumption, and the life of the halogen circuit is extended, and the halogen circuit can be lowered. The present invention provides a charge pump (eharge pump) circuit composed of a voltage doubled voltage driving circuit capacitor, a transistor and a control signal to complete the action of the charge pump. The appropriate timing on σ is matched by the following specific embodiments. Figure 200905646 First A is a circuit diagram of a multiple of the present invention, including a first implementation of a sway circuit, an N-channel transistor, a 2-channel transistor, and an N-channel transistor. 2〇4, a f-N-channel transistor 203, a fourth capacitor 206. The first-N capacitor 205 and a second storage electrode and a gate, the source is coupled: the second 2〇1 has One source, one turn is lightly connected to the first storage capacitor 2. = voltage line 208, and The second end of the container 205 is grounded. The first storage electrode is connected to a scan voltage line 2. The gate of the channel transistor 201 has a source, a gate and a gate. The first phase of the 媳=capacitor 206 coupled to the second storage capacitor 2〇6 is coupled to the second storage unit. , the pixel electrode 'and the other element of the electrode is: to, the halogen CCl is grounded. The second N channel is connected to a low voltage source, such as the voltage line 209. The third N pass; The pole is coupled to the scan and the gate. The source has a source, a terminal, and the drain is grounded, and the gate is blocked by the capacitor. N-channel transistor: to the scan voltage line 21 connected to the first-N channel transistor ^, ^ = and 1 pole ': device = one end, very lightly connected to the first: storage knows «two N channel transistor 2 (): the sub-electrical unit 206 to the signal transfer line 210. When the gate is lightly connected, the entire screen is scanned (where ^: scan time, and tF is the entire surface: c sweeps the voltage line first to transmit - scan voltage to turn on the first ramp = plug voltage 209 2 The channel transistor and the third N-body plus, the first billet voltage, and a data voltage transmitted by the line 208 are stored to H3, so that the storage capacitor 200905646 205 and the second storage container 205 are second. Termination ^: 06 ° At this time, the second stored electricity is caused by the first stored electricity = the channel transistor 2〇3 is turned on the ground of the storage capacitor 2〇5, so the first-storage has the same data = = when the first-end line scan is applied, 'the first-N channel transistor 2〇; - strip == 2〇2 and the third N-channel transistor 2〇3 are closed: ? the first end of the capacitor 205 and the Second storage capacitor ^
該資料電壓線2〇8去耗人 ^ 6的第知與 古雷办㈣一耦口时3玄旒轉移線210傳送一 1位控制訊號予該第四N通道電晶體 四n通道電晶體204，進而 以開啟a第 ，電壓轉移至該第二儲存電容器2。子6電; :=r器2。5第一端的電位藉由該第四電晶體二 ^開啟搞,至該第二儲存電容器2〇6的第二端，進而將該 =-儲存電容器2G6第-端抬升至該資料電壓的兩倍電 而使麵合的§亥晝素電極有兩倍的資料電壓作用於其 上二該第四電晶體2〇4被開啟後係一直保持開啟狀態直2 下—次掃描，以使該第二儲存電容器2〇6的第二端一直保 持f該資料電壓的電位，進而使得該第二儲存電容器2〇6 的第一端保持在兩倍資料電壓的電位直至一個晝面時間 的下一次掃描。 — 在第一具體實施例中，該第一 N通道電晶體201及第 二N通道電晶體202係分別製作在不同的綠路上，該第一 諸存電谷器205會有較小的電容負載，因此可縮小該第一 N通道電晶體201的尺寸大小，其寄生電容漏電流亦會較 小’進而降低該倍壓晝素驅動電路的功率消耗。 卓一 B圖係本發明倍壓晝素驅動電路的第二具體實 11 200905646 例的電路示意圖’其與第一具體實施例不同處係在於該第 四N通道電晶體204改以一 p通道電晶體207取代，而該 P通道電晶體207的閘極係耦接至該掃描電壓線209，其 源極耦接該第一 N通道電晶體2〇1的汲極及該第一儲存電 容器205的第一端’而其汲極耦接該第二儲存電容器2〇6 的第二端及該第三N通道電晶體203的源極。在第二具體 實施例中’調整掃描電壓波形在掃瞄時間結束後持續輸入 負電壓直到下一次掃描，如此以該P通道電晶體2〇7控制 該第一儲存電容器205儲存的資料電壓的轉移，該掃描電 壓線209亦可供做該訊號轉移線使用，而使得該p通道電 ，體207被開啟後呈持續開啟狀態，以使該第二儲存電容 ，206第二端電位保持在該資料電壓直至整個晝面結束。 第二具體實施例的倍壓晝素驅動電路無需額外的訊號轉移 線，可減少掃描驅動電路的製作成本。 偏ί二1係本發明倍壓畫素驅動電路的第三具體實施 例^路示意圖，其包括—第—Ν通道電晶體3(η、 = 電晶體3〇2、—第三N通道電晶體撕、-第- 電^體tot Π及一第二儲存電容器305。該第一 N通道 日日體301具有一源極、一汲極及一 至—資料電壓線3 G 7，該沒極係輪$第° ^係輕接 的第—端，而該第-儲存弟一儲存電容器304 應晝素Qc的一^ 3〇4的第一端亦麵接一對 極係：該第—N通道電晶體3〇1的閘 具電壓線306。該第二n通道電晶體： 壓線307,該汲極係_;係耦接至該資料電 及該第-社=職接衫―儲存電容器3G4的第-端 /弟一儲存電容器3〇5的第— J珩一知 的第二端係接地。該第二N通道電曰^二儲存電容器 、电日日體302的閘極係耦接 12 200905646 至一戒號轉移線308。該第二μ、孟、、 極、-汲極及一閘極，該源極:以晶，303具有一源 的第二端、該第二儲存電容器305的^一儲存電容器304 道電晶體302的汲極。該第的弟一端及該第二Ν通 耦接至該掃描電壓線3〇2。—、道電晶體303的閘極係 當進行整個晝面掃描時，該掃带 =電壓予該第-Ν通道電晶體= U = 體303的閘極，以開啟該第― "第一 N通道電曰曰 N通道電晶體303，進而將玆資晶體301及該第三 ，至該第-儲存電容器3二 二體303亦被開啟，使得第-儲存^二弟二二通， δ至接地電位，而使得該第β 的第一端耦 有該資料電壓的電位:接;在容器304的第-端具 轉移線308傳送一高電位控制訊號予：:寺二:,該訊號 3 〇 2的閘極，以開啟該第二Ν通道：-通遏電晶體 _貝料電壓線的該資料電屡儲存H2丄而使得該 在此之際，由於該掃描電壓線鄕存電容器305。 :第-N通道電晶體3〇1及該第 =第一端保持在該資料電壓的電: ^而有兩倍該資料電壓的電壓作用二== 在第三具體實施例中，係藉由該第_ 身料電壓儲存起來，以使得該第：儲:電=: 的弟二端保持在該諸電麼的電位，而叙 304 電晶體3〇2持續呈開啟狀態至整個晝面結 13 200905646 具體實施例的倍壓晝素驅動電路 倍壓晝素驅動電路僅具有三個 j耗較低。再 其電路結構亦較為簡單。 日日 '及二個儲存電容如該 第三B圖係本發明倍壓晝 ^ ’ 例的電路示意圖，其與第三具體實=第四具 二Ν通道電晶體3〇2改為—ρ ^不同處係在 ^ 而 器 該掃描電壓線306亦可供做〜訊號曰體309。如此〜4 實施例的該訊號轉移線308省略广各^線，而將第三具髁 掃描電壓改為負電位時即可開啟該;=掃描電壓線3〇^的 將該資料電壓線的資料電壓 ^道電晶體3〇9 , 305。 誘第二儲存電容裔 第四圖係本發明倍壓畫素驅動 的電路示意圖，其包括-第一 Ν通1雷曰第五具體實施例 通道電晶體•、一第以 道電晶體4〇6、一第-儲存電容器407、—^ 一儲^^通 具有一源極、-汲極及-閘極，該源極係耦接401 該汲，_該第1存電w/H電 而該第儲存電容器407的第二诚孫技仏 至一掃描電壓線41〇。該第二 曾、，以閘極係耦接 極、，及一問極，該源;係二該:體::源 4〇1的汲極及該第—儲存電容器術的第一端^電晶體 耦接该第二儲存電容器4 二汲極 一對應畫素Ccl的—畫素電r該端日亦轉接 的閘極係耦接至該掃描電壓線410。該第一 “402 -具有-源極、—汲極及一閘極，該 14 200905646 儲存電容器408的第二端， 該閘極_接至該糾電係接執至-接地電位， 404具有-源極、1極及該第四N通道電晶體 N通道電晶體401的及極、診二一：該源極係耦接讀第一 端及該第二N通道電晶體if存電容器407的第一 體404的汲極係耦接該第二.=、j。該第四N通道電晶 第三N通道電晶體403的源極。^ = 4⑽的第二端及該 的閘極耦接該第三儲存電容器二N通道電晶體4〇4 存電容器409的第二端係轉1 桩ί —端，而該第三儲 道電晶體405具有—源極稱：C立。該第五N通 至下-條掃描電壓線412，該汲極㈣該源极輕接 體404的間極及該第三儲存電容器彻的第=通道電晶 N通道電晶體405的閑極轉接至的—弟讀第五 412。該第六N通道電晶體406呈有1健知描電壓線 閘極，該源極_該下-條掃描電壓:線41;—，-接該第四N通道電晶體4 〇 4的閘極、爷^ ^亥及極耦 405的及極及該第三儲存電容器的第二Ϊ電晶體 通道電晶體406的閘極係輕接至該掃描電壓線^第六N 當進行整個晝面掃描時，該掃描先。 電壓予該第一 N通道電晶體4〇1、該第二—掃描 4〇2、該第三N通道電晶體4〇3及該第六^道^曰^晶體 的問極，以開啟該等電晶體，以使得該資料電：曰4體；06 -資料電壓儲存至該第-儲存電容器彻及線^的 容器408。在此之際’由於該第“通道電==， 第六N通道電晶體406亦被開啟，使得該第二 該 408的第二端搞合至接地電位，而該第二儲存=各器 的第-端電位相等於該資料電壓，該第三儲存電: 15 200905646 藉由該六N通道雷曰縣 -儲存電容器術的V二端重置。再者，該第 器407的第—端電位係相===此該第1存電容 描電壓線412進行掃γ护、^貝料電壓。當該下一 開啟，並且由於通道電晶體4 位:該第-ν通道電插電麵零Ϊ 該第二N通道電晶體4〇3及該二7通道電晶體402、 f狀態，而使得該資料電愿^ =電晶體4〇6呈關 存電容器術及該第二儲存料電壓與該第一儲 並使得該下—條掃描電 的第1去轉合， 儲存電容器4〇9，且由的掃描電壓儲存至該第二 係接地，該第三错存由電::=電容器•的第f: 下—條掃描電壓線的掃描 、弟—端的電位相等於該 體4 〇 4開啟。藉由開啟該^四N爵而將該第四N通道電晶 儲存電容器407的第—端 <道電晶體404，該第— 4〇8的第二端，因此將該第二儲至該第二儲存電容器 位抬升至該資料電壓的兩件=存電容器408的第—端電 409將掃描電壓儲存起來，因。由於該第三儲存電容器 4〇4被開啟之後，即可持 旦該第四N通道電晶體 束。在下-個晝面被掃描時、=狀態直至整個晝面結 娜的開啟，以重置該第三=由該第六N通道電晶體 第五具體實施例係#由 ^器409。 ”通道電晶體405,以將二:條掃描電壓線開啟該第 谷器409，進而使該第四N =垂壓儲存在該第三儲存電 態。第五具體實施例的倍麗蚩j晶體綱呈持續開啟狀 訊號轉移線。 旦驅動電路並不需要額外的 第五A圖係本發明倍 里素驅動電路的第六具體實施 16 200905646 例的電路示意圖，其包括—笛— 二N通道電晶體502、一第—通道電晶體501、一第 N通道電晶體5G4、—第^二道電晶體地、一第四 ^ ^ 弟儲存電容器505、一笫 谷态506及一第三儲存電容器5 N、s—儲存電 ;有-源極、-沒極及-間極，該源道電晶體 而該第-儲存電容器5〇5的，第，The data voltage line 2〇8 is used to consume the 6th and the Gulei office (4) a coupling port. The 3 Xuanyuan transfer line 210 transmits a 1-bit control signal to the fourth N-channel transistor four n-channel transistor 204. And, in order to turn on a, the voltage is transferred to the second storage capacitor 2. The voltage of the first end of the second capacitor is turned on by the fourth transistor, to the second end of the second storage capacitor 2〇6, and then the =-storage capacitor 2G6 The first end is raised to twice the voltage of the data voltage so that the surface of the § 昼 昼 电极 electrode has twice the data voltage applied to it. The fourth transistor 2 〇 4 is turned on and remains open. 2 scanning-lowering so that the second end of the second storage capacitor 2〇6 maintains the potential of the data voltage, so that the first end of the second storage capacitor 2〇6 is maintained at twice the data voltage The potential is up to the next scan of a kneading time. In the first embodiment, the first N-channel transistor 201 and the second N-channel transistor 202 are respectively fabricated on different green paths, and the first storage grids 205 have a smaller capacitive load. Therefore, the size of the first N-channel transistor 201 can be reduced, and the parasitic capacitance leakage current is also small, thereby reducing the power consumption of the voltage-pressing driving circuit. The second circuit diagram of the second voltage real circuit of the present invention is different from the first embodiment in that the fourth N-channel transistor 204 is changed to a p-channel power. The gate of the P-channel transistor 207 is coupled to the scan voltage line 209, and the source thereof is coupled to the drain of the first N-channel transistor 2〇1 and the first storage capacitor 205. The first end is coupled to the second end of the second storage capacitor 2〇6 and the source of the third N-channel transistor 203. In the second embodiment, the 'adjusted scan voltage waveform continues to input the negative voltage after the end of the scan time until the next scan, so that the transfer of the data voltage stored by the first storage capacitor 205 is controlled by the P-channel transistor 2〇7. The scan voltage line 209 is also used for the signal transfer line, so that the p-channel is electrically turned on, and the body 207 is turned on continuously, so that the potential of the second storage capacitor 206 is maintained at the data. The voltage is until the end of the entire surface. The voltage doubled pixel driving circuit of the second embodiment eliminates the need for an additional signal transfer line, thereby reducing the manufacturing cost of the scan driving circuit. A third embodiment of the galvanpy driving circuit of the present invention includes a first-channel channel transistor 3 (n, = transistor 3 〇 2, - a third N-channel transistor) And a second storage capacitor 305. The first N-channel day body 301 has a source, a drain, and a data line 3 G 7, the poleless wheel $°^ is the first end of the light connection, and the first storage terminal of the storage capacitor 304 is also connected to a pair of poles: the first N-channel The gate voltage line 306 of the crystal 3〇1. The second n-channel transistor: the pressure line 307, the drain line _; is coupled to the data power and the first body-service shirt-storage capacitor 3G4 The second end of the first-end/different storage capacitor 3〇5 is grounded. The second N-channel electric storage capacitor and the gate of the electric solar body 302 are coupled to each other 12 200905646 To a sign transfer line 308. The second μ, the um, the pole, the drain, and the gate, the source: the crystal, the 303 has a second end of the source, and the second storage capacitor 305 One storage 304 is a drain of the transistor 302. The first transistor and the second transistor are coupled to the scan voltage line 3〇2. The gate of the transistor 303 is used for the entire scan. The sweeping band=voltage is applied to the first-turn channel transistor=U=the gate of the body 303 to turn on the first "first N-channel electric N-channel transistor 303, and then the crystal 301 and the Third, the second storage body 3 of the first storage capacitor 3 is also turned on, so that the first storage diode is connected to the ground potential, so that the first end of the beta is coupled to the potential of the data voltage. Connected to the first end of the container 304 with a transfer line 308 to transmit a high-potential control signal to:: Temple 2: The gate of the signal 3 〇 2 to open the second channel: - pass transistor _ The data of the billet voltage line repeatedly stores H2 丄 so that at this time, since the scanning voltage line stores the capacitor 305. : the -N channel transistor 3〇1 and the first = first end remain in the The voltage of the data voltage: ^ and twice the voltage of the data voltage. 2 == In the third embodiment, the voltage is stored by the _ body material. So, so that the second: the second end of the first: storage = electricity =: at the potential of the electrical, while the 304 transistor 3 〇 2 continues to open to the entire surface of the junction 13 200905646 The halogen drive circuit of the halogen drive circuit has only three J consumptions, and the circuit structure is relatively simple. The Japanese and the two storage capacitors are the same as the third B diagram. The schematic diagram of the circuit is different from the third specific real=fourth second channel transistor 3〇2, which is changed to —ρ^, and the scanning voltage line 306 is also available for the signal body 309. The signal transfer line 308 of the embodiment of FIG. 4 omits the wide line, and the third voltage is changed to a negative potential; the data of the data line of the scan voltage line 3〇^ is turned on; Voltage ^3 transistor 3〇9, 305. The second storage capacitor is shown in the fourth diagram of the circuit of the present invention. The first embodiment includes a first channel, a first channel, a first embodiment, a channel transistor, and a first channel transistor. a first storage capacitor 407, a storage capacitor having a source, a drain, and a gate, the source being coupled to the capacitor 401, the first power storage w/H power The second capacitor of the storage capacitor 407 is turned to a scan voltage line 41A. The second Zen, the gate is coupled to the pole, and the pole is the source; the second is: the body: the drain of the source 4〇1 and the first end of the first storage capacitor The gate is coupled to the scan voltage line 410. The gate of the second storage capacitor 4 is coupled to the scan voltage line 410. The first "402 - has - source, - drain and a gate, the 14 200905646 stores the second end of the capacitor 408, the gate is connected to the electric current system to - ground potential, 404 has - a source, a pole, and a fourth pole of the fourth N-channel transistor N-channel transistor 401. The source is coupled to the first end and the second N-channel transistor if capacitor 407 The drain of the integrated 404 is coupled to the second .=, j. The fourth N-channel is electrically connected to the source of the third N-channel transistor 403. The second end of the ^4 (10) and the gate are coupled to the gate The third storage capacitor, the N-channel transistor 4〇4, the second end of the storage capacitor 409 is rotated to the end, and the third storage transistor 405 has a source-source: C--. a bottom-strip scan voltage line 412, the drain of the source (4) of the source light-contact body 404 and the third storage capacitor of the third-channel electro-crystalline N-channel transistor 405 Reading the fifth 412. The sixth N-channel transistor 406 has a gate electrode with a well-known voltage, the source-the lower-strip scan voltage: a line 41; -, - the fourth N-channel transistor 4闸4 gate The gate of the second transistor transistor 406 and the gate of the second transistor transistor 406 of the third storage capacitor are lightly connected to the scan voltage line ^6N when performing the entire face scan The scan is first applied to the first N-channel transistor 4〇1, the second-scan 4〇2, the third N-channel transistor 4〇3, and the sixth pole of the sixth transistor. To turn on the transistors so that the data is electrically: 曰4 body; 06 - the data voltage is stored to the container 408 of the first storage capacitor and the line ^. At this time 'because the first channel power ==, The sixth N-channel transistor 406 is also turned on, such that the second end of the second portion 408 is brought to the ground potential, and the second storage = the first-end potential of each device is equal to the data voltage, the third storage Electricity: 15 200905646 The V-terminal reset of the six-N channel Thunder County-Storage Capacitor. Further, the first end potential phase of the first unit 407 === the first storage capacitor voltage line 412 performs the sweep gamma protection and the bedding voltage. When the next turn-on, and because the channel transistor 4 bits: the first-v channel electrical plug-in surface is zero, the second N-channel transistor 4〇3 and the two 7-channel transistors 402, f state, The data is expected to be ^=the transistor 4〇6 is the storage capacitor and the second stored material voltage is coupled with the first storage and the first de-conversion of the lower-strip scan, the storage capacitor 4〇9, and The scan voltage is stored to the second system ground. The third fault is caused by the scan of the f:low-strip scan voltage line of the electric::=capacitor, and the potential of the younger end is equal to the turn of the body 4 〇4. By opening the fourth N-channel, the fourth N-channel transistor stores the first end of the capacitor 407, the second transistor, and the second terminal of the fourth terminal, thereby storing the second The second storage capacitor is raised to two of the data voltages = the first terminal 409 of the capacitor 408 stores the scan voltage. Since the third storage capacitor 4?4 is turned on, the fourth N-channel transistor can be held. When the next - face is scanned, the = state is turned on until the entire face is turned on to reset the third = by the sixth N-channel transistor. a channel transistor 405 for turning on the second: scanning voltage line to turn on the valley device 409, and then storing the fourth N = vertical pressure in the third storage state. The fifth embodiment of the second crystal The schematic is a continuous open signal transfer line. The drive circuit does not require an additional fifth A diagram. The sixth embodiment of the present invention is a circuit diagram of the example of the 200905646, which includes a flute-two N-channel power. The crystal 502, a first channel transistor 501, an Nth channel transistor 5G4, a second transistor crystal ground, a fourth memory capacitor 505, a valley state 506 and a third storage capacitor 5 N, s - storage electricity; with - source, - immersion and - interpole, the source channel transistor and the first - storage capacitor 5 〇 5, the first,
電晶體5G1的閘極係搞接至—掃描電壓線=第yN通道 通道電晶體502具有一源極、一沒 三 該第二N 接該第一儲存電容器505的第一 /極，該源極耦 =電，506的第-端，而該第—端亦 該第二儲 的-晝素電極。該第通道電晶體％ 『應晝素Clc 該掃描電壓線5 0 8。該第三N通道電晶體間槌係耦接至 —汲極及一閘極，該源極係輕接具有一源極、 第-端，而該第三儲存電容器5〇7=2電容器5〇7的 三N通道電晶體503的汲極係純該第:，地。該第 的第二端，而其閘極係耦接至該掃描電盤錄，電容器5〇6 N通道電晶體504具有一源極、_汲極及°該第四 係耦接該第一 N通道電晶體5〇1的汲極、=極，該源極 器505的第一端及該第二N通道電晶體〜儲存電容 四N通道電晶體504的汲極係耦接該第二$源極。該第 的第二端及該第三儲存電容器5〇7的第一端，子電容器506 輕接至下一條掃描電壓線51 〇。 而其閘極係 當進行整個晝面掃描時，該掃描電壓 掃描電壓予該第一 N通道電晶體5〇1、該第_08先傳送一 體502及該第三N通道電晶體5〇3的閘極，^ N通道電晶 晶體’以使該資料電疆線5〇9的-資料雷=開啟該等電 卞电崚儲存至該第一 17 200905646 ，存電容器5〇5及該第二儲存 存電容器505的第二蠕係接地兒谷，506。由於該第一儲 第—端電位即相等於該資料該第一儲存電容器505的 電晶體503被開啟，使得誃μ墾。再者由於該第三N通道 麵合至接地電>(立，因此“弟：儲存電容器506的第二端 相等於該資料電壓。接^:儲存電容=的第—端電位即 掃描，該第四Ν通道電曰辨ς二下了條掃描電壓線510的 於該掃描電壓線508的二:開啟。在此之際，由 電晶體50卜該第二Ν通道電晶體5〇2及該第亥第:通道 的第-端與該資料ΐί:=及儲The gate of the transistor 5G1 is connected to - the scanning voltage line = the yN channel channel transistor 502 has a source, and the second N is connected to the first / pole of the first storage capacitor 505, the source Coupling = electric, the first end of the 506, and the first end is also the second stored - halogen electrode. The first channel transistor % 『 昼 Cl Clc the scanning voltage line 5 0 8 . The third N-channel transistor is coupled to the drain and the gate, the source is lightly connected to have a source and a first end, and the third storage capacitor is 5〇7=2 capacitor 5〇 The drain of the three N-channel transistor 503 of 7 is purely the first: ground. The second end of the first circuit is coupled to the scan circuit, and the capacitor 5〇6 N-channel transistor 504 has a source, a drain, and a fourth system coupled to the first N. The first terminal of the source transistor 505 and the first N-channel transistor to the storage capacitor four N-channel transistor 504 are coupled to the second source. pole. The second end of the first and the first end of the third storage capacitor 5?7, the sub-capacitor 506 is lightly connected to the next scan voltage line 51?. The scan voltage is applied to the first N-channel transistor 5〇1, the _08 first transfer unit 502, and the third N-channel transistor 5〇3 when the gate scan is performed. Gate, ^ N-channel electro-crystal crystal 'to make the data electric line 5 〇 9 - data mine = turn on the electric 卞 electricity stored to the first 17 200905646, storage capacitor 5 〇 5 and the second storage The second creep of capacitor 505 is grounded, 506. Since the first storage terminal-end potential is equal to the data, the transistor 503 of the first storage capacitor 505 is turned on, so that 誃μ垦. Furthermore, since the third N-channel is connected to the grounding electric current, the second end of the storage capacitor 506 is equal to the data voltage. The first end potential of the storage capacitor= is scanned. The fourth channel is electrically connected to the second scanning voltage line 510 of the scanning voltage line 508: at this time, the transistor 50 is connected to the second channel transistor 5〇2 and the Dihai: The first end of the channel and the data ΐί:= and storage
】谷請的第二端係接地’其第一端電位即 J 資料電壓的兩倍電壓。 抬升至该 在第六具體實施例中’係藉由該第三儲存電容器5的 儲存該資料電壓，以使該第二儲存電容器5〇6的第二端 持在該資料電壓的電位直至整個晝面結束，而該第四 道電晶體504無需呈持續開啟狀態。在進行下—個晝面> 描時，再藉由開啟第三Ν通道電晶體503，以重置^第_ 儲存電容器507。第六具體實施例的倍壓晝素驅動^路= 需額外的訊號轉移線開啟該第四Ν通道電晶體5〇4，並且 該第四Ν通道電晶體504亦無需呈持續開啟狀態。 第五Β圖係本發明倍壓晝素驅動電路的第七具體實施 例的電路示意圖，其與第六具體實施例不同處係在於該^ 18 200905646 一 N通道電晶體％ 同的線路上。該第 通道电晶體5〇2係製作在不 至該資料電壓線彻，—極係直接搞接 接該資料電壓線5 ^ 電晶體501的源極耦 的第-端，而其二；;，接該第1存電容請 道電晶體504的源極係線5⑽。該第四Μ 極及該第1存通道電晶體5()1的汲】 The second end of the valley is grounded. 'The first terminal potential is twice the voltage of the J data voltage. Uplifting to the sixth embodiment, the data voltage is stored by the third storage capacitor 5 such that the second end of the second storage capacitor 5〇6 is held at the potential of the data voltage until the entire 昼The face ends and the fourth transistor 504 need not be in a continuously on state. The _th storage capacitor 507 is reset by turning on the third Ν channel transistor 503 while performing the next & & > The voltage doubling element driving circuit of the sixth embodiment = an additional signal transfer line is required to turn on the fourth channel transistor 5〇4, and the fourth channel transistor 504 does not need to be continuously turned on. The fifth diagram is a circuit diagram of a seventh embodiment of the voltage doubling element driving circuit of the present invention, which differs from the sixth embodiment in that the circuit is on the same line as the N-channel transistor. The first channel transistor 5〇2 is fabricated not to the data voltage line, and the pole system directly connects the first end of the source voltage coupling of the data voltage line 5^the transistor 501, and the second; Connect the first storage capacitor to the source line 5 (10) of the transistor 504. The fourth anode and the first channel of the transistor 5 () 1
j存電谷請的第二端及該第三儲存電=== 一端以及該第三N通道電晶體5G3的源極，而^ ^ 接條掃描電壓線5H)。由於該第—Nit道電m 及第二N通道電晶體502製作在不同的線路上，該 存電容505會有較小的電容負载，因此可縮小該^一 1^通 道電晶體501的尺寸大小，其寄生電容漏電流亦會較小， 進而降低該倍壓晝素驅動電路的功率消耗。 —以上所述僅為本發明之具體實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 19 200905646 【圖式簡單說明】 第一圖係一傳統倍壓晝素驅動電路的電路示意圖； 第二A圖係本發明倍壓晝素驅動電路的第一具體實 施例的電路示意圖； 第二B圖係本發明倍壓晝素驅動電路的第二具體實 施例的電路示意圖； 第三A圖係本發明倍壓晝素驅動電路的第三具體實 施例的電路示意圖； 第三B圖係本發明倍壓晝素驅動電路的第四具體實施 例的電路示意圖； 第四圖係本發明倍壓晝素驅動電路的第五具體實施例 的電路示意圖； 第五A圖係本發明倍壓晝素驅動電路的第六具體實施 例的電路示意圖；及 第五B圖係本發明倍壓晝素驅動電路的第七具體實施 例的電路示意圖。 【主要元件符號對照說明】 201、 301、401、501-…第一 N通道電晶體 202、 302、402、502----第二 N 通道電晶體 203、 303、403、503-…第三N通道電晶體 2〇4、404、504----第四N通道電晶體 205、 304、407、505----第一儲存電容器 206、 305、408、506-…第二儲存電容器 207、 309…-P通道電晶體 208、 307、411、509-…資料電壓線 209、 306、410、508—掃描電壓線 20 200905646 210、308…-訊號轉移線 405- …第五N通道電晶體 406- …第六N通道電晶體 409、507-…第三儲存電容器 412、510-…下一條掃描電壓線 k... 21The second end of the storage valley and the third storage power === one end and the source of the third N-channel transistor 5G3, and the ^z strip scan voltage line 5H). Since the first N-channel transistor m and the second N-channel transistor 502 are formed on different lines, the capacitor 505 has a small capacitive load, thereby reducing the size of the transistor 501. The parasitic capacitance leakage current is also small, which in turn reduces the power consumption of the voltage-substance driving circuit. The above description is only for the specific embodiments of the present invention, and is not intended to limit the scope of the claims of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following Within the scope of the patent application. 19 200905646 [Simple description of the diagram] The first diagram is a circuit diagram of a conventional voltage-doubled pixel drive circuit; the second diagram is a circuit diagram of the first embodiment of the voltage-doubled pixel drive circuit of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a circuit diagram of a second embodiment of a voltage doubling element driving circuit of the present invention; FIG. 3A is a circuit diagram of a third embodiment of the voltage doubling element driving circuit of the present invention; A circuit diagram of a fourth embodiment of a voltage-doubled voltamate driving circuit; a fourth circuit diagram showing a circuit of a fifth embodiment of the voltage doubling element driving circuit of the present invention; A circuit diagram of a sixth embodiment of the circuit; and a fifth diagram of the circuit of the seventh embodiment of the voltage doubling driving circuit of the present invention. [Main component symbol comparison description] 201, 301, 401, 501-... first N-channel transistors 202, 302, 402, 502---second N-channel transistors 203, 303, 403, 503-... third N-channel transistors 2〇4, 404, 504---fourth N-channel transistors 205, 304, 407, 505---first storage capacitors 206, 305, 408, 506-...second storage capacitors 207 309...-P channel transistors 208, 307, 411, 509-... data voltage lines 209, 306, 410, 508 - scanning voltage lines 20 200905646 210, 308... - signal transfer lines 405 - ... fifth N-channel transistors 406- ... sixth N-channel transistor 409, 507-... third storage capacitor 412, 510-... next scanning voltage line k... 21