TW200905210A - Built-in jitter measurement circuit - Google Patents

Abstract

A jitter measurement circuit and the method to calibrate the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In the test mode, a probability distribution function (PDF) of the jitter of the clock under test is obtained. In the calibration mode, a random clock, which is externally-generated or generated from a free run voltage-controlled oscillator of a circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on the detected phase relationship, for obtaining a counting value and a PDF indicative of the jitter of the test clock.

Description

200905210 P2006-017-TW-A 21681twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a dithering circuit, and a built-in clock jitter measuring circuit. Related [Prior Art] • Data pulse (When the signal is transmitted on the transmission line, if the signal is jittery, the clock recovery circuit (Cloek C±lrcuit 'CDR) or phase-locked loop (PLL) may be problematic, even the data may be a The jitter can be determined by (10): the time offset of the rising edge (or falling edge) of the signal relative to its ideal time position. Figure 1 shows the definition of jitter. The jitter έ makes the bit error rate of receiving ^ (BitErr〇rRate , BER) improve, low overall service quality (Quality 〇 fService). Inter-error (TIE 'Time Interval Ε _) refers to (four) one of the parameters of the jitter, which means that at any point in time, the received signal bit (or pulse) and the reference clock phase difference. Generally, the jitter can be classified as Deterministic C Jitter (DJ) and Random Jitter (RJ). Random jitter is randomly generated. Timing noise level jitter. The distribution is usually Gaussian distribution, also known as Normal Distribution. At present, external automatic test can be utilized. ATE (automatic test equipment) is used to measure jitter. However, because the signal is output to the automatic test equipment, the signal passes through the output/input pin. As a result, the measured jitter may not necessarily be the original jitter. In addition, 'automatic test equipment is expensive, it will increase the test cost. 200905210 P2006-017-TW-A 2l68ltwf.doc/p Therefore, it is better to have a low test cost, _ time,,, move Circuit, [Summary] The use of the 页 page instrument. In view of this, the present invention provides an accurate measurement of jitter, and can reduce the measurement: built jitter measurement circuit, which can be used by the instrument. ° Cost, time of flight and reduction Measurement The present invention provides a delay buffer in a built-in phase diagram, which can be used to correct the synchronization of the present invention. The latter 'reset synchronous dual-phase detector ^ measurement circuit, It can be used to measure the hysteresis effect of one of the examples of the present invention at each sampling. The jitter measurement circuit built in the measurement of the pulse signal to be measured, the synchronous two-phase detection circuit, and the amount of the jitter The circuit includes: a signal for different delay clock signals and a reference clock to the synchronous biphasic detection bit relationship; and - determining a phase relationship between the circuit, the calculation, the data lock and the count, and the logic is used to perform the jitter The value and probability ^ cloth has a measurement about the clock signal to be measured for a time difference measurement circuit, which is used for one time between the signals to be measured by the circuit to be tested - the time difference of the clock to be measured ":; Including - vibrating source, the circuit to be tested, ^ ·: synchronous biphasic_circuit, lightly connected to the element and the vth target detecting circuit includes - the first delay buffer, the unit 'when the source is in —, ♦ pulse subtraction-phase probability distribution map, with 200905210 P2006-017-TW-A 2168ltwf.d〇c/p according to the clock signal of the signal to be measured and the figure (4) The difference between the 1 divisions; the test pulse synchronous dual-phase detection circuit 'pair=, the road' is transferred to the phase plane logical operation, the data path _ out of the one of the inter-turn difference value. I. In order to obtain the invention - the example is provided -

C. The reference clock signal and the circuit to be tested are used for the difference between the signals. The _ circuit includes at least the clock time difference measurement circuit including: _ synchronous biphasic ς oscillation source, the The measuring circuit 'the synchronous two-phase _ circuit includes -, the domain: and the second delay buffering unit, when the oscillating source c is applied to the pulse signal to be tested, the phase is also oscillated according to the pulse to be purchased The phase of the signal is decorated with the image of the delay time difference caused by the younger brother and the second delay buffer unit to the positive number; and - the decision of the test day

The L-synchronous two-phase _ circuit, the synchronous two-phase detection circuit is connected to the phase relationship, and the count value of one of the time differences is obtained by the (4) and the λ^. The above and other objects, features and advantages of the present invention are set forth in the description of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [Embodiment] In order to clarify the content of the present invention, the following specific examples are an example that can be implemented according to the present invention. FIG. 2 shows a block diagram of the built-in jitter measurement circuit of the fx according to the first embodiment of the present invention. The jitter measurement circuit mainly includes: a synchronous two-phase detection and a decision circuit 25. The jitter measurement circuit is configured to detect the jitter of the clock signal to be tested of the circuit 21 to be tested by (3), that is, the error of the clock signal CLKtest relative to the reference clock signal CLKref. The circuit under test 21 can be a PLL, CDR, DLL (Delayed Phase Locked Loop), or other similar circuit that can generate another output clock signal based on the reference clock signal. The synchronous two-phase detector 23 is configured to detect a phase relationship between the clock signal CLKtest to be tested and the reference clock signal cLKref, and output two signals S1/S2 to the decision circuit 25. The decision circuit 25 counts the signal S1/S2 to obtain the count value R1/R2 and sends it to the calculation unit/computing software (not shown) at the back end to obtain the jitter value and its leg S value. Figure 3 shows a block diagram of the circuit of the synchronous two-phase detector 23 and the decision circuit 25. The synchronous two-phase detector 23 includes delay buffers 301 to 303 and phase detecting units 304 to 305. The decision circuit 25 includes logic circuits 311 to 312, latches 313 to 314, logic circuits 315 to 31?, a multiplexer 317 and a counter 318. The delay buffers 301 and 302 delay the reference clock signal CLKref 'and generate a delayed reference clock signal]) D and D2. The delay buffer 303 delays the clock signal CLKtest to be tested, and generates a delay to output a clock signal D3. The delays caused by the delay buffers 301 to 303 are different, and the amount of delay is adjustable. For example, the delay buffer 301 causes the least amount of delay, the delay buffer 303 causes a slightly larger amount of delay, and the delay buffer 302 causes the largest amount of delay. 200905210 P2006-017-TW-A 21681twf.doc/p The phase detecting units 304 to 305 are, for example! Type positive and negative crying Position detection: Unit 3. 4: 305 has: data input D, hour: input. Phase reset terminal RST and data output terminal q. The phase detection unit ~ coffee = "D" accepts the delay and the reference clock signal is still connected. ‘The clock input terminal c of id05 accepts the delay and outputs the clock to call D3. In the phase detection unit, the reset terminal RST receives the signal RST. The phase system, the data input _ q signal S1 and S2. %

The signal S1 (whose value may be i or 0) represents the phase relationship between the post-delay reference clock signal D1 and the delayed output clock signal. The signal S2 (which may be 1 or 〇) represents the phase relationship between the reference clock signal after the delay and the pulse signal D3 after the delay. Further, in order to solve the hysteresis effect, in the first embodiment, the reset signal RST resets the phase detecting units 304 and 305 every time the sample-pen (i.e., generates a signal S1/S2) is taken. The circuit circuits 311 and 312 receive the round-trip signals S1 and S2 of the phase detecting units 304 and 305. The latches 313 and 314 latch the output signals of the logic circuits 311 and 312 according to the output of the clock signal D3 after the delay. The logic circuits 315 and 316 receive the output signals of the latches 313 and 314, and output the clock signal D3 and the enable signal EN after the delay, wherein the enable signal is generated by an external test instrument. The combination of latches 313 and 314 and logic circuits 315 and 316 can generate pulse signals. The output signals of the logic circuits 311 and 312 are 1, and the logic circuits 315 and 316 output the pulse signals; if the output signals of the logic circuits 311 and 312 are 0, the logic circuits 315 and 316 do not output the pulse signals. 200905210 P2006-017-TW-A 21681twf.doc/p The multiplexer 317 selects one of the outputs of the logic circuits 315 and 316 according to the selection signal SEL. The counter 318 counts the output of the multiplexer 3i7 to generate a count value R1/R2. The counter 318 is, for example, a Ripple Counter. The combination of the latches 313/314 and 31 greatly accelerates the measurement of jitter. The second, BIST circuit has two modes of operation: test mode. In the Lai mode, the circuit source (such as the motor (10)) will operate normally; in the calibration mode, the vibration source will be at (4) (ftOe_mn). However, in another aspect of the present invention, the test signal Ktest to be tested is used to perform the right mode. That is to say, when in the calibration mode, the required random clock may be the material wheel, or the signal can be self-tuned by the circuit under test: vibration, clock signal dxstributi! f ^® (PDF'P -babil^y 3 stnbutw funetlQn). It is normally distributed in test mode. According to the signal Sl/S2, the phase 0d of the sigh + motion _ can be divided into 0 to be between 0_ and 0+ (when sl=1, J^-(although (4)' 0+ (when Sl=l , S2 = 1). S2 = 〇), and greater than in Figure 4, pi ~ P3 respectively, abundance (Ρ1 + Ρ 2+ Ρ 3-Π, 弋 table the area of the two blocks, when Sl = 1 and 仏〇, phase 0d^)°付号τ 10 200905210 P2006-017-TW-A 21681twf.doc/p Please refer to Figure 5 'which shows the probability of phase 0 d of the clock signal CLKtest in the calibration mode τ The distribution function graph. Since the oscillation source of the circuit to be tested is under free oscillation, the clock signal CLKtest to be measured is randomly generated. That is to say, the clock signal CLKtest to be tested is not associated with the reference clock signal CLKref, and The probability distribution function graph of the phase of the pulse signal CLKtest to be tested will be uniformly distributed. The symbol τ 〇 represents the period of the reference %•pulse CLKref (that is, the post-delay reference clock signal D1). The symbol T represents the delay buffer 3〇. The delay time difference between 1 and 302. CLKrefdl and CLKrefd2 respectively represent the delayed reference clock signals generated by the delay buffers 301 and 302 of FIG. 3] and ])2. According to the statistical characteristics of the distribution of the mean sentence generated when the oscillation source of the circuit under test is free to oscillate, T = P2' * T0 can be obtained. According to TO and P2', the delay time difference between the delay buffers 301 and 302 can be obtained. Figure 6 shows the phase "(3)f, cumulative distribiition function). The horizontal axis is the phase </>d of the iJb pulse signal CLKtest, and the root mean square (RMS) The value (σ) is the unit. According to Π, Ρ 2, the phase error _ and χ + (in σ) can be found using Figure 6. The value of Τ is calculated based on Ρ 2'. Then, by the relationship between τ and X-, x+, the phase size corresponding to σ can be obtained. If expressed by a formula, it is: σ = Τ / (χ + - χ -) For example, when Ρ1=0· 1100, Ρ2=0· 5414, the corresponding χ is -1.23 and χ+ is +0.39 . Therefore, σ=0·04/(0. 39-(-1.23))=0.025. Figure 7 shows the simulation results. The reference clock signal CLKref is 11 200905210 P2006-017-TW-A 21681twf.doc/p 2. 5GHz 'jitter of the clock signal CLKtest to be tested (j is i〇ps (ie 0.025UI). Please refer to the bottom Two jitter value error comparison tables to better understand whether there is a difference between the feed reset signal RST and the phase detector. Table 1 below shows the jitter value error comparison table obtained by not feeding the reset signal RST to the phase detector. Table 1 iPl P2 T error ~~~~ Ideal correction state 0. 0809 0. 5686 0. 0409 8.1% ^ Calibration state 1 0. 0809 0.5686 0. 0375 ------ 15.9% State 2 --- --- 0. 0809 0.5686 0. 0380 14. 8%~~~~ Calibration status 3 0. 0809 0.5686 0. 0369 17. 2%~~

In the above Table 1, the ideal correction state means that in the calibration mode, Figure 2 = the clock signal to be tested CLKtest is replaced by a controllable clock signal (generated by the benefit of the signal). This can control the phase of the clock signal ^ ίίίίί function diagram will be evenly distributed, and the phase difference between the control pulse and the pulse is evenly distributed. This allows correction of =. The correction state 242 correction state represents the result measured using different free oscillating frequencies in the calibration mode. Table 2 below shows the jitter error comparison table fed to the reset signal RST. Obtained by the phase detector

12 200905210 P2006-017-TW-A 21681twf.doc/p State---'- Correction state 1 0.1100 0. 5414 0.0389 —---- 3.8% Calibration state 2 0. 1100 0.5414 0. 0392 3. 0% Correction State 3 0. 1100 0. 5414 0.0379 — 6. 1°/〇 It can be seen from Table 1 and Table 2 that the jitter error obtained when feeding the reset signal RST to the phase detector is indeed small.

Fig. 8 is a circuit diagram showing the BIST circuit of the second embodiment of the present invention. Basically, the architecture of the BIST circuit of the second embodiment is identical to the BIST circuit of the first embodiment except that the multiplexer 317 and counter 318 of FIG. 2 are replaced with the count states 318a and 318b. As for the operation mode of the second embodiment, it can be basically understood from the description of the first embodiment, so that the above embodiment of the present invention has the following % road area small 'high operation speed. With high accuracy. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to use =?, __=: the present invention [early illustrated between the drawings] Fig. 1 shows the definition of jitter. According to the first embodiment of the present invention, the built-in jitter measurement electric block ^ shows the circuit of the two-phase _ turn decision circuit of FIG. 2, and FIG. 4 shows the phase of the phase signal of the day-to-day pulse signal in the test mode 13 200905210 P2006-017-TW-A 21681twf.doc/p rate distribution function graph. Figure 5 shows the probability distribution function of the phase of the pulse signal to be measured in the calibration mode. Figure 6 shows the cumulative probability distribution function of the phase of the pulse signal to be measured. Fig. 7 shows the simulation results of the first embodiment. Fig. 8 is a circuit diagram showing the built-in jitter measuring circuit of the second embodiment of the present invention. [Main component symbol description] 21: circuit under test 23: synchronous two-phase detector 25, 25': decision circuits 301 to 303: delay buffers 304 to 305: phase detecting units 311 to 312, 315 to 316: logic Circuits 313 to 314: latch 317: multiplexer 318, 318a, 318b: counter 14

Claims (1)

200905210 P2006-017-TW-A 21681twf.doc/p X. Patent application scope: 1. - Built-in jitter measurement circuit for outputting one of the clock signals to be tested relative to the "hair path" The jitter measurement circuit includes a synchronous two-phase detection circuit of the reference clock signal, coupled to the circuit for different time delays of the clock signal to be tested and the reference step, and measuring the delay T standby time for the test The phase relationship between the pulse signals; and the synchronous signal and the delayed phase-detected two-phase detection circuit 彳贞t the synchronous two-phase detection circuit, the same material loose lock and Wei, to: the phase _ Operation, capital-count value. It is judged that the jitter of the system is called the same ===: [the jitter measurement circuit described in [丨], where - second ==; = yuan, depends on the reference The clock is subtracted to generate - delay the reference clock signal to generate the delay 彳 彳ϊ 彳ϊ 日 , , , , , , , 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延 延The jitter measurement circuit of item 2: wherein the phase detector is coupled to the first delay buffer unit and 15 200905210 P2006-017-TW-A 21681twf.doc/p The third delay buffer unit detects the phase relationship between the reference pulse after the first delay and the clock signal to be measured after the delay; and a second a phase detector coupled to the second delay buffer unit and the third delay buffer unit to detect a phase relationship between the reference pulse after the second delay and the pulse signal to be measured after the delay; wherein each sampling The first and second phase detectors are reset once. 4. The jitter measurement circuit of claim 3, wherein the decision circuit comprises: a first logic circuit, the One output signal of the first phase detector is logically operated with one of the output signals of the second phase detector; and a second logic circuit, the output signal of the first phase detector and the second phase The output signal of the detector is logically operated. 5. The jitter measuring circuit of claim 4, wherein the determining circuit comprises: a first data latch, according to the delay, the time to be tested Pulse signal One of the first logic circuits outputs a signal; and a second data latch latches the output signal of one of the second logic circuits according to the pulse signal to be tested after the delay. 6. The jitter measuring circuit, wherein the determining circuit comprises: a third logic circuit, wherein the output signal of one of the first data latches, the pulse signal to be tested after the delay and the signal of the consistent energy are logically operated; 16 200905210 P2006-017-TW-A 21681twf.doc/p The fourth circuit, for the second number, after the delay, the time pulse to be measured can produce L material, A °. The output signal 7' is as described in claim 6 of the scope of the patent. The circuit of the decision includes: a π-side jitter measurement circuit, wherein the Xigong is 'from the second logic band with one of the four logic circuits The output signal and the output signal are compared with the first counter, and the count is δ. For example, the scope of the patent application is "". The output circuit is: The decision circuit includes: the jitter measurement circuit described by the member, wherein the brother '*言十皇 f 3& And the 'output (four) third circuit - the output signal axis "receives the circuit - the wheel out signal. As soon as the circuit is used for measurement, the time difference between the reference clock signal and the signal to be tested is at least one of the clock signals to be measured. The synchronization center 2, the county circuit includes: Biphase detection _ circuit package extension ^ a circuit coupled to the circuit to be tested, the synchronization unit 24 oscillating (9) the first delay buffer unit and the second delay buffer signal to phase: during normal operation, 'getting the phase of the pulse to be tested The machine map is configured to correct the first delay buffer unit and the difference according to the second delay of the clock signal to be tested: "the cloth 51"; and the delayed time step biphase caused by the reference clock signal For example, in the 28-way synchronous circuit, the phase-locking 舆 count, r, and the phase relationship of the enthalpy are logically operated, and the _count value is related to the time difference. 10. The time difference measuring circuit according to claim 9, wherein the first delay buffer unit delays the reference clock signal to generate a first After the delay, the second delay buffer unit delays the reference clock signal to generate a second delayed reference clock; and the synchronous two-phase detection circuit further includes: a third delay buffer unit, delaying the The clock signal to be tested is used to generate the clock pulse to be tested after the delay; wherein the delay amount of the third delay buffer unit is between the delay amount of the first and second delay buffer units. 11. The time difference measuring circuit according to claim 10, wherein the synchronous two-phase detecting circuit comprises: a first phase detector coupled to the first delay buffer unit and the third delay a unit for detecting a phase relationship between the reference pulse after the first delay and the pulse signal to be measured after the delay; and a second phase detector coupled to the second delay buffer unit and the third delay The buffer unit is configured to detect a phase relationship between the reference pulse after the second delay and the clock signal to be tested after the delay; wherein the first and second phase detectors are reset every time the sample is taken. 12. The time difference measuring circuit according to claim 11, wherein the determining circuit comprises: a first logic circuit, an output signal of the first phase detector and the second phase detector An output signal performs a logic operation; and a second logic circuit logically operates the output signal of the first phase detector and the output signal of the second phase detector. The method of claim 12, wherein the decision circuit comprises: - a data latch, according to the delay Measuring a clock signal to latch an output signal of the first logic circuit; and latching; the latcher latches an output signal of the first evasive circuit according to the delayed clock signal after the delay. The road number is calculated as described in claim 13 wherein the decision circuit comprises: - a third logic circuit, the first data latch = late test pulse signal and - enable logic The fourth logic circuit 'the second data latch number, the delayed _clock minus and the new energy signal = as described in claim 14 of the patent scope, the circuit, wherein the decision circuit The method includes: a day] measuring a multiplexer in the difference, from the third logic mine-C four logic circuit--taking the signal selection-; and outputting the signal and the first-----the number of the multiplexer - the output signal. The circuit, wherein the determining circuit comprises: a red peak difference metering number; a two-two counter, counting one of the third logical cells one output letter 171 tf, 11 'counting the fourth logic circuit < 'out H The time difference is Jin, and the output is k 5 tiger. And - H of the circuit to be tested, f test clock pulse - the time difference between the signals to be tested, 19 200905210 P2006-017-TW-A 21681twf.d〇c/p The circuit to be tested includes at least - The source, the synchronous two-phase _ circuit, the difference circuit includes: the Ϊ phase detecting circuit includes a -first delay buffer circuit, the synchronous saponite, when the oscillating source is in a phase of - a free two-one delay buffer signal A probability distribution map is shown in Fig. J; J is to be corrected by the probability distribution of the phase of the clock, and the phase clock signal ο Si punching unit refers to the time-number: to; step double === Measuring circuit, the same as the recognition;: There is a time difference - the count value. The road, wherein the time difference measured by the town of the town, and the time difference of the S17 item, the electric delay buffer unit delays the reference clock signal to delay the tea test clock; the second delay buffer unit delays the pulse The signal is generated to generate a reference clock after the second delay; and the same circuit further includes: a third delay buffer unit that delays the day sigma sigma to generate the delayed clock after the delay; The delay amount of the third delay buffer unit is between the delay amount of the first and the first delay buffer unit. 19. The time difference measuring circuit of claim 18, wherein the synchronous two-phase detecting circuit comprises: 4 a first phase detector coupled to the first delay buffer unit and . a second delay buffer unit for detecting a phase relationship between the reference pulse after the first delay and the clock signal to be measured after the delay; and a second phase detector coupled to the second delay buffer unit 20 200905210 P2006-017-TW-A 21681twf.doc/p The third delay buffer unit detects the phase relationship between the reference pulse after the second delay and the clock signal to be measured after the delay; Once sampled, the first and second phase detectors are reset. 20. The time difference measuring circuit of claim 19, wherein the determining circuit comprises: a first logic circuit, an output signal of the first phase detector and the second phase detector An output signal performs a logic operation; and the second logic circuit performs a logic operation on the output signal of the first phase detector and the output signal of the second phase detector. 21. The time difference measuring circuit of claim 20, wherein the determining circuit comprises: a first data latch, latching one of the first logic circuits according to the pulse signal to be tested after the delay And outputting a signal; and a second data latch, and latching the output signal of one of the second logic circuits according to the pulse signal to be tested after the delay. < 22. The time difference measuring circuit according to claim 21, wherein the determining circuit comprises: a third logic circuit, outputting a signal to one of the first data latches, and the time after the delay is to be tested The pulse signal is logically operated with the coincidence signal; and a fourth logic circuit performs logic operation on the output signal of one of the second data latches, the pulse signal to be tested after the delay, and the enable signal. 23. The time difference measurement device described in claim 22, wherein the decision circuit comprises: a multiplexer from the third logic circuit An output signal is selected from one of the output signals of the fourth logic circuit; and a first counter is used to count the output signal of one of the multiplexers. 24. The time difference measuring circuit of claim 22, wherein the determining circuit comprises: a second counter that counts an output signal of the third logic circuit; and a third counter that counts the fourth logic One of the circuits outputs a signal.