TW200903750A - Semiconductor device having heat sink - Google Patents

Semiconductor device having heat sink Download PDF

Info

Publication number
TW200903750A
TW200903750A TW097118962A TW97118962A TW200903750A TW 200903750 A TW200903750 A TW 200903750A TW 097118962 A TW097118962 A TW 097118962A TW 97118962 A TW97118962 A TW 97118962A TW 200903750 A TW200903750 A TW 200903750A
Authority
TW
Taiwan
Prior art keywords
wafer
heat sink
flowing
primer
metal
Prior art date
Application number
TW097118962A
Other languages
Chinese (zh)
Other versions
TWI370526B (en
Inventor
Chia-Chieh Hu
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW097118962A priority Critical patent/TWI370526B/en
Publication of TW200903750A publication Critical patent/TW200903750A/en
Application granted granted Critical
Publication of TWI370526B publication Critical patent/TWI370526B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Abstract

The present invention discloses a semiconductor device having a heat sink. The semiconductor device comprises a chip having an active surface flip-chip bonded on a substrate and a backside surface, a heat sink disposed above the backside surface of the chip, a solder layer formed between the heat sink and the backside surface of the chip, and no-flow underfill formed between the solder layer and the backside surface of the chip wherein the no-flow underfill includes metal particles (or plastic particles coated with metal), flux and underfill.

Description

200903750 九、發明說明： 【發明所屬之技術領域】 β匕本案發明係有關於一種具散熱裝置之半導體元件，特別 疋^種不需要將晶片背面覆金(c〇ating g〇ld)就可使輝錫 層藉由加有—定比例之細小粉末之非流動性底_〇-肠 underf:⑴，可增加銲錫層與膠材之間的接著面積，使銲錫層 強力黏著於該晶片背面上，而且不需使用助焊劑⑴ux)以減少 空洞（vmd)發生之一種覆晶晶片封裝黏著技術。 【先前技術】 按’半導體封裝(package)技術之突飛猛進，且 導體兀件之運作觀及壽命，目歧魏纽 ^ ==常重要的因素，從習知無叫= 雜重要讀轉徵。麵上，目前賴=1= 裝 項挑戰，可想而知，在小小的面積内要裝入越來越 多的電晶體’這使得半導體元件愈來愈熱== 善’方能使廢熱能有效消除，：= 長，也因此，在覆晶 熱需求愈麵大，㈣晶封裝之散 #難則，在7m/、、、、由 “準鱗如之散熱膠已 、一 M_L’目前業界已有人開始使用低溫融溶之200903750 IX. Description of the invention: [Technical field to which the invention pertains] The invention of the present invention relates to a semiconductor component having a heat dissipating device, and in particular, it is not necessary to apply a gold back surface to the wafer. The bismuth layer can increase the adhesion area between the solder layer and the glue by adding a non-flowing bottom-intestine underf: (1) of a small proportion of fine powder, so that the solder layer is strongly adhered to the back surface of the wafer. Moreover, there is no need to use flux (1) ux) to reduce the occurrence of voids (vmd) in a flip chip package adhesion technique. [Prior Art] According to the 'semiconductor package technology's rapid advancement, and the operational concept and life of the conductor element, Weigu ^ == often important factor, from the conventional no-call = miscellaneous important reading. On the surface, currently Lai = 1 = loading challenge, it is conceivable that more and more transistors should be installed in a small area 'This makes the semiconductor components hotter and hoter == Good' can make waste heat Can effectively eliminate, : = long, and therefore, the need for recrystallization heat is larger, (four) crystal package of the scattered # difficult, in 7m /,,, by "quasi-scale such as heat-dissipating glue, a M_L' current People in the industry have begun to use low temperature melting

P07006-TW ASE-1901 200903750 金屬例如銲錫作為晶背與散熱片間的導熱介面物質（Thermal Interface Material, TIM) ’ 但其需要在晶背（Chipback)覆金 (coatinggold)。然而，此覆金製程對晶圓廠或封裝廠而言都 非常困擾，因覆金製程(coating gold)很容易造成晶圓廠污 染。 有鑑於此，本案發明人研發出於封裝過程中不需晶背覆 金(coating gold on chip back)就可使得 s〇ider τίΜ 強固黏著於 曰曰皮，如此使付封裝散熱技術更精進，達到更有效率運作、更 節省成本及使用壽命更長之目標。 【發明内容】 本案發明之目的在於利用一非流動性底膠改善晶片背面 及輝錫層之_接著強度問題，使得不需晶背覆金就可使銲錫 層強力黏著於晶片背面（chip back)。 為有效達成上述目的，本案發明係一種具散熱裝置之半 導體几件’包括：-基板；—晶片，其具有—晶片主面及一晶 片背面，該晶片主面係以覆晶接合方式設置於該基板上；一散 熱=，設於該晶片背面之上；—銲錫層，設於該散熱片與該晶 片背面之間；以及一非流動性底膠，其包含金屬顆粒或表面鍍 有金屬之塑膠顆粒、助焊劑（nux)以及底膠(underfiU),該 非流動性底膠係設於該晶片背面與該銲錫層之間，用以增強該 晶片背面與該銲錫層間之接著強度。 本案發明係一種具散熱裝置之半導體元件製程，其方法 步驟包括：（a)將包含有金屬顆粒或表面鍍有金屬之塑膠顆 -6 -P07006-TW ASE-1901 200903750 Metals such as solder are used as the Thermal Interface Material (TIM) between the crystal back and the heat sink, but they need to be coated on the chip. However, this gold-clad process is very troublesome for fabs or packaging plants, as the coating gold can easily cause fab contamination. In view of this, the inventor of the present invention developed that the coating gold on chip back can make s〇ider τίΜ firmly adhere to the suede, so that the package cooling technology is more refined. More efficient operation, more cost savings and longer life. SUMMARY OF THE INVENTION The object of the present invention is to improve the problem of the adhesion strength of the back side of the wafer and the tin layer by using a non-flowing primer, so that the solder layer can be strongly adhered to the chip back without the need for crystal back gold. . In order to effectively achieve the above object, the invention is a semiconductor device having a heat dissipating device comprising: a substrate; a wafer having a main surface of the wafer and a back surface of the wafer, wherein the main surface of the wafer is disposed in a flip chip manner a substrate; a heat sink = disposed on the back surface of the wafer; a solder layer disposed between the heat sink and the back surface of the wafer; and a non-flowing primer comprising metal particles or a metal plated surface A granule, a flux (nux), and an underfill (underfiU) are disposed between the back surface of the wafer and the solder layer to enhance the adhesion strength between the back surface of the wafer and the solder layer. The invention is a semiconductor component process with a heat sink, and the method steps include: (a) plastic particles containing metal particles or metal-plated surfaces -6 -

P07006-TW ASE-1901 200903750 ，片底膠的一非流動性底膠塗佈於-晶片背面，該 日日片主面係以覆晶接合方式 (p.ece 〇f 上；（c)將-散熱片置於於該銲錫 μ氏膠 驟，其找核練底射的金獅^·^)柄—回焊步 結，而進—她咖時產生燒 :理:=;= 步：)亦可 上，細糊二置於該非流動性底膠 姐軸崎爛齡，用以作為 較佳者，其中該細小粉末金屬係由金、 合而成 銀或錫之部分或全部組 ίϊί面，該塑膠顆 較佳者’其中該導熱膠相對於兮非、、ώ t 導係數，故該非流動性底膠之厚声二、生底膠係具有極高之熱 整體導熱效果情況下控制於—適^^^不大巾虽影響該散熱單元 均勻散佈的方法係為噴佈 均勻散佈的方法係為印刷 較佳者，其中使該非流動性底勝 (jetting)的方法。 較佳者，其中使該非流動性底膠 (printing)的方法。P07006-TW ASE-1901 200903750, a non-flowing primer of the primer is applied on the back side of the wafer, and the main surface of the day is bonded by a flip chip (p.ece 〇f; (c) will - The heat sink is placed on the solder μ gum, and the gold lion ^·^) handle that looks for the nuclear shot is re-welded, and the heat is generated when the coffee is burned: the reason: =; = step:) Alternatively, the fine paste is placed on the non-flowing primer, which is used as a preferred one, wherein the fine powder metal is made of gold or a part or all of the group of silver or tin. The plastic pellet is better than the conductive coefficient of the non-flowing primer, so the thicker sound of the non-flowing primer is controlled by the high thermal conductivity of the bottom rubber. ^^^ The method of not absorbing the uniform dispersion of the heat dissipating unit is a method in which the uniform distribution of the spray cloth is preferred, and the method of making the non-flowing jetting is made. Preferably, the method of making the non-flowing primer.

P07006-TW ASE-1901 200903750 較佳者，其中該回焊係為攝氏100-200°C度之加熱過程。 【實施方式】 雖然本案發明可表現為不同形式之實施例，有關 本案發明之前述及其他技術内容，特點與功效，在配合 以下參考圖式之可行且較佳實施例的詳細說明中，將可 清楚的呈現。 請參照第一圖〜第三圖。其中第一圖係為本案發明 實施例之喷射或印刷（jetting or printing)非流動性底膠 (No-flow underfill)之剖面示意圖。其係首先在基板1〇 之上表面没置一晶片13，之後，再以喷槍11將包含金 屬顆粒或表面锻有金屬之塑膠顆粒、助焊劑（fjux)以及 底膠(underfill)之非流動性底膠12均勻地散佈於該晶片 13之晶片背面16 ’該晶片13之晶片主面15具有多數 個接觸單元（未示於圖中），用以與外界形成電性連接， 而該晶片背面16則用於傳導該晶片13所產生之熱能。 請參照第二圖，如圖所示係為本案發明實施例置放 銲錫層之剖面示意圖。其係首先在基板2〇之上表面設置 一晶片23，之後，再以喷槍η將包含金屬顆粒或表面 鍵有金屬之塑膠顆粒、助焊劑（fjux)以及底膠（underfill) 之非流動性底膠22均勻地散佈於該晶片23之晶片背面 26，該晶片23之晶片主面25具有多數個接觸單元（未 示於圖中），用以與外界形成電性連接，而該晶片背面 26則用於傳導該晶片23所產生之熱能。 之後’再將一具有高導熱性之銲錫層21 (例如一片狀銲 錫(Piece of Solder))置於該非流動性底膠22上。 -8 -P07006-TW ASE-1901 200903750 Preferably, the reflow system is a heating process of 100-200 ° C degrees Celsius. The present invention and the other technical contents, features and effects of the present invention will be described in conjunction with the following detailed description of possible and preferred embodiments of the drawings. Clear presentation. Please refer to the first figure to the third figure. The first of these is a schematic cross-sectional view of a jetting or printing No-flow underfill of an embodiment of the invention. It is first placed on the upper surface of the substrate 1 without a wafer 13, and then, by the spray gun 11, the non-flowing of plastic particles, flux (fjux) and underfill containing metal particles or surface forged metal is used. The primer 12 is evenly spread on the back surface 16 of the wafer 13 of the wafer 13. The main surface 15 of the wafer 13 has a plurality of contact units (not shown) for electrically connecting to the outside, and the back of the wafer 16 is used to conduct the heat energy generated by the wafer 13. Referring to the second figure, the cross-sectional view of the solder layer is shown in the embodiment of the present invention. Firstly, a wafer 23 is disposed on the upper surface of the substrate 2, and then the non-flowing property of the metal particles or the surface-bonded metal particles, the flux (fjux) and the underfill is performed by the spray gun η. The primer 22 is evenly spread over the wafer back surface 26 of the wafer 23. The wafer main surface 25 of the wafer 23 has a plurality of contact units (not shown) for electrically connecting to the outside, and the wafer back surface 26 It is then used to conduct the thermal energy generated by the wafer 23. Thereafter, a solder layer 21 having a high thermal conductivity (e.g., a Piece of Solder) is placed on the non-flowing primer 22. -8 -

P07006-TW ASE-190] 200903750 請參照第三圖，如圖所示係為本案發明實施例回焊過程 (reflow)之剖面示意圖。其係首先在基板30之上表面設 置一晶片33，之後，再以喷槍11將包含金屬顆粒或表 面鍍有金屬之塑膠顆粒、助焊劑（flux)以及底膠 (underfill)之非流動性底膠32均勻地散佈於該晶片33 之晶片背面36 ’該晶片33之晶片主面35具有多數個 接觸單元（未示於圖中），用以與外界形成電性連接， 而該晶片背面36則用於傳導該晶片33所產生之熱能。 之後，再將一具有高導熱性之銲錫層31 (例如一片狀銲 錫(piece of solder))置於該非流動性底膠32上，並將一 散熱片34覆蓋於該銲錫層31上。該銲錫層31與該非流 動性底膠32經回焊步驟後將該散熱片34與該晶片33 黏著。 第七圖所示為根據本發明一實施例之具散熱裝置 之半導體元件100,其主要包含一晶片110,其晶片主 面110a係以覆晶接合方式設置於一基板120上；以及 一散熱片130，其藉由一銲錫層140以及一非流動性底 膠150固接於該晶片110之晶片背面110b。晶片110 運作時所產生之熱能，係經由晶片晶片背面ll〇b、非 流動性底膠150、銲錫層140而傳導至散熱片130，再 經由其散熱至半導體元件1〇〇外部。 該基板120可以是一多層陶竟基板（multi-layer ceramic substrate)。該基板120亦可以是有機基板 (organic substrate )，例如，由玻璃纖維強化BT (bismaleimide-triazine)樹脂，或FR-4玻璃纖維強化環氧 樹月旨（fiberglass reinforced epoxy resin)製成之蕊層（coreP07006-TW ASE-190] 200903750 Please refer to the third figure, which is a schematic cross-sectional view of the reflow process of the embodiment of the present invention. Firstly, a wafer 33 is disposed on the upper surface of the substrate 30, and then the non-flowing bottom of the metal particles or the metal-plated plastic particles, the flux and the underfill is sprayed by the spray gun 11. The glue 32 is evenly spread over the wafer back surface 36 of the wafer 33. The wafer main surface 35 of the wafer 33 has a plurality of contact units (not shown) for electrically connecting to the outside, and the wafer back surface 36 is It is used to conduct the heat energy generated by the wafer 33. Thereafter, a solder layer 31 having a high thermal conductivity (e.g., a piece of solder) is placed on the non-flowing primer 32, and a heat sink 34 is overlaid on the solder layer 31. The solder layer 31 and the non-flowing primer 32 are adhered to the wafer 33 after the reflow step. FIG. 7 is a semiconductor device 100 having a heat dissipating device according to an embodiment of the present invention, which mainly includes a wafer 110 having a wafer main surface 110a disposed on a substrate 120 in a flip chip manner; and a heat sink 130, which is fixed to the wafer back surface 110b of the wafer 110 by a solder layer 140 and a non-flowing primer 150. The heat generated during the operation of the wafer 110 is conducted to the heat sink 130 via the wafer wafer back surface 〇b, the non-flowing primer 150, and the solder layer 140, and is then radiated to the outside of the semiconductor device 1 through the heat sink 130. The substrate 120 can be a multi-layer ceramic substrate. The substrate 120 may also be an organic substrate, for example, a glass fiber reinforced epoxy resin or a FR-4 fiberglass reinforced epoxy resin. (core

P07006-TW ASE-1901 200903750 layer)形成。該基板120至少包含兩組接墊（未示於圖 中）分別設於其上表面以及下表面，其中第一組接墊係 用以電性連接至晶片110，而第二組接墊係用以電性連 接至一外部印刷電路板並且其係分別電性連接至該基 板120上表面相對應之第一組接墊。如圖所示，該晶片 110係利用銲錫凸塊112與該基板120上表面相對應之 第一組接墊（未示於圖中）形成機械與電性連接。在晶 片110與基板120間具有一底膠(underfill)114用以密封 該些銲錫凸塊112間之空隙。如第六圖所示，該散熱片 130與基板120之間係設有一加固環160，使得該晶片 110係密封於該該散熱片130、基板120與加固環160 之間。 值得注意的是，本發明之非流動性底膠150係設於 晶片晶片背面ll〇b與銲錫層140之間，用以增強該晶 片晶片背面ll〇b與銲錫層140間之接著強度，並且幫 助吸收散熱片130與晶片110之間因熱膨脹係數不匹配 所造成之應力。該非流動性底膠150係包含金屬顆粒或 表面鍍有金屬之塑膠顆粒、助焊劑（flux)以及底膠 (underfill)。該非流動性底膠中之金屬顆粒含量較佳為 約40 wt%至約60 wt%。前述之金屬顆粒較佳係為奈米 等級之金屬（例如金、銀、錫或其混合物）粉末。前述 之塑膠顆粒較佳係為奈米等級之塑膠粉末。適用於本發 明非流動性底膠150之助焊劑較佳係為免洗助焊劑 (no-clean flux)。該非流動性底膠中之助焊劑含量較佳小 於2%，以免產生回焊過程的氣泡問題。 本案發明主要係利用一非流動性底膠改善晶片背 面及銲錫層之間的接著強度問題，使得不需晶背覆金就P07006-TW ASE-1901 200903750 layer) formed. The substrate 120 includes at least two sets of pads (not shown) disposed on the upper surface and the lower surface, wherein the first set of pads are electrically connected to the wafer 110, and the second set of pads are used. Electrically connected to an external printed circuit board and electrically connected to the first set of pads corresponding to the upper surface of the substrate 120, respectively. As shown, the wafer 110 is mechanically and electrically connected to the first set of pads (not shown) corresponding to the upper surface of the substrate 120 by solder bumps 112. An underfill 114 is disposed between the wafer 110 and the substrate 120 for sealing the gap between the solder bumps 112. As shown in the sixth figure, a reinforcing ring 160 is disposed between the heat sink 130 and the substrate 120 such that the wafer 110 is sealed between the heat sink 130, the substrate 120 and the reinforcing ring 160. It should be noted that the non-flowing primer 150 of the present invention is disposed between the back surface of the wafer wafer 11b and the solder layer 140 to enhance the bonding strength between the back surface of the wafer wafer 11b and the solder layer 140, and It helps to absorb the stress caused by the thermal expansion coefficient mismatch between the heat sink 130 and the wafer 110. The non-flowing primer 150 comprises metal particles or metal-plated plastic particles, a flux, and an underfill. The content of the metal particles in the non-flowing primer is preferably from about 40% by weight to about 60% by weight. The aforementioned metal particles are preferably powders of a metal of a nanometer grade (e.g., gold, silver, tin or a mixture thereof). The aforementioned plastic particles are preferably nanometer grade plastic powder. The flux suitable for use in the non-flowing primer 150 of the present invention is preferably a no-clean flux. The flux content of the non-flowing primer is preferably less than 2% to avoid bubble problems during the reflow process. The invention of the present invention mainly utilizes a non-flowing primer to improve the adhesion strength between the back surface of the wafer and the solder layer, so that the crystal backing is not required.

P07006-TW ASE-1901 -10- 200903750 可使銲錫層強力黏著於晶片背面（chip back)。根據本發 明一實施例之具散熱裝置之半導體元件製程，係參照第 四圖與第六圖詳述於下。詳細言之，根據本發明之製程 主要包括： (a) 將包含有金屬顆粒或表面鍍有金屬之塑膠顆 粒、助焊劑以及底膠的一非流動性底膠塗佈於一晶片背 面’該晶片主面係以覆晶接合方式設置於一基板上； (b) 將一銲錫層置於該非流動性底膠上； (c) 將一散熱片置於於該銲錫層上；以及 (d) 進行一回焊步驟，其中該非流動性底膠中的金 屬顆粒間會在回焊時產生燒結，而進一步增強該晶片背 面與銲錫間之接著強度。 在步驟(a)中，首先需將晶片11〇利用固設於晶片上 之錫鉛凸塊（solder bmnp)l 12與基板120進行接合。該 晶片上之錫鉛凸塊可利用習知的C4 (Controlled Collapse Chip Connection)製程形成，其包含步驟(A)在 晶片之晶片銲塾（bonding pad)上形成一球下金屬層 (under bump metallurgy, UBM);以及步驟（B)在 UBM 上 形成錫球突起。接著，將前述步驟的產物移至一回銲爐 (reflow oven)内’並且經由該回銲製程形成錫鉛凸塊ι12 用以電性以及機械性連接該晶片110以及基板12〇。接 著’如第四圖所示’將前述之包含有金屬顆粒或表面鍍 有金屬之塑膠顆粒、助焊劑以及底膠的非流動性底膠， 以喷佈(jetting)的方法均勻塗佈於晶片晶片背面n〇b。 此外，根據本發明之非流動性底膠亦可以印刷的方式塗 佈於晶片晶片背面11 〇b。 在步驟（b)中，如第五圖所示，以一自動化選取及P07006-TW ASE-1901 -10- 200903750 The solder layer can be strongly adhered to the chip back. The semiconductor device process with the heat sink according to an embodiment of the present invention is described in detail below with reference to Figures 4 and 6. In detail, the process according to the present invention mainly comprises: (a) coating a non-flowing primer containing metal particles or metal-plated plastic particles, a flux and a primer on the back side of a wafer. The main surface is disposed on a substrate by flip chip bonding; (b) placing a solder layer on the non-flowing primer; (c) placing a heat sink on the solder layer; and (d) performing A reflow step in which metal particles in the non-flowing primer are sintered during reflow, thereby further enhancing the bonding strength between the back surface of the wafer and the solder. In the step (a), the wafer 11 is first bonded to the substrate 120 by a tin-lead bump 12 fixed on the wafer. The tin-lead bump on the wafer can be formed by a conventional C4 (Controlled Collapse Chip Connection) process, which comprises the step (A) forming a sub-metal layer on the bonding pad of the wafer (under bump metallurgy) , UBM); and step (B) form a solder ball protrusion on the UBM. Next, the product of the foregoing step is moved into a reflow oven and a tin-lead bump ι12 is formed through the reflow process for electrically and mechanically connecting the wafer 110 and the substrate 12A. Then, as shown in the fourth figure, the non-flowing primer containing the metal particles or the metal-plated plastic particles, the flux and the primer is uniformly coated on the wafer by a jetting method. The back side of the wafer is n〇b. Further, the non-flowing primer according to the present invention can also be applied in a printed manner to the back surface 11 〇b of the wafer wafer. In step (b), as shown in the fifth figure, an automatic selection and

P07006-TW ASE-1901 -11 - 200903750 片狀銲·锡(piece of 置於該非流動性 安Π幾器將-銲錫層140a (例如- ::))(溶點較佳係為100-200。(：） 底膠150上。 访(C)中，如第六圖所示，以一自動化選取及容 見第五m文…片13〇(其上具有一膠層162)(參 圖）置於該銲錫層140a上。 可以理解的是，前 列步驟(b+c)取代：將一 置於該非流動性底膠上 性底膠。 述之步驟(b)與步驟（〇亦可以下 表面配置有一銲錫層之散熱片 ，使得該銲錫層係面向該非流動 至-回將前述步驟⑷或步驟(b+C)的產物移 度之加埶制:ί、”且進行一回銲製程（例如100-200。〇 流動性散熱片13G藉由銲錫層14G以及非 見第七固接於晶片n〇之晶片背面nob(參 的金屬i i間完成之後’該非流動性底膠中 面110b If雜曰® 1 &、'、"，而進一步增強該晶片晶片背 b ”知錫層14〇間之接著強度。 以限定月二ΐ述較佳實施例揭示，然其並非用 積神和範圍内，⑵ 【圖式簡單說明】 ^圍田視後附之申請專利範圍所狀者為準。 第 圖 圖^月實知例噴射或印㈣流動性底膠之剖面示意P07006-TW ASE-1901 -11 - 200903750 Sheet solder/tin (piece of the non-flowing ampoule will be solder layer 140a (for example -::)) (the melting point is preferably 100-200). (:) On the primer 150. In the interview (C), as shown in the sixth figure, an automatic selection and acceptance of the fifth m...sheet 13〇 (with a glue layer 162 thereon) (see figure) On the solder layer 140a, it can be understood that the preceding step (b+c) is substituted: one is placed on the non-flowing primer, and the step (b) and the step (described in the following surface configuration) a heat sink having a solder layer such that the solder layer is oriented to the non-flowing-to-return product of the aforementioned step (4) or step (b+C): ί," and performing a reflow process (eg, 100) -200. The flowable heat sink 13G is soldered to the back side of the wafer by the solder layer 14G and the seventh surface of the wafer n〇 (after the metal ii is completed), the non-flowing primer medium 110b If 1 &, ', ", and further enhance the bonding strength between the backside of the wafer wafer, and the preferred embodiment of the invention. It is not used in the scope of the gods and the scope, (2) [Simple description of the schema] ^The scope of the patent application scope attached to the field of the field is subject to the scope of the patent application. The figure shows the section of the spray or the (four) flowable primer.

P07006-TW ASE-1901 -12- 200903750 第一圖、本案發明實施例置放銲錫層之剖面示意圖。 第三圖、本案發明實施例回焊過程(reflow)之剖面示意圖。 係___本發明—實施例之具散熱裳 根縣發明—倾败錄絲£之半導妓件之剖面 【主要元件符號說明】 10:基板(substrate) 11:噴搶 12:非流動性底膝(Noflow underfill) 13:晶片 15:晶片主面 16:晶片背面 20:基板(substrate) 21:銲錫層(piece of solder) 22:非流動性底膠(N〇-fl〇w underfill) 23:晶片 25:晶片主面 26:晶片背面 3 〇:基板(substrate) 31:銲錫層 32:非流動性底膠(No-flow underfill) 33:晶片 34:散熱片 35:晶片主面 36:晶片背面 110:晶片110a:晶片主面P07006-TW ASE-1901 -12- 200903750 First, a schematic cross-sectional view of a solder layer placed in an embodiment of the present invention. The third figure is a schematic cross-sectional view of a reflow process of the embodiment of the present invention. ___The present invention - the embodiment of the heat sinking Shergen County invention - the section of the semi-guided piece of the retractable silk [main symbol description] 10: substrate (substrate) 11: spray robbing 12: illiquidity Noflow underfill 13: Wafer 15: Wafer main surface 16: Wafer back surface 20: Substrate 21: Piece of solder 22: Non-flowing primer (N〇-fl〇w underfill) 23 : Wafer 25: Wafer main surface 26: Wafer back surface 3 〇: Substrate 31: Solder layer 32: No-flow underfill 33: Wafer 34: Heat sink 35: Wafer main surface 36: Wafer Back surface 110: wafer 110a: main surface of the wafer

P07006-TW ASE-1901 -13 - 200903750 ll〇b:晶片背面 112銲錫凸塊 114底膠 120:基板 130:散熱片 140:銲錫層 140a:銲錫層 150:非流動性底膠 160:加固環 162:膠層 P07006-TW ASE-1901 -14-P07006-TW ASE-1901 -13 - 200903750 ll〇b: wafer back surface 112 solder bump 114 primer 120: substrate 130: heat sink 140: solder layer 140a: solder layer 150: non-flowing primer 160: reinforcement ring 162 : glue layer P07006-TW ASE-1901 -14-

Claims (1)

200903750 十、申請專利範圍： 1. 一種具散熱裝置之半導體元件，包括： 一基板； 一晶片，其具有一晶片主面及一晶片背面，該晶片主面 覆晶接合方式設置於該基板上； ' 一散熱片，設於該晶片背面之上； 一銲錫層，設於該散熱片與該晶片背面之間；以及 、，一非流動性底膠，其包含金屬顆粒或表面鍍有金屬之塑膠顆 粒:助焊劑（flux)以及底膠(underfill)，該非流動性底膠‘設 於該晶片背面與該銲錫層之間，用明強該W背面與該 層間之接著強度。 ' 2. 如申請專利範15第1項所述之具散紐置之半導體，盆 中該金屬顆粒係為奈米等級之金屬粉末。 八 3. 如申請專利範圍第2項所述之具散熱裝置之半導體元件，其 中該金屬係為由金、銀、錫或其混合物所組成之族群中選出。 4·?申請專利範圍第2項所述之具散熱裝置之轉 立 中該塑膠顆粒係為奈米等級之塑膠粉末。 八 5. t5請專利範圍第1項所述之具散熱裝置之半導體S件，並 中该助焊劑係為免洗助焊劑(no-ciean flux)。 ’、 6. =請專纖_丨項所述之具散熱裝置之半導立 中该非流動性底膠之助焊劑含量小於約2wt%。 ” 請專利範圍第1項所述之具散熱裝置之半導體元株，豆 该非流動性底耀之金屬顆粒含量為約40 wt%至約6〇二 P07006-TW ASE-1901 -15- 200903750 %。 & -種具散紐置之半導航件躲，其枝 (a) 將包含有麵職絲面财金屬之麵 日 及底膠的-非流祕底膠塗佈於 ：、彳助祥劍以 係以覆晶接合方式設置板上面’該晶片主面 (b) 將一銲錫層置於該非流動性底膠上; (c) 將一散熱片置於於該銲錫層上；以及 ⑷^行-轉频，使該祕紐轉 結，以固接該散熱片於該晶片背面。屬齡產生燒 “;申=利範圍第8項所述之具散熱 私，其中該金制_為奈料級之金屬粉末^導件1 10’如申请專利範圍第9項所述之具散熱 ^出其中該金屬係由金、銀、錫或其混;物所組 程’ J半導體元件製 13· 置之半導體元件製 製 14·如申請專利顧第8項所述之具散錄置之半導體元件 P07006-TW ASE-1901 -16- 200903750 程’其中該回焊步驟係為100-20(TC度之加熱過程。 15.範圍第8項所述之具散熱裝置之半導體元件製 私’其中該銲錫層的熔點係為1〇〇_2〇〇。匚。 種具散熱裝置之半導體元件製程，其方法步驟包括： a)將包έ有金屬顆粒或表面鑛有金屬之塑膠顆粒、助焊劑以 及底膠的一非流動性底膠塗佈於一晶片背面，該晶片主面 係以覆晶接合方式設置於一基板上； (b)將一表=配置有—銲錫層之散熱片置於該非流動性底膠 上’使彳于§亥鮮錫層係面向該非流動性底膠；以及 c進行一回焊步驟，使該非流動性底膠中的金屬顆粒產生燒 結，以固接該散熱片於該晶片背面。 17’$申請專利範圍第16項所述之具散絲置之半導體元件製 程’其中該金屬顆粒係為奈米等級之金屬粉末。 18’ =申請專·圍第Π項所述之具散絲置之半導體元件製 二，其中該金屬係由金、銀、錫或其混合物所組成之族群中 選出。 19·^申請專概®帛16顿述之錄絲置之半導體元件製 程’其中該塑膠顆粒係為奈米等級之塑膠粉末。 2〇·1申請專利範圍第16項所述之具散熱裝置之半導體元件製 程〃、中使该非流動性底膠塗佈方法係為喷佈（jetting)的方 法。 21’如申請專利範圍第16項所述之具散熱裝置之半導體元件製 P07006-TW ASE-1901 -17- 200903750 =其中㈣非流動性底雜佈方法係為_(printing)的 22.如申請專利範圍第16項所述之具散熱裝置之半導體元件 程，其中該回焊步驟係為1〇〇—2〇(rc度之加熱過程。 、 23.如申請專利範圍第16 私’其中該鲜錫層的炫 項所述之具散熱裝置之半導體元件製 點係為 100-20(TC。 P07006-TW ASE-1901200903750 X. Patent application scope: 1. A semiconductor component having a heat dissipating device, comprising: a substrate; a wafer having a main surface of the wafer and a back surface of the wafer, wherein the main surface of the wafer is laminated on the substrate; a heat sink disposed on the back surface of the wafer; a solder layer disposed between the heat sink and the back surface of the wafer; and, a non-flowing primer comprising metal particles or a metal plated surface Particles: Flux and underfill, the non-flowing primer is disposed between the back surface of the wafer and the solder layer, and is used to strengthen the bonding strength between the back surface of the W and the layer. 2. 2. For a semiconductor with a discrete center as described in the first paragraph of Patent No. 15, the metal particles in the basin are metal grades of nanometer grade. 8. A semiconductor component having a heat sink according to claim 2, wherein the metal is selected from the group consisting of gold, silver, tin or a mixture thereof. 4. The transfer of the heat sink as described in item 2 of the patent application scope is in the form of a nano-grade plastic powder. VIII 5. t5 The semiconductor S piece with heat sink according to item 1 of the patent scope, and the flux is no-ciean flux. The flux of the non-flowing primer is less than about 2% by weight. Please select the semiconductor element with heat sink as described in item 1 of the patent scope. The content of metal particles in the non-flowing base of the bean is about 40 wt% to about 6 〇 P07006-TW ASE-1901 -15- 200903750 % & - A half-navigation piece with a loose-branched set, the branch (a) will be coated with the surface of the face-faced silk metal and the bottom glue - non-flowing primer applied to: The sword is placed on the plate by flip-chip bonding. The main surface of the wafer (b) places a solder layer on the non-flowing primer; (c) placing a heat sink on the solder layer; and (4) Line-frequency shifting, the key is turned into a knot to fix the heat sink on the back of the wafer. The age is burned "the heat dissipation of the item mentioned in item 8 of the claim=li range", wherein the gold system is The metal powder of the material grade is controlled by a material as described in item 9 of the patent application scope, wherein the metal is made of gold, silver, tin or a mixture thereof; Manufacture of semiconductor components 14 as disclosed in claim 8 of the semiconductor component P07006-TW ASE-1901 -16- 20090375 0 process 'where the reflow step is 100-20 (the heating process of TC degree. 15. The semiconductor component of the heat dissipation device described in the item 8 of the scope) wherein the melting point of the solder layer is 1〇〇_ 2〇〇.匚. A semiconductor component process with a heat sink, the method steps include: a) coating a non-flowing primer coated with metal particles or metal particles with surface minerals, flux, and primer. Deployed on the back side of a wafer, the main surface of the wafer is placed on a substrate in a flip-chip bonding manner; (b) a heat sink disposed on the surface of the wafer is placed on the non-flowing primer. The fresh tin layer faces the non-flowing primer; and c performs a reflow step to sinter the metal particles in the non-flowing primer to fix the heat sink on the back side of the wafer. The semiconductor component process of the present invention is described in claim 17 wherein the metal particles are metal grades of nanometer grade. 18' = the semiconductor component of the fused wire according to the above-mentioned item, wherein the metal is selected from the group consisting of gold, silver, tin or a mixture thereof. 19·^Application for Specialization®帛16 The recording of the semiconductor component process of the recording wire. The plastic particle is a nano-grade plastic powder. The method for coating a semiconductor element having a heat sink according to item 16 of the patent application of claim 1 is a method of jetting the non-flowing primer. 21'The semiconductor component with heat sink device as described in claim 16 is P07006-TW ASE-1901 -17- 200903750 = where (4) the method of non-flowing bottom cloth is _ (printing) 22. If applying The semiconductor component process of the heat dissipating device described in claim 16 wherein the reflowing step is 1〇〇-2〇 (the heating process of rc degree. 23. If the patent application scope is 16th private) The semiconductor component of the solder layer of the tin layer is 100-20 (TC. P07006-TW ASE-1901).
TW097118962A 2007-07-12 2008-05-22 Semiconductor device having heat sink TWI370526B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW097118962A TWI370526B (en) 2007-07-12 2008-05-22 Semiconductor device having heat sink

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW96125459 2007-07-12
TW097118962A TWI370526B (en) 2007-07-12 2008-05-22 Semiconductor device having heat sink

Publications (2)

Publication Number Publication Date
TW200903750A true TW200903750A (en) 2009-01-16
TWI370526B TWI370526B (en) 2012-08-11

Family

ID=44722185

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097118962A TWI370526B (en) 2007-07-12 2008-05-22 Semiconductor device having heat sink

Country Status (1)

Country Link
TW (1) TWI370526B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9117792B2 (en) 2012-12-17 2015-08-25 Princo Middle East Fze Chip thermal dissipation structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9117792B2 (en) 2012-12-17 2015-08-25 Princo Middle East Fze Chip thermal dissipation structure
TWI508238B (en) * 2012-12-17 2015-11-11 Princo Corp Chip thermal system
US9362199B2 (en) 2012-12-17 2016-06-07 Princo Middle East Fze Chip thermal dissipation structure

Also Published As

Publication number Publication date
TWI370526B (en) 2012-08-11

Similar Documents

Publication Publication Date Title
JP4402717B2 (en) Flip chip mounting method and bump forming method using conductive particles
US7119432B2 (en) Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
JP4402716B2 (en) Flip chip mounting method and bump forming method using metal particle dispersion composition
TWI379364B (en) Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive
US6114413A (en) Thermally conducting materials and applications for microelectronic packaging
JP3329276B2 (en) Interconnect structure with conductive adhesive
US20050056365A1 (en) Thermal interface adhesive
WO2014046089A1 (en) Method for producing connection structure and anisotropic conductive adhesive
CN106129025B (en) Electronic device and method for manufacturing the same
TW201106434A (en) Method of manufacturing semiconductor device
US8569109B2 (en) Method for attaching a metal surface to a carrier, a method for attaching a chip to a chip carrier, a chip-packaging module and a packaging module
CN102482540A (en) Anisotropic conductive adhesive for ultrasonic bonding, and electronic component connection method using same
US11664302B2 (en) Integrated circuit module with a structurally balanced package using a bottom side interposer
US10943796B2 (en) Semiconductor device assembly having a thermal interface bond between a semiconductor die and a passive heat exchanger
CN103180079B (en) The manufacture method of solder transfer substrate, solder pre-coating method and solder transfer substrate
JP2019068046A (en) Thermally coupled package-on-package semiconductor
TW202123391A (en) Method for manufacturing electronic component device, and electronic component device
TW200903758A (en) Semiconductor device and method of manufacturing the same
US8183697B2 (en) Apparatus and methods of forming an interconnect between a workpiece and substrate
JP4129837B2 (en) Manufacturing method of mounting structure
TW202109688A (en) Method for manufacturing electronic component device and electronic component device
TW200903750A (en) Semiconductor device having heat sink
JP2012024834A (en) Solder material and method for preparing the same, and method for manufacturing semiconductor device using the same
US20040007780A1 (en) Particle-filled semiconductor attachment material
JP5864142B2 (en) Manufacturing method of heat conductive sheet