200900944 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種I合資料傳輸介面《系統與方法，特別 是，關於一種藉由整合多種傳輸協定於一傳輸界面以進行開 機、儲存及更新初體之技術領域。 【先前技術】 對於電腦或具運算能力的電子裝置而言，輸入/輸出 (input/output)係是一種具有多種不同功能單元的界面集合 (interface collection)，而透過此些界面集合 在雷腦 或具運算能力的電子裝置内的一中央處理單元能與相容於 界面規格的電子裝置（如記憶體）進行資料傳輸或通訊。而 這類型的中央處理單元在使用上，需於此處理晶片之外加 一程式記憶體，例如一電性可抹除式唯讀記憶體，每當微 控制器啟動(power on)時’把此電性可抹除式唯讀記憶體内 之勒體載入晶片内程式記憶體，以進行資料傳輸或通訊。 如第1圖所示’其繪示習知技藝之用以更新韌體之系 統之方塊圖。圖中’此系統100包含:一晶片内程式記憶體 (program memory) 1 (U、一韌體載入器（Firinware Loader) 102 及一外部裝置103。晶片内程式記憶體ιοί係用於儲存待 中央處理單元執行之程式。韌體載入器1〇2具有複數個介 面’至少包含一序列週邊介面（Serial Peripheral Interface， SPI) 1021、一積體電路間（inter-Integrated Circuit, I2C)介面 1022、及一通用串列匯流排（Universal-Serial-Bus，USB) 介面1023。這三個介面分別與韌體載入器所包含的一序列 5 200900944 週邊介面啟動裝置（SPI Boot) 1024、一積體電路間介面啟動 裝置(I2C Boot) 1025，以及一通用串列匯流排介面啟動裝 置1026 (USB Boot)連接，且一旦介面上連接一或多個外部 裝置103，例如於序列週邊介面1 〇21上連接一 spi快閃記 憶體（flash)1031或SPI電性可抹除式唯讀記憶體 (EEPROM)1031、於積體電路間介面1〇22上連接一 fc EEPR0M 1032，或於USB介面1023上連接個人電腦 (personal computer ’ PC) 1033，則三個介面啟動裝置丨〇24、 1025或1026將從相對應的快閃記憶體i〇31(spi EEPROM)、I C EEPROM 1032或個人電腦1〇33載入相應 之韌體。需要注意的是，因外部裝置1〇3包含各種支援^ 列週邊介面、積體電路間介面或通用串列匯流排介面之硬 體，因此，此韌體載入器1〇2還包含一仲裁器1〇27，係根 據由高至低優先權順序選擇性地在前些介面上 1031、1032或1033所儲存的韌體透過位址匯流排u及資 料匯流排12而載入晶片内程式記憶體1〇1，藉此完成更新 韌體的動作。 依前述所言，序列週邊介面·、積體電路間介面 1022’以及通用串列匯流排聰皆可供勃體更新之用。但 因為積體電路間介面1〇22非常普遍地被使用，若是積體電 路間介面1022被其他用途之積體電路間介面外部裝置所 佔滿，則將無法用來更職體，此時只能透過通用串列匯 流排介面1023或序列週邊介面聰來更新勃體，在使用 上變传缺乏彈性’同樣地’序列週邊介面1〇21或通用串列 匯流排1G23被使㈣，也會出現同樣地問題。因此依本文 6 200900944 所述’目前的傳輪介面無法同時兼固更新韌體之作動，在 使用上變得缺乏彈性。 因此’有必要提供一種整合上述各介面之系統及方法。 【發明内容】 因此本發明之主要目的在於提供一種藉由整合多種傳 輸協定於〜傳輸界面進行開機、儲存、更肋體之系統。 並且’-種整合f料傳輸介面之方法也被揭露’以彈性地 使用各個介面。 根據上述之目的，本發明係揭露一種整合資料傳輸介 面的^統’此系統包含:一微控制器、-資料傳輸單元及 -儲存媒體。微控制器内建一第一傳輸協定及一第二傳輸 協定。貧料傳輸單元，與微控制器連接 = 一傳輸協定之傳輪界面及一且第二匕=有八第 置’及資料傳輪裝置儲存，體7儲：媒C傳輸f 料傳輸單元，此儲存纟 、’係可連接資 -開機管理程式與1 ^福定’及儲存至少 -傳輸協定’經過資料傳輸單元對二 機管理程錢’再軸存制料人及執行開 微控制祕使用第二傳輸_ 仃存取，接著， 新。 得翰裝置進行韌體更 【實施方式】 从,旰脚粑时鏘曰前較佳的實施 是，本發明提供許多可適用的發明觀♦，“、、=應被理解的 體現於很寬廣多樣的特定且體背旦 而這些觀念能被 的實施例僅是㈣使財發日㈣特定^討論的特定具體 、、。稱，而且不會限制 7 200900944 本發明的範圍。 如第2圖所示，此圖為本發明之整合資料傳輪介面之 系統方塊圖。於圖中可知，此系統2包含一微控制器Μ、 一資料傳輸單元22及一儲存媒體23。此微控制器21内建 一第一傳輸協定211及一第二傳輸協定212，在第2圖中 第一傳輸協定211為SPI介面協定而一第二傳輪協定^2 為USB介面協定。資料傳輸單元22包含有一具第—傳輸 協定211之傳輸界面221及一具第二傳輸協定212之資^ 傳輸裝置222，且此資料傳輸裝置222儲存一物體。儲存 媒體23係連接資料傳輸單元22且此儲存媒體23内建第一 傳輸協定之傳輸機制，及用於儲存至少一開機管理程式 (Boot loader)及一應用資料。特別地，微控制器係為 CPU或8051單晶片處理器之其中一者，而儲存媒體為 型快閃記憶體、Nor型快閃記憶體或具識別資訊之記憶卡 其中之一者。及前述儲存媒體所包含的應用資料包含^一 核心映象、一應用程式及一内容。 而針對習知儲存開機管理程式之電子抹除式唯讀記憶 體無法拆離地裝設在傲入式系統上，由上述資料傳幹單元 與儲存媒體之間的連接模式，用於儲存開機管理程^及應 用資料之儲存媒體係可拆離地裝設在資料傳輸單元。需注 意地，於微控制器、資料傳輸單元及儲存媒體之第一=輸 協定皆係採用串列週邊介面（SPI)。 為人所熟知的，SPI是一種四線式的通訊介面，其使 用一主出從入(Master Out Slave In，M〇SI)、一主入從出 (Master In Slave 〇ut，MISO)、一串列時脈⑽灿⑶成， 200900944 SCK)等三線路進行資料傳輸，而從屬選擇線(slaveSelect， SS)則控制裝置的選擇。而前述第二傳輸協定係為通用串列 匯流排(USB) ’其因為通用串列匯流排係可支援Mic_ft 及Linux，因此能減少軟體開發的時間及過程。所以明顯 地，由上述提及的内文可知，微控制器内建有一 spi傳輸 協定及一 USB兩種傳輸協、資料傳輸單元内建有一 spi與 USB兩種傳輸協疋及儲存媒體内建有一 傳輸協定。 本系統以SPI與USB之傳輸特性，作為本發明之構思 說明。請參閱第3A圖所示，此圖為本發明之整合資料傳 輸介面之方法流程圖。此方法包含下列步驟： ^步驟31:提供内建一第一傳輸協定及一第二傳輸協 疋之一微控制器及内建一第一傳輸協定之一儲存媒體，且 倚存媒體儲存至少-開機管理程式及—應用㈣，如前述 所言：此第一傳輸協定與第二傳輸協定分別為§1>1傳輸協定 與USB傳輸協定； _步驟32:在微控制器與儲存媒體之間配置一具SPI傳 ，協定之傳輸界面及-具USB傳輸協^之資料傳輸裝置之 資料傳輸單元，且前述資料傳輸裝置儲存一韌體； 步驟33:於微控制器與資料傳輸單元之間形成一 spi 輸協S及-USB傳輪協定之溝通橋樑，及透過spi之傳 :，面使付微控制器經資料傳輸單元而載人儲存媒體之開 機管理程式；以及 π步驟34.將微控制器決定為一主工作模式及資料傳輸 早疋決定為一僕工作模式。 ”中作為主工作模式之微控制器再透過spl傳輸協定 9 200900944 之f通橋襟對儲存媒體之應用資料進行存取，接著，微控 制器透過USB傳輸協定之溝通橋樑對資料傳輸裝置所儲存 的韌體進行更新或覆寫（overwritten)。 而步驟33與步驟34間如以具識別資訊之記憶卡（如智 慧卡(Smartcard ’ SD)而言，此載入開機管理程式之部分資 3識別§己憶卡編號、加/解密或〗/〇等功能，同時，此 資料傳輸單元支援識別記憶卡功能，亦是一種驗證程序， 亦包含下列步驟：如第3B圖所示，承 步驟31:提供内建一第一傳輸協定及一第二傳輸協定 $-微控制器及内建—第—傳輸協定之_儲存媒體，且儲 :媒體儲存JL少—開機管理程式及__應用資料，如前述所 。.此第#輸協定與第二傳輪協定分別為spi傳輸協定與 USB傳輸協定； 〜步驟32:在微控制器與儲存媒體之間配置具spi傳輸協 疋之傳輸界面及一具USB傳輸協定之資料傳輸裝置之資料 傳輸單元，且此資料傳輸裝置儲存一韌體；200900944 IX. Description of the Invention: [Technical Field] The present invention relates to an I-in data transmission interface system and method, and more particularly to a system for booting, storing and updating by integrating multiple transmission protocols on a transmission interface The technical field of the initial body. [Prior Art] For a computer or an electronic device with computing power, an input/output is an interface collection having a plurality of different functional units, and the interface is collected in a thunderstorm or A central processing unit in a computing-capable electronic device can transmit or communicate data with an electronic device (such as a memory) that is compatible with interface specifications. In this type of central processing unit, a program memory, such as an electrically erasable read-only memory, is added to the processing chip, and this is done every time the microcontroller is powered on. Electrically erasable read-only memory is loaded into the on-chip program memory for data transfer or communication. As shown in Fig. 1, a block diagram of a conventional technique for updating a firmware is shown. In the figure, the system 100 includes: an in-chip program memory 1 (U, a firmware loader 102 and an external device 103. The in-chip program memory ιοί is used for storing The program executed by the central processing unit. The firmware loader 1 〇 2 has a plurality of interfaces 'containing at least one Serial Peripheral Interface (SPI) 1021 and an inter-integrated circuit (I2C) interface 1022 And a Universal-Serial-Bus (USB) interface 1023. These three interfaces respectively correspond to a sequence of 5 200900944 peripheral interface boot devices (SPI Boot) 1024, which are included in the firmware loader. An inter-device interface activation device (I2C Boot) 1025, and a universal serial bus interface activation device 1026 (USB Boot) connection, and once the interface is connected to one or more external devices 103, for example, a sequence peripheral interface 1 〇 21 Connect a spi flash memory (flash) 1031 or SPI electrical erasable read-only memory (EEPROM) 1031, connect an fc EEPR0M 1032 to the integrated circuit interface 1〇22, or connect to the USB interface. On the 1023, connect the personal computer 'PC' 1033, then the three interface boot devices 丨〇24, 1025 or 1026 will be from the corresponding flash memory i〇31 (spi EEPROM), IC EEPROM 1032 or PC 1 〇33 loads the corresponding firmware. It should be noted that the external device 1〇3 includes various hardware supporting the peripheral interface of the column, the interface between the integrated circuits, or the hardware of the universal serial bus interface. Therefore, the firmware is loaded. The input device 1〇2 further includes an arbiter 1〇27, which is based on the firmware stored in the previous interface 1031, 1032 or 1033 in a high-to-low priority order, through the address bus and the data sink. Row 12 is loaded into the in-chip program memory 1〇1, thereby completing the operation of updating the firmware. As described above, the serial peripheral interface, the integrated circuit interface 1022', and the universal serial bus are all available. It is used for the renewal of the body. However, since the integrated circuit interface 1〇22 is very commonly used, if the integrated circuit interface 1022 is occupied by the external device of the integrated circuit of other uses, it will not be used. The body, at this time can only pass through The serial bus interface 1023 or the serial interface of the sequence is used to update the Bodhi body. In use, the transmission is inelastic. 'Similarly' the sequence peripheral interface 1〇21 or the universal serial bus 1G23 is used (4), and the same problem occurs. . Therefore, according to the current 2009 200900944, the current transmission interface cannot simultaneously fix the firmware and become inelastic in use. Therefore, it is necessary to provide a system and method for integrating the above interfaces. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a system for booting, storing, and ribbing at a transport interface by integrating multiple transport protocols. And the method of integrating the f material transmission interface has also been disclosed to flexibly use the various interfaces. In accordance with the above objects, the present invention discloses an integrated data transmission interface. The system includes a microcontroller, a data transmission unit, and a storage medium. The microcontroller has a first transmission protocol and a second transmission protocol built in. Poor material transmission unit, connected with the microcontroller = one transmission agreement of the transmission wheel interface and one and the second 匕 = there are eight sets ' and the data transfer device storage, body 7 storage: medium C transmission f material transmission unit, this Storage 纟, 'system can be connected to the power-up management program and 1 ^ Fuding' and store at least - transmission agreement 'via the data transmission unit to the second machine management process money 're-arrangement of the producer and the implementation of the micro-control secret use Two transfers _ 仃 access, then, new. Determining the firmware for the device. [Embodiment] The preferred implementation of the device is that the invention provides a number of applicable inventions. ♦ “, , = should be understood to be broad and diverse. The specific and in-vivo embodiments of these concepts can only be used to make the specific date of the discussion on the financial day (4) specific, and not to limit the scope of the present invention as shown in Figure 2. This figure is a system block diagram of the integrated data transfer interface of the present invention. It can be seen that the system 2 includes a microcontroller, a data transmission unit 22 and a storage medium 23. The microcontroller 21 is built in. a first transmission protocol 211 and a second transmission protocol 212. In the second figure, the first transmission protocol 211 is an SPI interface protocol and the second transmission protocol ^2 is a USB interface protocol. The data transmission unit 22 includes a - a transmission interface 221 of the transmission protocol 211 and a transmission device 222 of the second transmission protocol 212, and the data transmission device 222 stores an object. The storage medium 23 is connected to the data transmission unit 22 and the storage medium 23 is built in Transmission protocol The transmission mechanism is used for storing at least one boot loader and an application data. In particular, the microcontroller is one of a CPU or an 8051 single-chip processor, and the storage medium is a type of flash memory. One of the body, the Nor type flash memory or the memory card with identification information, and the application data contained in the storage medium includes a core image, an application and a content. The program's electronic erasing type of read-only memory can not be detached and installed on the proud system. The connection mode between the data dissemination unit and the storage medium is used to store the boot management process and the storage of application data. The media is detachably installed in the data transmission unit. It should be noted that the first = transmission protocol for the microcontroller, data transmission unit and storage medium is based on the serial peripheral interface (SPI). SPI is a four-wire communication interface that uses a Master Out Slave In (M〇SI), a Master In Slave 〇ut (MISO), and a series of clocks (10). Can (3) into, 2 00900944 SCK) and other three lines for data transmission, while the slave select line (slaveSelect, SS) controls the selection of the device. The second transmission protocol is a universal serial bus (USB) 'because of the universal serial bus system Mic_ft and Linux can be supported, so the time and process of software development can be reduced. Obviously, from the above mentioned text, the microcontroller has a spi transmission protocol and a USB transmission protocol and data transmission unit. There is a SG and USB transmission protocol and a built-in transmission protocol for the storage medium. This system uses the transmission characteristics of SPI and USB as the concept description of the present invention. Please refer to FIG. 3A, which is a flow chart of the method for integrating the data transmission interface of the present invention. The method comprises the following steps: Step 31: providing a built-in first transmission protocol and a second transmission protocol, one of the microcontrollers and one of the first transmission protocols, and relying on the media storage at least - Boot-up management program and application (4), as mentioned above: this first transport protocol and the second transport protocol are respectively §1>1 transport protocol and USB transport protocol; _step 32: Configuring between the microcontroller and the storage medium An SPI transmission, a protocol transmission interface and a data transmission unit having a data transmission device of the USB transmission protocol, and the data transmission device stores a firmware; Step 33: forming a firmware between the microcontroller and the data transmission unit The communication bridge between the spi transmission association S and the USB transmission agreement, and the transmission through the spi: the boot management program that carries the microcontroller to the storage medium via the data transmission unit; and π step 34. The microcontroller Decided to decide on a main working mode and data transmission as a servant working mode. The microcontroller as the main working mode accesses the application data of the storage medium through the sp-transport protocol 9 200900944, and then the microcontroller stores the data transmission device through the communication bridge of the USB transmission protocol. The firmware is updated or overwritten. And between step 33 and step 34, if the memory card with identification information (such as smart card 'SD), this part of the boot management program is recognized 3 § Recalling the card number, encryption/decryption or 〗/〇 functions. At the same time, this data transmission unit supports the identification of the memory card function. It is also a verification procedure. It also includes the following steps: as shown in Figure 3B, proceed to step 31: Providing a built-in first transfer protocol and a second transfer protocol $-microcontroller and a built-in-transport agreement_storage medium, and storing: less media storage JL - boot management program and __ application data, such as In the foregoing, the first and second transmission protocols are respectively a spi transmission protocol and a USB transmission protocol; and step 32: configuring a transmission interface with a spi transmission protocol between the microcontroller and the storage medium; a data transmission unit of a USB transmission protocol data transmission device, and the data transmission device stores a firmware;
' 步驟33:於微控制器與資料傳輸單元之間形成一 SPI 傳輸協疋及一 USB傳輸協定之溝通橋樑，及透過SpI之傳 輸界面使得微控制器經資料傳輸單元而載入儲存媒體之開 機管理程式，其中此在資料傳輸單元傳輸過程中處於加密 (encrypt)狀態，而當微處理器載入儲存媒體之開機管理程 式之第一部分，且前述第一部分包含驗證(authentication) 及解密（decryption)的功能； 步驟33L當載入儲存媒體之開機管理程式完畢後，對 開機載入器程式進行解密以產生一驗證密碼； 10 200900944 姑㈣對㈣，料定是否開 放存取權，如驗證成功後，再進行繼續载入 機管理程式之m以完載人_^程^之體1 一 =34:將微控制器妓為-主工作鐵式及資料傳輸 早兀決疋為一僕工作模式。 作為主工作模式之微控制器再次使肖SPI傳㈣$， 經過資料傳輸單元而自儲存媒體載入及^于包含核心映 象'應用程式及内容之u資料’之後’微控制器透過 USB傳輪協定之溝通橋樑對資料傳輸裝置所儲存的勃體進 行更新或覆寫。 由上述内容可知’而如嵌入式系統採用s;pi傳輸協定 有多種好處’除了比起I2c '兩蕊介面、蕊介面傳輸協 定可達到更快的傳輸速度外，如以-喪人式系統A内的微 控制器以SPI傳輸協定而與另一嵌入式系統b内的一微控 制器串接(cascade)。如第4圖所示’此圖為兩微控制器一 串接之圖示。 ° 明顯地’具識別資訊之記憶卡44如安全數位記慎卡 (secure digital card，SD card)、一 多媒體記憶卡（multimedia card，MMC card)、一聰明媒體卡（smart media card，SM card) 至少儲存嵌入式系統A之一開機管理程式及一應用資料與 嵌入式系統B之一開機管理程式及一應用資料，且此記憶 卡44内建一 SPI傳輸協定。 於兩嵌入式系統開機時，於嵌入式系統A之微控制器 41透過資料傳輸單元42自記憶卡44載入相應之開機管理 程式及其應用資料後，嵌入式系統A之微控制器41可作 11 200900944 為嵌入式系統B之一資料傳輸單元，接著，嵌入式系統B 之微控制器43透過資料傳輸單元之SPI傳輸協定（嵌入式 系統A之微控制器）載入相應之開機管理程式及其應用資 料。 最後，本系統之微控制器並不局限SPI傳輸協定及 USB傳輸協定這兩種傳輸協定，請參照第5圖，此圖為微 控制器之另一介面之示意圖。由圖中可知，此系統之微控 制器5更包含一 LAN傳輸界面51，以支援線上燒錄 (In-System-Programming，ISP)功用。 再者，當資料傳輸單與微控制器之間同時藉由SPI傳 輸協定及USB傳輸協定進行資料傳輸時，則存有優先權的 問題，所以針對此問題，如第6圖所示，此資料傳輸單元 6更包含一仲裁器61 (arbitrator)用以決定具SPI傳輸協定之 傳輸界面62與具USB傳輸協定之資料傳輸裝置63間傳輸 控制權的歸屬，所以於資料傳輸單6與微控制器之間同時 進行資料傳輸時不會有資料衝突的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係為習知更新微控制器韌體之系統方塊圖； 12 200900944 第2圖係為本發明之整合資料傳輸介面的之系統之方 塊不意圖， 第3A圖及第3B圖係為本發明之整合資料傳輸介面的 之方法流程圖； 第4圖係為微控制器係透過序列週邊介面而與另一微 控制器串接(cascade)之示意圖； 第5圖係為微控制器之另一介面之示意圖；以及 第6圖係為資料傳輸單元之示意圖。 【主要元件符號說明】 100:系統； 101:晶片内程式記憶體； 102:韌體載入器； 1021:序列週邊介面； 1022:積體電路間介面； 1023:通用串列匯流排； 1024:序列週邊介面啟動裝置； 1025:積體電路間介面啟動裝置； 1026:通用串列匯流排介面啟動裝置； 1027滑裁器； 103:外部裝置； 1031 :SPI快閃記憶體； 1032: I2C電性可抹除式唯讀記憶體； 1033:個人電腦； 11:位址匯流排； 13 200900944 12:資料匯流排； 2:系統； 21:微控制器； 211:第一傳輸協定； 212:第二傳輸協定； 22··資料傳輸單元； 221:傳輸界面； 222:資料傳輸裝置； 23:儲存媒體； 31〜34:步驟； 4:整合資料傳輸介面之系統； 41:微控制器； 42:資料傳輸單元； 43:微控制器； 44:記憶卡； 5·.微控制器； 51丄AN傳輸界面； 6:資料傳輸單元； 61:仲裁器； 62:傳輸界面； 63:資料傳輸裝置； A:嵌入式系統；以及 B:嵌入式系統。 14Step 33: Form a communication bridge between the SPI transmission protocol and a USB transmission protocol between the microcontroller and the data transmission unit, and enable the microcontroller to load the storage medium through the data transmission unit through the transmission interface of the SpI. a management program, wherein the data transfer unit is in an encrypted state, and when the microprocessor loads the first part of the boot media management program, and the first part includes authentication and decryption. The function of step 33L is to decrypt the boot loader program to generate a verification password after the boot management program of the storage medium is completed; 10 200900944 (4) Yes (4), whether the open access is determined, if the verification is successful, Then continue to load the machine management program m to complete the manned _ ^ Cheng ^ body 1 = 34: the microcontroller is reduced to - the main working iron type and data transmission is a servant mode. The microcontroller as the main working mode again transmits the Xiao SPI (4)$, after loading from the storage medium through the data transfer unit and after the core image 'application and content u' is transmitted, the microcontroller transmits via USB. The communication bridge of the round agreement updates or overwrites the body stored in the data transmission device. It can be seen from the above that 'as for embedded systems using s; pi transmission protocol has many advantages' except that compared to I2c's two interfaces, the core interface transmission protocol can achieve faster transmission speed, such as - mourning system A The internal microcontroller is cascaded with a microcontroller within another embedded system b in an SPI transport protocol. As shown in Figure 4, this figure is a diagram of a series connection of two microcontrollers. ° Clearly, the memory card 44 with identification information such as a secure digital card (SD card), a multimedia card (MMC card), a smart media card (SM card) At least one of the booting system A and one of the application data and the embedded system B boot management program and an application data are stored, and the memory card 44 has an SPI transmission protocol built therein. When the two embedded systems are powered on, the microcontroller 41 of the embedded system A can be loaded into the corresponding boot management program and its application data from the memory card 44 through the data transfer unit 42. 11 200900944 is a data transmission unit of embedded system B. Then, the microcontroller 43 of the embedded system B loads the corresponding boot management program through the SPI transmission protocol of the data transmission unit (the microcontroller of the embedded system A). And its application materials. Finally, the microcontroller of this system does not limit the two transmission protocols of SPI transmission protocol and USB transmission protocol. Please refer to Figure 5, which is a schematic diagram of another interface of the microcontroller. As can be seen from the figure, the micro controller 5 of the system further includes a LAN transmission interface 51 to support the In-System-Programming (ISP) function. Furthermore, when data transmission between the data transmission sheet and the microcontroller is simultaneously performed by the SPI transmission protocol and the USB transmission protocol, there is a problem of priority. Therefore, as shown in FIG. 6, this data is as shown in FIG. The transmission unit 6 further includes an arbitrator 61 for determining the ownership of the transmission control between the transmission interface 62 having the SPI transmission protocol and the data transmission device 63 having the USB transmission protocol, so that the data transmission unit 6 and the microcontroller There will be no data conflicts when transferring data at the same time. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional system for updating a firmware of a microcontroller; 12 200900944 FIG. 2 is a block diagram of a system for integrating data transmission interfaces of the present invention, FIG. 3A and 3B is a flow chart of a method for integrating data transmission interface of the present invention; FIG. 4 is a schematic diagram of a microcontroller connecting to another microcontroller through a sequence peripheral interface; A schematic diagram of another interface of the microcontroller; and Figure 6 is a schematic diagram of the data transmission unit. [Major component symbol description] 100: System; 101: In-chip program memory; 102: Firmware loader; 1021: Sequence peripheral interface; 1022: Integrated circuit interface; 1023: Universal serial bus; 1024: Sequence peripheral interface activation device; 1025: integrated inter-system interface activation device; 1026: universal serial bus interface interface activation device; 1027 slider; 103: external device; 1031: SPI flash memory; 1032: I2C electrical Erasable read-only memory; 1033: personal computer; 11: address bus; 13 200900944 12: data bus; 2: system; 21: microcontroller; 211: first transfer protocol; 212: second Transmission protocol; 22··data transmission unit; 221: transmission interface; 222: data transmission device; 23: storage medium; 31~34: steps; 4: system for integrating data transmission interface; 41: microcontroller; Transmission unit; 43: Microcontroller; 44: Memory card; 5. Microcontroller; 51丄AN transmission interface; 6: Data transmission unit; 61: Arbiter; 62: Transmission interface; 63: Data transmission device; : embedded systems; and B: embedded systems. 14