200849825200849825
三達編號：TW3716PA 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種注入鎖定除三除頻器 (Divide-by-Three Injection-Locked Frequency Divider)，且 特別是有關於一種適合低電壓操作與高注入鎖定範圍之 注入鎖定除三除頻器。 【先前技術】 隨著通訊產業的發達，高頻鎖相迴路（Phase Lock Loop，PLL)已經廣泛地應用在各種有線與無線通訊系統 中，如頻率合成器或時脈產生器。在高頻鎖相迴路中，高 頻除頻器（Frequency Divider)為不可或缺之重要元件之 一，其用以接收原始訊號並經由對原始訊號之頻率除以一 個或多個不同之數值來降低其之頻率。 注入鎖定除三除頻器（Divide-by-Three Injection Locked Frequency Divider)為一種目前常用之高頻除頻器 架構，其結合訊號注入單元與壓控振蘯器(v〇ltage Controlled Oscillator)，如電感電容槽共振腔(LC Tank)振盪 态來對訊號注入單元接收之注入訊號進行除三頻。然而傳 統注入鎖定除三除頻器均需使用較高的電源電壓始可動 作，因此如何設計出可應用於低電壓操作的注入鎖定除三 除頻器，以彈性地應用於各種不同場合乃業界不斷致力的 方向之一0 200849825达达编号号: TW3716PA IX. Description of the Invention: [Technical Field] The present invention relates to a Divide-by-Three Injection-Locked Frequency Divider, and particularly relates to a suitable Low voltage operation and high injection locking range injection locking in addition to the three frequency divider. [Prior Art] With the development of the communication industry, a high-frequency phase-locked loop (PLL) has been widely used in various wired and wireless communication systems, such as a frequency synthesizer or a clock generator. In the high frequency phase-locked loop, the Frequency Divider is one of the indispensable important components for receiving the original signal and reducing it by dividing the frequency of the original signal by one or more different values. The frequency. Divide-by-Three Injection Locked Frequency Divider is a commonly used high frequency frequency divider architecture, which combines a signal injection unit with a voltage controlled oscillator (V〇ltage Controlled Oscillator). The LC Tank oscillating state is used to divide the injection signal received by the signal injection unit by three frequencies. However, the traditional injection locking except the three frequency dividers need to use a higher power supply voltage to operate. Therefore, how to design an injection-locking divide-by-three frequency divider that can be applied to low-voltage operation is used in various industries. One of the constant direction of the effort 0 200849825
二達編號：TW3716PA 【發明内容】 本發明係有關於一種注入鎖定除三除頻器 (Divide-by，Three Injection-Locked Frequency Divider)。本 發明之注入鎖定除三除頻器可應用於低電壓操作，並具有 低電功率消耗的功效，利於應用在無限通訊系統中。 率。第一與第二電晶體之第二端係透過第一與第 根據本發明（之第一方面），提出一種注入鎖定除三 除頻器’包括一弟一訊號源注入電路與一第二訊號源注入 電路與一振盪器。第一與第二訊號源注入電路用以分別輸 出一弟一注入訊说與一第二注入訊號。振盡器包括一第一 電晶體與一第二電晶體、一電感電容共振腔電路（Lc Tank)、一第一電感與一第二電感。第一與第二注入訊號 係分別注入至第一與第二電晶體之至少一端。電感電容 振腔電路係跨接於第一與第二電晶體之第一端與控制 之間，以作為第一與該第二電晶體之正迴授電路。電六命 感共振腔電路係決定振盪器之一振盪訊號之一共振頻4 & 電感耦 接至接地端，以實質上保留振盪訊號之二次|皆波訊號 中，第一與第二注入訊號和被保留下來之振盪訊鱿的"二其 言皆波訊號係透過第一與第二電晶體進行混波，以於第 人 第二電晶體之第一端端輸出一組差動對訊號。差動對與 之頻率等於一除頻頻率。除頻頻率實質上為第一為第成銳 入訊號的頻率的三分之一。 、〜生 為讓本發明之上述内容能更明顯易懂，下文特汽 佳實施例，並配合所附圖式，作詳細說明如下： 較 7 200849825达达编号: TW3716PA [Summary of the Invention] The present invention relates to a Divide-by (Three Injection-Locked Frequency Divider). The injection-locking divide-by-three frequency divider of the present invention can be applied to low-voltage operation and has the effect of low electric power consumption, which is advantageous for application in an infinite communication system. rate. The second end of the first and second transistors are transmitted through the first and the second aspect according to the invention (the first aspect), and an injection-locked divide-by-three frequency divider is provided, including a first-channel source injection circuit and a second signal. The source injection circuit is coupled to an oscillator. The first and second signal source injection circuits are configured to respectively output a first-injection and a second injection signal. The oscillating device includes a first transistor and a second transistor, a capacitor cavity circuit (Lc Tank), a first inductor and a second inductor. The first and second injection signals are respectively injected into at least one end of the first and second transistors. The inductor-capacitor cavity circuit is connected between the first end of the first and second transistors and the control to serve as a positive feedback circuit for the first and second transistors. The electric six-sensor resonant cavity circuit determines one of the oscillation signals of one of the oscillators. The resonant frequency is coupled to the ground to substantially retain the second of the oscillation signal. The first and second injections are The signal and the oscillating signal that is retained are both mixed by the first and second transistors to output a set of differential pairs at the first end of the second transistor of the first person. Signal. The differential pair and its frequency are equal to a divide frequency. The frequency of the frequency division is substantially one third of the frequency of the first sharp input signal. In order to make the above contents of the present invention more obvious and easy to understand, the following examples of the special steam, together with the drawings, are described in detail as follows: 7 200849825
三達編號：TW3716PA ^ 【實施方式】 弟1圖繪不本發明實施例之注入鎖定除三除頻哭、 (Divide-by-Three Injection-Locked Frequency Divider)之電 路圖。請參考第1圖。注入鎖定除三除頻器100包括振蘯 器110、訊號注入源電路120與130。振盡器ho包括電 晶體111與112、電感電容共振腔電路（lc Tank) 113、 電感114與115 〇 電感電容共振腔電路113係跨接於電晶體U1與ι12 之汲極與閘極之間，以作為電晶體111與112的正迴授電 路。電容電感共振腔電路113係決定振盪器ho之一振盈 號之一共振頻率f〇 〇 電晶體111與112的源極分別透過電感114與115箱 接至接地端，如此耦接方式係使得此振盪訊號之二次諧波 訊號被保留下來。此二次諧波訊號之頻率即為振盪訊號的 共振頻率的兩倍2f〇。 訊號注入源電路120與130分別輸出注入訊號vil與 Vi2至電晶體hi與η]之没極、源極、閘極或基極的至 少一端。在本發明實施例中，訊號源注入電路12〇與130 係以分別輸出注入訊號Vil與Vi2至電晶體ill與112之 没極為例。注入訊號Vil與Vi2分別透過電晶體ill和 112 ’與此二次諧波訊號進行混波，分別於電晶體nl與 112的没極輸出差動對訊號V〇l與Vo2。差動對訊號Vol 與Vo2之頻率係等於一除頻頻率fd。 當注入訊號Vil與Vi2之頻率約為振盪器110的共振 200849825 三達編號：TW3716PA 頻率的三倍時，亦即當注入訊號Vil與Vi2之頻率於、主 1〇〇 注入鎖定除二除頻器1〇〇即可對注入訊號Vil與Vi2進行 除三頻。注入鎖定除三除頻器100即於電晶體^與1 = 的>及極輸出除頻頻率為注入訊號VU與Vu夕、 以（頻率的三分 之一的差動對訊號V〇 1與V〇2。Sanda number: TW3716PA ^ [Embodiment] Figure 1 depicts a circuit diagram of the Divide-by-Three Injection-Locked Frequency Divider in the embodiment of the present invention. Please refer to Figure 1. The injection lock divide-by-three frequency divider 100 includes a vibrator 110 and signal injection source circuits 120 and 130. The vibrator ho includes transistors 111 and 112, an OLED capacitor 113 (lc Tank) 113, and inductors 114 and 115. The inductor-capacitor cavity circuit 113 is connected across the drains and gates of the transistors U1 and ι12. As a positive feedback circuit for the transistors 111 and 112. The capacitive inductive cavity circuit 113 determines one of the oscillators ho, one of the resonant frequencies, and the sources of the transistors 111 and 112 are respectively connected to the ground through the inductors 114 and 115, so that the coupling is such that The second harmonic signal of the oscillating signal is preserved. The frequency of this second harmonic signal is twice the resonance frequency of the oscillation signal 2f〇. The signal injection source circuits 120 and 130 respectively output the injection signals vil and Vi2 to at least one of the terminals, the source, the gate or the base of the transistors hi and η]. In the embodiment of the present invention, the signal source injection circuits 12A and 130 are respectively outputting the injection signals Vil and Vi2 to the transistors ill and 112, respectively. The injection signals Vil and Vi2 are mixed with the second harmonic signal through the transistors ill and 112', respectively, and differentially output signals V〇1 and Vo2 at the non-polar outputs of the transistors n1 and 112, respectively. The frequency of the differential pair signals Vol and Vo2 is equal to a frequency dividing frequency fd. When the frequency of the injection signals Vil and Vi2 is about the resonance of the oscillator 110 200849825 three times the frequency of the TW3716PA, that is, when the frequency of the injection signals Vil and Vi2 is at the main 1 〇〇 injection lock divided by the two frequency divider The injection signal Vil and Vi2 can be divided by three frequencies. The injection lock is divided by the three frequency dividers 100, ie, the transistor ^ and 1 = > and the polar output frequency is the injection signal VU and Vu, (the frequency is one-third of the differential pair signal V〇1 and V〇2.
由於電晶體111與112之源極係透過電感114與⑴ 耦接至接地端，而未與其他電晶體疊接， 二 咖1 *1 η ,认i U电曰日體丄i i 一 12僅感低電源電壓即可動作。注入鎖定除三除頻器wo 可操作在低電壓，並達成低功率消耗之功效。一本發^實施 例之注入鎖定除三除頻器可應用於低電壓操作的通訊系 統，例如是802· lla/b/g的通訊協定上。 茲說明本發明實施例之注入鎖定除三除頻器ι〇〇之 振盪器lio。在本發明實施例中，電感電容共振腔電路ιι3 係包括電感116與117、電容電路140，決定振盪器11〇 的振盪訊號的共振頻率f〇。電感116耦接於電晶體HI的 汲極與電源電壓Vdd之間，而電感in耦接於電晶體112 的汲極與電源電壓vdd之間。電容電路耦接於電晶體ln 〜112的閘極之間。在本發明實施例中，電容電路HQ可 較佳地包括可變電容Hi與142，依據一可調電壓vtune 改變其電容值，以決定共振頻率f0。如此可增加本發明實 施例之注入鎖定除三除頻器100之注入鎖定除頻範圍。 在本發明實施例中，電晶體丨11與112係較佳地以交 互耦合（Cross_couple)的方式耦接，亦即，電晶體”叉 9 200849825 三達編號：TW3716PA 的間極搞接電晶體112的沒極，而電晶體⑴的開 電晶體111較極。交互麵合的電晶體⑴與112係 等效負電阻來抵銷電感電容共振腔電路113中之電/、 耗’使—振堡器11G具有較理想之共振與㈣輸出操作二 餘况明訊號源注入電路12〇、13〇之内部電路。訊 源注入電路120與〗3〇分別包括電晶體121與⑶。 發明實施例中，電晶體⑵與131的汲 與出的沒極轉接。電晶Lu 地端。電晶體m與131之閘極分別1 原桎均⑽妾至接 與AC2,據以分別注入訊號yil鱼Vi2 /主入訊號源AC1 之汲極。由於電晶體lu與12;、、112鱼電晶體111與112 聯方式趣接至接地端，而非彼此。、131係分別以ϋ 例^注入鎖定除三除頻器僅需低電源=，本發明實施 除三頻。因此，本發明實施例之注入鎖jdd，即可進行 成低功率消耗的功效。 毛除二除頻器町遠 在本發明實施例中，注入訊號源 注入訊號源，注入訊請㈣係為差=係為姜動 /主入鎖定除三除頻器100更包 /入訊號。 f別對差動對錢_vg2進行緩咖與甽 號V〇l與ν〇2發生負載效應。緩衝電路，免差動對A 輸出經緩衝差動對訊號Vobl與Vob2。 、16〇係據以 在本發明實施例中，電晶體111、119 以N型金屬氧化半導體電晶體（咖$ 12^與131 # 並不限於此’亦可用P型金屬氧化半導體畲，實際應用^ 電晶體（PM〇S) 200849825 三達編號：TW3716PA 來替代。 體in與112之及極，而電晶體⑵斑 电曰曰 接地端為例，以將注入訊號Vil與Vi2、注入至電、^接至 際應用上，訊號源注 私日日體。實Since the sources of the transistors 111 and 112 are coupled to the ground through the inductors 114 and (1), but not overlapped with other transistors, the two are 1 * 1 η, and the i U 曰 丄 ii ii The low supply voltage can be operated. Injection Locking In addition to the three frequency dividers, it can operate at low voltages and achieve low power consumption. An injection lock-inhibition divide-by-three frequency divider of an embodiment can be applied to a communication system with low voltage operation, such as a communication protocol of 802·11a/b/g. The oscillator lio of the injection-locking divide-by-three-divider ι is described in the embodiment of the present invention. In the embodiment of the present invention, the inductor-capacitor resonant cavity circuit ιι3 includes inductors 116 and 117 and a capacitor circuit 140 for determining the resonant frequency f〇 of the oscillator signal of the oscillator 11〇. The inductor 116 is coupled between the drain of the transistor HI and the power supply voltage Vdd, and the inductor is coupled between the drain of the transistor 112 and the power supply voltage vdd. The capacitor circuit is coupled between the gates of the transistors ln ～112. In the embodiment of the present invention, the capacitor circuit HQ may preferably include variable capacitors Hi and 142, and the capacitance value thereof is changed according to an adjustable voltage vtune to determine the resonance frequency f0. This can increase the injection-locked frequency division range of the injection-locking divide-by-three frequency divider 100 of the embodiment of the present invention. In the embodiment of the present invention, the transistors 丨11 and 112 are preferably coupled in a cross-coupled manner, that is, the transistor "fork 9 200849825 达达号: TW3716PA inter-pole contact transistor 112 The eccentricity of the transistor (1) is relatively high. The inter-faceted transistors (1) and 112 are equivalent negative resistances to offset the electricity/consumption in the inductor-capacitor cavity circuit 113. The device 11G has a better resonance and (4) an output operation, and an internal circuit of the signal source injection circuits 12A and 13A. The source injection circuit 120 and the frame 3 include the transistors 121 and (3), respectively. The transistor (2) and the 没 and 没 of the transistor are transferred. The gate of the transistor is the ground. The gates of the transistors m and 131 are respectively 1 (10) 妾 to AC2, respectively, according to the signal yil fish Vi2 / The main input signal source is the drain of the source AC1. Since the transistor lu and the 12;, 112 fish crystals 111 and 112 are connected to the ground, not to each other, the 131 series are respectively injected into the lock and divided by three. The frequency converter only needs low power supply =, the present invention implements the third frequency. Therefore, the embodiment of the present invention In the case of the lock jdd, the power consumption can be reduced. In the embodiment of the present invention, the signal source is injected into the signal source, and the injection message is sent (4) is the difference = the system is the ginger/main In addition to the three frequency divider 100, the package/input signal is added. fDo not carry the load effect on the differential _vg2 and the nickname V〇l and ν〇2. The buffer circuit is free of differential pair A output. The differential signal pair Vobl and Vob2 are buffered. In the embodiment of the present invention, the transistors 111 and 119 are oxidized by the N-type metal oxide semiconductor transistor (the coffee is not limited to this). P-type metal oxide semiconductor germanium, practical application ^ transistor (PM〇S) 200849825 Sanda number: TW3716PA to replace. Body in and 112 and the transistor (2) spot power ground as an example, to be injected Signals Vil and Vi2, injected into electricity, connected to the application, the source of the signal is private.
的没極可以將12以13Q㈣g121與W 晶體m與112的^11與Vi2注入至振盈器㈣的電 可分別減至電:體=‘二，體121與131的源极亦 115輕接至接地蠕發明^源極，透過電感114與 ⑽中，只要訊，Π 例之注入鎖定除三除頻器 no的電晶體⑴:、互=Γ2°的電晶體121與振還器 s沪1卩1彻不相宜接，訊號源注入電路130的雷 曰曰體131與振盪器的電晶體i 亩：電 或透過域錢料接至接地端^相⑼’均直接轉接 恭4 例令’電感電容共振腔電路113係以包括 二=、可變電容141與"2為例’電感電容: 包括電感216與.可變電容如與 容共=:=用：4，任__ 器，均作為本 第2^會示本發明另一實施例之注入鎖定除三除頻 之产#之私路圖/主入鎖定除三除頻器2G0與100的不同 電曰體主入鎖疋除二除頻11咖之振盈器210除了包括 電曰曰體211與212、電感電容共振腔電路213、電感214 200849825The immersive can be used to inject 12 to 13Q (four) g121 and W crystals m and 112 ^11 and Vi2 into the vibrator (four) can be reduced to electricity: body = 'two, the source of the body 121 and 131 is also lightly connected to Grounding creep invention ^ source, through the inductor 114 and (10), as long as the signal, the injection of the transistor except the three frequency divider no (1):, the transistor 121 and the vibrator s Shanghai 1卩1 is not suitable, the signal source injection circuit 130 of the Thunder body 131 and the oscillator of the transistor i mu: electricity or through the domain money to the ground terminal ^ phase (9) 'all directly forward Christine 4 order 'inductance The capacitor resonant cavity circuit 113 is composed of two =, variable capacitors 141 and " 2 as an example of 'inductance and capacitance: including the inductance 216 and the variable capacitance, such as the total capacitance =: = with: 4, any __ device, both as The second embodiment of the present invention shows the injection locking in addition to the three-divided frequency production of the private road map / master lock in addition to the three frequency dividers 2G0 and 100 of the different electric body master locks in addition to the second division The frequency oscillator 210 includes an electric body 211 and 212, an inductor-capacitor resonant cavity circuit 213, and an inductor 214 200849825.
三達編號：TW3716PA 與215以外，更包括電容216與217。電容216與217分 別和電感214與215並聯。訊號源注入電路220與230内 之電晶體221與231之源極係分別耦接至電晶體211與212 之汲極。電晶體221與231之汲極係分別耦接至電晶體211 與212之源極。振盪器210的振盪訊號的共振頻率係為fo。 訊號源注入電路220與230内的電晶體221與231分 別將注入訊號Vil’與Vi2’注入至振盪器210的電晶體 211與213的汲極與源極。在本發明實施例中，電晶體211 之閘極源極寄生電容、電感214與電容216係可等效為一 等效阻抗，而電晶體212之閘極源極寄生電容、電感215 與電容217亦可等效為另一等效阻抗。這些等效阻抗係用 以保留注入訊號Vil’與Vi2’之三次諧波項，因此能以 避免注入訊號Vil’與Vi2’衰減，以避免注入鎖定除頻 器200的三倍頻注入鎖定除頻範圍變小。 注入訊號Vil’與Vi2’係透過電晶體211和212， 與振盪器210的振盪訊號的二次諧波訊號進行混波，分別 於電晶體211與212的汲極端輸出一組差動對訊號Vol’ 與Vo2’ 。如此，當注入訊號ViΓ與Vi2’的頻率位於注 入鎖定除三除頻器200的三倍頻注入鎖定除頻範圍内時， 注入鎖定除三除頻器200即可對注入訊號ViΓ與Vi2’ 進行除三頻的機制，輸出除頻頻率為注入訊號Vil’與 Vi2’之頻率的三分之一，且具有一組差動對輸出訊號 Vol，與 Vo2，。 茲說明將電容216與217並聯於電感214與215的優 12 200849825 三達編號：TW3716PA 點。當電晶體221迦a 源極時，電晶體211、遍的沒極輕接電晶體211與212的 效果，且能保留注入知\212與接地端需形成類似於渡枚的 以防止注入訊號Vii，號Vl\共Vl2中之三次諧波項， 振盪器210不包含你〜…Vl2中之二次諧波項衰減。若 配電晶體211與21^ 216與217 ’電感214與215需搭 抗。為產生足夠大的：=:生電容來產生等效阻 尺寸需設計為較大，t 電晶體2U與212的 容。 而侍以產生足夠大的閘極源極寄生電 因此’精由將齋^^ 極源極寄生電容。如，曰曰體211與212不需貢獻大的閘 小，進一步使振盪U晶體211與212的尺寸即可縮 注入鎖定除10的電流減小’降低功率消耗。 ⑽，分別緩衝輪:;=〇〇:可包括緩衝電路24。與 Vobl，與Vob2, 。 ^01與Vo2，，輸出經缓衝電壓 ί 注入鎖定除三除頻器2〇〇之電晶體211與212係以 NM0S為例、221與231係以職為例，實際應用上並不 限於此，電晶體211與212亦可以臓來替代；電晶體 221與231亦可以NM0S來替代。 本發明實施例之注人鎖定除三除頻器，在實際應用上 可以由振盡的兩電晶體之純、閘極、源極或基極其中 任一端注入訊號源也能達到除三的效果。 本發明實施例中，由於振^110、210之兩電晶體 13 200849825 三達編號：TW3716PA 111與II2、211與212透過電感耦接至备地 注入電路120與130、220與230之電晶體12^與 與23卜減接或透過電餘接至接地端，因此，本發明實 施例之注入鎖定除三除頻器僅需使用低電源電壓即可對 注入訊號進躲三之魏。因此，本發料施例之注入鎖 定除三除頻器可應用於低電壓操作，並具有低電功率消耗 的功效，利於應用在無線通訊系統中。Sanda number: TW3716PA and 215, including capacitors 216 and 217. Capacitors 216 and 217 are coupled in parallel with inductors 214 and 215, respectively. The source of the transistors 221 and 231 in the signal source injection circuits 220 and 230 are coupled to the drains of the transistors 211 and 212, respectively. The drains of the transistors 221 and 231 are coupled to the sources of the transistors 211 and 212, respectively. The resonant frequency of the oscillation signal of the oscillator 210 is fo. The transistors 221 and 231 in the signal source injection circuits 220 and 230 inject the injection signals Vil' and Vi2' into the drain and source of the transistors 211 and 213 of the oscillator 210, respectively. In the embodiment of the present invention, the gate source parasitic capacitance of the transistor 211, the inductor 214 and the capacitor 216 are equivalent to an equivalent impedance, and the gate source parasitic capacitance of the transistor 212, the inductor 215 and the capacitor 217 It can also be equivalent to another equivalent impedance. These equivalent impedances are used to preserve the third harmonic term of the injected signals Vil' and Vi2', thereby avoiding attenuation of the injected signals Vil' and Vi2' to avoid triple-frequency injection-locked frequency division of the injection-locked frequency divider 200. The range becomes smaller. The injection signals Vil' and Vi2' are mixed with the second harmonic signals of the oscillation signals of the oscillator 210 through the transistors 211 and 212, and a set of differential pair signals are outputted at the 汲 terminals of the transistors 211 and 212, respectively. 'With Vo2'. Thus, when the frequency of the injection signals ViΓ and Vi2' is within the triple-frequency injection-locked frequency division range of the injection-locked divide-by-three-divider 200, the injection-locking divide-by-three-divider 200 can perform the injection signals ViΓ and Vi2'. In addition to the tri-band mechanism, the output frequency is one-third of the frequency of the injected signals Vil' and Vi2', and has a set of differential pair output signals Vol, and Vo2. It is noted that the capacitors 216 and 217 are connected in parallel to the inductors 214 and 215. 200849825 Sanda number: TW3716PA point. When the transistor 221 has a source, the transistor 211, the effect of the transistor 211 and 212 is not very lightly connected, and the implant can be kept and the ground is formed to prevent the injection signal Vii. , the third harmonic term in Vl\common Vl2, the oscillator 210 does not contain the attenuation of the second harmonic term in your ~...Vl2. If the distribution crystals 211 and 21^216 and 217' inductors 214 and 215 are to be reacted. To produce a sufficiently large:=: raw capacitor to produce an equivalent resistance size, it is designed to be larger, t the capacitance of the transistors 2U and 212. And the waiter produces a large enough gate source parasitic power. Therefore, the fine source will parasitic capacitance. For example, the bodies 211 and 212 do not need to contribute a large gate, and the size of the oscillating U crystals 211 and 212 can be further reduced by the current reduction of the lock divided by 10' to reduce power consumption. (10), respectively, the buffer wheel: ; = 〇〇: may include the buffer circuit 24. With Vobl, with Vob2, . ^01 and Vo2, the output buffered voltage ί is injected and locked. In addition to the three frequency dividers 2, the transistors 211 and 212 are exemplified by NM0S, and the 221 and 231 series are used as examples. The practical application is not limited to this. The transistors 211 and 212 can also be replaced by transistors; the transistors 221 and 231 can also be replaced by NM0S. In the embodiment of the present invention, the three-frequency divider is locked, and in practical applications, the signal source can be injected from any of the pure, gate, source or base of the two transistors, and the effect of dividing by three can also be achieved. . In the embodiment of the present invention, the two transistors 13 of the vibrations 110 and 210 are 200849825. The three numbers: TW3716PA 111 and II2, 211 and 212 are inductively coupled to the transistors 12 of the ground injection circuits 120 and 130, 220 and 230. ^ and 23 are reduced or transmitted through the power to the ground. Therefore, the injection-locking divide-by-three-divider of the embodiment of the present invention only needs to use a low power supply voltage to enter the signal. Therefore, the injection lock of the present embodiment can be applied to low voltage operation and has low electric power consumption, which is advantageous for application in a wireless communication system.
、而上所述，職本發明已以―較佳實施_露如上， ^並非Μ限定本發明。本發明㈣技術領射具有通 吊知識者，在不脫離本發明之精神和範_，當可作各種 =更動與㈣。因此’本㈣之保護範圍當視後附之申請 專利範圍所界定者為準。 200849825As described above, the present invention has been described above in terms of "better implementation", and is not intended to limit the invention. The invention (4) technology leads to those who have the knowledge of the invention, and can make various changes and (4) without departing from the spirit and scope of the invention. Therefore, the scope of protection of this (4) is subject to the definition of the scope of the patent application attached. 200849825
三達編號：TW3716PA 【圖式簡單說明】 第1圖繪示本發明實施例之注入鎖定除三除頻器 (Divide-by-Three Injection-Locked Frequency Divider)之電 路圖。 第2圖繪示本發明另一實施例之注入鎖定除三除頻 器之電路圖。 【主要元件符號說明】 110、210 :振盪器 m、112、121、13卜 21 卜 212、22卜 231 :電晶體 113、 213 :電感電容共振腔電路 114、 115、116、117、214、215 :電感 120、130、220、230 ·•訊號源注入電路 140 :電容電路 141、142 :可變電容 150、160 :緩衝電路 216、2Π ··電容 15Sanda number: TW3716PA [Simple description of the drawing] Fig. 1 is a circuit diagram of a Divide-by-Three Injection-Locked Frequency Divider according to an embodiment of the present invention. Fig. 2 is a circuit diagram showing an injection-locking divide-by-three frequency divider according to another embodiment of the present invention. [Description of main component symbols] 110, 210: oscillators m, 112, 121, 13b 21 212, 22b 231: transistors 113, 213: inductor-capacitor cavity circuits 114, 115, 116, 117, 214, 215 : Inductors 120, 130, 220, 230 • Signal source injection circuit 140: Capacitor circuits 141, 142: Variable capacitors 150, 160: Buffer circuits 216, 2 Π · Capacitors 15