TW200849250A - Nonvolatile memory device and driving method thereof - Google Patents

Abstract

Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.

Description

200849250 IX. INSTRUCTIONS: [Technical Field] The invention disclosed herein is generally a memory component, and more particularly a non-volatile I non-volatile memory component; It is about a kind of drive % [Prior Art] 资料 Non-volatile memory components even if stored in t. Flashing is still reserved for the unit ° coffee. Because the flash memory component is -4 sms; the flash memory component is widely used in computers, and the jitter is early. This flash memory component is classified into NOR and also called u.

The difference between the NAND 〇 N0R body is about how to connect the memory cell to the bit line. In general, the NOR flash memory device is advantageous in terms of high speed performance, which is disadvantageous in terms of high integration due to its high current consumption. NAND flash memory components are advantageous in terms of high integration because they consume less current than N〇R flash memory components. • Figure 1 is a circuit diagram of a memory cell array no using a double patterning technique (% DPT). In general, dpt is a patterning technique that overcomes the limitations of photolithography devices. According to the DPT, the memory cell array is formed in such a manner that an even pattern is formed first and then an odd pattern is formed. 2A to 2C are perspective views of the shape of the word line and the bit line in FIG. 1 and the configuration. Specifically, Figure 2a is 6 200849250

— — A A cross-sectional view of the channel of the memory cell taken along line A-A’ of Figure 1. The channel width of the 2A' word line of Fig. 2 is different depending on whether the word line is an even number line or an odd number. Herein, the even digit line has a channel width Lgl smaller than the pass visibility Lg2 of the odd digit line. Fig. 2B is a view taken along line 4 B B of the figure. A cross-sectional view of the width of the active regi〇n of the body unit. Referring to Figure 2B, the active area of the even memory cell has a width AW1 that is less than the width AW2 of the active area of the number of body cells. Figure 2C illustrates the metal width of odd bit lines and even bit lines. See f) The 2C 'even bit line has a width BW2 less than the odd bit line BW2 〇 Figure 3 is a graphical illustration of the threshold voltage distribution of the memory cell fabricated according to the DPT. Referring to Fig. 3, there is a difference in threshold voltage distribution depending on whether the memory unit is an even unit or an odd unit. As used herein, an even memory unit means a memory unit connected to an even digit line, and an odd memory unit means a memory unit connected to an odd digit line. However, in a typical non-volatile memory component that performs a programmatic operation in accordance with the incremental step pulse programming (J ISPP) method, the stylized operating conditions (eg, stylized starting voltage) (Vo), ISPP. Incremental level (ΔΙδΡΡ) and stylized stop voltage (Vm) are determined from the total distribution regardless of whether the memory unit is an odd or even unit. Here, the 'programmed operating conditions satisfy the following equations 1 and 2 (Equation 1) (Equation 2)

Vm = V0^mAisPP AVm' = Vm — VQ 7 200849250 where m is the number of iterations of the stylized loop used to reach the stylized stop voltage (vm). • As illustrated in Figure 3, the total distribution is relatively broadly distributed than even memory cells and odd memory cells. Therefore, it is difficult to optimize the typical non-volatile memory components for stylized time because the stylized operating conditions are determined based on the total threshold voltage distribution. This is because the stylization time is generally proportional to the width of the threshold voltage distribution. In addition, the width of the distribution (Δ%) becomes larger in the C1 纟1spp operation, and thus the number of iterations (m) of the stylized cycle is correspondingly increased. This causes an increase in the stress of the memory cell, which ultimately leads to deterioration of the reliability of the memory cell. 4 is an equivalent circuit diagram of a conventional bit line structure and a sensing method, with associated voltage-time curves. As illustrated in Fig. 2C, the bit line width differs depending on whether the bit line is an odd bit line or an even bit line. Therefore, the parasitic resistance and the parasitic capacitance are different depending on whether the bit line is an odd bit line or an even bit line. Towel #, even bit line 〇 i resistance Re A material touch parasitic resistance R 〇, and even bit line • Parasitic capacitance Ce is smaller than the parasitic capacitance Co of the odd bit line. This is attributed to the fact that the width of the even bit line is deleted from the width of the odd bit line. This may make the RC time constant based on whether the value element line is an odd bit line or

The even bit lines are different. For the branch description, it is assumed that the RC time constant (ReCe) of the even-numbered turns is greater than the Rc time constant (RoCo) of the odd-numbered lines. As a result, the operating conditions are sensed (for example, pre-charging time, development time 8 Ο

Cj, that is, under the sensing operation condition of a typical non-volatile memory element, the sensing time Ts is determined such that it includes a pre-charging time Tpc of an odd-numbered bit line that is relatively longer than the even-numbered bit line, and The development time Td of an even bit line that is relatively longer than the development time of the countable bit line. As illustrated in Fig. 4, the waiting times Tw1 and Tw2 occur in even bit lines and odd bit lines, respectively. That is, typical non-volatile character elements cannot optimize the sensing time. Referring again to Fig. 4, the even bit line BLe is precharged faster than the odd bit line BLo in the precharge operation of the even bit line BLe. However, the 'precharge time □pC is limited by the precharge time of the odd bit line BL〇. In the development operation of the odd bit line BLo, the odd bit line bl 〇 200849250 development time will be different depending on whether the bit line is an even odd bit line. In this paper, the charge_ is =^ line rises until the pre-charge voltage (for example, the time of the power supply. The development time refers to the bit line voltage from the county charge voltage M (trip voltage) Vtrip f ^ 〇 even Digital position, 贞彳 充 充 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The pre-charging time, and the development time is shorter than the development time of the even-numbered bit line.—, the surface volatile memory component operates regardless of the bit line, and the odd bit line operates with the same sensing operation condition. Developed faster than the even bit line BLe. However, in this case, the cell current development time Td is limited by the development time of the even bit line BLe. This guide 9 200849250 causes read/verify characteristics of non-volatile memory elements Degraded. Therefore, there is a need for an improved non-volatile memory element structure. [Invention] The present invention provides a non-volatile memory element and method for optimizing performance based on a difference in threshold voltage distribution. • Shumingzhi-The embodiment provides a method for planting a facial memory component and includes determining the structural position of the memory cell to be driven; reducing the threshold voltage of the unit (4) unit The distributed operating conditions drive the memory unit. Further embodiments of the present invention provide a non-volatile memory element. The non-volatile memory element includes: a memory cell array including a plurality of memory cells Each of the plurality of memory cells is located at a plurality of word lines, where the intersection of the plurality of bit lines; the column decoder is lightly coupled to the memory bank and is configured to select the plurality of word lines One of the words; and the word line is generated as the threshold voltage associated with the selected one of the plurality of memory cells </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; See the description of the hair in more detail with the accompanying drawings. The preferred embodiment of this document is embodied in the text, and the formula (10) is not to be construed as being limited to the embodiment. In fact, the embodiments are provided such that the disclosure of 10 200849250 Z/Jjupu will be thorough and complete. The scope of the present invention will be fully conveyed to those skilled in the art. The non-volatile memory element according to the embodiment of the present invention determines the structural shape and position of the memory unit to be driven, and thus is determined according to the determination. • The result is operated with operating conditions appropriate to the distribution characteristics of the memory cells to be driven, wherein the structure shape and position comprise the width of the word line, the width and height of the active region (10) ve region, and between two adjacent word lines. distance. Therefore, it is possible to improve the threshold voltage distribution characteristics and the performance degradation caused by the structural shape and position of the memory unit. The operation stop includes the word line voltage, the bit line voltage, the well voltage (wellv〇ltage), and the bean timing. 〃 The non-volatile memory element according to the first embodiment may be adapted to be driven in an independent manner according to the distribution characteristics of the memory cells in which the memory cells are even cells or odd cells. In this paper, the memory odd number is determined based on whether the memory unit is connected to an even digit line or an odd digit line. That is, hereinafter, a memory cell connected to an even digit line will be referred to as an even memory cell, and a memory cell * connected to an odd digit line will be referred to as an odd memory cell. Figure 5 is a functional block diagram of a non-volatile memory element 100 in accordance with a first embodiment of the present invention. The non-volatile memory element 1 of Figure 5 is a NAND (four) memory element. However, it will be apparent to those skilled in the art that the present invention is also applicable to other memory components (eg, mask read only memory (MROM), programmable ROM (PROM)). Ferroelectric random access memory (ferr〇dectric 11 Ο Ο 200849250 r^«;rmory, FRAM&gt;N0R ^} nand 5 ' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The line voltage generator 13 页面, the page buffer = 士 and the control logic 150. Via the double patterning technique (10), the memory cell array 11 〇. The non-volatile memory element _ , according to the memory unit is an even unit The odd-numbered cells are also operated in different ways. For this purpose, the word line voltage generator 130 of the present invention performs a f-fetch operation to provide separate programs suitable for odd-numbered memory cells and even-numbered voltage distributions. Control/read operation conditions. Control = Individual sensing operation conditions suitable for odd bit lines and even bit lines during the face selection/verification operation. Here, part of the verification operation. 卞F and % Memory list The array 110 includes a plurality of memory cells, and the memory cell arrays of FIG. 1 have substantially the same structure. The plurality of memory cells included in the memory cell array 110 are disposed in a plurality of to wL31 and a plurality of bit lines BLe. 〇 to the area where BLen i and BLon-1 cross each other. The 1-bit data or η-bit data in the memory unit, where n is 2 or more than 2: Store more than 1 word line WL〇 to WL31 into even The digital lines WL〇, WL2, ..., WL30 and the odd digit lines wu, WL3, ..., ^ are used to damage the memory cell array 11〇, °, muscle 2, ..., WL3 by using DPT ' The width is different from the width of the odd digit line = line WL3, ..., WL31. In the following, for convenience of description, the fake 12 Ο

200849250 厶 / J丄 The line width of the even bit lines BLeO to BLen-1 is narrower than the line width of the odd bit lines BL〇0 to BLon-1. Therefore, the memory cells of the memory cell array 11 are mainly classified into even memory cells and odd memory cells. Each cell string (also referred to as a nand string) of the memory single-tray array 11A includes a plurality of floating gate transistors M〇 to M31. The plurality of floating gate transistors M0 to M31 are connected in series between the string selection transistor sst and the ground selection transistor GST arranged in the same string. A plurality of word lines WL 〇 to WL31 are configured to cross the cell strings (i.e., NAND strings). Word lines WL0 to WL31 are respectively connected to the control gates of the corresponding floating gate transistors M0 to M31 of each string. The programming/reading voltage is applied via word lines WL 〇 to WL 31, whereby the data is programmed into the corresponding floating gate transistors M0 to M31 or read from the corresponding floating gate transistors M 〇 to M 31. . The non-volatile memory component further includes a page buffer 140 for programming data into the memory cell array 110 or reading data from the memory cell array 110. The column decoder 120 decodes the supply from a column address buffer (not shown), bit j to select at least one of the plurality of word lines WL 〇 WL WL 31 and then apply the word line voltage to the 敎 word line. Here, the word line voltage is supplied from the word line voltage generator 130. The column address corresponds to the location data of the selected word line. More specifically ^, the column address contains the location data indicating that the 敎 word line is the servant word line digit line. α meaning. The word line voltage generator 130 generates a word line to be supplied to the selected word line. The word line voltage can be a program and a verify voltage during the staging operation, and can be a read voltage during the read operation, and = 13 200849250 The voltage can be erased during the process. In detail, the word line voltage generator 132 of the present invention, when the selected word line is an even digital line, the even voltage trim circuit 132 adjusts the word line voltage to supply the first stylized voltage and the first voltage to敎 word line. Here, the first-stylized "^ Ο u two read voltages are suitable for the threshold of even-numbered memory cells: Γ:ΐέ: ί? is described more fully below with reference to Figure 6. When the 'odd voltage trimming circuit 134 adjust == select:: r here, the second pass 'voltage two material threshold according to the memory unit is even memory 1 charge = also describe: yuan 'the word line money of the invention The voltage of each of the threshold voltage distributions of the 13G countable memory cells is supplied to the 敎 word line in the corresponding memory. The verify voltage or the read page buffer 140 is read/cut. W0 is in the control logic 15〇=2nd lower bit line. It will output the input/output circuit (not shown) to the outside and output it to the pass/fail detection circuit (Fumu/Moon) == is determined during the stylization operation from page 2: ^ 之 枓 通过 通过 。 。 。 通过 通过 通过 通过 通过 2008 2008 2008 2008 2008 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = During the erase operation, the control margin port 130 and the page buffer 14 are controlled. Control 4 =, = rotation (4) The even number of her two = (3) and the reading of the Wei Wei u4 + _: 3⁄4 road invention control logic 15 〇 contains, 疋., this even time balance two ways ^ There is no (four) 兀 line sensing operating conditions of Fu Wu And odd-time trimming circuit (5). The following Ο1 electric time and unit current development time describe these non-twist line sensing operating conditions. &lt;Heart-seeking-bit-to-trim circuit 152 control · face buffer 11 just to the first Qing to the first - unit current development time, she will test π. Similarly, the odd time trim circuit 154 controls,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, A more fully described one. 〃耆 Ο :: Logic 150 controls the page buffer 140 such that the time sense bit line is developed with the appropriate precharge time current according to the corresponding bit line being an odd bit line. That is, the control logic = face buffer 1114G to drive the bit line with different bit line operating conditions depending on whether the remaining line is an even low line or an odd bit line. The non-volatile memory element 100 is therefore the most Jiahua Specifically, in the heart==100, can be read by the stylized voltage optimized for the threshold voltage distribution according to whether the word line is an even digital line or an odd, spring. The voltage drives the word line, and can be optimized by the pre-charging time and the unit electric furnace according to the bit line being an even number - ^ 1 the vertical line is an odd bit line. t Even if the memory unit is based on memory The body unit is an even-numbered memory single--is odd-numbered memory unit with different threshold voltage distribution characteristics, and the ~^ memory element 100 is still for even-numbered memory units or odd-numbered eating. , causing stylized/reading body Ο 效能 performance improvement. The discussion below with reference to Figures 6 through 8 provides information on how to improve stylization/read/erase performance in non-sexual memory component 100 = more detail.乂 ^ Figure 6A to Figure 6C are diagrammatic illustrations of the method of adjusting the pressure of the non-volatile memory element 1 of Figure 5. Fig. 6A illustrates a threshold voltage distribution according to whether the memory unit is a memory unit or an odd memory unit. Referring to Fig. 6A', the threshold voltage distribution of the odd-numbered memory cells is relatively high = even = the threshold voltage distribution of the memory cells. Although Fig. 6A illustrates that the threshold voltage distribution of the odd-numbered memory cells is higher than the threshold voltage distribution of the even-numbered memory cells, the present invention is not limited to this case. The non-volatile memory component 100 can operate in accordance with a stylized fall condition optimized for even memory single distribution and odd memory cell distribution, respectively. Non-volatile memory component 10. It can be peaked by the incremental order (Ispp) method. According to the ISPP method, the program is repeated twice as long as the V Vggm repeats the fine-grained self-starting of the money cycle.

Package I. This 1SPP method is disclosed in the article entitled "A 3.3V 32Mb NAND 16 200849250 / j jvyμι丄

Flash Memory with Incremental Step Pulse Programming Scheme", IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, November 1995, pages 1149 to 1156 (Snh, Kang-De〇g et al.) This document is incorporated herein by reference. First, a stylized method of odd memory cells will be described. Figure 6B: illustrates the stylized operating conditions according to the threshold voltage distribution of even memory cells. The operating conditions include a stylized starting voltage Ve〇, an ISPP increment level AlSPPe, a stylized stop voltage vem, and a first verification voltage Vvfe. The maximum number of stylized cycles can be m. The threshold voltage of the even memory unit The distribution satisfies Equations 3 and 4 below.

Vem ~ VeO + mAISSPe AVwe = Vem - VeO - _ - (Equation 3) ..... (Equation 4)

U ... see Figure 6B to program the even memory unit with the first stylized operating conditions. Here, the first stylized operation condition includes a first stylized start pressure VeO, a first-ISPP increment level recommendation coffee, a first stylized stop + voltage Vem, and a first verification voltage Vvfe. This first-stylized "can be designed to be used for the threshold voltage of the even-numbered memory cells. The first two pieces can be supplied from the even-numbered voltage trimming circuit 132. In the material of the recording unit, the material is _, ^^^ -Incremental level △ Talk 6 sequentially increases the voltage level of the voltage level Vpgm is supplied to the corresponding word line. The flying picture 6C illustrates the distribution of the finite charge according to the odd memory unit. 200849250 厶/ J jv^ /μ丄丄化 operating conditions. In this paper, the stylized operating conditions include a second stylized starting voltage V〇0, a second ISPP increment level...卯%, a second stylized stop voltage Von, and a second verification. The voltage Vvf〇. The maximum number of stylized cycles can be η. The second stylized starting voltage is higher than the first stylized starting voltage lion. However, it is not necessary to make the second stylized starting voltage ν〇〇 higher than The first stylized starting voltage Ve0. The threshold voltage distribution of the odd memory cells satisfies the following Equations 5 and 6.

Von = V〇0 + nAISSPo , -........................ (Equation 5) AVwo = Von - VoO . ...................................6) See Figure 6C' stylized with the second stylized operating conditions Odd memory unit. Here, the second stylized operating condition includes a second stylized starting voltage VoO, a first ISPP increment level, a second stylized stop voltage Von, and a second verify voltage Vvf0. This second stylized operating condition can be designed to be optimal for the threshold voltage distribution of odd memory cells. A second stylized operating condition can be provided from the odd voltage trim circuit 134. During the stylized operation of the even memory cells, a stylized voltage v having a voltage level sequentially increased by the second incremental level AISPPo is supplied to the corresponding word line. m Referring to Figures 6A and 6B, the stylized operation of the non-volatile memory element 100 is performed under respective stylized operating conditions, depending on the threshold voltage distribution of the odd-numbered memory cells and the even-numbered memory cells. That is, stylized = start voltage VeO and V〇0, ISPP increment level and _ rush, 18 200849250 stylized stop voltage Vem and Von, and the maximum number m of stylized cycles and η according to the 'fee to be driven' The body early element is an odd memory unit and an even memory unit. In the conventional non-volatile memory element illustrated in Fig. 3, in the program operation, the program operation condition is determined based on the width AVw of the total threshold voltage distribution. However, in an embodiment of the invention, the stylized operation of the non-volatile memory element 100 is performed under the conditions of a stylized operation suitable for the threshold voltage distribution characteristic of the memory cell. In detail, the programmed operating conditions are determined based on the width AVwe of the threshold voltage distribution of the even-numbered memory cells and the width of the threshold voltage distribution of the odd-numbered memory cells, respectively. Therefore, the stylized time of the non-volatile memory element 1 of the present invention is shorter than the stylized time of the conventional non-volatile memory element based on the width AVw of the total threshold voltage distribution. In addition, in this issue, the number of times that the number of revolutions can be reduced can be counted by the number of non-volatile memory components. Therefore, it is possible to improve the reliability of the memory unit. 〇〇 二财发明—A non-volatile memory component of an embodiment 1 (9) is a graphical illustration of the voltage taken. To Lei 八/士士新/有图7, the threshold of the memory unit The knives are mainly divided into the even-numbered memory unit memory unit's threshold voltage distribution ^^'s marginal money distribution and odd memory single cloth. As illustrated in Fig. 7, the odd number is recorded early; the threshold voltage distribution is relatively high with a voltage distribution. Therefore, in the threshold of the memory of the invention, the read voltage of the material decision is different according to the delay of the memory component in the memory component. , odd memory unit 200849250 jL / d ^ kjull read voltage Vro 彳 彳 毒 毒 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文130 electric power trimming circuit 134 electric slow Vro and v in non-volatile memory - 1GG, to be supplied to the yuan and each other. Also, the number of memory cells or even memory single oo erase voltage according to the record The component_ can be implemented to reproduce the memory cell or the even-numbered memory cell or the even-numbered volatilization to λ. According to the invention, the non-illustrative description of the embodiment. The application of the curve, such as the *4 towel, the even-numbered bit line or the odd-numbered bit, is the same as the flat method. However, the conventional time-matching bit line for the bit line sensing is from the 8th, the silk touches. Is even (for example, the pre-charged bit line senses the operating conditions you *^ 'Reading/verifying the non-volatile memory component 100's operation/compensation_yuan line sensing operation to read the memory from the memory unit ^ = :, , !! The measurement operation is mainly divided into the bit line pre-charging part, The bit line development section and (4) the sensing part. During the pre-charging part of the bit line, the spring is pre-charged to a predetermined voltage level. During the development of the bit line, the voltage of the 7L line is based on the connected recording line. The memory fresh element is changed by cutting the unit or turning on the unit. For example, if the memory unit is a turn-on unit, the charge accumulated in the bit line 20 200849250 Z/jDUpil is discharged via the memory unit, so that two If the memory unit is a cut-off unit, the voltage is lowered by a predetermined voltage. The data sensing unit maintains the voltage at the voltage and determines that the bit is connected to the unit by the sensing unit. Whether the memory unit of several lines is a turn-on unit or a flat method. See Figure 5 and Figure 2 for the time-matching of the even-numbered bit lines. The matching squares are as follows. Even-time trimming circuit] = % of the line:: : η first-sensing operating conditions include first First; 乂 and brother - early element current development π between Tpce know non-volatile memory components: the description of the non-volatile memory components in the coffee: sd. Therefore, by waiting time (TW1), the total sense Measured, not illustrated in Figure 4, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Balance method

Ff Td〇 ° ;〇 ~: Tpc〇 and the second one, 预先, pre-charge time Tpe. It is equal to two = Td in Figure 7. Sum. The second memory of the 7L piece of 贱 f f f _ _ _ 罘 罘 罘 早 早 早 do do 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Therefore, since the waiting time = two in the description of Fig. 4 is not required: the bud of the conventional non-selective memory element explained in Fig. 4, the (10) two/first charging time, and the first single 7L ^ _ off Tde. Odd time trimming circuit ^ 〇 First charging time Tpc. And the first - early heart development time Td. . Therefore, non-known non-volatile memory components can reduce the total time of 0. Since the bribe bit line BLe〇 to BLeiM is oddly bit-reading BL〇〇, another 0Γ1 has a smaller width, so the former is faster than the latter. Precharged. In addition, since the cell currents of the even bit lines BLe0 to BLeIM 〇 HBLo0 to see (10)·1 are small, the former requires: Line: Clear and correct. Therefore, the first-de-charge time plus the pre-charge "co." On the other hand, the first cell current ON is longer than the first cell current development time Tdo. Therefore, the difference in the total sensing time is not wide. The even sensing time two is similar to the odd sensing time Ts〇. The symbol ', 贝, 贝, in the two-dimensional memory element 100, is an odd-numbered bit line according to the bit line, which is an even number of 5 lines 而Optimized sensing operation conditions - ^ operation. HI this, used to sense the bit time of the bit line to reduce the ^ ^, thereby reducing the read / verify operation in non-volatile memory components忉/中22 200849250

2/J^UpiI The time it takes to execute. Figure 9 is a flow chart illustrating a non-binarization method in accordance with an embodiment of the present invention. See the public • Volatile memory component 10D 夕条口七于古μ, riding code crying 1? 1 is the following method. The column address is decoded in operation S110 -n± ★ °°° to select the word line corresponding thereto. The same is moved to the word line voltage generator 130. In operation si2, it is an even digital line. In operation, if the 子ίΐ II sub-line is supplied from the even-numbered voltage trimming circuit 132 μ stylized operating condition τ circuit 132 The selected word line is an odd-numbered green type. In operation S140, if the -w sub-line is used, the stylized operation is performed under the condition that the odd-numbered voltage trimming circuit 134 is used by the library-stylized operation. To illustrate the bit line subtraction/single 仏 ί0 of a physical component 100 according to the present invention, a non-volatile 流程图 flow chart is shown in Fig. 5 and Fig. 5, and the second-line sensing method is as follows. In operation S220, the second = Luo = then receive the poor material read / verify life / m control page buffer flat circuit page buffer just so = _ eight countable time trim circuit w control line. Brother - sense the sense of operating conditions The odd-numbered bits are operated in a different manner according to the above-mentioned present invention, and the individual elements are operated in a different manner according to the memory unit. Specifically, in the root military device element (10) of the root example 200849250. , in the memory unit is even 7L differential odd-numbered memory cells and drive word lines for stylized/read/verify/erase operation conditions of materialization. In the = bit line is an even bit _ is a strange touch ^ line (4) Optimisation: Drive the bit line under conditions. 1] This may improve the voltage distribution of the memory cell and the degradation due to the difference in the age of the memory cell.

Embodiments of the invention are also applicable to non-volatile memory elements having a three-dimensional memory array structure. In this component, the individual layers of the memory array can have different threshold voltage distributions and performance characteristics. This three-dimensional array structure has been disclosed in the following patent: U.S. Patent No. 5,835,396, issued to <RTIgt; </RTI> </RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; US Patent No. 6,034,882 (March 7, 2000); and U.S. Patent No. 7,002,825 (February 21, 2006) entitled "WORDLINE ARRANGEMENT HAVING SEGMENTED WORDLINES", these patents will be cited The manner of incorporating is incorporated herein. In an embodiment of the invention, the non-volatile memory elements can be configured to operate in different ways depending on each layer of the memory array. Figure 11 is a diagram illustrating an embodiment in accordance with the present invention. A cross-sectional view of a three-dimensional (3-D) memory array 210. The 3-D memory array 210 can be a flash memory array, a read only memory (ROM) array, a static random access memory 24 200849250 27350ριί body (SRAM) Array, Shi Xi·oxide·nitride-oxide, (s〇N〇s) β-hexene array or the like. See Figure Η, although 3_D memory array 210 has a first layer 212 and a second layer 214, but the invention is not necessarily limited to a two-layer memory array structure: money, bulk array_containing substrate 202 formed by Shi Xi or the like. - or more The read material layer (shown one) is provided at different levels in the memory f column 210. In detail, the memory material layer 204p is stacked over the substrate 202. An insulating layer 206 such as an oxide layer is disposed over Between each of the layers of the sparse material layer 204 such that the memory material layer 204 is separated from the % edge layer 2〇6 may comprise a host dielectric layer, such as borosilicate glass (BSG), phosphorite Salt glass (psG) and disk silicate glass (BPSG), see Figure 记忆 'The memory of the first memory array of the first layer 212 is placed on the substrate 202, and the second layer 214 The memory unit of the second memory array is disposed on the material layer 204. Therefore, the threshold voltage distribution of the memory unit belonging to the first memory 不同于 _ is different from the threshold of the memory unit belonging to the second memory Array Voltage distribution. Non-volatile memory components can be configured to Figure 12 is a functional block diagram of a non-volatile character encoding element 200 in accordance with a second embodiment of the present invention. Figure 12 is a non-volatile material. The memory 200 includes a 3-D | replied array 21 解码, a decoder 22 〇, a page buffer cry 230, and a control logic 24 〇. The memory array 21 is as described above with reference to FIG. η. The non-salt cardiac component 200 is configured to be in accordance with the corresponding 25 200849250 27350pif, and the ADD 5 memory unit belongs to the memory array 210 - Layer 212 migrates the second layer 214 of the array 210 to control the memory system's production system - 24 〇. In particular, the control logic includes a first layer of control logic 242 configured to control memory cells belonging to the first layer 212, and configured to control memory cells belonging to the second layer 214 The second layer of control logic 244. 13A to 13C are diagrammatic illustrations of the stylized 5 method of the non-volatile memory element 〇 of Fig. 12. In detail, FIG. 13A is a diagram showing the threshold voltage distribution of the memory cells belonging to the first layer 2, 12 and the first layer 214, and the memory cell placed on the material layer 2〇4. Compared with the substrate placed on the base 2, the body has a poor threshold voltage characteristic. Thus, the threshold voltage of the memory cells in the 'first layer 212' can be higher than the threshold voltage of the memory cells in the second layer 214. Figure 13B is a graphical illustration of the stylized operating conditions for the threshold voltage distribution of the first 12 cells of the memory array 21〇. The programmed operating conditions include a stylized starting voltage vl 〇, an Ispp increment level ° ΔΙδρρ1, a stylized stop voltage vim, and a first verify voltage Vvfl. The maximum number of stylized loops can be m. Notes in the first layer • The threshold voltage distribution satisfies Equations 7 and 8 below. heart

Vlm = V10 + mAISSPl _ ............................... Equation 7) ^w\ = V\m-V10 ........................... (Equation 8) Referring to Figure 13B', the first layer is programmed with the first stylized operating conditions. 2 26 200849250 27350pif The three have recalled the unit. Here, the first stylized operating condition includes a first programmed starting voltage V10, a first ISPP increment level Δjspp, a first programmed stop voltage Vim, and a first verify voltage Vvfl. This first program/匕 operating condition can be optimized for the threshold voltage distribution of the memory cells in the first sound: 212. The first stylized operating condition can be provided from the first level control logic 242. When the memory cells in the first layer 212 are programmed, the programmed voltage Vpgm having the voltage level sequentially increased by the first ISPP increment level ΔΒΡΡΐ can be supplied to the corresponding word line. Figure 13C is a graphical illustration of the stylized operating conditions for the threshold voltage distribution of the sensible unit of the second layer 214 of the § 己 体 array. Here, the stylized operating conditions include a second stylized starting voltage V2, a second ISPP increment level, a second stylized stop voltage v2n, and a second verify voltage Vvf2. The maximum number of stylized loops can be n. The threshold voltage distribution of the memory cells in the second layer satisfies the following Equation 9 to ^ 10 〇r V2n = V2Q + nMSSP2 ............, • ......... ............(Equation 9) : ...................(Equation 10) See Figure 13C for the second stylization The operating conditions stylize the second layer of the second layer 214. Here, the stylized operating condition includes a second stylized starting voltage V20, a second ISPP increment level Δbpm, a first sigma stop voltage V2n, and a second verify voltage Vvf2. This second pass can be optimized for the threshold voltage distribution of the memory cells in the second 214. A second stylized operating condition can be provided from the second level control logic 244. When the memory cells in the second layer 214 are programmed, the programmed voltage Vpgm having the voltage level sequentially increased by the second ISPP increment level MSPP2 can be supplied to the corresponding word line. The non-volatile memory component 200 is configured to determine whether the addressed sensible unit belongs to the first layer 212 or the second layer 214. The memory cells are programmed with different stylized operating conditions based on the identified layers of the memory array 210. Thus, the non-volatile memory component 200 optimizes the operating conditions for the threshold voltage distribution of the memory cells in the first layer 212 and the second layer 214. Figure 14A and Figure 14B are graphical illustrations of the read/verify voltages of the non-volatile memory component 2A of Figure 12. Referring to FIG. 14A and FIG. 14B, the threshold voltage of the cell of the non-volatile memory device is mainly divided into the threshold voltage of the memory cell in the first layer 212 and the § memory in the second layer 214. The threshold voltage of the unit. As shown in Fig. A and Fig. Η = ϋ, the threshold voltage distribution of the memory cells in the layer 212 of the memory cells in the second layer 214 is the threshold voltage distribution. In the case of the case, each of the memory cells stores 2-bit data. In a volatile memory element, the read voltage differs depending on whether the memory is on the first layer 212 or the second layer 214. For example, the memory cell has a relatively higher read/verify voltage than the memory cell in the first layer 212. Specifically, the memory unit in the second layer 214 is as large as -2, _2, _2^1_2, ^仏2, and *仏2 are large 28 Ο

200849250 27350pif in the second layer 212 of the bridge, the bridge reading voltage -,, the reading voltage of the memory unit ^ and: = the first layer of the verification (4) VvfH, fine] and fine · 1 and 242 control. The second layer 214 is controlled by the second layer control logic 244 by the f-layer control logic -2, ^Vr3-2 t MVvft^; And the vf3-2 memory element 2 〇 °, the read to the word line / element is located in the multi-layer memory array ... layer 212 is extended in the second layer 214 and the erase voltage of the body element 200; military narrative Also in the memory 212 can also be changed according to the memory unit located in the first layer of the enamel layer 214. In the non-volatile memory component, depending on whether the memory element belongs to the first layer 212 or 筮- is οι" to ‘3 s 214, a separate read voltage is performed. Therefore, the non-volatile memory family 200 is compared with the conventional non-volatile seven-replica 7L device in which the read operation is performed with the same read voltage regardless of whether the memory cell is located in the first layer 212 or the second f214. The read margin can be improved. = As noted above, the non-volatile memory elements can be configured to optimize operating conditions based on the structural differences and location of the fe unit. The present invention is applicable to other regions having different threshold voltage distribution characteristics and performance characteristics depending on the structural position (e.g., between memory blocks, between mats, and between memory groups). For example, the non-volatile memory elements can be configured to vary the memory blocks of adjacent decoders from the far-end decoder. In addition, the non-volatile memory can vary in operating conditions between memory blocks used for memory of a particular purpose. The control logic 2 of the non-volatile memory component described by the brother/slaver 24D ff/ is used to control the memory unit sound belonging to the first layer 212 for controlling the memory list belonging to the second layer 214. 'Ο元Ϊ = ^ However, the non-volatile memory of the present invention is:   As illustrated in Figure 15, the policing =: 300 includes configuration to control the column decoder ==! logic 340. Leveling information (4) Control control 1 Control logic tearing through configuration with preset operation = operation JL and way 350 contains the first level trim information register 352, drive series: 4: preset operating conditions for the best Ground

(J contains the 4th whole message. The leveling information circuit 350 further includes 3 layers of the balance of the temporary register 354, 34〇 of the preset operation conditions to #料^,: used to adjust the control 邈 compilation information. The leveling information circuit second work = = will be a single ® lion, 1 &gt; a horse to enter the address ADD to determine the first adjustment information of the distribution of the temporary register is still the second layer 340. Although the figure h ~, rh The younger brother went to the control logic and temporarily transferred to the control logic to temporarily cry 359. The monthly balance of the poor communication circuit 35〇 contains two levels of information to cry 10 ^ and 354, but the invention is not limited to two trim information or 'leveling information The circuit can be stored with three or three 30 200849250 27350 pif (four) for more than zz equalization information registers according to the present invention. Block diagram. See ® 16, memory device 10 of the memory system 10. The non-volatile bribe contains _to memory control to control non-sweet memory ^^12, and the (four) control _ 14 can be configured as (for example) W5 towel transfer key (4) component 12 〇 non-volatile memory Element 2: =, component (10), piece 300 in Figure 12. ^ Non-volatile memory element non-volatile memory in Figure 5. The information stored in item 1. With the addition of digital assistants (PDAs), such as hives, the addition of personal information (MPEG) audio layer 3 (MH console and dynamic professional community for code and data) Storage. In addition, the use of high-resolution f ^ = _ memory devices can be used in home applications based on 4:: ) (GPS) components. For the non-volatile memory components of the example: applicable: 4:::: two sets: the calculation system · the central processing unit (C, work. The embedded system can include the operating system execution library And the operating system can be placed by the embedded system such as military; 2 type-specific operation. The embedded system can be built such as digital TV = industry I, communication device, video converter or Figure 17 is the family of the camera In the device, the function block diagram of the non-volatile memory of the body element according to an embodiment of the present invention is shown in Fig. 17, 31 200849250 厶 / JJ UpJL 丄肷 己 己 体糸 〇 2〇 contains Ray, $ j unit ((10) 22 S'2, 2] to the bus of the central processing element 28 referred t tone. Hexanoic prong member 26 and the control states having a non-volatile or more ==

The non-volatile memory component 28 can store the core data (N is a positive integer) processed by the controller 26. The body is not shown, but the embedded memory system 2 includes an application chipset, a camera image processor (Cls), and other components. The chronograph controller % and non-coffee, for example, configure the non-volatile memory component 28 for: J: Solid Disk Drive/ScDisk (SSD). The plant may package the non-volatile memory element 28 and/or the memory controller 26 in a variety of ways depending on the design choice. For example, the non-volatile grammar element 28 and/or the memory controller 26 can be mounted on a package (卯 ^ on on package, P 〇 P ), a spherical grid array ( bau grici grabbing, bga )seal

Package, chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), nest Volt package Die in waffle pack, wafer form die, on-board chip (chip_on_board ' COB ), ceramic dual in-line package (CERDIP), plastic metric square flat package (piastic Metric quad flat pack (MQFP), thin quad flatpack (TQFP), small outline (SOIC), shrink small package (SSOP), thin small package (TSOP), system 32 200849250 package (system in package, SIP), multi-chip package (inulti_chip package 'MCP), wafer-level manufacturing package (wafer_ievei's package, WFP) or wafer-level processing stack package (known as seven (10) processed stack package, WSP )in. According to embodiments of the non-volatile memory component, it is possible to improve the threshold voltage distribution and performance because the non-volatile memory component operates in different ways depending on the structural location of the memory cell. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Therefore, the scope of the invention is to be construed as being limited by the scope of the invention and the scope of the invention. [Simple description of the diagram] The electricity = the shape of the memory cell array using the double patterning technology (DPT) = the shape of the word line and the bit line and the memory single note along the line of Figure 1 ", intercepted A cross-sectional view of the width of the active region of the unit, and the metal width of the bit line and the even bit line of Figure 2C. Figure 4 is a conventional voltage distribution of the memory cell fabricated by DTM. The bit line structure and the equivalent circuit diagram of the sensing method are 33 埯, Ban H f 腹 兀 兀 is the threshold voltage distribution characteristic of the odd memory unit, ' 〇〇

200849250 II / JdV / Bu / 丄丄 and associated voltage-time curve. Fig. 5 is a functional block diagram of a non-part of the embodiment of the present invention. X (raw 3 has a non-volatile memory operation of FIG. 6A to FIG. 6C A FIG. 5, and FIG. 6C shows a schematic description of the read voltage of the root gamma-solid turn of FIG. 7 . FIG. 9 is a diagram illustrating voltage time curves sensed by bit lines in a non-揎=body element according to an embodiment of the present invention: FIG. 9 is a diagram illustrating an embodiment of the present invention. Flowchart of a stylized method for non-volatile components. (9) A diagram for explaining a bit line sensing method of a non-volatile odd-body 70 piece according to an embodiment of the present invention. A cross-sectional view of a two-dimensional memory array of a non-volatile memory element in accordance with an embodiment of the present invention. Figure 12 is a functional block diagram of a non-volatile memory element in accordance with a second embodiment of the present invention. 13A to 13c are diagrams illustrating a &amp; characterization method of the non-volatile memory element of FIG. 12, wherein FIG. 13A illustrates the second layer of the stalk, the stalk, the tooth, and the sputum according to the memory unit. Limit voltage distribution, Figure 13B illustrates the memory list for the 34th 200849250 27350ριί layer The stylized operation of the element, and Figure 13C illustrates the stylized operation of the memory cells of the second layer. Figure 14A and Figure 14B are graphical illustrations of the read/verify voltages of the non-volatile memory elements of Figure 12. Figure 15 is a functional block diagram of a non-volatile memory element in accordance with a third embodiment of the present invention. Figure 16 is a functional block diagram of a memory system in accordance with an embodiment of the present invention. Functional block diagram of the embedded memory system of the non-volatile memory element of one embodiment. [Description of main component symbols] 10: Memory system 12: Non-volatile memory component 14: Memory controller 20: Embedding Memory System 21: Bus Bars 22: Central Processing Unit (CPU) • 24: Static Random Access Memory (SRAM): 26: Memory Controller 28: Non-volatile Memory Element 1〇〇: Non-volatile Memory element 110: Memory cell array 120: Column decoder 130: Word line voltage generator 35 200849250 Z/JDUpi 丄 132: Even voltage trim circuit 134: Odd voltage trim circuit 140: Page buffer. 15 0: control logic 152: even time trim circuit 154: odd time trim circuit 200: non-volatile memory element 202: substrate ^ 204: memory material layer 206: insulating layer 210: memory array 212: first layer 214: Second layer 220: decoder 230: page buffer 240: control logic 242: first layer control logic • 244: second layer control logic: 300 • non-volatile memory element 320: column decoder 330: page Buffer 340: Control logic 350: Leveling information circuit 352: First level trim information register 36 200849250 27350pif 354: Layer 2 trim information register ADD: Address AW1: Width of active area of even memory unit. AW2: width of the active area of the odd memory cell BLe: even bit line BLeO - BLen-Ι : even bit line BLo: odd bit line BLoO - BLon - Ι : odd bit line c BW1 : even bit line Width BW2: width of odd bit line Ce: parasitic capacitance of even bit line Co · parasitic capacitance of odd bit line GST : ground selection transistor Lgl : channel width of even digital line Lg2 : channel of odd digital line Width MO — M 31: Floating gate transistor G Re · · Parasitic resistance of even bit line • ReCe : RC time constant of even bit line - Ro : Parasitic resistance of odd bit line

RoCo: RC time constant of odd bit lines SST : string selection transistor Td : development time

Tde: first unit current development time Tdo: second unit current development time 37 200849250 2735ϋριί

Tpc: pre-charge time

Tpce: first pre-charge time

Tpco: second pre-charge time

Ts: sensing time

Tse: first sensing time

Tso: second sensing time

Twl: waiting time

Tw2: Waiting time V10: First stylized starting voltage V20: Second stylized starting voltage

Vim: first stylized stop voltage V2n: second stylized stop voltage

VeO: the first stylized starting voltage

Vem: the first stylized stop voltage

Vm: Stylized stop voltage

Vo : Stylized starting voltage V〇0 ··Second stylized starting voltage

Von: second stylized stop voltage

Vpgm: stylized voltage

VrM: read voltage Vrl-2 of the memory cell in the first layer · Read voltage Vr2-1 of the memory cell in the second layer: read voltage Vr2-2 of the memory cell in the first layer : Read voltage Vr3-1 of the memory cell in the second layer: Read voltage of the memory cell in the first layer 38 200849250 27350ριί

Vr3-2: Read voltage of the memory cell in the second layer Vre : Read voltage of the even memory cell Vro · Read voltage of the odd memory cell . Vtrip : Trip voltage

Vvfl: first verification voltage

Vvfl-Ι : memory cell in the first layer, verification voltage Vvfl-2: verification voltage Vvf2 of the memory cell in the second layer: second verification voltage ^ Vvf2-1 : memory unit in the first layer Verification voltage

Vvf2-2: verification voltage Vvf3-1 of the memory cell in the second layer: verification voltage Vvf3-2 of the memory cell in the first layer: verification voltage Vvfe of the memory cell in the second layer: first verification Voltage Vvfo: second verification voltage WL0 - WL31: word line ΔISPP: ISPP increment level 〇 AISPP1: first ISPP increment level • AISPP2: second ISPP increment level: AlSPPe: first ISPP increment level AISPPo: The second ISPP increment level AVw ··the width of the total threshold voltage distribution AVwe: the width of the threshold voltage distribution of the even memory unit AVwo · The width of the threshold voltage distribution of the odd memory unit 39

Claims (1)

200849250 2735Upii X. Patent Application Range: 1. A method for driving a non-volatile memory element, the method comprising: • determining a structural shape and a position of a memory unit to be driven; and based on the determined result The optimized operating conditions drive the memory unit. A method of driving a non-volatile memory device as described in claim 1, wherein the operating conditions include a word line voltage, a bit line voltage, a well voltage, and a timing thereof. 3. The method of driving a non-volatile memory element as recited in claim 1, wherein the operating condition comprises a stylizing/reading/erasing condition. 4. The method of driving a non-volatile memory element according to claim 1, wherein the threshold voltage distribution differs depending on whether the memory unit to be driven is an even memory unit or an odd memory unit, and The width of the even digit line to which the even memory unit is connected is different from the width of the odd digit line to which the (J odd memory unit is connected). 5. The driving non-volatile as described in claim 4 The method of the memory device, wherein the operating condition is a stylized operating condition, and the memory unit is based on the word line to which the memory unit to be driven is connected to the even number of words The odd-numbered memory unit is further programmed with one of a first stylized operating condition and a second stylized operating condition, the first stylized operating condition and the second stylized operating condition being different from each other. The method of driving a non-volatile memory element according to claim 5, wherein driving the memory unit comprises performing an incremental step An hopping pulse stylization (ISPP) method, and the first stylized operating condition includes, and each of the first stylized operating conditions includes a stylized starting power, an ISPP increment level, and a stylized stop 7. The method of driving a non-volatile memory element according to the above-mentioned claim 1, wherein said operating condition is an even number according to a bit line to which said memory unit to be driven is connected The meta-line is also an odd-numbered bit line without (the same, wherein the operating condition is a bit line sensing operation condition, and driving the memory unit includes whether the bit line is an even bit line or an odd bit 兀The sensing operation condition is performed by one of the first sensing operating condition and the second sensing operating condition, the first sensing operating condition and the second sensing operating condition being different from each other. 8. The method of driving a non-volatile memory=piece according to claim 1, wherein the non-volatile memory element has a memory array having at least a first layer and a second layer, and a driving platform Memory The element includes one of a first driving operation condition and a second driving domain, the first driving operating condition and the second driving operating condition, according to the memory unit to be driven belonging to the *second layer Different from each other. μ ', 9 · A non-volatile memory component, comprising: ▲ at least two memory fresh elements, with nuclear structure and distribution characteristics of position changes; and control packet, which is configured to control The respective memory unit 41 200849250 L· / J JVjpil optimizes the operating conditions. The non-volatile memory element and the position described in the ninth item of the range include the word active area saltiness and the oil phase material line. The distance between the two. The four memory units are included in at least two memory layers. A non-volatile memory element comprising: a memory cell array comprising a plurality of memory cells, the plurality of cells, each of which is located in a plurality of word lines and a plurality of bits An intersection of the lines; a column decoder having a domain to the memory to select one of the plurality of word lines; and a phantom, and a 'heart generator' coupled to the a column decoder and configured to output a word pressure, the word line cake having an operational condition of a threshold distribution associated with a selected one of the plurality of cells. In the item of item 12, wherein the distribution of the limited surface is selected according to the plurality of households, whether it is an even memory unit or an odd memory. 14. The non-wave according to claim 13 of the patent application scope. The word line voltage generator includes an X. 兀 兀 兀 even voltage trimming circuit, and the selected one of the plurality of memories 42 Ο Ο 200849250 unit is the even number Outputting the word line power in the first stylized operating condition of the memory unit And an odd voltage trimming circuit that outputs the word line voltage under a second stylized operating condition when the selected one of the home memory cells is the (four) number memory cell. The non-volatile memory element as described in claim 14 wherein the even voltage trimming circuit is configured to generate the word line voltage in a first read/verify condition during a read/verify operation, And the odd voltage trimming circuit is configured to generate the word line overpacking by the second read/verify condition 'the first read/verify condition and the third read/verify condition are different from each other. The non-volatile memory component of claim 13, wherein the non-volatile memory component comprises: an At page buffer coupled to the memory cell array and via a group A bit line associated with the one of the plurality of memory cells reads data associated with the selected one of the plurality of memory cells; and controls a chat, coupled To the page buffer and via The state is selected as described in the cryptographic memory unit - the even number, the body f field is the number of memory cells, and the selected one of the plurality of logger units Associated with the bit line. 17 · For a towel, please (4) 16 items, the control logic includes: an even-numbered trimming circuit configured to be in the plurality The memory 43 is pre-charged with respect to the selected one of the plurality of memory cells for a first pre-charge time when the selected one of the Z/3DUpiI units is the even-numbered unit a meta-line, and for the first cell current development, develop the bit line associated with the selected one of the plurality of memory cells; and an odd time trim circuit configured to Pre-charging the bit associated with the selected one of the plurality of memory cells for a second pre-charge time when the selected one of the plurality of memory cells is the odd-numbered cell Yuan line, and for the second unit current is on The development with time of the plurality of memory cells in a selected one of said bit line associated. 18. The non-volatile memory component of claim 12, wherein the memory cell array has a three-dimensional memory structure; and a threshold voltage distribution is selected according to the plurality of memory cells One is different from the first layer of the memory cell array or the second layer of the memory cell array. C. The non-volatile memory element of claim 18, wherein the word line voltage generator comprises: : first layer control logic configured to be in the plurality of memories The selected one of the body cells is associated with the first layer of the memory cell array using a first stylized operating condition to output the word line voltage; and the second layer of control logic is grouped Using the second stylized operating condition to rotate the selected one of the plurality of memory cells when associated with the second 44 200849250 Z/33UpiI layer of the memory cell array Word line voltage. 20. The non-volatile memory element of claim 19, wherein the control layer is configured to be associated with the first layer of the memory array The first read/verify condition is used to output the word line voltage during a read/verify operation, and the second layer control logic is configured to be associated with the second layer of the memory cell array The second read/verify condition is used to rotate the word line voltage during the read/verify operation of the cascading, the first read/verify condition and the second read/verify condition being different from each other. 45