TW200849250A - Nonvolatile memory device and driving method thereof - Google Patents

Nonvolatile memory device and driving method thereof Download PDF

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Publication number
TW200849250A
TW200849250A TW097106627A TW97106627A TW200849250A TW 200849250 A TW200849250 A TW 200849250A TW 097106627 A TW097106627 A TW 097106627A TW 97106627 A TW97106627 A TW 97106627A TW 200849250 A TW200849250 A TW 200849250A
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memory
voltage
stylized
odd
layer
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TW097106627A
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Chinese (zh)
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TWI501228B (en
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Ki-Tae Park
Ki-Nam Kim
Yeong-Taek Lee
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Samsung Electronics Co Ltd
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/24Bit-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.

Description

200849250 九、發明說明: 【發明所屬之技術領域】 本文中所揭露之本發明大體而 記憶體元件,且更特定士 ϋ疋關於一種非揮發性 I非揮發性記憶體元件之;法非限制)是關於一種驅動 % 【先前技術】 彳 非揮發性記憶體元件即使在 t所儲存之資料。快閃記 為仍保留單元 °咖。由於快閃記憶體元件-4抹; 元,故快閃記憶體元件正廣泛用於電腦、記抖早 此快閃記憶體元件分類成NOR也叫u 、200849250 IX. INSTRUCTIONS: [Technical Field] The invention disclosed herein is generally a memory component, and more particularly a non-volatile I non-volatile memory component; It is about a kind of drive % [Prior Art] 资料 Non-volatile memory components even if stored in t. Flashing is still reserved for the unit ° coffee. Because the flash memory component is -4 sms; the flash memory component is widely used in computers, and the jitter is early. This flash memory component is classified into NOR and also called u.

NAND 〇 N0R 體之間的-個差別是關於如何將記憶體單元連接至位^ 線。-般而1,N0R快閃記憶體元件在高速效能方面有 利,而其在高整合性方面歸因於其高電流消耗而是不利 的。NAND快閃記憶體元件在高整合性方面是有利的,因 Ο 為其比N〇R快閃記憶體元件消耗更小之電流量。 • 圖1為使用雙圖案化技術(double patterning technique, % DPT)之記憶體單元陣列no的電路圖。大體而言,dpt 是克服光微影裝置之限制的圖案化技術。根據DPT,以首 先形成偶數圖案且其後形成奇數圖案之方式來形成記憶體 單元陣列。 圖2A至圖2C為圖1中之字線(wordline)以及位元線 (bitlme)之形狀以及組態的立體說明。具體言之,圖2a為 6 200849250The difference between the NAND 〇 N0R body is about how to connect the memory cell to the bit line. In general, the NOR flash memory device is advantageous in terms of high speed performance, which is disadvantageous in terms of high integration due to its high current consumption. NAND flash memory components are advantageous in terms of high integration because they consume less current than N〇R flash memory components. • Figure 1 is a circuit diagram of a memory cell array no using a double patterning technique (% DPT). In general, dpt is a patterning technique that overcomes the limitations of photolithography devices. According to the DPT, the memory cell array is formed in such a manner that an even pattern is formed first and then an odd pattern is formed. 2A to 2C are perspective views of the shape of the word line and the bit line in FIG. 1 and the configuration. Specifically, Figure 2a is 6 200849250

— — A 說明沿圖1之線A-A’截取的記憶體單元之通道之截面圖。 麥看圖2A’字線之通道寬度根據字線是偶數字線還是奇數 字,而不同。在本文中,偶數字線具有小於奇數字線之通 逞見度Lg2的通道寬度Lgl。圖2B為說明沿圖丨之線 4 B B截取的。己彳思體單元之主動區域(active regi〇n)之寬度 的截面圖。麥看圖2B,偶數記憶體單元之主動區域具有小 於可數體單元之主動區域之寬度AW2的寬度AW1。 圖2C說明奇數位元線以及偶數位元線之金屬寬度。參看 f) 目2C ’偶數位元線具有小於奇數位元線之冑度BW2的寬 度 BW1 〇 圖3為根據DPT製造之記憶體單元之臨限電壓分佈的 圖解說明。參看圖3,根據記憶體單元是偶數單元還是奇 數單元而存在臨限電壓分佈之差異。在本文中,偶數記憶 體單兀意謂連接至偶數字線之記憶體單元,且奇數記憶體 單元意謂連接至奇數字線之記憶體單元。然而,在根據增 里 1¾ 躍脈衝程式化(increinental step pulse programming, (J ISPP)方法而執行程式化操作的典型非揮發性記憶體元件 • 中’程式化操作條件(例如,程式化起始電壓(Vo)、ISPP . 增量級別(ΔΙδΡΡ)以及程式化停止電壓(Vm))不管記 憶體單元是奇數單元還是偶數單元均自總分佈判定。此 處’程式化操作條件滿足以下方程式1以及2。 (方程式1) (方程式2)— — A A cross-sectional view of the channel of the memory cell taken along line A-A’ of Figure 1. The channel width of the 2A' word line of Fig. 2 is different depending on whether the word line is an even number line or an odd number. Herein, the even digit line has a channel width Lgl smaller than the pass visibility Lg2 of the odd digit line. Fig. 2B is a view taken along line 4 B B of the figure. A cross-sectional view of the width of the active regi〇n of the body unit. Referring to Figure 2B, the active area of the even memory cell has a width AW1 that is less than the width AW2 of the active area of the number of body cells. Figure 2C illustrates the metal width of odd bit lines and even bit lines. See f) The 2C 'even bit line has a width BW2 less than the odd bit line BW2 〇 Figure 3 is a graphical illustration of the threshold voltage distribution of the memory cell fabricated according to the DPT. Referring to Fig. 3, there is a difference in threshold voltage distribution depending on whether the memory unit is an even unit or an odd unit. As used herein, an even memory unit means a memory unit connected to an even digit line, and an odd memory unit means a memory unit connected to an odd digit line. However, in a typical non-volatile memory component that performs a programmatic operation in accordance with the incremental step pulse programming (J ISPP) method, the stylized operating conditions (eg, stylized starting voltage) (Vo), ISPP. Incremental level (ΔΙδΡΡ) and stylized stop voltage (Vm) are determined from the total distribution regardless of whether the memory unit is an odd or even unit. Here, the 'programmed operating conditions satisfy the following equations 1 and 2 (Equation 1) (Equation 2)

Vm = V0^mAisPP AVm' = Vm — VQ 7 200849250 其中m是用於達到程式化停止電壓(vm)的程式化 循環之迭代次數。 • 如圖3中所說明,總分佈比偶數記憶體單元以及奇數 記憶體單元之分佈相對廣泛。因此,難以使典型非揮發性 • 記憶體元件具有最佳化程式化時間,因為程式化操作條件 是根據總臨限電壓分佈判定的。此因為程式化時間一般而 $ 言與臨限電壓分佈之寬度成比例。另外,分佈之寬度(△% ) C1 纟1spp操作中變大,且因此程式化循環之迭代次數(m) 相應地增加。此導致記憶體單元之應力增加,從而最終導 致記憶體單元之可靠性劣化。 圖4為習知位元線結構以及感測方法之等效電路圖以 ,相關聯之電壓-時間曲線。如圖2C中所說明,位元線之 覓度根據位元線是奇數位元線還是偶數位元線而不同。因 此’蒼看,4,寄生電阻以及寄生電容亦根據位元線是奇 數位元線還疋偶數位元線而不同。巾#,偶數位元線之寄 〇 i電阻Re A料触讀之寄生電阻R〇,且偶數位元線 •之寄生電容Ce小於奇數位元線之寄生電容Co。此歸因於 '偶數位元線之寬度刪丨於奇數位元線之寬度腹2的事 貫。此可能使RC時間常數根據值元線是奇數位元線還是Vm = V0^mAisPP AVm' = Vm — VQ 7 200849250 where m is the number of iterations of the stylized loop used to reach the stylized stop voltage (vm). • As illustrated in Figure 3, the total distribution is relatively broadly distributed than even memory cells and odd memory cells. Therefore, it is difficult to optimize the typical non-volatile memory components for stylized time because the stylized operating conditions are determined based on the total threshold voltage distribution. This is because the stylization time is generally proportional to the width of the threshold voltage distribution. In addition, the width of the distribution (Δ%) becomes larger in the C1 纟1spp operation, and thus the number of iterations (m) of the stylized cycle is correspondingly increased. This causes an increase in the stress of the memory cell, which ultimately leads to deterioration of the reliability of the memory cell. 4 is an equivalent circuit diagram of a conventional bit line structure and a sensing method, with associated voltage-time curves. As illustrated in Fig. 2C, the bit line width differs depending on whether the bit line is an odd bit line or an even bit line. Therefore, the parasitic resistance and the parasitic capacitance are different depending on whether the bit line is an odd bit line or an even bit line. Towel #, even bit line 〇 i resistance Re A material touch parasitic resistance R 〇, and even bit line • Parasitic capacitance Ce is smaller than the parasitic capacitance Co of the odd bit line. This is attributed to the fact that the width of the even bit line is deleted from the width of the odd bit line. This may make the RC time constant based on whether the value element line is an odd bit line or

偶數位元線而不同。為了枝描述,假定偶數侃線之RC 時間常數(ReCe)大於奇數位元線之Rc時間常數 (RoCo )。 結果,感測操作條件(例如,預先充電時間、開發時 8 ΟThe even bit lines are different. For the branch description, it is assumed that the RC time constant (ReCe) of the even-numbered turns is greater than the Rc time constant (RoCo) of the odd-numbered lines. As a result, the operating conditions are sensed (for example, pre-charging time, development time 8 Ο

Cj 亦即,在典型非揮發性記憶體元件之感測操作條件 下,感測時間Ts經判定以致其包含相對長於偶數位元線之 預先1電時間的奇數位元線之預先充電時間Tpc以及相對 長於可數位元線之開發時間的偶數位元線之開發時間 Td。如圖4中所說明,等待時間Twl以及Tw2分別發生 於偶數位元線以及奇數位元線中。亦即,典型非揮發性記 體元件不能最佳化感測時間。 再次參看圖4,在偶數位元線BLe之預先充電操作 中’偶數位元線BLe比奇數位元線BLo快地預先充電。然 而’預先充電時間丁pC受奇數位元線BL〇之預先充電時間 限制。在奇數位元線BLo之開發操作中,奇數位元線bl〇 200849250 間(development time))將根據位元線是偶 奇數位元線而不同。在本文中,充電_是=^ 線上升直至預先充電電壓(例如,電源電 的時間。開發時狀指使位元線電壓自縣充^電單降篆 M (trip voltage) Vtrip f ^ 〇 為偶數位猶,貞彳誠充€_短於奇触 充 _間,且開發時間長於奇數位讀之開發時間。=充 右位兀線為奇數位元線,卿先充電時間長於触位元線 之預先充電時間,且開發時間短於偶數位元線之開發時 間。—,典麵揮發性記憶體元件不管位元線是偶數位 凡線逛是奇數位元線均以相同感測操作條件操作。 比偶數位元線BLe快地開發。然而,在此狀況下,單元電 流開發時間Td受偶數位元線BLe之開發時間限制。此導 9 200849250 致非揮發性記憶體元件之讀取/驗證特性降級。因此需要改 良之非揮發性記憶體元件結構。 【發明内容】 • 本發明之貫施例提供一種基於臨限電壓分佈之差異而 最佳化效能的非揮發性記憶體元件以及方法。 • 树明之―實施例提供-種鶴麵發性記憶體元件 之方法&amp;包含.判疋待驅動之記憶體單元之結構位置; 減使關定結絲錄據記㈣單元之臨限電壓分佈的 操作條件驅動記憶體單元。 、、本發明之另-實施例提供—種非揮發性記憶體元件。 所述非揮發性記憶體元件包含:記憶體單元陣列,其包含 多個記憶體單元,多個記憶體單元中之每一者位於多個字 線,多個位元線之相交處;列解碼器,其輕接至記憶體單 兀陣=且經組態以選擇多個字線中之一者;以及字線· 產生為,其I禺接至列解碼器且經組態以輸出字線電麼 據與多個記憶體單元中之一選定者相關聯的 〇 臨限电壓分佈之操作條件。 : 【實施方式】 : ,諸圖經包含以提供對本發明之進—步 之例示性書部分。圖式說明本發明 以^ 連同描述用來解釋本發明之原理。 糾妙Γ看隨附圖式較詳細地描述本發明之較佳纽 本文中所陆、十、— ⑽式具體化且不應理解為限於 处貫施例。實情為,提供此等實施例以使得 10 200849250 Z/Jjupu 本揭露案將是透徹且完整的,且將向熟習此項技術者充分 傳達本發明之範疇。 根據本發明之-實施例的非揮發性記憶體元件判定待 ..驅動之記憶體單元的結構形狀以及位置,且因此根據判定 • 結果而以適合於待驅動之記憶體單元之分佈特性的操作條 件操作。其中結構形狀以及位置包含字線之寬度、主動區 域⑽ve region)之寬度與高度以及兩個相鄰字線之間的距 離。因此,有可能改良臨限電壓分佈特性以及由記憶體單 兀之結構形狀以及位置引起的效能降級。其中操作停件包 含字線電壓、位元線電壓、井電壓(wellv〇ltage)以及豆 時序。 〃 可以適合於根據記憶體單元是偶數單元還是奇數單元 的記憶體單元之分佈特性的獨立方式來驅動根據第一實施 例之非揮發性記憶體元件。在本文中,根據記憶體單元連 接至偶數字線還是奇數字線而判定記憶體單 奇數。亦即,在下文中,連接至偶數字線之記憶體單元將 〇 被稱作偶數記憶體單元,且連接至奇數字線之記憶體單元 * 將被稱作奇數記憶體單元。 • 圖5為根據本發明之第一實施例之非揮發性記憶體元 件100的功能方塊圖。圖5之非揮發性記憶體元件1〇〇為 NAND㈣記憶體元件。然而,對於熟習此項技術者而言 很明顯,本發明亦可適用於其他記憶體元件(例如,遮罩 唯4 g己fe體(mask read only memory,MROM)、可程式化 ROM ( PROM )、鐵電式隨機存取記憶體(ferr〇dectric 11 Ο Ο 200849250 r^«;rmory, FRAM&gt;N0R ^} nand 5 ’ _發性記憶體元件⑽包含記憶體單元 ’、列解碼器120、字線電壓產生器13〇、頁面緩衝 =士以及控制邏輯150。經由雙圖案化技術⑽丁)f 肴,明之記憶體單元陣列11〇。非揮發性記憶體元件_ ,據記憶體單元是偶數單元還是奇數單元而以不同方式操 f。為此目的,本發明之字線電壓產生器、130在程式似 f取操作_提供適合於奇數記憶體單元以及偶數 ^之^限電壓分佈的各別程式化/讀取操作條件。控制= 輯 麵取/驗證操作期間提供適合於奇數位元線以及 偶數位兀線的各別感測操作條件。此處,驗 化操作之一部分。 卞F与%式 記憶體單元陣列110包含多個記憶體單元,且 圖1之記憶體單元陣列實質上相同的構造。記憶體單元陳 列110中所包含之多個記憶體單元配置於多個 至wL31與多個位元線BLe〇至BLen i以及 BLon-1彼此交叉的區域處。記憶體單元中 1 位元資料或η位元資料,其中n為2或2以上之整:存1 多個字線WL〇至WL31分成偶數字線WL〇、 WL2、…、WL30以及奇數字線wu、WL3、...、^ 由於使用DPT ’來製傷記憶體單元陣列11〇, ° 勵、肌2、...、WL3〇之寬度不同於奇數字線=線 WL3、…、WL31之寬度。在下文中,為了方便描述,假 12 ΟCj, that is, under the sensing operation condition of a typical non-volatile memory element, the sensing time Ts is determined such that it includes a pre-charging time Tpc of an odd-numbered bit line that is relatively longer than the even-numbered bit line, and The development time Td of an even bit line that is relatively longer than the development time of the countable bit line. As illustrated in Fig. 4, the waiting times Tw1 and Tw2 occur in even bit lines and odd bit lines, respectively. That is, typical non-volatile character elements cannot optimize the sensing time. Referring again to Fig. 4, the even bit line BLe is precharged faster than the odd bit line BLo in the precharge operation of the even bit line BLe. However, the 'precharge time □pC is limited by the precharge time of the odd bit line BL〇. In the development operation of the odd bit line BLo, the odd bit line bl 〇 200849250 development time will be different depending on whether the bit line is an even odd bit line. In this paper, the charge_ is =^ line rises until the pre-charge voltage (for example, the time of the power supply. The development time refers to the bit line voltage from the county charge voltage M (trip voltage) Vtrip f ^ 〇 even Digital position, 贞彳 充 充 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The pre-charging time, and the development time is shorter than the development time of the even-numbered bit line.—, the surface volatile memory component operates regardless of the bit line, and the odd bit line operates with the same sensing operation condition. Developed faster than the even bit line BLe. However, in this case, the cell current development time Td is limited by the development time of the even bit line BLe. This guide 9 200849250 causes read/verify characteristics of non-volatile memory elements Degraded. Therefore, there is a need for an improved non-volatile memory element structure. [Invention] The present invention provides a non-volatile memory element and method for optimizing performance based on a difference in threshold voltage distribution. • Shumingzhi-The embodiment provides a method for planting a facial memory component and includes determining the structural position of the memory cell to be driven; reducing the threshold voltage of the unit (4) unit The distributed operating conditions drive the memory unit. Further embodiments of the present invention provide a non-volatile memory element. The non-volatile memory element includes: a memory cell array including a plurality of memory cells Each of the plurality of memory cells is located at a plurality of word lines, where the intersection of the plurality of bit lines; the column decoder is lightly coupled to the memory bank and is configured to select the plurality of word lines One of the words; and the word line is generated as the threshold voltage associated with the selected one of the plurality of memory cells </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; See the description of the hair in more detail with the accompanying drawings. The preferred embodiment of this document is embodied in the text, and the formula (10) is not to be construed as being limited to the embodiment. In fact, the embodiments are provided such that the disclosure of 10 200849250 Z/Jjupu will be thorough and complete. The scope of the present invention will be fully conveyed to those skilled in the art. The non-volatile memory element according to the embodiment of the present invention determines the structural shape and position of the memory unit to be driven, and thus is determined according to the determination. • The result is operated with operating conditions appropriate to the distribution characteristics of the memory cells to be driven, wherein the structure shape and position comprise the width of the word line, the width and height of the active region (10) ve region, and between two adjacent word lines. distance. Therefore, it is possible to improve the threshold voltage distribution characteristics and the performance degradation caused by the structural shape and position of the memory unit. The operation stop includes the word line voltage, the bit line voltage, the well voltage (wellv〇ltage), and the bean timing. 〃 The non-volatile memory element according to the first embodiment may be adapted to be driven in an independent manner according to the distribution characteristics of the memory cells in which the memory cells are even cells or odd cells. In this paper, the memory odd number is determined based on whether the memory unit is connected to an even digit line or an odd digit line. That is, hereinafter, a memory cell connected to an even digit line will be referred to as an even memory cell, and a memory cell * connected to an odd digit line will be referred to as an odd memory cell. Figure 5 is a functional block diagram of a non-volatile memory element 100 in accordance with a first embodiment of the present invention. The non-volatile memory element 1 of Figure 5 is a NAND (four) memory element. However, it will be apparent to those skilled in the art that the present invention is also applicable to other memory components (eg, mask read only memory (MROM), programmable ROM (PROM)). Ferroelectric random access memory (ferr〇dectric 11 Ο Ο 200849250 r^«;rmory, FRAM&gt;N0R ^} nand 5 ' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The line voltage generator 13 页面, the page buffer = 士 and the control logic 150. Via the double patterning technique (10), the memory cell array 11 〇. The non-volatile memory element _ , according to the memory unit is an even unit The odd-numbered cells are also operated in different ways. For this purpose, the word line voltage generator 130 of the present invention performs a f-fetch operation to provide separate programs suitable for odd-numbered memory cells and even-numbered voltage distributions. Control/read operation conditions. Control = Individual sensing operation conditions suitable for odd bit lines and even bit lines during the face selection/verification operation. Here, part of the verification operation. 卞F and % Memory list The array 110 includes a plurality of memory cells, and the memory cell arrays of FIG. 1 have substantially the same structure. The plurality of memory cells included in the memory cell array 110 are disposed in a plurality of to wL31 and a plurality of bit lines BLe. 〇 to the area where BLen i and BLon-1 cross each other. The 1-bit data or η-bit data in the memory unit, where n is 2 or more than 2: Store more than 1 word line WL〇 to WL31 into even The digital lines WL〇, WL2, ..., WL30 and the odd digit lines wu, WL3, ..., ^ are used to damage the memory cell array 11〇, °, muscle 2, ..., WL3 by using DPT ' The width is different from the width of the odd digit line = line WL3, ..., WL31. In the following, for convenience of description, the fake 12 Ο

200849250 厶 / J丄 定偶數位元線BLeO至BLen-1之線寬比奇數位元線BL〇0 至BLon-1之線寬窄。因此,記憶體單元陣列11〇之記憶 體單元主要分類成偶數記憶體單元以及奇數記憶體單元。 記憶體單tl陣列11〇之每一單元串(亦被稱作nand 串)包含多個浮動閘極電晶體M〇至M31。多個浮動閘電 晶體M0至M31串聯連接於配置於同一串中的串選擇電晶 體sst與接地選擇電晶體GST之間。多個字線WL〇至 WL31經配置以交叉單元串(亦即,NAND串)。字線WL0 至WL31分別連接至每一 串之對應浮動閘極電晶體 M0至M31的控制閘極。經由字線WL〇至WL31施加程 式化/讀取電壓,藉此將資料程式化至對應浮動閘極電晶體 M0至M31或自對應浮動閘極電晶體M〇至M31讀取資 料。。非揮發性記憶體元件更包含用以將資料程式化至記憶 體單元陣列110或自記憶體單元陣列110讀取資料的頁 緩衝器140。 ' 列解碼器120解碼自列位址缓衝器(未圖示)供應之 ,位j以選擇多個字線WL〇至WL31中之至少一者了接 著將字線電壓施加至敎字線。此處,自字線電壓產生器 130供,字線電壓。列位址對應於選定字線之位置資料。 更具體^,列位址包含表示敎字線是傭字線 數字線的位置資料。 α 义。字線電壓產生器130產生待供應至選定字線之字線電 ι此處,字線電壓在程式化操作期間可為程式 及驗證電壓,在讀取操作期間可為讀取電壓,且在抹= 13 200849250 作期間可為抹除電壓。詳言之,本發明之字線電壓產生器 (trimcircuit) 132 當選定字線為偶數字線時,偶數電壓配平電路132調 ,字線電壓以便將第—程式化電壓、第—驗 壓供應至敎字線。此處,第—程式化“ ^ Ο u 二讀取電壓適合於偶數記憶體單元之臨限 :Γ:ΐέ:ί?在以下參看圖6較充分地加以描述。 整字二將Ζ數予線時’奇數電壓配平電路134調 ==選::r此處,第二程‘ 電壓二料狀臨限 根據記憶體單元是偶數記憶 1 充=也加以描述: 元’本發明之字線錢產生器13G 可數記憶體單 元之各別臨限電壓分佈触的化=於對應記憶體單 取電壓供應至敎字線。 ;、驗證電壓或讀 頁面緩衝器140在讀取/猞切 ®後衝裔W0在控制邏輯15〇 =二制下位元線。將在讀取 輸入/輸出電路(未圖示)輸出至外側由 頃取之賁料輸出至通過/失敗偵測電路(夫^木/月間 ==定在程式化操作期間自頁面二:^ 之貝枓於通過資料。通過/失敗_電路將通過= 200849250 敗信=程式化操作之備測結果)輸出 電壓產生哭1以;^ 讀取/抹除操作期間控制字緣 口口 130以及頁面緩衝器14〇。控 4 =,=輪產生㈣之偶數她二= ⑶以及讀配平魏u4 +的_者 :¾路 發明之控制邏輯15〇包含 、疋。之,本 偶數時間配平兩路^ 有不㈣兀線感測操作條件的 夫吾以及奇數時間配平電路⑸。以下 Ο Ϊ1電時間以及單元電流開發時間描述此等不2 兀線感測操作條件。 &lt;心寻不问位 -予配平電路152控·面緩衝11刚以致以第 卿至第—單元電流開發時間她 百而驗π 同樣地,奇數時間配平電路154控制 、、、’衝斋14〇以致以第二預先充電時間以及第—單— =間感測奇數位元線一 7較充分地加以描述。 〃耆圖 Ο ::邏輯150控制頁面緩衝器140以致根據對應位元 以線遇是奇數位元線而以適當之預先充電時間 電流開發時間感測位元線。亦即,控制邏輯^ =面緩衝1114G以根據餘線是偶數低線還是奇數 位兀線而以不同位元線朗操作條件驅動位元線。 非揮發性記憶體元件100因此對於 =隱體單元最佳化操作。具體言之,;心 二=件100中,可藉由根據字線是偶數字線還是奇 、,泉而對於臨限電壓分佈最佳化之程式化電壓、驗證電^ 15 200849250 讀取電壓驅動字線,且可藉由根據位元線是偶數 -^ 1立線 是奇數位元線而最佳化之預先充電時間以及單元電炉 ^ 時間驅動位元線。 t 即使記憶體單元根據記憶體單元是偶數記憶體單- 是奇數記憶體單元而具有不同臨限電壓分佈特性,~ ^ 性記憶體元件100仍對於偶數記憶體單元或奇數吃.产軍, 元之臨限電壓分佈裁剪操作,從而引起程式化/讀取^體單 Ο Ο 效能改良。以下參看圖6至圖8之論述提供關於在非二 性記憶體元件100中如何改良程式化/讀取/抹除效能 = 多細節。 乂 ^圖6A至圖6C為圖5之非揮發性記憶體元件1〇〇之带 壓調整方法的圖解說明。圖6A說明根據記憶體單元是^ 數記憶體單元還是奇數記憶體單元的臨限電壓分佈特=。 參看圖6A’奇數記憶體單元之臨限電壓分佈相對高=偶數 =憶體單元之臨限電壓分佈。儘管圖6A說明奇數記憶體 單元之臨限電壓分佈高於偶數記憶體單元之臨限電壓分 佈’但本發明並不限於此狀況。 非揮發性記憶體元件100可以分別根據偶數記憶體單 分佈以及奇數記憶體單元之分佈而最佳化的程式化摔 二條件而操作。非揮發性記憶體元件10。可藉由增量階^ 式化(Ispp)方法峰式化。根據ISPP方法,程式 逐二f Vpgm在程錢週期之重複細自程錢起始電屢 止預想寬之增量電壓增量地增加至程式化停200849250 厶 / J丄 The line width of the even bit lines BLeO to BLen-1 is narrower than the line width of the odd bit lines BL〇0 to BLon-1. Therefore, the memory cells of the memory cell array 11 are mainly classified into even memory cells and odd memory cells. Each cell string (also referred to as a nand string) of the memory single-tray array 11A includes a plurality of floating gate transistors M〇 to M31. The plurality of floating gate transistors M0 to M31 are connected in series between the string selection transistor sst and the ground selection transistor GST arranged in the same string. A plurality of word lines WL 〇 to WL31 are configured to cross the cell strings (i.e., NAND strings). Word lines WL0 to WL31 are respectively connected to the control gates of the corresponding floating gate transistors M0 to M31 of each string. The programming/reading voltage is applied via word lines WL 〇 to WL 31, whereby the data is programmed into the corresponding floating gate transistors M0 to M31 or read from the corresponding floating gate transistors M 〇 to M 31. . The non-volatile memory component further includes a page buffer 140 for programming data into the memory cell array 110 or reading data from the memory cell array 110. The column decoder 120 decodes the supply from a column address buffer (not shown), bit j to select at least one of the plurality of word lines WL 〇 WL WL 31 and then apply the word line voltage to the 敎 word line. Here, the word line voltage is supplied from the word line voltage generator 130. The column address corresponds to the location data of the selected word line. More specifically ^, the column address contains the location data indicating that the 敎 word line is the servant word line digit line. α meaning. The word line voltage generator 130 generates a word line to be supplied to the selected word line. The word line voltage can be a program and a verify voltage during the staging operation, and can be a read voltage during the read operation, and = 13 200849250 The voltage can be erased during the process. In detail, the word line voltage generator 132 of the present invention, when the selected word line is an even digital line, the even voltage trim circuit 132 adjusts the word line voltage to supply the first stylized voltage and the first voltage to敎 word line. Here, the first-stylized "^ Ο u two read voltages are suitable for the threshold of even-numbered memory cells: Γ:ΐέ: ί? is described more fully below with reference to Figure 6. When the 'odd voltage trimming circuit 134 adjust == select:: r here, the second pass 'voltage two material threshold according to the memory unit is even memory 1 charge = also describe: yuan 'the word line money of the invention The voltage of each of the threshold voltage distributions of the 13G countable memory cells is supplied to the 敎 word line in the corresponding memory. The verify voltage or the read page buffer 140 is read/cut. W0 is in the control logic 15〇=2nd lower bit line. It will output the input/output circuit (not shown) to the outside and output it to the pass/fail detection circuit (Fumu/Moon) == is determined during the stylization operation from page 2: ^ 之 枓 通过 通过 。 。 。 通过 通过 通过 通过 通过 2008 2008 2008 2008 2008 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = During the erase operation, the control margin port 130 and the page buffer 14 are controlled. Control 4 =, = rotation (4) The even number of her two = (3) and the reading of the Wei Wei u4 + _: 3⁄4 road invention control logic 15 〇 contains, 疋., this even time balance two ways ^ There is no (four) 兀 line sensing operating conditions of Fu Wu And odd-time trimming circuit (5). The following Ο1 electric time and unit current development time describe these non-twist line sensing operating conditions. &lt;Heart-seeking-bit-to-trim circuit 152 control · face buffer 11 just to the first Qing to the first - unit current development time, she will test π. Similarly, the odd time trim circuit 154 controls,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, A more fully described one. 〃耆 Ο :: Logic 150 controls the page buffer 140 such that the time sense bit line is developed with the appropriate precharge time current according to the corresponding bit line being an odd bit line. That is, the control logic = face buffer 1114G to drive the bit line with different bit line operating conditions depending on whether the remaining line is an even low line or an odd bit line. The non-volatile memory element 100 is therefore the most Jiahua Specifically, in the heart==100, can be read by the stylized voltage optimized for the threshold voltage distribution according to whether the word line is an even digital line or an odd, spring. The voltage drives the word line, and can be optimized by the pre-charging time and the unit electric furnace according to the bit line being an even number - ^ 1 the vertical line is an odd bit line. t Even if the memory unit is based on memory The body unit is an even-numbered memory single--is odd-numbered memory unit with different threshold voltage distribution characteristics, and the ~^ memory element 100 is still for even-numbered memory units or odd-numbered eating. , causing stylized/reading body Ο 效能 performance improvement. The discussion below with reference to Figures 6 through 8 provides information on how to improve stylization/read/erase performance in non-sexual memory component 100 = more detail.乂 ^ Figure 6A to Figure 6C are diagrammatic illustrations of the method of adjusting the pressure of the non-volatile memory element 1 of Figure 5. Fig. 6A illustrates a threshold voltage distribution according to whether the memory unit is a memory unit or an odd memory unit. Referring to Fig. 6A', the threshold voltage distribution of the odd-numbered memory cells is relatively high = even = the threshold voltage distribution of the memory cells. Although Fig. 6A illustrates that the threshold voltage distribution of the odd-numbered memory cells is higher than the threshold voltage distribution of the even-numbered memory cells, the present invention is not limited to this case. The non-volatile memory component 100 can operate in accordance with a stylized fall condition optimized for even memory single distribution and odd memory cell distribution, respectively. Non-volatile memory component 10. It can be peaked by the incremental order (Ispp) method. According to the ISPP method, the program is repeated twice as long as the V Vggm repeats the fine-grained self-starting of the money cycle.

包I。此1SPP方法揭露於題為“A 3.3V 32Mb NAND 16 200849250 么 / j jvyμι丄Package I. This 1SPP method is disclosed in the article entitled "A 3.3V 32Mb NAND 16 200849250 / j jvyμι丄

Flash Memory with Incremental Step Pulse Programming Scheme” , IEEE Journal of Solid-State Circuits,第 30 卷, 第 11 期,1995 年 11 月,第 1149至 1156 頁(Snh,Kang-De〇g 等人)的文件中,此文件以引用的方式併入本文中。 首先,將描述奇數記憶體單元之程式化方法。圖6B : 說明根據偶數記憶體單元之臨限電壓分佈的程式化操作條 件。在本文中,程式化操作條件包含程式化起始電壓Ve〇、 ISPP增量級別AlSPPe、程式化停止電壓vem以及第一驗 〇 證電壓Vvfe。程式化循環之最大次數可為m。偶數記憶體 單元之臨限電壓分佈滿足以下方程式3以及4。Flash Memory with Incremental Step Pulse Programming Scheme", IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, November 1995, pages 1149 to 1156 (Snh, Kang-De〇g et al.) This document is incorporated herein by reference. First, a stylized method of odd memory cells will be described. Figure 6B: illustrates the stylized operating conditions according to the threshold voltage distribution of even memory cells. The operating conditions include a stylized starting voltage Ve〇, an ISPP increment level AlSPPe, a stylized stop voltage vem, and a first verification voltage Vvfe. The maximum number of stylized cycles can be m. The threshold voltage of the even memory unit The distribution satisfies Equations 3 and 4 below.

Vem ~ VeO + mAISSPe AVwe = Vem - VeO - _—(方程式3) .....(方程式4)Vem ~ VeO + mAISSPe AVwe = Vem - VeO - _ - (Equation 3) ..... (Equation 4)

U …爹看圖6B,以第-程式化操作條件程式化偶數記憶體 单兀。此處,第-程式化操作條件包含第—程式化起始 壓VeO、第-ISPP增量級別薦咖、第一程式化停止+ 壓Vem以及第一驗證電壓Vvfe。此第—程式化“ 可經設計以對於偶數記憶體單元之臨限電壓分 的。可自偶數電壓配平電路132提供第一二 件。在對錄記單元之料倾作_,料^以^ -贈增量級別△聊6依序增加之電壓位準的程 壓Vpgm供應至對應字線。 飞电 圖6C說明根據奇數記憶體單元之臨限電屬分佈的程 17 200849250 厶/ J jv^/μ丄丄 式化操作條件。在本文中,程式化操作條件包含第二程式 化起始電壓V〇0、第二ISPP增量級別…卯%、第二程式 化停止電壓Von以及第二驗證電壓Vvf〇。程式化循環之最 大次數可為η。第二程式化起始電壓彻高於第—程式化 起始電壓獅。然而,不必要使第二程式化起始電壓ν〇〇 高於第一程式化起始電壓Ve0。奇數記憶體單元之臨限電 壓分佈滿足以下方程式5以及6。U ... see Figure 6B to program the even memory unit with the first stylized operating conditions. Here, the first stylized operation condition includes a first stylized start pressure VeO, a first-ISPP increment level recommendation coffee, a first stylized stop + voltage Vem, and a first verification voltage Vvfe. This first-stylized "can be designed to be used for the threshold voltage of the even-numbered memory cells. The first two pieces can be supplied from the even-numbered voltage trimming circuit 132. In the material of the recording unit, the material is _, ^^^ -Incremental level △ Talk 6 sequentially increases the voltage level of the voltage level Vpgm is supplied to the corresponding word line. The flying picture 6C illustrates the distribution of the finite charge according to the odd memory unit. 200849250 厶/ J jv^ /μ丄丄化 operating conditions. In this paper, the stylized operating conditions include a second stylized starting voltage V〇0, a second ISPP increment level...卯%, a second stylized stop voltage Von, and a second verification. The voltage Vvf〇. The maximum number of stylized cycles can be η. The second stylized starting voltage is higher than the first stylized starting voltage lion. However, it is not necessary to make the second stylized starting voltage ν〇〇 higher than The first stylized starting voltage Ve0. The threshold voltage distribution of the odd memory cells satisfies the following Equations 5 and 6.

Von = V〇0 + nAISSPo , -..............................(方程式5) AVwo = Von - VoO . ....................................6) 參看圖6C’以第二程式化操作條件程式化奇數記憶體 單元。此處,第二程式化操作條件包含第二程式化起始電 壓VoO、第一 ISPP增量級別、第二程式化停止電 壓Von以及第二驗證電壓Vvf0。此第二程式化操作條件可 經設計以對於奇數記憶體單元之臨限電壓分佈為最佳的。 可自奇數電壓配平電路134提供第二程式化操作條件。在 對偶數記憶體單元之程式化操作期間,將具有以第二 增量級別AISPPo依序增加之電壓位準的程式化電壓v 供應至對應字線。 m 參看圖6A以及圖6B,視奇數記憶體單元以及偶數圮 憶體單元之臨限電壓分佈而在各別程式化操作條件下執4一 非揮發性記憶體元件100之程式化操作。亦即,程式化= 始電壓VeO以及V〇0、ISPP增量級別以及_冲〇、 18 200849250 程式化停止電壓Vem以及Von,以及程式化循環之最大次 數m以及η根據待驅動之€ ’fe體早元是奇數記憶體單元卞 是偶數記憶體單元而不同。 在圖3中所說明之習知非揮發性記憶體元件中,在程 式化操作中,基於總臨限電壓分佈之寬度AVw而判定程 式化操作條件。然而,在本發明之實施例中,在適合於^ 驅動之記憶體單元之臨限電壓分佈特性的程式化操;條件 下執行非揮發性記憶體元件100之程式化操作。詳言之, 分別基於偶數記憶體單元之臨限電壓分佈之寬度AVwe以 及奇數記憶體單元之臨限電壓分佈之寬度^乂^而判定程 式化操作條件。因此,本發明非揮發性記憶體元件1〇〇之 程式化時間短於基於總臨限電壓分佈之寬度AVw而判定 =式化知作條件的習知非揮發性記憶體元件之程式化時 =另外,在本發日狀實_巾,科化彳轉之次數可小 古白知非揮發性記憶體元件之程式化循環之次數。因此, 百可能改良記憶體單元之可靠性。 !〇〇二财發明之—實施例之非揮發性記憶體元件 1㈨的頃取電壓之圖解說明。來 雷厭八/士士新/有圖7,記憶體單元之臨限 刀佈主要分成偶數記憶體單 數記憶體單元之臨限電壓分^^之臨限錢分佈以及奇 憶體單布。如圖7中所說明,奇數記 収早;^之臨限電壓分佈相對高 一 電壓分佈。因此,在本發明厂數記憶體單兀之臨限 ”料決策之讀取電壓根據記憶體元件中丄用 延是奇數記憶體單元而不同。収早兀疋偶數圮憶體單70 舉例而言,奇數記憶體單元 200849250 jL / d^kjull 之讀取電壓Vro吝於彳足毒 本文中,可分別自。字線憶體單元之讀取電麗加。在 以及132施加讀取# Ί生$ 130之電麼配平電路134 电缓Vro以及v 在非揮發性記愔― 1GG中,待供應至 元而彼此列。又,數記憶體單元還是偶數記憶體單 o o 致抹除電壓根據記_體元件_可經實施以 憶體單元恤此^早R奇數記憶料元還是偶數記 揮發為λ於絲據本發明之—實施例之非 圖解說明。不管心# 3位兀線感,剌電壓時間曲線之 等地應用如® 4巾所^偶數位元線還是奇數位猶均同 平方法。然而的用於位元線感測之習知時間配 數位元線奴餘从目8Β,絲触猶是偶 (例如,預先充料間的位元線感測操作條件 你* ^ ’在非揮發性記憶體元件100之讀取/驗證摔 作^執_元線感測操作以自記憶體單元讀取資^ = :、、、!測操作主要分成位元線預先充電部分、位元線開發 科以及㈣感測部分。在位元線預先充電部分期間純 、、泉預先充黾至預定電壓位準。在位元線開發部分期間, 仇7L線電壓根據連接錄元線之記憶鮮元是切斷單元還 是接通單元而改變。 舉例而言,若記憶體單元為接通單元,則在位元線中 20 200849250 Z/jDUpil 積聚之電荷經由記憶體單元放電,以使 二,若記憶體單元為切斷單元,則使位:電壓降 預定電壓。在資料感測部 ^使位辑維持於 之電壓而判定連接至 / 曰由感測所開發位元 切斷單元。位几線之記憶體單元為接通單元還是 平方法。參看圖5圖2 ^用於感測偶數位元線之時間配 Ο 配千方去如下。偶數時間配平電路】 =線之%間 :::。η第-感測操作條件包含第一預先; 乂及弟-早元電流開發 π間Tpce 知非揮發性記憶體元件之:所說明之習 於在非揮發性記憶體元件咖 :s d。因此,由 等待時間(TW1),故總感測、了不^要圖4中所說明之 ο 習知發性記憶體元件之_時。:4中所說明之 看圖===:線之時間配平方法。參 下。奇數時間配平電路線之時間配平方法如Von = V〇0 + nAISSPo , -........................ (Equation 5) AVwo = Von - VoO . ...................................6) See Figure 6C' stylized with the second stylized operating conditions Odd memory unit. Here, the second stylized operating condition includes a second stylized starting voltage VoO, a first ISPP increment level, a second stylized stop voltage Von, and a second verify voltage Vvf0. This second stylized operating condition can be designed to be optimal for the threshold voltage distribution of odd memory cells. A second stylized operating condition can be provided from the odd voltage trim circuit 134. During the stylized operation of the even memory cells, a stylized voltage v having a voltage level sequentially increased by the second incremental level AISPPo is supplied to the corresponding word line. m Referring to Figures 6A and 6B, the stylized operation of the non-volatile memory element 100 is performed under respective stylized operating conditions, depending on the threshold voltage distribution of the odd-numbered memory cells and the even-numbered memory cells. That is, stylized = start voltage VeO and V〇0, ISPP increment level and _ rush, 18 200849250 stylized stop voltage Vem and Von, and the maximum number m of stylized cycles and η according to the 'fee to be driven' The body early element is an odd memory unit and an even memory unit. In the conventional non-volatile memory element illustrated in Fig. 3, in the program operation, the program operation condition is determined based on the width AVw of the total threshold voltage distribution. However, in an embodiment of the invention, the stylized operation of the non-volatile memory element 100 is performed under the conditions of a stylized operation suitable for the threshold voltage distribution characteristic of the memory cell. In detail, the programmed operating conditions are determined based on the width AVwe of the threshold voltage distribution of the even-numbered memory cells and the width of the threshold voltage distribution of the odd-numbered memory cells, respectively. Therefore, the stylized time of the non-volatile memory element 1 of the present invention is shorter than the stylized time of the conventional non-volatile memory element based on the width AVw of the total threshold voltage distribution. In addition, in this issue, the number of times that the number of revolutions can be reduced can be counted by the number of non-volatile memory components. Therefore, it is possible to improve the reliability of the memory unit. 〇〇 二财发明—A non-volatile memory component of an embodiment 1 (9) is a graphical illustration of the voltage taken. To Lei 八/士士新/有图7, the threshold of the memory unit The knives are mainly divided into the even-numbered memory unit memory unit's threshold voltage distribution ^^'s marginal money distribution and odd memory single cloth. As illustrated in Fig. 7, the odd number is recorded early; the threshold voltage distribution is relatively high with a voltage distribution. Therefore, in the threshold of the memory of the invention, the read voltage of the material decision is different according to the delay of the memory component in the memory component. , odd memory unit 200849250 jL / d ^ kjull read voltage Vro 彳 彳 毒 毒 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文 本文130 electric power trimming circuit 134 electric slow Vro and v in non-volatile memory - 1GG, to be supplied to the yuan and each other. Also, the number of memory cells or even memory single oo erase voltage according to the record The component_ can be implemented to reproduce the memory cell or the even-numbered memory cell or the even-numbered volatilization to λ. According to the invention, the non-illustrative description of the embodiment. The application of the curve, such as the *4 towel, the even-numbered bit line or the odd-numbered bit, is the same as the flat method. However, the conventional time-matching bit line for the bit line sensing is from the 8th, the silk touches. Is even (for example, the pre-charged bit line senses the operating conditions you *^ 'Reading/verifying the non-volatile memory component 100's operation/compensation_yuan line sensing operation to read the memory from the memory unit ^ = :, , !! The measurement operation is mainly divided into the bit line pre-charging part, The bit line development section and (4) the sensing part. During the pre-charging part of the bit line, the spring is pre-charged to a predetermined voltage level. During the development of the bit line, the voltage of the 7L line is based on the connected recording line. The memory fresh element is changed by cutting the unit or turning on the unit. For example, if the memory unit is a turn-on unit, the charge accumulated in the bit line 20 200849250 Z/jDUpil is discharged via the memory unit, so that two If the memory unit is a cut-off unit, the voltage is lowered by a predetermined voltage. The data sensing unit maintains the voltage at the voltage and determines that the bit is connected to the unit by the sensing unit. Whether the memory unit of several lines is a turn-on unit or a flat method. See Figure 5 and Figure 2 for the time-matching of the even-numbered bit lines. The matching squares are as follows. Even-time trimming circuit] = % of the line:: : η first-sensing operating conditions include first First; 乂 and brother - early element current development π between Tpce know non-volatile memory components: the description of the non-volatile memory components in the coffee: sd. Therefore, by waiting time (TW1), the total sense Measured, not illustrated in Figure 4, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Balance method

Ff Td〇 ° ;〇 ~: 包衿間Tpc〇與第二單 予歹、罘一預先充 先充電時間Tpe。等於如圖7中二=Td。之和。第二預 憶體7L件之贱充料f _ 之典_揮發性記 罘一早元電流開發時間丁 do 21 200849250 2 73卿打 短於圖 T以兄切之典型單元電流開發時。因此, 由於不需要圖4中所說明之等待時間=二: 中所說明之習知非择發性記憶體元件之 -蕾、⑽二/ 先充電時間如以及第一單 7L ^ _關Tde。奇數時間配平電路^ 〇 先充電時間Tpc。以及第 -早兀心開發時間Td。。因此,非 =知非揮發性記憶體元件相比可減少總則時 间0 由於贿位元線BLe〇至BLeiM比奇數位讀BL〇〇 另外0Γ1具ΐ較小的寬度,故前者比後者快地預先充電。 另外,由於偶數位元線BLe0至BLeIM之 〇 HBLo0至见⑽·1之單元電流小’故前者需:行:發 晴糾持續咖。因此,第―減充電時間加 預i充電”co。另一方面,第一單元電流開 X e長於第一單元電流開發時間Tdo。因此,不广 在總感測時間之大差異。亦即,偶數感測時間 二 間類似於奇數感測時間Ts〇。 符 ',、貝日寸 一在2發性記憶體元件100中,在根據位元線是偶數 位5線遂是奇數位元線而最佳化的感測操作條件下執彳— ^操作。HI此,用於感測位元線所f要之喊測時間減'^, 從而減少使讀取/驗證操作在非揮發性記憶體元件忉/中 22 200849250Ff Td〇 ° ;〇 ~: Tpc〇 and the second one, 预先, pre-charge time Tpe. It is equal to two = Td in Figure 7. Sum. The second memory of the 7L piece of 贱 f f f _ _ _ 罘 罘 罘 早 早 早 do do 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Therefore, since the waiting time = two in the description of Fig. 4 is not required: the bud of the conventional non-selective memory element explained in Fig. 4, the (10) two/first charging time, and the first single 7L ^ _ off Tde. Odd time trimming circuit ^ 〇 First charging time Tpc. And the first - early heart development time Td. . Therefore, non-known non-volatile memory components can reduce the total time of 0. Since the bribe bit line BLe〇 to BLeiM is oddly bit-reading BL〇〇, another 0Γ1 has a smaller width, so the former is faster than the latter. Precharged. In addition, since the cell currents of the even bit lines BLe0 to BLeIM 〇 HBLo0 to see (10)·1 are small, the former requires: Line: Clear and correct. Therefore, the first-de-charge time plus the pre-charge "co." On the other hand, the first cell current ON is longer than the first cell current development time Tdo. Therefore, the difference in the total sensing time is not wide. The even sensing time two is similar to the odd sensing time Ts〇. The symbol ', 贝, 贝, in the two-dimensional memory element 100, is an odd-numbered bit line according to the bit line, which is an even number of 5 lines 而Optimized sensing operation conditions - ^ operation. HI this, used to sense the bit time of the bit line to reduce the ^ ^, thereby reducing the read / verify operation in non-volatile memory components忉/中22 200849250

2/J^UpiI 執行所耗費的時間。 一圖9為說明根據本發明之一實施例之非 二式化方法之流程圖。參看 公 • 揮發性記憶體元件10D夕条口七於古μ 中,騎碼哭1?1之•式化方法如下。在操作S110 -n± ★馬°° 12〇解碼列位址以選擇對應於其之字線。同 中” 移至字線電壓產生器130。在操作si2〇 〇 是偶數字線。在操作陶,若ϊίΐ I I 子線,則在自偶數電壓配平電路132 μ 程式化操作條件 τ电路132供應之弟一 選定字線為奇數丰綠式 在操作S140中,若 之第-w 子線,則在自奇數電壓配平電路134供庫 之弟-程式化操作條件下執行程式化操作。 仏應 ,I。為說明根據本發明之一實 體兀件100的位元線减測 /剛上仏 ί0,非揮發ί 流程圖。參看圖5以及圖 操作防。中二線感測方法如下。在 〇令。在操作S220中二、羅= 則接收貧料讀取/驗證命 / m控制頁面緩衝器平電路 頁面緩衝器刚以致=_之八可數時間配平電路w控制 線。 弟—感測操作條件感測奇數位元 根據以上所述之本發 — 體元件根據記憶體單元是 早-而以各別方式操作。具體言:,在根二 200849250 — 上 施例之f軍發性記憶體元件⑽中,在根據記憶體單元是 偶數疏體早7L歧奇數記憶體單元而對於料化分 佳化之程式化/讀取/驗證/抹除操作條件下驅動字線。在= 據位元線是偶數位元_是奇触^線㈣佳化之 : 作條件下驅動位元線。1]此,有可能改良記憶體單元之^ 限電壓分佈以及由記憶體單元之結齡置之差異引起 能降級。 Ο2/J^UpiI The time it takes to execute. Figure 9 is a flow chart illustrating a non-binarization method in accordance with an embodiment of the present invention. See the public • Volatile memory component 10D 夕条口七于古μ, riding code crying 1? 1 is the following method. The column address is decoded in operation S110 -n± ★ °°° to select the word line corresponding thereto. The same is moved to the word line voltage generator 130. In operation si2, it is an even digital line. In operation, if the 子ίΐ II sub-line is supplied from the even-numbered voltage trimming circuit 132 μ stylized operating condition τ circuit 132 The selected word line is an odd-numbered green type. In operation S140, if the -w sub-line is used, the stylized operation is performed under the condition that the odd-numbered voltage trimming circuit 134 is used by the library-stylized operation. To illustrate the bit line subtraction/single 仏 ί0 of a physical component 100 according to the present invention, a non-volatile 流程图 flow chart is shown in Fig. 5 and Fig. 5, and the second-line sensing method is as follows. In operation S220, the second = Luo = then receive the poor material read / verify life / m control page buffer flat circuit page buffer just so = _ eight countable time trim circuit w control line. Brother - sense the sense of operating conditions The odd-numbered bits are operated in a different manner according to the above-mentioned present invention, and the individual elements are operated in a different manner according to the memory unit. Specifically, in the root military device element (10) of the root example 200849250. , in the memory unit is even 7L differential odd-numbered memory cells and drive word lines for stylized/read/verify/erase operation conditions of materialization. In the = bit line is an even bit _ is a strange touch ^ line (4) Optimisation: Drive the bit line under conditions. 1] This may improve the voltage distribution of the memory cell and the degradation due to the difference in the age of the memory cell.

本發明之實施例亦可適用於具有三維記憶體陣列結構 之非揮發性記憶體元件。在此元件中,記憶體陣列之各別 層可具有不同臨限電壓分佈以及效能特性。此三維陣列結 構已分別揭露於以下專利中:題為 “THREE-DIMENSIONAL READ-ONLY MEMORY” 的美 國專利第5,835,396號(1998年12月7曰);題為 &quot;VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION”的美國專利第6,034,882號(2000年3月 7 日);以及題為 “WORDLINE ARRANGEMENT HAVING SEGMENTED WORDLINES” 的美國專利第 7,002,825 號 (2006年2月21曰),此等專利案將以引用的方式併入本 文中。在本發明之實施例中,非揮發性記憶體元件可經組 態以根據記憶體陣列之每一層而以不同方式操作。 圖11為說明根據本發明之一實施例之三維(3-D)記 憶體陣列210的截面圖。3-D記憶體陣列210可為快閃記 憶體陣列、唯讀記憶體(ROM)陣列、靜態隨機存取記憶 24 200849250 27350ριί 體(SRAM)陣列、石夕·氧化物·氮化物-氧化物,(s〇N〇s) β己fe體陣列或其類似物。參看圖Η,儘管3_D記憶體陣列 210具有第-層212卩及第二層214,但本發明不一定限於 . 兩層記憶體陣列結構。 : 錢、體陣列_包含由石夕或其類似物形成之基板 202。-或多個讀體材料層綱(展示一者)提供於記憶 體f列210中之不同層級處。詳言之,記憶體材料層204 p 堆豐於基板202上方。諸如氧化物層之絕緣層206安置於 夕個疏體材料層204中之每一者之間以便使記憶體材料 層204刀離%緣層2〇6可包含主體介電層,諸如硼矽酸 鹽玻璃(BSG)、磷石夕酸鹽玻璃(psG)以及·碟石夕酸鹽玻 璃(BPSG)〇 一,看圖Π ’第一層212之第一記憶體陣列之記憶體單 兀安置於基板202上,且第二層214之第二記憶體陣列之 記憶體單元安置於材料層204上。因此,屬於第一記憶體 ίχ _之記憶體單元的臨限電壓分佈不同於屬於第二記憶體 •陣列之記憶體單元的臨限電壓分佈。非揮發性記憶體元件 可經組態而以對於多層記憶體陣列210中之每-層最佳化 • 的操作條件來操作。 圖12為根據本發明之第二實施例之非揮發性記情體 元件200的功能方塊圖。參看圖12,非揮發性記憶體;件 200包含3-D |己憶體陣列21〇、解碼器22〇、頁面緩衝哭 230以及控制邏輯24〇。沾記憶體陣列21〇如以上參看圖口 η所述非揮餐性心隱體元件200包含經組態以根據對應 25 200849250 27350pif 於位,ADD之5己憶體單元屬於記憶體陣列210之第-層 212遷版陣列210之第二層214而控制記憶體單元 的才工制遴輯—24〇。具體言之,控制邏輯細包含經組態以 :控制屬於第-層212之記憶體單元的第一層控制邏輯 242,以及經組態以控制屬於结 • 制屬於弗二層214之記憶體單元的第 二層控制邏輯244。 圖13A至圖13C為圖12之非揮發性記憶體元件· 〇 之程式化5法的圖解說明。詳言之,圖13A為屬於第-層 2、12以及第一層214之記憶體單元之臨限電壓分佈的圖解 η兒明大體而口,*置於材料層2〇4上之記憶體單元比安 置於基,2〇2上之體單^^具有較差的臨限電壓特性。 因此’第-層212中之記憶體單元之臨限電壓可高於第二 層214中之記憶體單元之臨限電壓。 圖13Β為根據記憶體陣列21〇之第一 12 單元之臨限電壓分佈的程式化操作條件之圖解說明。程式 化操作條件包含程式化起始電壓vl〇、Ispp增量級別 ° ΔΙδρρ1、程式化停止電壓vim以及第一驗證電壓Vvfl。 程式化循環之最大次數可為m。第一層中之記 • 臨限電壓分佈滿足以下方程式7以及8。 心Embodiments of the invention are also applicable to non-volatile memory elements having a three-dimensional memory array structure. In this component, the individual layers of the memory array can have different threshold voltage distributions and performance characteristics. This three-dimensional array structure has been disclosed in the following patent: U.S. Patent No. 5,835,396, issued to <RTIgt; </RTI> </RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; US Patent No. 6,034,882 (March 7, 2000); and U.S. Patent No. 7,002,825 (February 21, 2006) entitled "WORDLINE ARRANGEMENT HAVING SEGMENTED WORDLINES", these patents will be cited The manner of incorporating is incorporated herein. In an embodiment of the invention, the non-volatile memory elements can be configured to operate in different ways depending on each layer of the memory array. Figure 11 is a diagram illustrating an embodiment in accordance with the present invention. A cross-sectional view of a three-dimensional (3-D) memory array 210. The 3-D memory array 210 can be a flash memory array, a read only memory (ROM) array, a static random access memory 24 200849250 27350ριί body (SRAM) Array, Shi Xi·oxide·nitride-oxide, (s〇N〇s) β-hexene array or the like. See Figure Η, although 3_D memory array 210 has a first layer 212 and a second layer 214, but the invention is not necessarily limited to a two-layer memory array structure: money, bulk array_containing substrate 202 formed by Shi Xi or the like. - or more The read material layer (shown one) is provided at different levels in the memory f column 210. In detail, the memory material layer 204p is stacked over the substrate 202. An insulating layer 206 such as an oxide layer is disposed over Between each of the layers of the sparse material layer 204 such that the memory material layer 204 is separated from the % edge layer 2〇6 may comprise a host dielectric layer, such as borosilicate glass (BSG), phosphorite Salt glass (psG) and disk silicate glass (BPSG), see Figure 记忆 'The memory of the first memory array of the first layer 212 is placed on the substrate 202, and the second layer 214 The memory unit of the second memory array is disposed on the material layer 204. Therefore, the threshold voltage distribution of the memory unit belonging to the first memory 不同于 _ is different from the threshold of the memory unit belonging to the second memory Array Voltage distribution. Non-volatile memory components can be configured to Figure 12 is a functional block diagram of a non-volatile character encoding element 200 in accordance with a second embodiment of the present invention. Figure 12 is a non-volatile material. The memory 200 includes a 3-D | replied array 21 解码, a decoder 22 〇, a page buffer cry 230, and a control logic 24 〇. The memory array 21 is as described above with reference to FIG. η. The non-salt cardiac component 200 is configured to be in accordance with the corresponding 25 200849250 27350pif, and the ADD 5 memory unit belongs to the memory array 210 - Layer 212 migrates the second layer 214 of the array 210 to control the memory system's production system - 24 〇. In particular, the control logic includes a first layer of control logic 242 configured to control memory cells belonging to the first layer 212, and configured to control memory cells belonging to the second layer 214 The second layer of control logic 244. 13A to 13C are diagrammatic illustrations of the stylized 5 method of the non-volatile memory element 〇 of Fig. 12. In detail, FIG. 13A is a diagram showing the threshold voltage distribution of the memory cells belonging to the first layer 2, 12 and the first layer 214, and the memory cell placed on the material layer 2〇4. Compared with the substrate placed on the base 2, the body has a poor threshold voltage characteristic. Thus, the threshold voltage of the memory cells in the 'first layer 212' can be higher than the threshold voltage of the memory cells in the second layer 214. Figure 13B is a graphical illustration of the stylized operating conditions for the threshold voltage distribution of the first 12 cells of the memory array 21〇. The programmed operating conditions include a stylized starting voltage vl 〇, an Ispp increment level ° ΔΙδρρ1, a stylized stop voltage vim, and a first verify voltage Vvfl. The maximum number of stylized loops can be m. Notes in the first layer • The threshold voltage distribution satisfies Equations 7 and 8 below. heart

Vlm = V10 + mAISSPl _ ................................方程式7) ^w\ = V\m-V10 ......... .................(方程式8 ) 參看圖13B’以第一程式化操作條件程式化第一層2 26 200849250 27350pif 之㊂己憶體單元。此處,第一程式化操作條件包含第一程式 化起始電壓V10、第一 ISPP增量級別△jspp〗、第一程式 化停止電壓Vim以及第一驗證電壓Vvfl。可對於第一声 :212中之記憶體單元之臨限電壓分佈最佳化此第一程式/匕 •操作條件。可自第一層控制邏輯242提供第一程式化操作 條件。當對第一層212中之記憶體單元程式化時,可將具 有以第一 ISPP增量級別ΔΒΡΡΐ依序增加之電壓位準的程 式化電壓Vpgm供應至對應字線。 圖13C為根據§己憶體陣列21 〇之第二層214之記情體 單元之臨限電壓分佈的程式化操作條件之圖解說明。此 處,程式化操作條件包含第二程式化起始電壓V2〇、第二 ISPP增量級別、第二程式化停止電壓v2n以及^ 二驗證電壓Vvf2。程式化循環之最大次數可為n。第二層 中之記憶體單元之臨限電壓分佈滿足以下方程式9以^ 10 〇 r V2n = V2Q + nMSSP2 ............ , • .....................(方程式9) : ...................(方程式10) 芩看圖13C,以第二程式化操作條件程式化第二層214 之3己丨思體單元。此處,弟一程式化操作條件包含第二程式 化起始電壓V20、第二ISPP增量級別△bpm、第=程^ 化停止電壓V2n以及第二驗證電壓Vvf2。可對於第二^ 214中之記憶體單元之臨限電壓分佈最佳化此第二程^ 27 Ο Ο 200849250 27350pif 操作條件。可自第二層控制邏輯244提供第二程式化操作 條件。當對第二層214中之記憶體單元程式化時,可將具 有以第二ISPP增量級別MSPP2依序增加之電壓位準的程 式化電壓Vpgm供應至對應字線。 非揮發性記憶體元件200經組態以判定所定址之記情 體單元屬於第一層212還是第二層214。基於記憶體陣列 210之所識別層而以不同程式化操作條件程式化記憶體單 元。因此,非揮發性記憶體元件200對於第一層212以及 第二層214中之記憶體單元的臨限電壓分佈最佳化程 操作條件。 士圖14A以及圖14B為圖12之非揮發性記憶體元件2〇〇 之讀取/驗證電壓的圖解說明。參看圖14A以及圖14B,本 ,明之非揮發性記憶體元件巾的記龍單元之臨限電 壓主要分成第一層212中之記憶體單元之臨限電壓以及第 層214中之§己憶體單元之臨限電壓。如圖“A以及圖“Η = ϋ,第二層214中之記憶體單元之臨限電壓分佈相 二者層212中之記憶體單元之臨限電壓分佈。在所 況貝例中,記憶體單元中之每一者儲存2位元資料。 一 ^揮發性記憶體元件中,讀取電壓根據記憶體 於第-層212還是第二層214而不同。舉例而言, 中之記憶體單元比第一層212中之記憶體單元 具有較向的讀取/驗證電壓。 具體言之,第二層214中之記憶體單元 堡如-2、把_2、呢_2^1_2、^仏2以及*仏2大 28 ΟVlm = V10 + mAISSPl _ ............................... Equation 7) ^w\ = V\m-V10 ........................... (Equation 8) Referring to Figure 13B', the first layer is programmed with the first stylized operating conditions. 2 26 200849250 27350pif The three have recalled the unit. Here, the first stylized operating condition includes a first programmed starting voltage V10, a first ISPP increment level Δjspp, a first programmed stop voltage Vim, and a first verify voltage Vvfl. This first program/匕 operating condition can be optimized for the threshold voltage distribution of the memory cells in the first sound: 212. The first stylized operating condition can be provided from the first level control logic 242. When the memory cells in the first layer 212 are programmed, the programmed voltage Vpgm having the voltage level sequentially increased by the first ISPP increment level ΔΒΡΡΐ can be supplied to the corresponding word line. Figure 13C is a graphical illustration of the stylized operating conditions for the threshold voltage distribution of the sensible unit of the second layer 214 of the § 己 体 array. Here, the stylized operating conditions include a second stylized starting voltage V2, a second ISPP increment level, a second stylized stop voltage v2n, and a second verify voltage Vvf2. The maximum number of stylized loops can be n. The threshold voltage distribution of the memory cells in the second layer satisfies the following Equation 9 to ^ 10 〇r V2n = V2Q + nMSSP2 ............, • ......... ............(Equation 9) : ...................(Equation 10) See Figure 13C for the second stylization The operating conditions stylize the second layer of the second layer 214. Here, the stylized operating condition includes a second stylized starting voltage V20, a second ISPP increment level Δbpm, a first sigma stop voltage V2n, and a second verify voltage Vvf2. This second pass can be optimized for the threshold voltage distribution of the memory cells in the second 214. A second stylized operating condition can be provided from the second level control logic 244. When the memory cells in the second layer 214 are programmed, the programmed voltage Vpgm having the voltage level sequentially increased by the second ISPP increment level MSPP2 can be supplied to the corresponding word line. The non-volatile memory component 200 is configured to determine whether the addressed sensible unit belongs to the first layer 212 or the second layer 214. The memory cells are programmed with different stylized operating conditions based on the identified layers of the memory array 210. Thus, the non-volatile memory component 200 optimizes the operating conditions for the threshold voltage distribution of the memory cells in the first layer 212 and the second layer 214. Figure 14A and Figure 14B are graphical illustrations of the read/verify voltages of the non-volatile memory component 2A of Figure 12. Referring to FIG. 14A and FIG. 14B, the threshold voltage of the cell of the non-volatile memory device is mainly divided into the threshold voltage of the memory cell in the first layer 212 and the § memory in the second layer 214. The threshold voltage of the unit. As shown in Fig. A and Fig. Η = ϋ, the threshold voltage distribution of the memory cells in the layer 212 of the memory cells in the second layer 214 is the threshold voltage distribution. In the case of the case, each of the memory cells stores 2-bit data. In a volatile memory element, the read voltage differs depending on whether the memory is on the first layer 212 or the second layer 214. For example, the memory cell has a relatively higher read/verify voltage than the memory cell in the first layer 212. Specifically, the memory unit in the second layer 214 is as large as -2, _2, _2^1_2, ^仏2, and *仏2 are large 28 Ο

200849250 27350pif 於弟^一層212中之却橋雕结-,, 中之記憶體單元的讀取電壓^及:=第一層犯 驗證㈣VvfH、精]以及 及細·1以及 242控制。第二層214中之 ^由f—層控制邏輯 -2, ^ Vr3-2 t MVvft^ ; 由第二層控制邏輯244控制。 及vf3-2 記憶體元件2〇°中,供應至字線之讀取/ 元位於多層記憶體陣列以… 層212中延是第二層214中而 ^ 體元件200之抹除電壓;軍叙性圯憶 212中還1 亦可根據記憶體單元位於第-層 甲疋昂一層214中而變化。 另^在非揮發性記憶體元件細中,根據記憶 元屬於第一層212還是筮-爲οι」 〜单 ‘ 3 s 214而以各別讀取電壓執行 一^作。因此,非揮發性記憶體科200與習知非揮發 性七憶體7L件(其中不管記憶體單元位於第—層212還是 第二f214中均以相同讀取電壓來執行讀取操作)相比可 改良讀取邊限(read margin)。 =以上所述,非揮發性記憶體元件可經組態以根據記 fe脰單元之結構差兴以及位置而最佳化操作條件。本發明 可應用於根據結構位置而具有不同臨限電壓分佈特性以及 效能特性的其他區域(例如,記憶體區塊之間、墊塊(mat) 之間,以及記憶體組之間)。舉例而言,非揮發性記憶體元 件可經組態以使鄰近解碼器之記憶體區塊與遠離解碼器之 29 200849250 2/J^upn :=,制條件變化。另外,非揮發性記憶體 凡件可L以使用於特定目的之記憶 之記憶體區塊之間的操作條件變化。 兄/、奴使用 24D ff/所說明之非揮發性記憶體元件綱之控制邏輯 2=匕3用於控制屬於第一層212之記憶體單元 声 用於控制屬於第二層214之記憶體單‘ Ο 元Ϊ = ^ 然而,本發明之非揮發性記憶體 呓情體:们、二:述組悲。如圖15中所說明,細务性 緩己=:300包含經組態以控制列解碼器 ==!邏輯340。配平資訊電㈣控制控制 1 控制邏輯撕經組態而以預設操作 =操^ JL且有路350包含第—層配平資訊暫存器352, 驅動輯:4:之預設操作條件以便最佳地200849250 27350pif in the second layer 212 of the bridge, the bridge reading voltage -,, the reading voltage of the memory unit ^ and: = the first layer of the verification (4) VvfH, fine] and fine · 1 and 242 control. The second layer 214 is controlled by the second layer control logic 244 by the f-layer control logic -2, ^Vr3-2 t MVvft^; And the vf3-2 memory element 2 〇 °, the read to the word line / element is located in the multi-layer memory array ... layer 212 is extended in the second layer 214 and the erase voltage of the body element 200; military narrative Also in the memory 212 can also be changed according to the memory unit located in the first layer of the enamel layer 214. In the non-volatile memory component, depending on whether the memory element belongs to the first layer 212 or 筮- is οι" to ‘3 s 214, a separate read voltage is performed. Therefore, the non-volatile memory family 200 is compared with the conventional non-volatile seven-replica 7L device in which the read operation is performed with the same read voltage regardless of whether the memory cell is located in the first layer 212 or the second f214. The read margin can be improved. = As noted above, the non-volatile memory elements can be configured to optimize operating conditions based on the structural differences and location of the fe unit. The present invention is applicable to other regions having different threshold voltage distribution characteristics and performance characteristics depending on the structural position (e.g., between memory blocks, between mats, and between memory groups). For example, the non-volatile memory elements can be configured to vary the memory blocks of adjacent decoders from the far-end decoder. In addition, the non-volatile memory can vary in operating conditions between memory blocks used for memory of a particular purpose. The control logic 2 of the non-volatile memory component described by the brother/slaver 24D ff/ is used to control the memory unit sound belonging to the first layer 212 for controlling the memory list belonging to the second layer 214. 'Ο元Ϊ = ^ However, the non-volatile memory of the present invention is:   As illustrated in Figure 15, the policing =: 300 includes configuration to control the column decoder ==! logic 340. Leveling information (4) Control control 1 Control logic tearing through configuration with preset operation = operation JL and way 350 contains the first level trim information register 352, drive series: 4: preset operating conditions for the best Ground

(J 含第4整貝訊。配平資訊電路350更包 3罘一層配平貧訊暫存器354, 34〇之預設操作侔件以#料^、:有用於调正控制邈輯 整資訊。配平資訊電路二工第= 將繁一®獅、1&gt; 一 w馬所輸入位址ADD以判定 配平資i暫存器说之第一調整資訊還是第二層 340。儘管圖h〜、rh之弟一凋整貧訊轉移至控制邏輯 暫存哭359\况月配平貧訊電路35〇包含兩個配平資訊 存哭十^及354,但本發明並不限於兩個配平資訊暫 或者’配平資訊電路柳可包含儲存與三個或三個 30 200849250 27350pif ㈣為根據本發明zz個以上配平資訊暫存器。 塊圖。參看® 16,記憶h霄施例之記憶體系統10.的方 器14之非揮發性記贿包含_至記憶體控制 以控制非揮雜記聽^^12,記㈣控_ 14經組態 可為(例如)W5巾轉紐記㈣元件12 〇 之非揮發性記憶體元件2:=,元件⑽、圖12中 件300。 ^圖5中之非揮發性記憶體元 非揮發性記憶體元件1 所儲存資料。隨著諸如蜂巢時仍可保留 數位助理(PDA)、攜 i之仃“件增加,個人 (MPEG)音訊層3 (M H控制台以及動晝專業團體 用於程式碼以及資料儲存。另外卜非憶體元件曰益 用於諸如高解析度f ^ =_性記憶體元件可 〇 以上層相關聯之 根據4:: ί統(GPS)元件的家庭應用中。 於嵌入式系統。為=例的非揮發性記憶體元件可適用 :統執行適合4;:::二置:之計算系統·入式 中央處理單元(C 、作。嵌人式系統可包含 作業系統執行庫用以及作業系統。可由嵌入式系統之 置於諸如軍事;2式以齡特定操作。嵌入式系統可建 諸如數位電視 =業I置、通信裝置、視訊轉換器或 圖17為位相機之家庭料的裝置中。 體元件的歲入據本發明之一實施例之非揮發性記憶 大5己憶體系'统20之功能方塊圖。參看圖17, 31 200849250 厶 / J J UpJL丄 肷入式§己憶體糸統2〇包含雷、$ j 單元(⑽22、S‘2,至匯流排2】之中央處理 性記t音體元件28 。己杈體控制态26以及非揮發 ==或具有與以上(J contains the 4th whole message. The leveling information circuit 350 further includes 3 layers of the balance of the temporary register 354, 34〇 of the preset operation conditions to #料^,: used to adjust the control 邈 compilation information. The leveling information circuit second work = = will be a single ® lion, 1 &gt; a horse to enter the address ADD to determine the first adjustment information of the distribution of the temporary register is still the second layer 340. Although the figure h ~, rh The younger brother went to the control logic and temporarily transferred to the control logic to temporarily cry 359. The monthly balance of the poor communication circuit 35〇 contains two levels of information to cry 10 ^ and 354, but the invention is not limited to two trim information or 'leveling information The circuit can be stored with three or three 30 200849250 27350 pif (four) for more than zz equalization information registers according to the present invention. Block diagram. See ® 16, memory device 10 of the memory system 10. The non-volatile bribe contains _to memory control to control non-sweet memory ^^12, and the (four) control _ 14 can be configured as (for example) W5 towel transfer key (4) component 12 〇 non-volatile memory Element 2: =, component (10), piece 300 in Figure 12. ^ Non-volatile memory element non-volatile memory in Figure 5. The information stored in item 1. With the addition of digital assistants (PDAs), such as hives, the addition of personal information (MPEG) audio layer 3 (MH console and dynamic professional community for code and data) Storage. In addition, the use of high-resolution f ^ = _ memory devices can be used in home applications based on 4:: ) (GPS) components. For the non-volatile memory components of the example: applicable: 4:::: two sets: the calculation system · the central processing unit (C, work. The embedded system can include the operating system execution library And the operating system can be placed by the embedded system such as military; 2 type-specific operation. The embedded system can be built such as digital TV = industry I, communication device, video converter or Figure 17 is the family of the camera In the device, the function block diagram of the non-volatile memory of the body element according to an embodiment of the present invention is shown in Fig. 17, 31 200849250 厶 / JJ UpJL 丄肷 己 己 体糸 〇 2〇 contains Ray, $ j unit ((10) 22 S'2, 2] to the bus of the central processing element 28 referred t tone. Hexanoic prong member 26 and the control states having a non-volatile or more ==

非揮發性記憶體元件28可儲存由/待由^= ; 控制器26處理之心元資料(N為正整數)。❿體 儘官未圖示,但嵌入式記憶體系統2 而更包含應用晶片組、相機影像處理器(Cls)、行動^^ ^其他兀件。記龍控制器%以及非 咖、(例如)將非揮發性記憶體元件28用於:J: 的固悲磁碟機/磁碟(SSD)而組態。 、厂 可根據設計選擇而以多種方式封裝非揮發性記憶體元 件28及/或記憶體控制器、26。舉例而言,非揮發性記情體 元件28及/或記憶體控制器26可安裝於層疊封裝(卯ck^e on package,P〇P )、球狀柵格陣列(bau grici 抓吵,bga )封The non-volatile memory component 28 can store the core data (N is a positive integer) processed by the controller 26. The body is not shown, but the embedded memory system 2 includes an application chipset, a camera image processor (Cls), and other components. The chronograph controller % and non-coffee, for example, configure the non-volatile memory component 28 for: J: Solid Disk Drive/ScDisk (SSD). The plant may package the non-volatile memory element 28 and/or the memory controller 26 in a variety of ways depending on the design choice. For example, the non-volatile grammar element 28 and/or the memory controller 26 can be mounted on a package (卯 ^ on on package, P 〇 P ), a spherical grid array ( bau grici grabbing, bga )seal

裝、晶片級封裝(chip scale package, CSP)、塑膠引線晶片 載體(plastic leaded chip carrier,PLCC)、塑膠雙列直插式 封裝(plastic dual in-line package,PDIP )、窩伏爾包裝之晶 粒(die in waffle pack )、晶圓形式之晶粒、板上晶片 (chip_on_board ’ COB )、陶免雙列直插式封裝(ceramic dual in-line package,CERDIP )、塑膠公制四方扁平包裝(piastic metric quad flat pack,MQFP)、薄型四方爲平包裝(thin quad flatpack,TQFP)、小型封裝(small outline,SOIC)、 收縮型小型封裝(SSOP)、薄型小型封裝(TSOP)、系統 32 200849250 級封裝(system in package,SIP)、多晶片封裝(inulti_chip package ’ MCP)、晶圓級製造封裝(wafer_ievei趾士的以 package,WFP )或晶圓級處理堆疊封裝(鄕知七⑽ processed stack package,WSP )中。 根據非揮發性記憶體元件之實施例,有可能改良臨限 電壓分佈以及效能,因為非揮發性記憶體元件根據記憶體 單元之結構位置而以不同方式操作。 Ο Ο 應認為以上所揭露標的物是說明性而非約束性的,且 附加之申請專利範圍意欲涵蓋屬於本發明之真正精神以及 範疇的所有此等修改、增強以及其他實施例。因此,在法 律所允許之最切度上,本發明之齡應由所容許的對以 下申請專利範_及其鱗物之最廣泛解釋而狀且不應 由上述實施方式約束或限制。 【圖式簡單說明】 的電=為使用雙圖案化技術(DPT)之記憶體單元陣列 組態=中之字線以及位元線之形狀以及 記憶體單說明沿圖1之線“,截取的 in單元之主動區域之寬度的截面圖,且圖2C 兄月^位元線以及偶數位元線之金屬寬度。 圖解3^*DPT製造之記憶體單元之臨限電壓分佈的 圖4為習知位元線結構以及感測方法之等效電路圖以 33 埯 、班H f腹早兀是催 遂是奇數記憶體單元的臨限電壓分佈特性,’ 〇 〇Package, chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), nest Volt package Die in waffle pack, wafer form die, on-board chip (chip_on_board ' COB ), ceramic dual in-line package (CERDIP), plastic metric square flat package (piastic Metric quad flat pack (MQFP), thin quad flatpack (TQFP), small outline (SOIC), shrink small package (SSOP), thin small package (TSOP), system 32 200849250 package (system in package, SIP), multi-chip package (inulti_chip package 'MCP), wafer-level manufacturing package (wafer_ievei's package, WFP) or wafer-level processing stack package (known as seven (10) processed stack package, WSP )in. According to embodiments of the non-volatile memory component, it is possible to improve the threshold voltage distribution and performance because the non-volatile memory component operates in different ways depending on the structural location of the memory cell. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Therefore, the scope of the invention is to be construed as being limited by the scope of the invention and the scope of the invention. [Simple description of the diagram] The electricity = the shape of the memory cell array using the double patterning technology (DPT) = the shape of the word line and the bit line and the memory single note along the line of Figure 1 ", intercepted A cross-sectional view of the width of the active region of the unit, and the metal width of the bit line and the even bit line of Figure 2C. Figure 4 is a conventional voltage distribution of the memory cell fabricated by DTM. The bit line structure and the equivalent circuit diagram of the sensing method are 33 埯, Ban H f 腹 兀 兀 is the threshold voltage distribution characteristic of the odd memory unit, ' 〇〇

200849250 二/ JdV/卜/丄丄 及相關聯之電壓-時間曲線。 圖5為_本發明n施例之非 件的功能方塊圖。 X (生3己 圖6A至圖6C A圖5之非揮發性記憶 化操作,且圖6C說以 圖7為根縣伽之—實闕之轉 的讀取電壓之圖解說明。 己k體7M牛 料圖!^及®8B制於根據本發明之―實施例之非揎 =仏體元件中之位元線感測的電壓時間曲線之圖: 圖9為說明根據本發明之一實施例之非揮發性 元件的程式化方法之流程圖。 生⑼ 一圖ίο為說明根據本發明之一實施例之非揮發性奇 體70件的位元線感測方法之流程圖。 一圖u為說明根據本發明之一實施例之非揮發性記憶 體元件的二維記憶體陣列之截面圖。 圖12為根據本發明之第二實施例之非揮發性記憶體 元件的功能方塊圖。 篮 。、圖13A至圖13c為圖12中之非揮發性記憶體元件之 &amp;式化方法的圖解說明,其中圖13A說明根據記憶體單元 屬於莖一爲、班 、牙尽遇疋第二層的臨限電壓分佈,圖13B說明對第 34 200849250 27350ριί 一層之記憶體單元的程式化操作,且圖13C說明對第二層 之記憶體單元的程式化操作。 圖14Α以及圖14Β為圖12中之非揮發性記憶體元件 . 之讀取/驗證電壓的圖解說明。 圖15為根據本發明之第三實施例之非揮發性記憶體 元件的功能方塊圖。 圖16為根據本發明之一實施例之記憶體系統的功能 方塊圖。 η 圖17為具有根據本發明之一實施例之非揮發性記憶 體元件的嵌入式記憶體系統之功能方塊圖。 【主要元件符號說明】 10 :記憶體系統 12 :非揮發性記憶體元件 14:記憶體控制器 20 :嵌入式記憶體系統 21 :匯流排 Ο 22 :中央處理單元(CPU) • 24 :靜態隨機存取記憶體(SRAM) : 26 :記憶體控制器 28 :非揮發性記憶體元件 1〇〇 :非揮發性記憶體元件 110 :記憶體單元陣列 120 :列解碼器 130 :字線電壓產生器 35 200849250 Z/JDUpi 丄 132 :偶數電壓配平電路 134 :奇數電壓配平電路 140 :頁面緩衝器 . 150 :控制邏輯 152 :偶數時間配平電路 154 :奇數時間配平電路 200 :非揮發性記憶體元件 202 :基板 ^ 204 :記憶體材料層 206 :絕緣層 210 :記憶體陣列 212 :第一層 214 :第二層 220 :解碼器 230 :頁面緩衝器 240 :控制邏輯 〇 242 :第一層控制邏輯 • 244:第二層控制邏輯 : 300 ··非揮發性記憶體元件 320 :列解碼器 330 :頁面緩衝器 340 :控制邏輯 350 :配平資訊電路 352 :第一層配平資訊暫存器 36 200849250 27350pif 354:第二層配平資訊暫存器 ADD :位址 AW1 :偶數記憶體單元之主動區域之寬度 . AW2 :奇數記憶體單元之主動區域之寬度 BLe :偶數位元線 BLeO —BLen-Ι :偶數位元線 BLo :奇數位元線 BLoO — BLon-Ι :奇數位元線 c BW1 :偶數位元線之寬度 BW2 :奇數位元線之寬度 Ce :偶數位元線之寄生電容 Co ··奇數位元線之寄生電容 GST :接地選擇電晶體 Lgl :偶數字線之通道寬度 Lg2 :奇數字線之通道寬度 MO —M31 :浮動閘極電晶體 G Re ··偶數位元線之寄生電阻 • ReCe :偶數位元線之RC時間常數 - Ro :奇數位元線之寄生電阻200849250 II / JdV / Bu / 丄丄 and associated voltage-time curve. Fig. 5 is a functional block diagram of a non-part of the embodiment of the present invention. X (raw 3 has a non-volatile memory operation of FIG. 6A to FIG. 6C A FIG. 5, and FIG. 6C shows a schematic description of the read voltage of the root gamma-solid turn of FIG. 7 . FIG. 9 is a diagram illustrating voltage time curves sensed by bit lines in a non-揎=body element according to an embodiment of the present invention: FIG. 9 is a diagram illustrating an embodiment of the present invention. Flowchart of a stylized method for non-volatile components. (9) A diagram for explaining a bit line sensing method of a non-volatile odd-body 70 piece according to an embodiment of the present invention. A cross-sectional view of a two-dimensional memory array of a non-volatile memory element in accordance with an embodiment of the present invention. Figure 12 is a functional block diagram of a non-volatile memory element in accordance with a second embodiment of the present invention. 13A to 13c are diagrams illustrating a &amp; characterization method of the non-volatile memory element of FIG. 12, wherein FIG. 13A illustrates the second layer of the stalk, the stalk, the tooth, and the sputum according to the memory unit. Limit voltage distribution, Figure 13B illustrates the memory list for the 34th 200849250 27350ριί layer The stylized operation of the element, and Figure 13C illustrates the stylized operation of the memory cells of the second layer. Figure 14A and Figure 14B are graphical illustrations of the read/verify voltages of the non-volatile memory elements of Figure 12. Figure 15 is a functional block diagram of a non-volatile memory element in accordance with a third embodiment of the present invention. Figure 16 is a functional block diagram of a memory system in accordance with an embodiment of the present invention. Functional block diagram of the embedded memory system of the non-volatile memory element of one embodiment. [Description of main component symbols] 10: Memory system 12: Non-volatile memory component 14: Memory controller 20: Embedding Memory System 21: Bus Bars 22: Central Processing Unit (CPU) • 24: Static Random Access Memory (SRAM): 26: Memory Controller 28: Non-volatile Memory Element 1〇〇: Non-volatile Memory element 110: Memory cell array 120: Column decoder 130: Word line voltage generator 35 200849250 Z/JDUpi 丄 132: Even voltage trim circuit 134: Odd voltage trim circuit 140: Page buffer. 15 0: control logic 152: even time trim circuit 154: odd time trim circuit 200: non-volatile memory element 202: substrate ^ 204: memory material layer 206: insulating layer 210: memory array 212: first layer 214: Second layer 220: decoder 230: page buffer 240: control logic 242: first layer control logic • 244: second layer control logic: 300 • non-volatile memory element 320: column decoder 330: page Buffer 340: Control logic 350: Leveling information circuit 352: First level trim information register 36 200849250 27350pif 354: Layer 2 trim information register ADD: Address AW1: Width of active area of even memory unit. AW2: width of the active area of the odd memory cell BLe: even bit line BLeO - BLen-Ι : even bit line BLo: odd bit line BLoO - BLon - Ι : odd bit line c BW1 : even bit line Width BW2: width of odd bit line Ce: parasitic capacitance of even bit line Co · parasitic capacitance of odd bit line GST : ground selection transistor Lgl : channel width of even digital line Lg2 : channel of odd digital line Width MO — M 31: Floating gate transistor G Re · · Parasitic resistance of even bit line • ReCe : RC time constant of even bit line - Ro : Parasitic resistance of odd bit line

RoCo :奇數位元線之RC時間常數 SST :串選擇電晶體 Td :開發時間RoCo: RC time constant of odd bit lines SST : string selection transistor Td : development time

Tde :第一單元電流開發時間 Tdo :第二單元電流開發時間 37 200849250 2735ϋριίTde: first unit current development time Tdo: second unit current development time 37 200849250 2735ϋριί

Tpc :預先充電時間Tpc: pre-charge time

Tpce :第一預先充電時間Tpce: first pre-charge time

Tpco :第二預先充電時間Tpco: second pre-charge time

Ts :感測時間Ts: sensing time

Tse :第一感測時間Tse: first sensing time

Tso :第二感測時間Tso: second sensing time

Twl :等待時間Twl: waiting time

Tw2 :等待時間 V10 :第一程式化起始電壓 V20 :第二程式化起始電壓Tw2: Waiting time V10: First stylized starting voltage V20: Second stylized starting voltage

Vim :第一程式化停止電壓 V2n :第二程式化停止電壓Vim: first stylized stop voltage V2n: second stylized stop voltage

VeO :第一程式化起始電壓VeO: the first stylized starting voltage

Vem :第一程式化停止電壓Vem: the first stylized stop voltage

Vm :程式化停止電壓Vm: Stylized stop voltage

Vo :程式化起始電壓 V〇0 ··第二程式化起始電壓Vo : Stylized starting voltage V〇0 ··Second stylized starting voltage

Von :第二程式化停止電壓Von: second stylized stop voltage

Vpgm :程式化電壓Vpgm: stylized voltage

VrM :第一層中之記憶體單元的讀取電壓 Vrl-2 ··第二層中之記憶體單元的讀取電壓 Vr2-1 :第一層中之記憶體單元的讀取電壓 Vr2-2:第二層中之記憶體單元的讀取電壓 Vr3-1 :第一層中之記憶體單元的讀取電壓 38 200849250 27350ριίVrM: read voltage Vrl-2 of the memory cell in the first layer · Read voltage Vr2-1 of the memory cell in the second layer: read voltage Vr2-2 of the memory cell in the first layer : Read voltage Vr3-1 of the memory cell in the second layer: Read voltage of the memory cell in the first layer 38 200849250 27350ριί

Vr3-2:第二層中之記憶體單元的讀取電壓 Vre :偶數記憶體單元之讀取電壓 Vro ··奇數記憶體單元之讀取電壓 . Vtrip :跳脫電壓Vr3-2: Read voltage of the memory cell in the second layer Vre : Read voltage of the even memory cell Vro · Read voltage of the odd memory cell . Vtrip : Trip voltage

Vvfl :第一驗證電壓Vvfl: first verification voltage

Vvfl-Ι :第一層中之記憶體單元的,驗證電壓 Vvfl-2 :第二層中之記憶體單元的驗證電壓 Vvf2 :第二驗證電壓 ^ Vvf2-1 :第一層中之記憶體單元的驗證電壓Vvfl-Ι : memory cell in the first layer, verification voltage Vvfl-2: verification voltage Vvf2 of the memory cell in the second layer: second verification voltage ^ Vvf2-1 : memory unit in the first layer Verification voltage

Vvf2-2 :第二層中之記憶體單元的驗證電壓 Vvf3-1 :第一層中之記憶體單元的驗證電壓 Vvf3-2:第二層中之記憶體單元的驗證電壓 Vvfe :第一驗證電壓 Vvfo :第二驗證電壓 WL0 — WL31 :字線 △ISPP : ISPP增量級別 〇 AISPP1 :第一 ISPP增量級別 • AISPP2 :第二ISPP增量級別 : AlSPPe :第一 ISPP增量級別 AISPPo :第二ISPP增量級別 AVw ··總臨限電壓分佈之寬度 AVwe :偶數記憶體單元之臨限電壓分佈之寬度 AVwo ··奇數記憶體單元之臨限電壓分佈之寬度 39Vvf2-2: verification voltage Vvf3-1 of the memory cell in the second layer: verification voltage Vvf3-2 of the memory cell in the first layer: verification voltage Vvfe of the memory cell in the second layer: first verification Voltage Vvfo: second verification voltage WL0 - WL31: word line ΔISPP: ISPP increment level 〇 AISPP1: first ISPP increment level • AISPP2: second ISPP increment level: AlSPPe: first ISPP increment level AISPPo: The second ISPP increment level AVw ··the width of the total threshold voltage distribution AVwe: the width of the threshold voltage distribution of the even memory unit AVwo · The width of the threshold voltage distribution of the odd memory unit 39

Claims (1)

200849250 2735Upii 十、申請專利範圍: 1·種驅動非揮發性記憶體元件之方法,所述方法包 含: • 判疋待驅動之記憶體單元的結構形狀以及位置;以 及 基於所述所判定結果而以最佳化操作條件驅 動所述 記憶體單元。 0 2·如申請專利範圍第1項所述之驅動非揮發性記憶體 兀件之方法,其中所述操作條件包含字線電壓、位元線電 壓、井電壓以及其時序。 3·如申請專利範圍第1項所述之驅動非揮發性記憶體 元件之方法,所述操作條件包含程式化/讀取/抹除條件。 4·如申请專利範圍第1項所述之驅動非揮發性記憶體 元件之方法’其中臨限電壓分佈根據待驅動之所述記憶體 單元是偶數記憶體單元還是奇數記憶體單元而不同,且所 述偶數記憶體單元所連接至之偶數字線的寬度不同於所述 (J 奇數記憶體單元所連接至之奇數字線的寬度。 5·如申請專利範圍第4項所述之驅動非揮發性記憶體 • 元件之方法,其中所述操作條件為程式化操作條件,所述 記憶體單元根據待驅動之所述記憶體單元所連接至之字線 疋所述偶數ΰ己f思體早元還疋所述奇數記憶體單元而以第一 程式化操作條件以及第二程式化操作條件中之一者程式 化,所述第一程式化操作條件與所述第二程式化操作條件 彼此不同。 40 200849250 Z/^&gt;DUpil 6.如申請專利範圍第5項所述之驅動非揮發性記憶體 元件之方法,其中驅動所述記憶體單元包含執行增量階躍 脈衝程式化(ISPP)方法,且所述第一程式化操作條件以 . 及所述第一程式化操作條件中之每一者包含程式化起始電 麼、ISPP增量級別以及程式化停止電壓。 7·如申印專利乾圍弟1項所述之驅動非揮發性記憶體 元件之方法,其中所述操作條件根據待驅動之所述記憶體 單元所連接至之位元線是偶數位元線還是奇數位元線而不 (、 同,其中所述操作條件為位元線感測操作條件,且驅動所 述記憶體單元包含根據所述位元線是偶數位元線還是奇數 位兀線而以第一感測操作條件以及第二感測操作條件中之 一者^執行所述感測操作條件,所述第一感測操作條件與 戶斤述第二感測操作條件彼此不同。 8·如申请專利範圍第1項所述之驅動非揮發性記憶體 =件之方法,其中所述非揮發性記憶體元件具有具備至少 第—層以及第二層之記憶體陣列,且驅動所述記憶體單元 包含根據待驅動之所述記憶體單元屬於 *第二層而使用第—驅動操作條件以及第二驅域 -·中之一者,所述第一驅動操作條件與所述第二驅動操作條 件彼此不同。 μ ’、 9·一種非揮發性記憶體元件,包含: ▲至少兩個記憶鮮元,其具核結構雜以及位置 而變化之分佈特性;以及 控制包路,其經組態以控制所述各別記憶體單元之 41 200849250 L· / J JVjpil 最佳化操作條件。 件,範圍第9項所述之非揮發性記憶體元 狀以及位置包含字主動區 咸度以及油相料線之間的距離。 t料鄉㈣9賴紅師發性記憶體元 二:所述兩個記憶體單元分別被至少兩 記憶體 層所包含。 o o 12·—種非揮發性記憶體元件,包含: 記憶體單元陣列,其包含多個記憶體單元,所述多 個記,體早7C中之每—者位於多個字線與多個位元線之 相交處; 列解碼器,其域至記憶體 以選擇所述多個字線中之一者;以及 平幻且、、工、,且'心 „產生器’其耦接至所述列解碼器且經組態 以輸出字^壓,所述字線糕具有_與所述多個記 億體#中之選定-者相關聯之臨限分佈的操作條 件。 13·如申請專利範圍第12項所述之 件,其中所,限麵分佈根據所述多二 戶斤述選定—者是偶數記憶體單元還是奇數記憶 同。 14.如申請專利範圍第13項所述之非揮 . 件,其中所述字線電壓產生器包含·· X 。己fe體兀 偶數電壓配平電路,苴奴 乂在所述多個記憶體 42 Ο Ο 200849250 單元中之所述選定-者為所述偶數記憶體單元時以第一 程式化操作條件輸出所述字線電壓;以及 奇數電壓配平電路,其經_以在所述乡個記憶體 單元中之所述選定-者為所㈣數記憶體單元時以第二 程式化操作條件輸出所述字線電壓。 15.如申请專利帛14項所述之非揮發性記憶體元 件’其中在讀取/驗證操作期間,所述偶數電壓配平電路經 組態而以第-讀取/驗證條件產生所述字線電壓,且所述奇 數電壓配平電路經組態而以第二讀取/驗證條件產生所述 字線包壓’所第-讀取/驗證條件與所述第三讀取/驗證 條件彼此不同。 16·如申请專利範圍第13項所述之非揮發性記憶體元 件,其中所述非揮發性記憶體元件包含: At頁面緩衝器’其耦接至所述記憶體單元陣列且經組 悲以經由與所述多個記憶體單元中之所述敎一者相關 聯的位元線讀取與所述多個記憶體單元中之所述選定一 者相關聯的資料;以及 控制逛輯,其耦接至所述頁面緩衝器且經組態以根 ΐ所ΐ多巧記憶體單元中之所述選定—者是所述偶數記 ,體f域是所料數記憶體單元喊顺所述多個記 體單元中之所述選定一者相關聯的所述位元線。 17·如巾請專觀㈣16項所狀_發性記憶體元 件,其中所述控制邏輯包含: 偶數恰間配平電路,其經組態以在所述多個記憶體 43 200849250 Z/3DUpiI 單元中之所述選定一者為所述偶數單元時對於第一預先 充電時間預先充電與所述多個記憶體單元中之所述選定 一者相關聯的所述位元線,且對於第一單元電流開發時 . 間開發與所述多個記憶體單元中之所述選定一者相關聯 的所述位元線;以及 奇數時間配平電路,其經組態以在所述多個記憶體 單元中之所述選定一者為所述奇數單元時對於第二預先 充電時間預先充電與所述多個記憶體單元中之所述選定 ^ 一者相關聯的所述位元線,且對於第二單元電流開發時 間開發與所述多個記憶體單元中之所述選定一者相關聯 的所述位元線。 18.如申請專利範圍第12項所述之非揮發性記憶體元 件,其中所述記憶體單元陣列具有三維記憶體結構;以及 臨限電壓分佈根據所述多個記憶體單元中之所述選 定一者與所述記憶體單元陣列之第一層還是所述記憶體 單元陣列之第二層相關聯而不同。 C 19.如申請專利範圍第18項所述之非揮發性記憶體元 • 件,其中所述字線電壓產生器包含: : 第一層控制邏輯,其經組態以在所述多個記憶體單 元中之所述選定一者與所述記憶體單元陣列之所述第一 層相關聯時使用第一程式化操作條件來輸出所述字線電 壓;以及 第二層控制邏輯,其經組態以在所述多個記憶體單 元中之所述選定一者與所述記憶體單元陣列之所述第二 44 200849250 Z/33UpiI 層相關聯時使用第二程式化操作條件來輪出所述字線電 壓。 、 20·如申請專利範圍第19項所述之非揮發性記憶體元 • 件’其中所述弟一層控制邏輯經組態以在與所述記憶體單 , 元陣列之所述弟一層相關聯之讀取/驗證操作期間使用第 一讀取/驗證條件來輸出所述字線電壓,且所述第二層控制 邏輯經組態以在與所述記憶體單元陣列之所述第二層相關 〇 聯之讀取/驗證操作期間使用第二讀取/驗證條件來輪出所 述字線電壓,所述第一讀取/驗證條件與所述第二讀取/驗 證條件彼此不同。 45200849250 2735Upii X. Patent Application Range: 1. A method for driving a non-volatile memory element, the method comprising: • determining a structural shape and a position of a memory unit to be driven; and based on the determined result The optimized operating conditions drive the memory unit. A method of driving a non-volatile memory device as described in claim 1, wherein the operating conditions include a word line voltage, a bit line voltage, a well voltage, and a timing thereof. 3. The method of driving a non-volatile memory element as recited in claim 1, wherein the operating condition comprises a stylizing/reading/erasing condition. 4. The method of driving a non-volatile memory element according to claim 1, wherein the threshold voltage distribution differs depending on whether the memory unit to be driven is an even memory unit or an odd memory unit, and The width of the even digit line to which the even memory unit is connected is different from the width of the odd digit line to which the (J odd memory unit is connected). 5. The driving non-volatile as described in claim 4 The method of the memory device, wherein the operating condition is a stylized operating condition, and the memory unit is based on the word line to which the memory unit to be driven is connected to the even number of words The odd-numbered memory unit is further programmed with one of a first stylized operating condition and a second stylized operating condition, the first stylized operating condition and the second stylized operating condition being different from each other. The method of driving a non-volatile memory element according to claim 5, wherein driving the memory unit comprises performing an incremental step An hopping pulse stylization (ISPP) method, and the first stylized operating condition includes, and each of the first stylized operating conditions includes a stylized starting power, an ISPP increment level, and a stylized stop 7. The method of driving a non-volatile memory element according to the above-mentioned claim 1, wherein said operating condition is an even number according to a bit line to which said memory unit to be driven is connected The meta-line is also an odd-numbered bit line without (the same, wherein the operating condition is a bit line sensing operation condition, and driving the memory unit includes whether the bit line is an even bit line or an odd bit 兀The sensing operation condition is performed by one of the first sensing operating condition and the second sensing operating condition, the first sensing operating condition and the second sensing operating condition being different from each other. 8. The method of driving a non-volatile memory=piece according to claim 1, wherein the non-volatile memory element has a memory array having at least a first layer and a second layer, and a driving platform Memory The element includes one of a first driving operation condition and a second driving domain, the first driving operating condition and the second driving operating condition, according to the memory unit to be driven belonging to the *second layer Different from each other. μ ', 9 · A non-volatile memory component, comprising: ▲ at least two memory fresh elements, with nuclear structure and distribution characteristics of position changes; and control packet, which is configured to control The respective memory unit 41 200849250 L· / J JVjpil optimizes the operating conditions. The non-volatile memory element and the position described in the ninth item of the range include the word active area saltiness and the oil phase material line. The distance between the two. The four memory units are included in at least two memory layers. A non-volatile memory element comprising: a memory cell array comprising a plurality of memory cells, the plurality of cells, each of which is located in a plurality of word lines and a plurality of bits An intersection of the lines; a column decoder having a domain to the memory to select one of the plurality of word lines; and a phantom, and a 'heart generator' coupled to the a column decoder and configured to output a word pressure, the word line cake having an operational condition of a threshold distribution associated with a selected one of the plurality of cells. In the item of item 12, wherein the distribution of the limited surface is selected according to the plurality of households, whether it is an even memory unit or an odd memory. 14. The non-wave according to claim 13 of the patent application scope. The word line voltage generator includes an X. 兀 兀 兀 even voltage trimming circuit, and the selected one of the plurality of memories 42 Ο Ο 200849250 unit is the even number Outputting the word line power in the first stylized operating condition of the memory unit And an odd voltage trimming circuit that outputs the word line voltage under a second stylized operating condition when the selected one of the home memory cells is the (four) number memory cell. The non-volatile memory element as described in claim 14 wherein the even voltage trimming circuit is configured to generate the word line voltage in a first read/verify condition during a read/verify operation, And the odd voltage trimming circuit is configured to generate the word line overpacking by the second read/verify condition 'the first read/verify condition and the third read/verify condition are different from each other. The non-volatile memory component of claim 13, wherein the non-volatile memory component comprises: an At page buffer coupled to the memory cell array and via a group A bit line associated with the one of the plurality of memory cells reads data associated with the selected one of the plurality of memory cells; and controls a chat, coupled To the page buffer and via The state is selected as described in the cryptographic memory unit - the even number, the body f field is the number of memory cells, and the selected one of the plurality of logger units Associated with the bit line. 17 · For a towel, please (4) 16 items, the control logic includes: an even-numbered trimming circuit configured to be in the plurality The memory 43 is pre-charged with respect to the selected one of the plurality of memory cells for a first pre-charge time when the selected one of the Z/3DUpiI units is the even-numbered unit a meta-line, and for the first cell current development, develop the bit line associated with the selected one of the plurality of memory cells; and an odd time trim circuit configured to Pre-charging the bit associated with the selected one of the plurality of memory cells for a second pre-charge time when the selected one of the plurality of memory cells is the odd-numbered cell Yuan line, and for the second unit current is on The development with time of the plurality of memory cells in a selected one of said bit line associated. 18. The non-volatile memory component of claim 12, wherein the memory cell array has a three-dimensional memory structure; and a threshold voltage distribution is selected according to the plurality of memory cells One is different from the first layer of the memory cell array or the second layer of the memory cell array. C. The non-volatile memory element of claim 18, wherein the word line voltage generator comprises: : first layer control logic configured to be in the plurality of memories The selected one of the body cells is associated with the first layer of the memory cell array using a first stylized operating condition to output the word line voltage; and the second layer of control logic is grouped Using the second stylized operating condition to rotate the selected one of the plurality of memory cells when associated with the second 44 200849250 Z/33UpiI layer of the memory cell array Word line voltage. 20. The non-volatile memory element of claim 19, wherein the control layer is configured to be associated with the first layer of the memory array The first read/verify condition is used to output the word line voltage during a read/verify operation, and the second layer control logic is configured to be associated with the second layer of the memory cell array The second read/verify condition is used to rotate the word line voltage during the read/verify operation of the cascading, the first read/verify condition and the second read/verify condition being different from each other. 45
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