200847642 九、發明說明： 【發明所屬之技術領域】 本發明係有關於時序回復參數產生電路以及使用此時序回復 參數產生電路的訊號接收電路，特別有關於使用Mueller & Muller演算法之時序回復參數產生電路以及使用此時序回復參數 產生電路的訊號接收電路。 【先前技術】 一般而言，訊號處理電路當中會有一個時序回復電路修正取樣 器的取樣相位以得到正確的訊號。第丨圖繪示了習知技術之訊號 接收電路100。訊號接收電路1〇〇包含一取樣器、一類比數位 轉換器103 (ADC)、一數位訊號處理器1〇5以及一時序回復(timing recovery)電路107。數位訊號處理器1〇5包含一等化器1〇9以及 一量化器111，而時序回復電路107包含一時序回復參數產生電路 Π3、一迴路濾波器115以及一電壓控制振盪器in。取樣器ιοί 用以取樣類比訊號AS以產生取樣訊號SS、類比數位轉換器103 用以將取樣訊號SS轉換成數位訊號DS。數位訊號DS經等化器 109處理後形成等化數位訊號EDS，數位訊號DS經等化器1〇9和 量化器111處理後形成處理後數位訊號PDS。時序回復參數產生 電路113便根據等化數位訊號EDS以及處理後數位訊號PDS產生 時序回復參數TP，而後迴路濾波器ι15和電壓控制震盪器(VC〇) 117便根據時序回復參數TP調整取樣時脈訊號SCLK。 200847642 在此系統中，接收端看到的訊號可以冲卜^⑺表示， k 其中n(t)為白色高斯雜訊，T為週期。若假設第爪個symbol經 過取樣後假設取樣時間點為r +mT，則取樣過的訊號可以 χ(τ-l· mT) = h(r) am ，其中㈣?)表 不雜汛’時序回復（timingrecover^電路107便用以使取樣器 取樣在適當的相位而使得SNR比最高。 第2圖繪示了習知技術之利用脈衝響應而找出取樣點的示意 圖。脈衝響應以h(t)表示，接收端的脈衝響應是發射端的滤波器、 接收鈿的濾波器和通道（channel)之總和。如第2圖所示，符元 (symbol) h〇為現今訊號的脈衝響應（impulseresp〇nse) hi與h 則分別上一個週期與下一個週期的訊號的脈衝響應。一般而言， h0、M口 ^之間會存在著符碼間干擾(ISI)效應，第2圖所示之脈 衝響應即有著嚴重的ISI效應。然而，ISI效應對於時序回復電路 1〇7而言卻是重要的參考資訊。—般而言，會以時序函姉峡 fimction) 圖戶斤示在第3圖中，父零點(财0<^〇以1^〇如)义即 元ho的巾間點，理論上為最佳取樣點。時序函數可由聰心& muller演异法計算而得。第4圖緣示了習知技術之 mueller & muller 演算法之電路圖。如第4圖所示，時序回復參數產生電路⑴即 為使用mUeto&mulier·法之’絲產生之 π便供給㈣之處理雜個。_mueto&muiiei^^ 6 200847642 詳細描述已揭露於學術期刊·· K H MudlerandM Muiler，“Timing200847642 IX. Description of the Invention: [Technical Field] The present invention relates to a timing recovery parameter generating circuit and a signal receiving circuit using the timing recovery parameter generating circuit, and particularly relates to a timing response parameter using the Mueller & Muller algorithm A circuit is generated and a signal receiving circuit that uses the timing recovery parameter generating circuit. [Prior Art] In general, there is a timing recovery circuit in the signal processing circuit that corrects the sampling phase of the sampler to obtain the correct signal. The figure shows a signal receiving circuit 100 of the prior art. The signal receiving circuit 1A includes a sampler, an analog-to-digital converter 103 (ADC), a digital signal processor 1〇5, and a timing recovery circuit 107. The digital signal processor 1〇5 includes an equalizer 1〇9 and a quantizer 111, and the timing recovery circuit 107 includes a timing recovery parameter generating circuit Π3, a loop filter 115, and a voltage controlled oscillator in. The sampler ιοί is used to sample the analog signal AS to generate a sample signal SS, and the analog digital converter 103 is used to convert the sample signal SS into a digital signal DS. The digital signal DS is processed by the equalizer 109 to form an equalized digital signal EDS. The digital signal DS is processed by the equalizer 1〇9 and the quantizer 111 to form a processed digital signal PDS. The timing recovery parameter generating circuit 113 generates a timing recovery parameter TP according to the equalized digital signal EDS and the processed digital signal PDS, and the rear loop filter ι15 and the voltage controlled oscillator (VC〇) 117 adjust the sampling clock according to the timing recovery parameter TP. Signal SCLK. 200847642 In this system, the signal seen by the receiving end can be represented by ^(7), where k(n) is white Gaussian noise and T is periodic. If it is assumed that the first claw symbol is sampled and the sampling time point is r +mT, the sampled signal can be τ(τ-l· mT) = h(r) am , where (4)?) (The timingrecover^ circuit 107 is used to sample the sampler at the appropriate phase to maximize the SNR ratio. Figure 2 is a schematic diagram showing the sampling point using the impulse response of the prior art. The impulse response is h(t) It indicates that the impulse response at the receiving end is the sum of the filter at the transmitting end, the filter and the channel receiving the 。. As shown in Fig. 2, the symbol h 〇 is the impulse response of the current signal (impulseresp〇nse) Hi and h are the impulse responses of the signals of the previous cycle and the next cycle. In general, there is an inter-symbol interference (ISI) effect between h0 and M, and the impulse response shown in Figure 2 is There is a serious ISI effect. However, the ISI effect is an important reference for the timing recovery circuit 1〇7.—Generally, it will be shown in the third picture, the parent is shown in Fig. 3, the parent. Zero point (Cai 0<^〇1^〇如如) means the point of the ho, On the optimum sampling point. The time series function can be calculated by the Confidence & muller algorithm. Figure 4 shows the circuit diagram of the mueller & muller algorithm of the prior art. As shown in Fig. 4, the timing recovery parameter generating circuit (1) supplies the processing of (4) using the π generated by the mUeto & muier method. _mueto&muiiei^^ 6 200847642 Detailed description has been exposed in academic journals·· K H MudlerandM Muiler, “Timing
Recovery in Digital Synchronous Data Receivers，” IEEE Trans.Recovery in Digital Synchronous Data Receivers,” IEEE Trans.
Communications，vol. Com_24, pp 516_531，May 1976。 如上所述’利用mueller & muller演算法可藉由ISI效應而求得Communications, vol. Com_24, pp 516_531, May 1976. As described above, using the mueller & muller algorithm can be obtained by the ISI effect.
正確之取樣點。然而，第1圖中所述的等化器109卻有消除ISI 效應的效果’如此反而會造成取樣點的判斷錯誤。如第5圖所示， 經過等化器109之處理後，符元h。、hi和h i之間不會有⑸現象。 然而’這樣的符元在經過鱗函數之處理後，會如第6圖所示， 在=應該出現交零點的地方出現一個區域γ。如此新的取樣點 可能落於區域Υ中的任—點，零和點會漂移，因此可能會造成取 樣點的選擇錯誤’並造成時序回復電路1〇7的損壞。而且，在此 結構中，封閉式的迴路包含了等化器，等化器可 ⑹verge)的情況。 # 除此之外，由於通道的脈衝響應是不對稱的，因此若傳輸訊號 ^輪線過長，不對稱的情況會更嚴重。第6 _示了因為傳輸 梅路而不對稱的脈衝響應之示意圖。如第6騎示，符元以不 3 3圖或第5圖所示的hQ、卜和匕—般是完美的波形，而是有 :延長域z ’如此亦會干制正確取_的觀。隨著線長 零和點會逐漸右移’也就是轉點會接近下—個訊號。 打^化器對於上-個訊號之干擾的抗性比下—個訊號之干擾的 几ϋ來得鬲，因此這樣的情況是極需避免的。 200847642 • 因此，需要一種新穎的發明來改善上述問題。 【發明内容】 因此’本發明的目的之-為提供一種訊號接收電路，其參考未 經過荨化處理的訊號計算出正確的取樣點。 本發明的目的之一為提供一種時序回復參數產生電路，其可修 正因為傳輸線之長度而產生的誤差。 本發明的目的之一為提供一種時序回復參數產生電路，其可根 據脈衝響應之權重調整取樣點。 本發明之實施例揭露了一種訊號接收電路，包含：一取樣器， 用以接收一類比訊號並根據一取樣時脈取樣該類比訊號以形成一 取樣訊號；一類比數位轉換器，耦接至該取樣器，用以將該取樣 峨轉換成-數位訊號；一等化器，搞接至該類比數位轉換器， 用以等化該數位訊號以形成一等化數位訊號；一量化器，粞接至 忒等化器，用以量化該等化數位訊號以形成一處理後數位訊號； 以及一時序回復電路，直接連接至該取樣器之輸出端以及耦接至 °亥里化為’用以根據該處理後數位訊號以及該數位訊號來調整該 取樣時脈之時序。 本發明之實施例亦揭露了一種時序回復參數產生電路，用以估 測取樣時脈之時序誤差以產生一目標時序回復參數，包含：一 8 200847642 數健號翻電路，㈣接收—數钱砂纽-處理後數位訊 號’一H電路，雛至該數位訊號處理電路，係使用Mueller & ^ ’’、开法，用以接收该處理後數位訊號以及該數位訊號並根 據該處理後數位訊號以及該數位訊號計算出一初步時序回復參 數；一候選值產生電路，用以提供複數個候選值；以及一多工器， 搞接於_异電路以及雜選值產生電路之間，贱根據一選擇 訊號選擇該複數個候選值其中之—以作為—調整值；其中該計算 電路另根_調整值以及該初步時相復參數域生該目標時序 回復參數。 本么明之實施例更揭露了一種時序回復參數產生電路，用以估 ’則取樣時脈之時序誤差以產生一目標時序回復參數，包含：一 數位汛唬處理電路，用以接收一數位訊號以產生一處理後數位訊 號’叶算電路，係使用Mueller & Muller演算法，用以接收該 處理後數位訊號以及該數位訊號並根據該處理後數位訊號以及該 數位訊號計算出一初步時序回復參數；以及一調整值產生電路， 耦接至該計算電路，用以根據數位訊號之前一訊號以及後一訊號 的第一權重值以及一第二權重值產生一調整值；其中該計算電 路根據該調整值來調整該初步時序回復參數以產生該目標時序回 復參數。 【實施方式】 第8圖繪示了根據本發明之實施例的訊號接收電路8〇0之電路 圖。如第8圖所示，訊號接收電路800與訊號接收電路1〇〇相同， 9 200847642 亦包含一取樣器801、一類比數位轉換器803、一數位訊號處理 器805以及一時序回復電路807。數位訊號處理器805亦包含一等 化器809以及一量化器811，而時序回復電路807亦包含一時序回 復參數產生電路813、一迴路濾波器815以及一電壓控制振盡器 817 〇 訊號接收電路800與訊號接收電路1〇〇的不同之處在於在訊號 接收電路800中時序回復電路807並不直接耦接於等化器⑽9和 811之間，而是直接耦接於等化器809之前。因此，時序回復電路 807並不依據被等化器809所處理過的等化數位訊號eds作為調 整取樣時脈SCLK之依據，而是利用未被等化器8〇9所處理過的 數位訊號DS作為調整取樣時脈SCLK之依據。 藉由此結構，由於時序回復電路807使用未被等化器8〇9所處 理過的數位訊號DS作為調整取樣時脈SCLK之依據。因此不會有 如述的因為ISI現象而造成取樣點錯誤之問題，而且閉式迴路不 包含等化器，等化器不會有發散的危險。此外，時序回復電路807 亦不會有損壞的危險。 ;第9崎示了根據本發明的時相復參數產生 電路90】之電路圖，其可改善上述之因為傳輸線之長度而造成取 擇錯誤之縣。如第9 0卿’時細復參數產生電路· j-計算電路903、一候選值產生電路贿、以及一多工器術。 計算電路903在本實施例中亦是使用mueller&_er演算法，其 10 200847642 搞接至第8圖所示之等化器109以及量化器ill，用以接收處理後 數位訊號PDS以及數他號DS錄據處理魏位峨咖以及 數位訊號DS計算出—初步時序回復參數。候選值產生電路9仍 用以提供複數個候選值（此實施例中為候選值丨〜5)。多工器9町 耦接於計异電路9〇3以及候選值產生電路9〇5之間，用以根據一 選擇訊號SS選擇複數個候選值其中之一以作為一調整值顧 且計算電路903另根據調整值ADV來調整該取樣時脈之時序。 在此實施例中，計算電路9〇3餘接至第8圖之類比數位轉換 器803而接收由類比數位轉換^ 8〇3所產生的數位訊號Μ，選擇 訊號SS可為調整訊號接收電路_之增益的自動增益控制訊號 (autogain control signai)，候選值卜5則是對應不同的傳輸線長度 之數值。易而言之，但這些參數並非用以限定本發明，此電路之 架構亦可視需求而代人不同之參數’其亦在本發明的範圍之内。 計算電路903雖然以mueiier&muner演算法為基礎，但亦可以用 其他演算法算出初步時序回復參數。 除此之外，在此實施例中計算電路903係將初步時序回復參數 減去調整值ADV而產生時序回復參數TP，但並非用以限定本發 明。易而言之，時序回復參數TP原本是由 /(γ)ι(α(γ+γ)—蛛—r))q(n)計算出來，在時序回復參數產生電路 9〇1則變成了 /⑺= > + r))=>—aj—心·。如上所述時序 回復參數ΤΡ若減去一正值，有將取樣點往左移的效果。 200847642 . 帛1G_示了賴在第9 _示之時相復參數產生電路的 對照表。如第U) _示’當傳輸線長度為Q公尺時，選擇候選值 1 ’當傳輸線長度為50公尺時，選擇候選值2……以此類推。而不 同的候遠值則對應到不同的、值。因此，時序回復表數產生電 路撕係利用選擇訊號SS選擇出對應不同傳輸線長度的、 值’而後再將初辦序轉參數減去“值喊生時序回復參數 須/主W的疋若Kcabie值為正，有使取樣點左移的效果，可避 Γ免碱文下-訊號的影響。若值為負，則有使取樣點右移的 效果，可避免訊號受前-訊號的影響。然而，如上所述，等化器 對於前-個訊號之干擾的抗性比下一個訊號之干擾的抗性來得 高，因此本實施例皆以正值的1舰值做例子，但並不表示時序回 復參數產生電路901僅適用於正的k值。 第11〜13圖纷示了不同之取樣點與權重之關係的示意圖。第 14圖綠示了根據本發明之第二實施例的時序回復參數產生電路 1400之電路圖，時相復參數產生测係_訊號之權重調 整取樣點。請先參照第11〜13圖，如第圖所示，權重會反 應出取樣點之偏移現象。例如在第u圖中，當取樣點往左偏時， 很明顯的右邊之權重Q會比左邊的權重p來得小。而在第12圖 中取樣點並無偏移之情況，因此權重Μ和權重n的大小一樣。 同樣的，在第13圖中取樣點往右偏，因此χ點的權重會比丫點 的權重來得小。 如上所述，只要得知前一訊號以及後一訊號的權重，便可得知 12 200847642 取樣點雜左雜右軸。時序喊參數產生電路14⑻便利用此 概念调整取樣點。如第14圖所示，時序回復參數產生電路觸 包含-计算電路1·、—權重計算電路·以及一調整值產生電 路1405。計算電路1401係使用Mueller & Muller演算法，用以 接收-數健號以及-處理紐位峨酬並根據處理後數位訊 號PDS以及數位訊號ds計算出一初步時序回復參數。權重計算 電路1彻祕至計算電路剛，用以根據數位訊號之前一訊號以 及後一詋唬分別計异出一第一權重值评〗以及一第二權重值π]。 調整值產生電路M〇5轉接至計算電路刪，用以根據第一權重值 W!以及第二權重值％產生一調整值ADV。計算電路·則根 據調整值ADV來調整初步時相復錄以產生時序回復參數 tp。須注意的是’第14圖中雖以權重計算電路14〇3計算出權重， 但並非用以限定本發明，熟知此項技#者當可_其他方法而得 到所須的射值，其亦在本發_範圍之内。 在此實施例中，調整值電路1405係將第一權重\^減去第二 權重％以產生調整值ADV，而計算電路12〇1係將初步時序回復 參數減去婦值ADV而產生時相復參數TP。若料13圖作為 例子’將X點的權重作為第—權重^，將γ點的權重作為第二 權重W2 H周整值adv為負值，如此便得知取樣點該往左偏。 相反的，若以第11圖作為例子，將Ρ點的權重作為第一權重Wi， 將Q點的權重作為第二權重％，則調整值ADV為正值，如此便 得知取樣點該往右偏。 13The correct sampling point. However, the equalizer 109 described in Fig. 1 has the effect of eliminating the ISI effect', which in turn causes a judgment error of the sampling point. As shown in Fig. 5, after the processing by the equalizer 109, the symbol h is obtained. There will be no (5) phenomenon between hi and hi. However, after such a symbol is processed by the scale function, as shown in Fig. 6, an area γ appears where = zero crossing should occur. Such a new sampling point may fall at any point in the area ,, and the zero sum point may drift, which may cause the selection of the sampling point to be erroneous and cause damage to the timing recovery circuit 1〇7. Moreover, in this configuration, the closed loop contains an equalizer, and the equalizer can be (6) verge). # In addition, since the impulse response of the channel is asymmetrical, if the transmission signal is too long, the asymmetry will be more serious. Figure 6 shows a schematic diagram of the asymmetric impulse response due to the transmission of the road. For example, if the 6th rider shows that the symbol is not the 3Q or the hQ, Bu and 匕 shown in Figure 5, it is a perfect waveform, but there is: extension of the domain z 'so will also make the correct view . As the line length zero and the point will gradually shift to the right 'that is, the turning point will be close to the next signal. The resistance of the device to the interference of the previous signal is better than the interference of the next signal, so this situation is extremely difficult to avoid. 200847642 • Therefore, a novel invention is needed to improve the above problems. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a signal receiving circuit that calculates a correct sampling point with reference to a signal that has not been subjected to deuteration. It is an object of the present invention to provide a timing recovery parameter generating circuit which corrects an error due to the length of a transmission line. It is an object of the present invention to provide a timing recovery parameter generating circuit that adjusts sampling points according to the weight of an impulse response. An embodiment of the invention discloses a signal receiving circuit comprising: a sampler for receiving a analog signal and sampling the analog signal according to a sampling clock to form a sampling signal; an analog converter coupled to the signal a sampler for converting the sample 峨 into a digital signal; a first equalizer coupled to the analog digital converter for equalizing the digital signal to form an equalized digital signal; a quantizer And an equalizer for quantizing the equalized digital signal to form a processed digital signal; and a timing recovery circuit directly connected to the output of the sampler and coupled to the image to be used as The processed digital signal and the digital signal adjust the timing of the sampling clock. An embodiment of the present invention also discloses a timing recovery parameter generating circuit for estimating a timing error of a sampling clock to generate a target timing recovery parameter, comprising: an 8 200847642 digital health circuit, (4) receiving - counting sand New-processed digital signal 'an H circuit, to the digital signal processing circuit, using Mueller & ^ '', open method for receiving the processed digital signal and the digital signal and according to the processed digital signal And the digital signal calculates a preliminary timing recovery parameter; a candidate value generating circuit is configured to provide a plurality of candidate values; and a multiplexer is connected between the _ different circuit and the hash value generating circuit, The selection signal selects the plurality of candidate values as the - adjustment value; wherein the calculation circuit has another root_adjustment value and the preliminary time phase complex parameter domain to generate the target timing recovery parameter. The embodiment of the present invention further discloses a timing recovery parameter generating circuit for estimating a timing error of a sampling clock to generate a target timing recovery parameter, comprising: a digit processing circuit for receiving a digital signal Generating a processed digital signal 'leaf circuit, using Mueller & Muller algorithm, for receiving the processed digital signal and the digital signal and calculating a preliminary timing recovery parameter according to the processed digital signal and the digital signal And an adjustment value generating circuit coupled to the calculation circuit for generating an adjustment value according to the first signal of the digital signal and the first weight value of the subsequent signal and a second weight value; wherein the calculation circuit is based on the adjustment The value adjusts the preliminary timing recovery parameter to generate the target timing recovery parameter. [Embodiment] FIG. 8 is a circuit diagram of a signal receiving circuit 8〇0 according to an embodiment of the present invention. As shown in FIG. 8, the signal receiving circuit 800 is identical to the signal receiving circuit 1A. 9 200847642 also includes a sampler 801, an analog-to-digital converter 803, a digital signal processor 805, and a timing recovery circuit 807. The digital signal processor 805 also includes an equalizer 809 and a quantizer 811, and the timing recovery circuit 807 also includes a timing recovery parameter generating circuit 813, a loop filter 815, and a voltage control oscillating device 817 〇 signal receiving circuit. The difference between the 800 and the signal receiving circuit 1 is that the timing recovery circuit 807 is not directly coupled between the equalizers (10) 9 and 811 in the signal receiving circuit 800, but is directly coupled to the equalizer 809. Therefore, the timing recovery circuit 807 does not use the equalized digital signal eds processed by the equalizer 809 as the basis for adjusting the sampling clock SCLK, but uses the digital signal DS that has not been processed by the equalizer 8〇9. As the basis for adjusting the sampling clock SCLK. With this configuration, the timing recovery circuit 807 uses the digital signal DS that has not been processed by the equalizer 8〇9 as the basis for adjusting the sampling clock SCLK. Therefore, there is no problem that the sampling point is wrong due to the ISI phenomenon, and the closed circuit does not include the equalizer, and the equalizer does not have the risk of divergence. In addition, the timing recovery circuit 807 is not at risk of damage. The ninth is a circuit diagram of the time-phase complex parameter generating circuit 90 according to the present invention, which can improve the above-mentioned county which causes the error due to the length of the transmission line. For example, the "0" complex parameter generating circuit j-calculation circuit 903, a candidate value generating circuit bribe, and a multiplexer. In this embodiment, the calculation circuit 903 also uses the mueller&_er algorithm, and its 10 200847642 is connected to the equalizer 109 and the quantizer ill shown in FIG. 8 for receiving the processed digital signal PDS and the number of other signals. The DS record processing Wei Wei and the digital signal DS calculate the preliminary timing recovery parameters. The candidate value generating circuit 9 is still used to provide a plurality of candidate values (the candidate values 丨 〜 5 in this embodiment). The multiplexer 9 is coupled between the counting circuit 9〇3 and the candidate value generating circuit 9〇5 for selecting one of the plurality of candidate values according to a selection signal SS as an adjustment value and calculating circuit 903. The timing of the sampling clock is also adjusted according to the adjustment value ADV. In this embodiment, the calculation circuit 〇3 is connected to the analog-to-digital converter 803 of FIG. 8 to receive the digital signal 产生 generated by the analog-to-digital conversion 〇8〇3, and the selection signal SS can be the adjustment signal receiving circuit _ The gain of the automatic gain control signal (autogain control signai), the candidate value of 5 is the value corresponding to the length of the different transmission line. In other words, these parameters are not intended to limit the invention, and the architecture of the circuit may also vary depending on the requirements, and it is also within the scope of the invention. Although the calculation circuit 903 is based on the mueiier & muner algorithm, other algorithms can be used to calculate the preliminary timing recovery parameters. In addition, in this embodiment, the calculation circuit 903 subtracts the adjustment value ADV from the preliminary timing recovery parameter to generate the timing recovery parameter TP, but is not intended to limit the present invention. In short, the timing recovery parameter TP is originally calculated by /(γ)ι(α(γ+γ)- spider-r))q(n), and becomes 9 in the timing recovery parameter generating circuit 9〇1. (7)= > + r))=>—aj—heart·. As described above, the timing recovery parameter 减 subtracts a positive value and has the effect of shifting the sampling point to the left. 200847642 . 帛1G_ shows a comparison table of the complex parameter generation circuits at the time of the 9th _. As shown in Fig. U) _ shows 'When the transmission line length is Q meters, the candidate value 1 ' is selected. When the transmission line length is 50 meters, the candidate value 2 is selected... and so on. Different distance values correspond to different values. Therefore, the timing recovery table number generating circuit tearing system uses the selection signal SS to select the value corresponding to the length of the different transmission lines, and then subtracts the initial sequence rotation parameter from the value of the value. If it is positive, there is an effect of shifting the sampling point to the left to avoid the influence of the underlying text-signal. If the value is negative, there is an effect of shifting the sampling point to the right to avoid the influence of the pre-signal. As described above, the equalizer's resistance to the interference of the previous signal is higher than the interference of the next signal. Therefore, in this embodiment, the positive value of the ship value is taken as an example, but the timing is not represented. The reply parameter generation circuit 901 is only applicable to a positive k value. Figures 11 to 13 show a schematic diagram of the relationship between different sampling points and weights. Fig. 14 is a green diagram showing the timing recovery parameters according to the second embodiment of the present invention. The circuit diagram of the circuit 1400 is generated, and the time-phase complex parameter is used to generate the weight of the measurement system _ signal to adjust the sampling point. Please refer to the 11th to 13th pictures first, as shown in the figure, the weight will reflect the offset phenomenon of the sampling point. For example, in the first u, when the sampling point is to the left In the partial time, it is obvious that the weight Q on the right side is smaller than the weight p on the left side. In the 12th picture, the sampling point has no offset, so the weight Μ is the same as the weight n. Similarly, in the 13th In the figure, the sampling point is shifted to the right, so the weight of the defect is smaller than the weight of the defect. As mentioned above, as long as the weight of the previous signal and the latter signal is known, it can be known that 12 200847642 sampling point miscellaneous The right axis. The timing shouting parameter generating circuit 14 (8) facilitates the adjustment of the sampling point by this concept. As shown in Fig. 14, the timing recovery parameter generating circuit touches the inclusion-computing circuit 1·, the weight calculating circuit, and an adjustment value generating circuit 1405. The calculation circuit 1401 uses the Mueller & Muller algorithm to receive the -number key and the processing button and calculate a preliminary timing recovery parameter based on the processed digital signal PDS and the digital signal ds. The weight calculation circuit 1 The secret calculation circuit is used to calculate a first weight value and a second weight value π according to a signal before and after the digital signal. The adjustment value generating circuit M〇5 Connected to the calculation circuit to generate an adjustment value ADV according to the first weight value W! and the second weight value %. The calculation circuit then adjusts the preliminary phase phase duplication according to the adjustment value ADV to generate the timing recovery parameter tp. Note that although the weight calculation circuit 14〇3 calculates the weight in FIG. 14 , it is not intended to limit the present invention, and those skilled in the art can obtain the required image value by other methods. In this embodiment, the adjustment value circuit 1405 subtracts the second weight % from the second weight to generate the adjustment value ADV, and the calculation circuit 12〇1 subtracts the preliminary timing recovery parameter. The woman phase value ADV produces the phase complex parameter TP. If the figure 13 is taken as an example, the weight of the X point is taken as the first weight ^, and the weight of the γ point is taken as the second weight W2 H week integer value adv is negative, so Know that the sampling point should be left to the left. On the contrary, if the weight of the defect is taken as the first weight Wi and the weight of the Q point is taken as the second weight %, the adjustment value ADV is positive, so that the sampling point should be right. Partial. 13
V 200847642 須注意的是’计异電路1401雖然以mueller & muller演管法為 基礎，但亦可以用其他演算法算出初步時序回復參數。而且，時 序回復參數產生電路1400在本實施例中雖使用在第8圖所示的訊 號接收電路800上，但相同的架構亦可使用在其他之電路上，其 亦在本發明的範圍之内。 縱上所述，第8圖所示的訊號接收電路8〇〇係用以找出正確的 取樣點（即取樣相位），而第9圖和第12圖所示的時序回復參數產 生電路900和1400係用以辅助訊號接收電路8〇〇以找出更精確的 取樣點。 $ 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖繪示了習知技術之訊號接收電路。 第2圖繪示了有ISI現象的脈衝響應。 第3圖繪示了習知技術之利用脈衝響應而找綠樣•點的示意圖 第4圖繪示了習知技術之mueller & muller演算法之電路圖。 第5圖繪示了無isi現象之脈衝響應的示意圖。 第6圖繪示了_第5圖所示的脈衝響應找出取樣點之示意圖。 第7圖繪示了因為傳輸線路而不對稱的脈衝響應之示咅圖 第8圖繪示了根據本發明之實施例的訊號魏電路圖。 第9圖繪示了根據本發明之第—實施例的時細復參數產生 14 200847642 電路之電路圖。 了不同之取樣點與權重V 200847642 It should be noted that the 'counting circuit 1401 is based on the mueller & muller method, but other algorithms can be used to calculate the preliminary timing recovery parameters. Moreover, the timing recovery parameter generation circuit 1400 is used in the signal receiving circuit 800 shown in FIG. 8 in this embodiment, but the same architecture can be used on other circuits, which is also within the scope of the present invention. . In the above, the signal receiving circuit 8 shown in FIG. 8 is used to find the correct sampling point (ie, the sampling phase), and the timing recovery parameter generating circuit 900 shown in FIGS. 9 and 12 is The 1400 is used to assist the signal receiving circuit 8 to find more accurate sampling points. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing a signal receiving circuit of the prior art. Figure 2 shows the impulse response with the ISI phenomenon. FIG. 3 is a schematic diagram showing a conventional technique for finding a green sample using a pulse response. FIG. 4 is a circuit diagram showing a mueller & muller algorithm of the prior art. Figure 5 is a schematic diagram showing the impulse response without the isi phenomenon. Figure 6 is a schematic diagram showing the sampling points of the impulse response shown in Figure 5. FIG. 7 is a schematic diagram showing an asymmetrical impulse response due to a transmission line. FIG. 8 is a circuit diagram showing a signal according to an embodiment of the present invention. Figure 9 is a circuit diagram showing the circuit of the hourly complex parameter generation according to the first embodiment of the present invention. Different sampling points and weights
第10圖繪示了使用在第9圖 對照表。 第11〜13圖繪示 弟14圖纷 電路之電路圖。 所示之時序回復參數產生電路的 【主要元件符號說明】 100、800訊號接收電路 1〇卜801取樣器 103、803類比數位轉換器 105、805數位訊號處理器 107、807時序回復電路 109、809等化器 in、811量化器 113、813時序回復參數產生電路 115、815迴路濾波器 117、817電壓控制振盪器 901時序回復參數產生電路 903計算電路 905候選值產生電路 907多工器 1400時序回復參數產生電路 15 200847642 1401計算電路 1403權重計算電路 1405調整值產生電路Figure 10 depicts a comparison table used in Figure 9. Figures 11 to 13 show the circuit diagram of the circuit of the brother 14 . [Main component symbol description] of the timing recovery parameter generating circuit shown in the figure 100, 800 signal receiving circuit 1 801 sampler 103, 803 analog digital converter 105, 805 digital signal processor 107, 807 timing recovery circuit 109, 809 Equalizer in, 811 quantizer 113, 813 timing recovery parameter generation circuit 115, 815 loop filter 117, 817 voltage control oscillator 901 timing recovery parameter generation circuit 903 calculation circuit 905 candidate value generation circuit 907 multiplexer 1400 timing response Parameter generation circuit 15 200847642 1401 calculation circuit 1403 weight calculation circuit 1405 adjustment value generation circuit