200847430 九、發明說明： 【發明所屬之技術領域】 特別是有關一種金氧半 本發明係有關一種半導體元件及其操作方法 導體元件及其操作方法。 【先前技術】 日進千里的積體電路技術造就電腦、通訊與網路業的蓬勃發展，而盆 進步的原動力，在於金氧半導體元件尺寸不斷地縮小而改善了切換速度與 雜功率，同時亦提升了電路之元件積·度與功祕(如資_存、邏輯 運算訊號處理等），以邏輯疋件為例，高速度的邏輯元件須仰賴足夠高的 飽和没極電流與低閘極電容，而低耗電量麵仰賴更低的漏電流。 不匕在金氧半導體元件縮小化的過程中，金氧半導體元件的結構是 以三維結_縮小，習知的金氧轉體元件結構係如第—圖所示，係包括 基板10在此基板1〇内係具有源極1〇2、沒極⑽以及通道仙，而在 基板ίο的上方係形成依序形綱極介電層12以及閘極層14，而對於此金 氧半V體it件來4 ’除了整體的長、寬外，剖面_極氧化層12厚度與源 極102及極1〇4接面深度···等等結構上的因素，皆會影響此金氧半導體的 表現例如·藉由長度與寬度小型化以提昇金氧半導體元件積成的密度， 另外，因為驅動電流和通道長度成反比的關係，因此通道101長度的減少 此逹到增進，轉i力的效果’而在製程上的主要瓶綱係在於微影技術 的限制’且由於源極1〇2、沒極1〇4所具有的電性表現係不同於通道1〇1的 電/±表現’不但使得金氧半導體元件在製程上變得複雜，因此，當源極⑽、 /及極104與通道！01之間發生離子擴散的問題時，則將使得整體元件在應 200847430 科的微縮性變得很差，另外’由於源極102、没極1〇4與通道ι〇ι之間的 電性問題’在習知的金氧半導體元件中的閘極下方係形成一反轉層 (inversion layer)i41以使得此金氧半導體可實現讀取的操作不過卻 •使得載子在此反轉層141⑽行傳遞時，反而引發-感應電流的產生，造 成錄半賴元件在電性上的失效；又，就錢轉體元縣身的特性而 言，為了魏航臟通道效應與料道效躺辟，_舰應的控制 則可針對調整金氧半導體元件麻方向結構的參數以為手段，例如：減少 閘極介電層12厚度與接面深度，以及增加基板1〇的離子植入濃度…等等。 然而，上述改變接面深度、增加基板的離子植入濃度的方法，在習知 的技術中多透過離子植入之手段進行，以使金氧半導體元件可獲得精確的 電子特性。因為被植入的離子必須先加速至具有足夠能量與速度植入至元 件中，以到達預定的植入深度，同時，離子植入的摻質濃度則是可透過製 程參數加以精密地控制。 惟’就目前常見的金氧半導體元件結構而言，為了避免金氧半導體元 件尺寸微小化後所導致的種種問題，係在金氧半導體元件的基板内不同區 域中形成各種不同離子植入種類、離子植入濃度的離子植入區域，但因為 金氧半導體元件的尺寸縮小，因而使得各個離子植入區域相對變得更小， 且各個離子植入區域之間的間距變小，反而使得整體的金氧半導體元件之 結構變得更加複雜’同時也提高了元件的製程複雜度、降低了最終元件的 精準度。 以美國專利第6704235號為例，其係提供一種記憶元件之結構，請參 200847430 中在兩導電層21、25之間的複數層狀結構係構成一 /L ^ , °己憶早元，且此些層狀 結構係包括有半導體層22、儲存介電層26、淺棺A & π 八層23、重植入層24， 不過，由於在此習知的記憶元件中的層狀結構不麵當地複雜且多層，同 時更必須根據不同層狀結構的功能以逐層触刻出特定的形狀，因此，對於 製作的流程上來說，係相當地繁複且必須耗費較高的製程與材料成本。 基於上述之習知技術可知，本發明係郎_種金屬半物元件及其操 作方法，以解決習知技術所遭遇之困難。 【發明内容】 本發明之主要目的，絲出-種金財導航件及鶴作方法，直係 藉由平厂離子植入層結構取代習知源極、沒極之結構，以降低金氧半導體 元件在進行程式化、抹除時所需之功率。 本發明之另-目的，係提出—種金財導體元件及其操作方法 藉由較簡化的金氧半導體結構，以使得金氧半導體在堆疊成 唯元 件之微縮性可大幅提昇。 ^ 一、准凡 為達上述之目的，树賴供—種錄铸狀轉 導體元件係包括一元件層，於此元件層之至少一表面上係形成-離子植t :在離子植人層上則形成至少—_結構，且在此間極結構係包括—介 一刪’其中’蝴蝴鄉㈣自料導體材科、或 疋絕緣材科、或是複合材料，且元件層射以底縣板 / 結構的型態來呈現，且且有單 間層狀 /、有早一離子植入種類的離子植入層係同時可提供 源極、汲極與__，心梅層之三、 200847430. 明治結構’且較常見的材料則有氧切/氮鑛氧化石夕 則係可選自多晶稽料或是金屬材料...等等。 本發明尚提供一種金氧半導體元科 入層的70件層上形成複數烟極結構， 線，且在此些閘極結構上更形成與字元 錯的位元線與字元線以構成_金氧半導200847430 IX. Description of the invention: [Technical field to which the invention pertains] In particular, the invention relates to a semiconductor element and a method of operating the same, and a method of operating the same. [Prior Art] The integrated circuit technology of the company has created a boom in the computer, communication and networking industries. The driving force behind the advancement of the basin is that the size of the MOS components is continuously reduced, which improves the switching speed and the power, and also improves The component product and degree of the circuit (such as resource storage, logic operation signal processing, etc.), taking logic components as an example, high-speed logic components must rely on a sufficiently high saturation current and low gate capacitance. The low power consumption side relies on lower leakage current. In the process of downsizing the MOS device, the structure of the MOS device is reduced by a three-dimensional junction, and the conventional MOS device structure is as shown in the first figure, including the substrate 10 on the substrate. The 1〇 internal system has a source 1〇2, a dipole (10), and a channel fairy, and a sequential polar dielectric layer 12 and a gate layer 14 are formed on the upper side of the substrate ίο, and for this gold oxide half V body it In addition to the overall length and width, the thickness of the profile _ pole oxide layer 12 and the depth of the junction of the source 102 and the pole 1 〇 4··· etc. will affect the performance of the MOS. For example, the length and width are miniaturized to increase the density of the MOS device. In addition, since the drive current is inversely proportional to the length of the channel, the length of the channel 101 is reduced, and the effect of the transfer force is improved. The main bottle system in the process is the limitation of lithography technology, and the electrical performance of the source 1〇2 and the 极1〇4 is different from the electric/± performance of the channel 1〇1. Metal oxide semiconductor components become complicated in the process, so when the source (10), / and pole 104 and channel! When the problem of ion diffusion occurs between 01, the micro-component of the whole component in the 200847430 family becomes poor, and the 'electricity problem between the source 102, the poleless 1〇4 and the channel ι〇ι 'An inversion layer i41 is formed under the gate in the conventional MOS device so that the MOS can perform the reading operation. However, the carrier is inverted at the layer 141 (10). When it is transmitted, it causes the generation of induced current, which causes the electrical failure of the recorded components. In addition, in terms of the characteristics of the body of the money, the dirty channel effect and the material effect of the Wei Hang are The control of the ship should be used to adjust the parameters of the structure of the MOS element, such as reducing the thickness of the gate dielectric layer 12 and the junction depth, and increasing the ion implantation concentration of the substrate 1 and the like. However, the above-described method of changing the junction depth and increasing the ion implantation concentration of the substrate is carried out by means of ion implantation in a conventional technique to obtain accurate electronic characteristics of the MOS device. Because the implanted ions must first be accelerated to have sufficient energy and velocity to be implanted into the component to reach a predetermined implant depth, while the ion implanted dopant concentration is precisely controlled by process parameters. However, in order to avoid various problems caused by the miniaturization of the size of the MOS device, various kinds of ion implantation types are formed in different regions of the substrate of the MOS device, The ion implantation concentration of the ion implantation region, but because of the size reduction of the MOS device, the respective ion implantation regions are relatively smaller, and the spacing between the respective ion implantation regions becomes smaller, instead making the overall The structure of MOS devices has become more complex' while also increasing the complexity of the components and reducing the accuracy of the final components. Taking U.S. Patent No. 6,704,235 as an example, it provides a structure of a memory element, and the plurality of layered structures between the two conductive layers 21 and 25 in 200847430 constitute a /L ^ , ° recall early, and The layered structure includes a semiconductor layer 22, a storage dielectric layer 26, a shallow A & π eight layer 23, and a re-implant layer 24, however, since the layered structure in the conventional memory element is not The surface is complex and multi-layered, and at the same time, it is necessary to touch a specific shape layer by layer according to the function of different layer structures. Therefore, the process is quite complicated and requires high process and material costs. Based on the above-described conventional techniques, the present invention is directed to a metal element and an operating method thereof to solve the difficulties encountered by the prior art. SUMMARY OF THE INVENTION The main object of the present invention is to extract a gold-sourced navigation device and a crane method, and replace the conventional source and the immersive structure by a flat ion-implanted layer structure to reduce the MOS component. The power required to program and erase. Another object of the present invention is to provide a gold-conducting conductor element and a method of operating the same by a relatively simplified MOS structure, so that the miniaturization of the MOS semiconductor in a stack can be greatly improved. ^ I. For the purpose of the above, the tree-casting conductor component comprises a component layer, and at least one surface of the component layer is formed - ion implantation: on the ion implant layer Forming at least a structure of -, and in this case, the structure of the pole structure includes - the first one is deleted, wherein 'the butterfly body (four) self-material conductor material, or the insulating material, or the composite material, and the element layer is shot with the bottom plate The structure of the structure is presented, and there is a single layered/Ion-implanted ion-implanted layer that provides source, bungee and __, and the heart-beauty layer, 200847430. Meiji The structure 'and the more common materials are aerobic/nitrogen oxide oxides, which can be selected from polycrystalline materials or metal materials...etc. The present invention further provides a complex structure of a plurality of smoke poles formed on a layer of 70 layers of a MOS semiconductor, and a bit line and a word line formed on the gate structure are formed to form a _ Gold oxygen semiconducting
… 4 ‘ . 1、阳僻，叫吋，更由於 本發明之錢料縣身之結構亦可在此元件狀姆應兩表面上分別形 成離子植ϋ此，由本㈣之錢轉航件所構紅_結構無論 在-維或是三維的的堆疊，皆具有相當高的堆疊密度。 另外’本發明亦同時提出-種金氧半導體元件之操作方法，其係應用 於上述之錢半導件所構紅_結構輯作，其巾，此金氧半導體 陣列結構係包括複數條位元線與複數條字樣，每—位元線係透過位元接 觸窗搞接概個錄料航聽與—__接^齡元線則係 福接於複數個金氧半賴元件_贿構上，勤此些字元線以控制金氧 半導體元件的_ ’祕元崎着败缺的金氧半導體元件 内，除狀外’更複數恤元接觸t雛複數位元線，贿得麵接在 不同元件層上的金氧半導體元件得以相互祕，進而形成—三維的陣列結 構；在本Μ之錄料體元狀_方紐財，首先糊—字元線與 -位元線崎取位元線上之-金氧轉體元件；再_此字元線與位元線 以分別應偏壓’靖此偏壓傳送至被選取的金氧铸體元件^最後， 當此金氧半導體接收偏壓後’此金氧半導體係改難内部儲存層之電荷儲 200847430 -存狀態’以完成資料的程式化、抹除或是讀取的操作。 底下藉由具體實施例配合所_賦詳加_，當更容練解本發明 之目的、技術内容、_及其所達成之功效。 【實施方式】 為後供化城賴縮性更高的金氧半導體元件，本發明係提出 種金乳半^體％件及其操作紐，㈣下將詳細揭露本發明之實施態 樣，並同時佐，式來獅翻。 〜 …首先，細下的實鶴樣中，皆係以半導體材料賴朗基板型態做 為70件層的例子W進仃說明’不過，除了町所述之半導體基板外，本發 明中所使用的元件層在材料的選取更可選自於絕緣材料或是複合材料，例 如：具有重離子植人與聽子植人暖井基板、錢氧化·板等等，同 時’ 70件層的鶴則除了可以為基板的形式外，亦可為半導體結構内之任 -層狀結構，而以下所揭露的半導體基板僅制以做為酬之其中一種元 件層麵。請先參考第三_心錢為本發明之第—種錄半導體元件 之結構截面示意圖’在-P型半導體基板30上係形成—具有N型離子的離 子植入層32，此離子植入層32係為-具有單-離子種類的層狀結構，且此 離子植入層32之離子濃度高低、軒分佈...料參數係可根據+同需求以 進行調整’不過’若依據麟子植人層32所提供的魏㈣，其係可分為 N型源極區域321、N型汲極區域322以及夾設在N型源極區域321與n型 没極區域322之間的N型通道區域323，而在N型通道區域323的上方則係 形成一閘極結構34，且此閘極結構34係包括介電層與閘極層⑽4，且介電 層的結構係由隔離層341/儲存層342/隔離層343所構成。故，由於在1^型 200847430 離子植入層32内的N型源極區域32卜N型沒極區域322以及N型通道區 域323係，、有相同離子種類、相同離子濃度，當載子在此n型離子植入層 32内進订遷移時’不會因為不同離子植人之接面畴致載子在遷移時形成 一空乏層’也因此’因為沒有空乏層的形成，載子的遷移能障大幅降低， 使付施壓於此錄半導體耕綱的讎將可有效崎低，並增加載子遷 移的速率。 另外’在第四圖中係提供第二種金氧半導體元件之結構截面示意圖， 不同於第二圖之金氧半導體結構，此實施態樣中的金氧半導體元件雛的 半導體基板30’係為_，而位於此N型半導體基板3〇,上的離子植入層 32則係為P型，且此P型離子植入層32，内亦可區分為P型源極區域 321’、P型没極區域322，與p型通道區域微，，而相同地，在離子植入 層32’上係形成一閘極結構34，且此閘極結構34亦包括有介電層34卜 342、343與閘極層344。不過，無論上述第三圖或第四圖中所揭露的金氧 半導體心構，、中的閘極結構係選自浮動閘極或電荷能陷儲存間極，於此 將不進一步贅述。 由於本發明之金氧半導體元件之結構係具有較為簡單的結構，因此無 須經過繁複離子植人製程即可實現，因此，就二維方向的結構微縮性而言， 請參考第五_私本發明之第1金氧轉體元僻觸實補樣，僅 需要在- P型半導體基板3〇上先形成一 N型離子植入層犯，並在適當的位 置上形成複數_極結構34 ’即可在二維㈣上織複數個金氧半導體元 件，以形成-金氧半導體元件陣列；除此之外，請參考第六圖所示，其係 200847430 為本發明之第二種金氧半導體元件陣列的實施態樣，在此相互耦接之金氧 半導體結構巾，N型離子植人層32係自P鲜導體基板3()的侧邊延伸，且 複數個閘極結構34係形成於N型離子植入層32上。另外，請再同時參考 第五圖與第七圖所示，其中第七圖係為本發明之第三種金氧半導體元件陣 列的實施態樣，在此實施態樣帽示之金氧半導體元件陣列結構係為第五 圖所示之結構的延伸，主要的特徵係在於原本第五圖中的p型半導體基板 30的第-表面與第二表面上，分別形成第_ N型離子植人層32與第二n型 離子植入| 32 ’因此形成如本實施態樣中所示的一 p型半導體層％，失設 在第- N型離子植入層32與第二N型離子植入層32之間的金氧半導體^ 構，並且分別在第-N型離子植人層32與第二N型離子植人層％上的適 當位置處形成複數第-難結構34與第二閘極結構34，最終則形成一具有 三維方向的金氧半導體元件之結構。... 4 ' . 1, singularity, screaming, and more, due to the structure of the money material of the invention, it is also possible to form an ion implant on the surface of the elemental body, which is constructed by the money transfer device of (4) The red_structure has a relatively high stacking density whether in a dimensional or three-dimensional stack. In addition, the present invention also proposes a method for operating a MOS device, which is applied to the red-structure of the above-mentioned money semiconductor, and the MOS array structure includes a plurality of bits. Line and a plurality of words, each bit line is connected through the bit contact window to make a record and aeronautical listening and -__ connect to the age line is connected to a plurality of gold and oxygen components These dice lines are used to control the MOS device's _ 'The secret element of the MOS semiconductor component, except for the shape of the 'multiple singular element touch the t-multiple bit line, the bribe is connected The MOS devices on the different component layers are mutually secreted, thereby forming a three-dimensional array structure; in the 体 Μ 体 方 方 方 纽 纽 方 方 方 , , , , , , 糊 糊 字 字 字 字 字 字 字 字 字 字 字 字 字 字 字 字On-line-gold-oxygen rotating element; re-_this word line and bit line should be biased respectively to transmit the bias voltage to the selected gold-oxygen casting element ^ Finally, when the MOS receiving bias After 'this MOS semiconductor system changed the charge storage of the internal storage layer 200847430 - save state' to complete Stylized material, erase or read operation. The purpose of the present invention, the technical content, and the effect achieved by the present invention are further exemplified by the specific embodiment. [Embodiment] The present invention provides a gold-milk semiconductor component and an operation button thereof, and (4) will disclose the embodiment of the present invention in detail, and At the same time, the lion is turned over. ~ ... First of all, in the case of the actual crane sample, the semiconductor material is based on the substrate type of the semiconductor material, and the description is made in the description of the semiconductor substrate. However, in addition to the semiconductor substrate described in the town, the invention is used. The material layer can be selected from insulating materials or composite materials, for example, heavy ion implanted and listener implanted warm well substrates, money oxidation plates, etc., and '70-layered cranes In addition to being in the form of a substrate, it may be a layer-layer structure within the semiconductor structure, and the semiconductor substrate disclosed below is only one of the component layers. Please refer to the third _ heart money for the first part of the invention - a cross-sectional view of the structure of the semiconductor device is formed on the -P type semiconductor substrate 30 - an ion implantation layer 32 having N-type ions, the ion implantation layer The 32 series is a layered structure having a single-ion type, and the ion concentration of the ion implantation layer 32 is high and low, and the distribution of the material parameters can be adjusted according to the same requirements of the same 'but'. The Wei (four) provided by the human layer 32 can be divided into an N-type source region 321, an N-type drain region 322, and an N-type channel interposed between the N-type source region 321 and the n-type gate region 322. A gate structure 34 is formed over the N-type channel region 323, and the gate structure 34 includes a dielectric layer and a gate layer (10) 4, and the structure of the dielectric layer is provided by the isolation layer 341/ The storage layer 342 / the isolation layer 343 is formed. Therefore, since the N-type source region 32 in the ion implant layer 32 of the 1^ type 200847430 is in the N-type non-polar region 322 and the N-type channel region 323, the same ion species and the same ion concentration are present, when the carrier is at In the n-type ion implantation layer 32, when the migration is carried out, 'there is no formation of a depletion layer when the carrier is migrated due to different ion implantation.' Therefore, because there is no formation of a depletion layer, the migration of the carrier The energy barrier is greatly reduced, so that the pressure on the semiconductor farming platform can be effectively reduced and the rate of carrier migration can be increased. In addition, in the fourth figure, a schematic cross-sectional view of a second MOS device is provided, which is different from the MOS structure of the second embodiment. The semiconductor substrate 30' of the MOS device in this embodiment is _, the ion implantation layer 32 on the N-type semiconductor substrate 3 is P-type, and the P-type ion implantation layer 32 can be further divided into a P-type source region 321 ', P-type The gate region 322 is formed with a gate structure 34 on the ion implantation layer 32', and the gate structure 34 also includes a dielectric layer 34, 342, 343. And gate layer 344. However, regardless of the oxynitride core structure disclosed in the above third or fourth embodiment, the gate structure is selected from the floating gate or the charge energy storage junction, and will not be further described herein. Since the structure of the MOS device of the present invention has a relatively simple structure, it can be realized without a complicated ion implantation process. Therefore, in terms of structural miniaturization in a two-dimensional direction, please refer to the fifth invention. The first gold-oxygen-converting element is required to form an N-type ion implantation layer on the -P-type semiconductor substrate 3, and form a complex-pole structure 34' at an appropriate position. A plurality of MOS devices can be woven on the two-dimensional (four) to form an array of MOS devices; in addition, please refer to the sixth figure, which is 200847430, which is the second MOS device of the present invention. In an embodiment of the array, the gold-oxygen semiconductor structure sheets coupled to each other, the N-type ion implant layer 32 extends from the side of the P fresh conductor substrate 3 (), and the plurality of gate structures 34 are formed in the N The type of ion implant layer 32. In addition, please refer to the fifth and seventh figures at the same time, wherein the seventh figure is an implementation of the third MOS device array of the present invention, and the MOS device of the embodiment is shown. The array structure is an extension of the structure shown in FIG. 5, and the main feature is that the first-surface and the second surface of the p-type semiconductor substrate 30 in the fifth FIG. 32 and the second n-type ion implantation | 32 ' thus forming a p-type semiconductor layer % as shown in this embodiment, missing in the -N-type ion implantation layer 32 and the second N-type ion implantation a MOS structure between the layers 32, and forming a plurality of the first-difficult structure 34 and the second gate at appropriate positions on the first-N-type ion implant layer 32 and the second N-type ion implant layer Structure 34 ultimately forms a structure having a MOS element in a three dimensional direction.
惟’上述之所有實施態獅皆以P型半導體基板、p型半導體層、與NHowever, all of the above-mentioned implementations have a P-type semiconductor substrate, a p-type semiconductor layer, and N.
型離子植人層為例純’獨此躺構树翻於_半導體基板、N 型半導體層、與P型離子植入層之金氧半導體元件，或是利用絕緣基板、 絕緣層、複合餘、複合層辑代上述的财轉縣板卿成之金氧半 導體元件，亦皆為本發明所涵蓋之範圍。 再請參考第八圖卿，其係為本發明之具有三維方_金氧半導體 列之示意圖，在此金氧半導體陣列3中，係包括複數條位元線犯，複數 位元接觸純〗’概條元線__ 421，概悔歸開關仙 複數源極線接觸窗442，複數條源極線(We une)撕由於源極線4〇 200847430 位於位元線42的下方，m & 文於本圖中係以虛線表示源極線40)與複數條字元 線46子兀線46係形成於二維方向上，其中，源極線接觸窗秘在三維方 〇 並且不同70件層之源極線接觸窗442係輕接該耕層之源 極線k擇開關则，而源極線4()係透過此些源極線接觸窗祕以與不同元 件層之源極線k擇開關4〇1輕接，且利用此些源極線選擇開關·以再麵 ;不同兀件層的金氧半導體疋件綱。而位元接觸窗私丨在三維方向上相 搞接並且不同疋件層之位元接觸窗441係輕接該元件層之位元線選擇 開關42卜並且對於同—元件層之位元線選擇開關似而言，其係與此元件 層上的所有金氧铸體元件咖耗接，並且此些位元接觸請在最上層 7件層上職與位元線42進_接。而字元線4_捕數個金氧半 V體7L件300透過閘極結構以相互耗接所形成者，且由於此些金氧半導體 元件獅之結構係可如上述所提供之任一實施態樣中所示的半導體結構， 故於此將不再讀述；社叙錄半導航件_ 3之齡方法的流程 係則如第九®所示，而其中的金氧半導體元件結構難如第三騎示，因 此，首先在步驟S10中’在此金氧半導體元件陣列3中，先開啟雛於此 些金氧半導體元件咖與相對應之位元線上42的位元線選擇開_，同 時’亦開啟與此些位元線42相對應之源極線4〇所搞接的源極線選擇開關 4〇1 ’在步驟S12中，則係透過一字元線46、源極線4〇以選取至少一位元 線42上之一金氧半導體元件·在步驟su中，藉由被選定的字元線站、 源極線4G與位元線42以分別傳送一偏壓至被選定的金氧半導體元件咖 内；在步驟S16中’當金氧半導體元件3〇〇接收此偏觀，係改變其内部 12 200847430 相對應之儲存層342之電荷儲存狀態 ，以更改金氧半導體元件300内儲存 層342之記憶内容。 而在上述的操作方法中，係依據施用不同的偏壓可以決定金氧半導體 内健存層之不同的記憶行為，例如：當金氧半導體進行程式化的操作時， 輸入之偏壓係可使得電子/電洞自金氧半賴狀離子植人層巾的通道區 域進入至齡層’並使得與之對應之位元線自1(或0)改㈣Q(或丨）狀態， 而電子/電洞機之機侧會依據不_元件層的種_有所獨，當元件 層為p型半導體材料時，電子/電洞的移動機制可為閘極或通道區域富爾諾 罕穿随法(Fowler Nordheim Tunneling，即Tunneling)、基板熱洞注入法 (Substrate Hot Hole injecti〇n，SHH injecti〇n)、帶對帶熱電子注入法 (Band-To-Band Hot Electron injection，BTBHE inject ion)之其中之- 個方法，而當耕層為N型半導體材料時，電子/電洞的移動機制則可為閑 極或通道區域富爾諾罕穿隧法、基板熱電子注入法（驗触此 Electron injection > SHE injection) ^ t^,^^(Band_T〇_BandThe type of ion implanted layer is purely 'individually lying on the _ semiconductor substrate, the N-type semiconductor layer, the MOS device with the P-type ion implantation layer, or the insulating substrate, the insulating layer, the composite residue, The composite layer is also included in the scope of the present invention. Referring again to the eighth figure, which is a schematic diagram of the three-dimensional square-metal oxide semiconductor column of the present invention, in which the MOS array 3 includes a plurality of bit line sins, and the complex bits contact the pure 〗 The general line __ 421, the return to the switch complex source line contact window 442, the plurality of source lines (We une) tear because the source line 4 〇 200847430 is located below the bit line 42, m & In the figure, the source line 40) and the plurality of word lines 46 are formed in a two-dimensional direction, wherein the source line contact window is in a three-dimensional manner and different in 70 layers. The source line contact window 442 is lightly connected to the source line of the plough layer, and the source line 4() is connected to the source line of the different component layers through the source line contact window. 4〇1 is lightly connected, and the source line selection switch is used to re-face; the metal oxide semiconductor component of different element layers. The bit contact window is connected in the three-dimensional direction and the bit contact window 441 of the different element layers is lightly connected to the bit line selection switch 42 of the element layer and the bit line selection for the same-element layer The switch is similar to all the gold-oxygen casting components on the component layer, and these bit contacts should be connected to the bit line 42 on the uppermost 7-layer. And the word line 4_ captures a plurality of gold oxide half V body 7L pieces 300 through the gate structure to form a mutual contact, and since the structure of the MOS device lion can be implemented as described above The semiconductor structure shown in the aspect, so it will not be read here; the flow chart of the method of semi-navigation _ 3 age is as shown in the ninth, and the structure of the MOS device is difficult. Third riding, therefore, first, in step S10, in the MOS device array 3, the bit line selection of the MOS devices and the corresponding bit line 42 is first turned on, At the same time, the source line selection switch 4〇1' connected to the source line 4 corresponding to the bit lines 42 is also turned on. In step S12, the word line 46 and the source line 4 are transmitted through the word line 46. 〇 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取In the MOS device, in step S16, 'when the MOS device 3 〇〇 receives this bias, the system changes 12200847430 therein corresponding to the storage layer 342 of charge storage state, to change the contents of the memory MOS storage layer 342 of the element 300. In the above operation method, different memory behaviors of the MOS layer can be determined according to different bias voltages applied, for example, when the MOS semiconductor is programmed, the input bias voltage can make The electron/hole from the channel region of the gold-oxygen-half-like ion implanted layer towel enters the ageing layer' and causes the corresponding bit line to change from 1 (or 0) to (four) Q (or 丨) state, and electronic/electrical The machine side of the hole machine will be different depending on the type of the component layer. When the component layer is a p-type semiconductor material, the movement mechanism of the electron/hole can be the Furano or the channel region. Fowler Nordheim Tunneling (Tunneling), Substrate Hot Hole injecti〇n (SHH injecti〇n), Band-To-Band Hot Electron Injection (BTBHE inject ion) a method, and when the plough layer is an N-type semiconductor material, the movement mechanism of the electron/hole can be a Furano channel tunneling method or a substrate hot electron injection method in the idle or channel region (the Electron injection is touched) > SHE injection) ^ t^,^^(Band_T _Band
Hot Hole injection，圆injecti〇n);當金氧半導體進行抹除的操作 時，輸入之偏壓係可使得電子/電洞自金氧半導體内之儲存層中遷移出，並 透過離子植人射騎道區軸離開錢铸體，趣得與之龍之位元 線自0改魏1狀態’相同地，電子/電洞的移動機制亦會受到不同的元件 層材料而有抑’當元件層的材料為”铸騎料時，電子/電洞的移動 機制則亦為閘極或通道區域富爾諾罕穿隧法、美板熱電〜、、、、^ 熱電子注入法，而當元件層材料為N型半導吐& 干¥體材枓時，電子/電洞的移動機 200847430 制則亦為閘極或通道區域富爾諾罕穿隧法、基板熱電子注入法、帶對帶熱 電洞注入法；而當金氧半導體進行讀取的操作時，若元件層中的離子植入 層為N型離子，_取_電流為電子赫，反之，若元件射的離子植 入層為P型離子，則讀取到的電流係為電洞電流。 且為了確保每-個電子/電洞的傳遞過程皆完整地完成，在上述的所有 操作模式巾’當偏壓完全輸人金氧半導體之後，皆可再增加—_的流程， 以確保金氧半導體之記憶狀態是否完成。Hot hole injection, round injecti〇n); when the MOS is erased, the input bias can cause the electron/hole to migrate out of the storage layer in the MOS and pass through the ion implant The axis of the riding area leaves the money casting body, and the bit line of the dragon is the same as that of the dragon. The movement mechanism of the electron/hole is also subject to different component layer materials. The material is "when the material is cast, the movement mechanism of the electron/hole is also the Furano channel tunneling method of the gate or channel region, the thermoelectric injection method of the US plate thermoelectric ~, ,, ^, and when the component layer When the material is N-type semi-conductive spit & dry material, the electron/hole mobile device 200847430 is also a Furano channel tunneling method in the gate or channel region, substrate hot electron injection method, and tape-to-belt Thermal hole injection method; when the gold oxide semiconductor performs the reading operation, if the ion implantation layer in the device layer is an N-type ion, the _current is an electron Hz, and if the ion implantation layer of the device is For P-type ions, the current read is the hole current. And to ensure every electricity. The sub/hole transfer process is completely completed. In all the above operation modes, the process can be further increased after the bias voltage is completely input to the MOS device to ensure the memory state of the MOS semiconductor is completed. .
综合上述可知，本發明之金氧半導體元件及其操作方法係可藉由簡化 的金氧半導體結構錢行載子_移，且由於在祕區域、汲極區域與通 ^、n有電性上的差異’因此載子在遷料可避免因為電性逆轉 肖耗的此里’啊’更藉此以制降賊子遷移時所需的鱗，不但可 以有效提高金氧半導__效率，也可以使得金氧半導體在進行程式 化、抹除或是讀取之操作時職耗的能量得以下降。 =上____轉㈣娜，其目的姆習該技術者 此，、、本發明之内容並據以實施限定本發明之專利範圍，故，凡其 恤，編含 所述之申請專利範圍中。 【圖式簡單說明】 第一圖為習知的金氧半導體元件結構之截面示意圖。 =圖為另1知的金氧半導體树結構之截面示意圖。 第一圖為本發明之第一種 第四圖為本翻狀結顯面示意圖。 金氧半導體元件之結構截面示意圖。 200847430 第五圖為本發明之第—種金氧半導體元件陣列的實施態樣。 第六圖為本發明之第二種金 复虱+導體元件陣列的實施態樣。 第七圖為本發明之第三種錄铸體元件陣觸實施態樣。 弟八圖為本發明之具有3:雜 々、 維方向的金氧半導體陣列之示意圖 弟九圖為本發明之金氧半導體元 【主要元件符號說明】 10基板 102源極 12閘極介電層 141反轉層 20基板 22半導體層 24重植入層 26儲存散介電層 300金氧半導體元件 30 P型半導體基板 321 N型源極區域 323 N型通道區域 341隔離層 343隔離層 30’ N型半導體基板 321’ P型源極區域 件陣列之操作方法的流程圖。 101通道 104汲極 14閘極層 21導電層 23淺植入層 25導電層 32 N型離子植入層 322 N型汲極區域 34閘極結構 342儲存層 344閘極層 32’ P型離子植入層 322’ P型汲極區域 200847430 323, P型通道區域 40 401 源極線選擇開關 42 441 位元接觸窗 442 46 字元線 3 30, P型半導體層 源極線 位元線 源極線接觸窗 金氧半導體陣列 16In summary, the MOS device of the present invention and the method of operating the same can be carried out by a simplified MOS structure, and because of the electrical properties in the secret region, the drain region, and the pass. The difference 'so the carrier can be avoided in the relocation of the material because of the electrical reversal of the 'ah', so as to reduce the scale required for the thief migration, not only can effectively improve the gold-oxygen semiconductor __ efficiency, also It can reduce the energy consumption of the MOS when it is programmed, erased or read. = ____ _ (4) Na, the purpose of the application of this technology, the content of the present invention and the implementation of the scope of the patent to limit the scope of the invention, therefore, the scope of the patent application . BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic cross-sectional view of a conventional MOS device structure. = The figure is a schematic cross-sectional view of another known MOS tree structure. The first figure is the first type of the invention. Schematic cross-section of a MOS device. 200847430 The fifth figure is an embodiment of the first type of MOS device array of the present invention. The sixth figure is an embodiment of the second gold reticle + conductor element array of the present invention. The seventh figure is a third aspect of the present invention.八八图 is a schematic diagram of a gold oxide semiconductor array having a 3: impurity and dimension direction of the present invention. The ninth diagram of the present invention is a gold oxide semiconductor element of the present invention. [Main component symbol description] 10 substrate 102 source 12 gate dielectric layer 141 inversion layer 20 substrate 22 semiconductor layer 24 re-implant layer 26 storage bulk dielectric layer 300 oxynitride device 30 P-type semiconductor substrate 321 N-type source region 323 N-type channel region 341 isolation layer 343 isolation layer 30' N Flowchart of a method of operating a P-type source region device array of a type semiconductor substrate 321'. 101 channel 104 drain 14 gate layer 21 conductive layer 23 shallow implant layer 25 conductive layer 32 N-type ion implantation layer 322 N-type drain region 34 gate structure 342 storage layer 344 gate layer 32' P-type ion implant Incoming layer 322' P-type drain region 200847430 323, P-type channel region 40 401 source line selection switch 42 441 bit contact window 442 46 word line 3 30, P-type semiconductor layer source line bit line source line Contact window MOS array 16