TW200845542A - Power switch circuit - Google Patents

Abstract

A power switch circuit comprises a level shift, a first inverter, a second inverter and an output circuit. The level shift outputs a first output signal and a second output signal according to a control signal. The first inverter outputs a first inverse output signal according to the first output signal, and the second inverter outputs a second inverse output signal according to the second output signal, wherein the first inverse output signal and the second inverse output signal are non-overlap. The output circuit selectively outputs a first voltage level or a second voltage level according to the first inverse output signal and the second inverse output signal.

Description

200845542

达达编号号: TW3681PA IX. Description of the Invention: [Technical Field] The present invention relates to a power supply switching circuit, and more particularly to a power supply switching circuit for reducing transient current and power consumption. [Prior Art] Please refer to FIG. 1 , which is a conventional power switching circuit. The conventional ^ power switching circuit 10 includes a level shifter n〇 (Level Shift) and an output circuit 120. The level shifter no outputs the output signal N0 and the output signal N1 according to the control signal VSS-SEL, and the output circuit 12 determines that its output voltage is equal to the voltage level Nv% or the voltage level GND according to the output signal N0 and the output number N1. / Further, the level shifter 110 further includes p-type transistors ML 〇, P. The control transistor of the type transistor ML, the N-type transistor ML2, the N-type transistor ML3, and the inverter ILOcp-type transistor ML〇 is coupled to the input terminal of the inverter il〇, and the P-type transistor ML1 The control end is coupled to the output of the inverter IL〇. The first ends of the P-type transistor ML0 and the P-type transistor ML1 receive the voltage level VDD, and the second ends of the N-type transistor ML2 and the N-type transistor ML3 receive the voltage level NVSS. The second ends of the P-type transistor ML0 and the p-type transistor ML1 are respectively coupled to the first ends of the N-type transistor ML2 and the N-type transistor ML3, and the ^-type transistor ML2 and the N-type transistor ML3 The control ends are respectively coupled to the second ends of the p-type transistor ML1 and the p-type transistor ml. The output circuit 120 further includes a pull-up transistor MPU and a pull-down transistor 5 200845542

• Sanda number: TW3681PA MPD. The first ends of the pull-up transistor MPU and the pull-down transistor MpD respectively receive the voltage level NVSS and the voltage level GND, and pull up the transistor _ and pull-down, and the control ends of the crystal MPD are respectively coupled to the p-type transistor The second end of the red 〇 and p-type transistor ML1 is to selectively output a voltage level NVSS or a voltage level GND. Please refer to FIG. 2, which is a waveform of a conventional power switching circuit.

Figure. For example, the voltage level VDD is equal to 2.5V and the voltage level NVSS is equal to -7V. When the control signal VSS-SEL is changed from 2·5V, the output signal NO is changed from -7V to 2·5ν, and the output signal is changed from 2 5V to -7V' so that the voltage level of the output circuit 12〇 output is determined by — Change to 0V 〇 Conversely 'When the control signal VSS-SEL is changed from 0V to 2.5V, the output signal NO is changed from 2. 5V to -7V, and the output signal N1 is changed from -7V to 2.5V" so that the output circuit 12 The voltage level of the output is changed by -7V. However, because the output signal NO and the output signal N1 are partially overlapped, the pull-up transistor mpu and the pull-down transistor MPD are simultaneously enabled at part time, such as 54. And 73ns. While the current n (MPU) flows through the pull-up transistor MPU, the current n (MPD) also flows through the pull-down transistor MPD. In other words, the transient current (Transient Current) will flow through the pull-up transistor MPU and pull-down transistor MPD, resulting in an increase in the power consumption of the conventional power supply switching circuit 10. 200845542

The invention relates to a power switching circuit. The level shifter is coupled to the output circuit via the first inverter and the second inverter to provide an output circuit that does not overlap each other. a first inverted output signal and a second inverted output signal. In this way, the generation of transient current (Transient Current) is avoided and the power consumption of the power switching circuit is reduced. According to the present invention, a power supply switching circuit is proposed. The power switching circuit includes a level shifter, a first inverter, a second inverter, and an output circuit. • The level shifter outputs a first output signal and a second output signal based on a control signal. The first inverter outputs a first inverted output signal according to the first output signal, and the second inverter outputs a second inverted output signal according to the second output signal. The first inverted output signal and the second inverted output signal do not overlap each other. The output circuit selectively outputs the first voltage level or the second voltage level according to the first inverted output signal and the second inverted output signal. In order to make the above-mentioned contents of the present invention more comprehensible, the following is a detailed description of the preferred embodiment, and the following description is given in detail: [Embodiment] Please refer to FIG. 3, which is shown as A block diagram of a power switching circuit in accordance with a preferred embodiment of the present invention. The power switching circuit 30 includes a level shifter 310 (Level Shift), an output circuit 320, an inverter 330, and an inverter 340. The level shifter 310 outputs the output signal N4 to the inverter 330 in accordance with the control signal LSEL, and outputs the output signal N5 to the inverter 340 in accordance with the control signal v_SEL. 200845542

Sanda number: TW3681PA Inverters 330 and 340 are, for example, Complementary Metal-Oxide-Semiconductor (CMOS) inverters. The inverters 330 and 340 receive the output signals N4 and N5, respectively, and invert the output signals N4 and N5 to output the non-overlapping inverted output signals N6 and N7 to the output circuit 320, respectively. The output circuit 320 receives the first inverted output signal N6 and the second inverted output signal N7, and selectively outputs the voltage level VI or the voltage level V2 according to the first inverted output signal N6 and the second inverted output signal N7. . Since the sinusoidal output "5 Tiger N 6 and N 7 are not mutually exclusive, the generation of transient current (Transient Current) can be avoided, thereby reducing the power consumption of the power switching circuit 30. Further, the power switching circuit 30 can be, for example, a positive power switching circuit or a negative power switching circuit. If the power switching circuit 30 is a positive power switching circuit, the voltage level VI and the voltage level V2 are greater than 〇. Conversely, if the power supply switching circuit 30 is a negative power supply switching circuit, the voltage level VI and the voltage level V2 are less than or equal to zero.

Please refer to FIG. 4, which is a circuit diagram showing a positive power switching circuit. The positive power supply switching circuit 40 includes a level shifter 410, an output circuit 420, an inverter ΙΒ0, and an inverter IB1. The level shifter 410 outputs output signals N8 and N9 in accordance with the control signal VCC_SEL. Inverters ΙΒ0 and IB1 invert the output signals N8 and N9 and output inverted output signals N10 and Nil, and the inverted output signals N10 and Nil do not overlap each other (Non-Overlap). The output circuit 420 determines the output voltage VCC equal to the voltage level VPP or the voltage level VDD according to the inverted output signals N10 and Nil, and the voltage level VPP 8 200845542

5伏。 The TW3681PA is, for example, 10V, and the voltage level VDD is, for example, 2. 5V. The level shifter 410 further includes a p-type transistor ML0, a P-type transistor ML1, an N-type transistor ML2, an N-type transistor ML3, and an inverter IL〇i-type transistor ML2. The input terminal of the phase il il is coupled to the output terminal of the inverter IL0. The first end of the p-type turtle as body ML0 and the P-type transistor ml 1 receives the voltage level VPP' and the second end of the N-type transistor ML2 and the N-type transistor ML3 receives the voltage level G·. The second end of the P-type transistor ML1, the first end of the N-type transistor ML3, the control end of the P-type transistor ML0 are coupled to the wheel end of the inverter IB0, and the second end of the P-type transistor ML0 The first end of the N-type transistor ML2 and the control end of the p-type transistor ML1 are coupled to the input end of the inverter IB1. The output circuit 420 further includes a pull-up transistor MPU and a pull-down transistor MPD' wherein the 'pull-up transistor mpu and the pull-down transistor mpd are, for example, p-type transistors. The first end of the pull-up transistor MPU and the pull-down transistor MPD _ receive the voltage level VPP and the voltage level VDD, and the control terminals of the pull-up transistor MPU and the pull-down transistor MPD are respectively coupled to the inversion IB〇 and the output of the inverted phase. When the pull-up transistor is enabled, the voltage level VPP is output through the second end of the pull-up transistor MPU. Conversely, when the pull-down transistor MPD is enabled, the voltage level VDD is rotated by the other end of the pull-down transistor MPD. Referring to Fig. 5, there is shown a detailed circuit diagram of the inverters ΙΒ0 and IB1 of Fig. 4. The inverters IB and IM are respectively composed of a P-type transistor ML4 and an N-type transistor ML5, respectively. P-type electric crystal 9 200845542

Ξ, ΜΜΜ : The first end of the TW3681PA body ML4 receives the voltage level VPP, and the second end of the 电-type transistor ML5 receives the voltage level G·. The second end of the p-type transistor ML4 is coupled to the first end of the 电-type transistor ML5, and the control end of the 电-type transistor ML4 is coupled to the control end of the 电-type transistor ML5. The conductive parameter ρ of the ρ-type transistor ML4 is larger than the conductive parameter of the ν-type transistor ML5. The conductive parameter of the cold rP-type transistor ML4 (eight, and the conductive parameter of the N-type transistor 齓5 (where =(|) gossip (I) is the i-degree length ratio of 10 electric bodies, ~ is the hole mobility rate; & is the electron mobility; G is the oxide layer capacitance of the soap area. The field ¥ package parameter 10,000 is greater than the conduction parameter That is, the output voltage rise speed is greater than the fall speed. As a result, the principle of first turn-off and turn-on will cause the inversion, and the inverted output signals N1〇 and N11 of IB0 and IB1 are not overlapped with each other. In the first place, the transient current of the current supply switching circuit 40 is reduced when the pull-up transistor Mpu and the pull-down transistor MPD are simultaneously turned on, thereby reducing the power consumption of the positive power switching circuit 40. The figure is a waveform diagram of a positive power switching circuit. For example, the voltage level VDD is equal to 2·5 ν, and the voltage level vpp is equal to 10 V. When the control signal VCC_SEL is changed from 2. 5 V to 〇 v After that, the output signal N8 is changed from 0V to 10V, and the second round of the signal N9 is changed from rain to ν. The inverted output signal has just changed from 10v to 〇v, and the inverted output signal m纟0V is changed to 10V, so that the output voltage VCC of the wheel-out circuit is changed from 10V to 2. 5V. Conversely, when the control signal VCC- SEL changed from Gv to 2 n 200845542

Sanda number: TW3081PA output "is number N8 changed from 10V to 0V' and the second output signal Ng changed from ον to 10V. The inverted output number Ν10 is changed from ιον to ιον, and the inverted output js number Nil is changed from 10V to 0V' so that the output voltage VCC of the turn-off circuit 420 is changed from 2.5V to 10V. Since the inverted output signals N10 and Nil do not overlap (Non-Overlap), the pull-up transistor MPU and the pull-down transistor MPD are not simultaneously enabled. Therefore, the transient current (Transient Current) is not generated while flowing through the pull-up transistor MPU and the pull-down transistor mpd, and the power consumption of the positive power switching circuit 40 is reduced. Please refer to the figure of brother 7, which is the circuit diagram of the negative power switching circuit. The negative power supply switching circuit 70 includes a level shifter 71 〇, an output circuit 720, an inverter IB0, and an inverter IB1. The level shifter 710 outputs output signals N12 and N13 in accordance with the control VSS_SEL. The inverters ΙΒ0 and iBi respectively invert the output ##N12 and N13, and output the inverted output signals N14 and N15 of the non-overlap. The output circuit 720 _ selectively outputs the voltage level NVSS or the voltage level GND according to the inverted output signals N14 and M. The voltage level NVSS is, for example, -7V, and the voltage level GND is, for example, 0V. The level shifter 710 further includes a p-type transistor ml, a P-type transistor, an N-type transistor ML2, an N-type transistor ML3, and an inverter IL0. The control terminal of the p-type transistor ML0 is coupled to the input terminal of the inverter iL, and the control terminal of the transistor ML1 is coupled to the output terminal of the inverter iL. The first end of the p-type transistor ML0 and the P-type transistor MU receives the voltage level VDD, and the voltage level VDD is, for example, 2. 5v, and the N-type transistor ML2 and n 11 200845542 Sanda number: TW3681PA type transistor The second end of the ML3 receives the voltage level MSS. The second end of the P-type transistor ML1, the first end of the N-type transistor muscle 3, and the control system of the N-type transistor ML2 are lightly connected to the input terminal of the inverter, IB〇,

The second end of the P-type transistor ML0, the first end of the N-type transistor 2, and the control end of the N-type transistor ML3 are coupled to the wheel-in end of the inverter Ιβ1. The output circuit 720 further includes a pull-up transistor MPU and a pull-down transistor MPD', wherein the pull-up transistor MPU and the pull-down transistor MPD are, for example, Ν

Type transistor. The second end of the pull-up transistor MPU and the pull-down transistor MPD respectively receive the voltage level SS and the voltage level GND, and the pull-up transistor and the control terminal of the pull-down transistor MPD are respectively connected to the inversion phase. The outputs of IB1 and (10). When the pull-up transistor MPU is enabled, the voltage level is pulled up by the first end of the private body. Conversely, when the pull-down transistor MPD is enabled, the voltage level VSS is output through the first terminal of the pull-down transistor MPD. Referring to Fig. 8, there is shown a detailed circuit diagram of the inverters IB and IB1 of Fig. 7. The inverter j and the Ιβ1 are respectively composed of a P t electric B body ML6 and an N type transistor ML7, respectively. The first end of the p-type transistor ML6 receives the voltage level VDD, and the second end of the N-type transistor ML7 receives the voltage level NVSS. The second end of the p-type transistor is coupled to the first end of the N-type transistor ML7, and the control end of the p-type transistor ML6 is coupled to the control end of the N-type transistor ML7. The conductivity parameter of the N-type transistor M L 7 is greater than the conductivity parameter of the conductivity parameter U-type transistor ML6 of the p-type transistor M L 6 , and the conduction parameter of the N-type transistor ML7 (!) team. Among them, today) for electricity 12 200845542

Sanda number: TW3681PA The width to length ratio of the crystal; ~ is the hole mobility; eight is the electron mobility; C is the oxide capacitance per unit area. When the conduction parameter is greater than the conduction parameter, that is, the wheel voltage drop rate is greater than the rise speed, the inverted output signals Ν14 and Ν15 of the inverters ΙΒ0 and Ιβ1 outputs are not overlapped with each other (〇verlap). In this way, under the principle of first turning off and then turning on, the transient current (Transient _ Current) generated when the pull-up transistor Mpu and the pull-down transistor MPD are simultaneously turned on will be avoided, thereby reducing the power consumption of the negative power switching circuit. . Please refer to Fig. 9, which is a waveform diagram of a negative power switching circuit. For example, the voltage level VDD is equal to 2.5V and the voltage level NVSS is equal to -7V. When the control signal VSS-SEL is changed from 2.5¥ to (^, the output signal N12 is changed from -7V to 2.5V, and the output signal N13 is changed from 2. 5V to -7V. The inverted output signal N14 is changed by 2·5V. It is -7V, and the inverted output signal N15 is changed from -7V to 2.5V, so that the output voltage VSS of the output circuit 720 is changed from 0V to -1^. • Conversely, when the control signal VSS-SEL is changed from 0V to 2 After 5ν, the output signal Ν12 is changed from 2·5V to -7V, and the output signal Ν13 is changed from -7V to 2·5V. The inverted output signal Ν14 is changed from -7V to 2. 5V, and the inverted output signal Ν15 is 2·5V is changed to -7V, so that the output voltage VSS of the output circuit 720 is changed from -7V to 0V. Since the inverted output signals Ν14 and Ν15 do not overlap (Non-Overlap), the pull-up transistor 1?11 and pull The power-down crystal|〇^ will not be simultaneously enabled, so it will not generate transient current (Transient Current) while flowing through the pull-up transistor MPU and pull-down transistor MPD, into 13 200845542

The third wire number: TW3081PA reduces the power consumption of the negative power switching circuit 70. . The power switching circuit disclosed in the above embodiments of the present invention utilizes the inverted output signal of the inverted phase two output so that the pull-up transistor and the pull-down transistor are not simultaneously enabled. Therefore, it will generate Transient Current while flowing through the pull-up transistor and pull-down the transistor, thereby reducing the power consumption of the power switching circuit. The present invention has been described above with reference to a preferred embodiment, and is not intended to limit the invention. Those skilled in the art having the knowledge of the present invention can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 14 200845542

Sanda number: TW3081PA [Simple description of the diagram] Figure 1 shows the traditional power switching circuit. Figure 2 is a waveform diagram showing a conventional power switching circuit. Figure 3 is a block diagram of a power switching circuit in accordance with a preferred embodiment of the present invention. Figure 4 is a circuit diagram showing a positive power switching circuit. Fig. 5 is a detailed circuit diagram showing the inverters IB0 and IB1 of Fig. 4. ® Figure 6 shows the waveform of the positive power switching circuit. Figure 7 is not a circuit diagram of the negative power switching circuit. Fig. 8 is a detailed circuit diagram showing the inverters IB0 and IB1 of Fig. 7. Figure 9 is a waveform diagram showing a negative power switching circuit. 15 200845542

Sanda number: TW3681PA [Description of main component symbols] 10: Conventional power switching circuit 30 · Power switching circuit 40 according to a preferred embodiment of the present invention: Positive power switching circuit 70: Negative power switching circuit 110, 310, 410, 710 : level shifters 120, 320, 420, 720: output circuits ML0, ML1, ML4, ML6 · P-type transistors - ML2, ML3, ML5, ML7 · N-type transistors 330, 340, IL0, ΙΒ0 IB1: Inverter MPU: Pull-down transistor MPD: Pull-up transistor VSS-SEL, VCC-SEL, V-SEL: Control signals NO, N1, Μ, N5, N8, N9, N12, N13: Output signal Ν2, Ν3, Ν6, Ν7, Ν10, Ν11, Ν14, Ν15: Inverted output signal • VSS, VCC: output voltage

Il (MPD), Il (MPU), I2 (MPD), I2 (MPU), I3 (MPD), I3 (MPU): Current VDD, NVSS, GND, V Bu V2, VPP: Voltage Level

Claims (1)

200845542 三达号·· TW3681PA X. Patent application scope: 1. A power switching circuit comprising: a level shifter (Level Shift) for outputting a first output signal and a second output according to a control signal a first inverter for outputting a first inverted output signal according to the first output signal; a second inverter for outputting a second inverted output signal according to the second output signal, The first inverted output signal and the second inverted output signal are not overlapped with each other; an output circuit for selectively selecting the first inverted output signal and the second inverted output signal according to the first inverted output signal A first voltage level or a second voltage level is output. 2. The power switching circuit of claim 1, wherein the first inverter comprises: a first P-type transistor having a first conductive parameter; and a first N-type transistor The first P-type transistor is coupled to the first P-type transistor, and has a second conductive parameter, the first conductive parameter being different from the second conductive parameter. 3. The power switching circuit of claim 2, wherein the first conductive parameter is greater than the second conductive parameter when the first voltage level or the second voltage level is greater than zero. 4. The power switching circuit of claim 2, wherein the second conductive parameter is greater than the first conductive parameter when the first voltage level or the second voltage level is less than or equal to zero. 17 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The type of transistor is coupled to the second p-type transistor and has a fourth conductive parameter, the third conductive parameter being different from the fourth conductive parameter. [6] The power switching circuit of claim 5, wherein when the first electronic level or the second voltage level is greater than zero, the third book conductive parameter is greater than the fourth conductive parameter. The power switching circuit of claim 5, wherein the fourth conductive parameter is greater than the third conductive parameter when the first voltage level or the second voltage level is less than or equal to zero. 8. The power switching circuit of claim 1, wherein the inverter is a Complementary Meta-Oxide-Semiconductor (CMOS) inverter. _9. The power switching circuit according to claim 1, wherein the second inverter is a complementary metal-oxide semiconductor inverter (Complementary Metal-Oxide- Semiconductor Inverter). The power switching circuit of claim 1, wherein the output circuit comprises a pull-up transistor and a pull-down transistor, wherein the pull-up transistor and the pull-down transistor are respectively The first inverted output k number and the second inverted output signal selectively output the first voltage level or the second voltage level. 18 200845542 三达号·' TW3681PA Please refer to the electric W-changing circuit described in item 1G of the patent scope, where the pull-up transistor and the drop-off transistor ^^路, as in the patent application scope item u: two pull The control terminal of the power-down crystal is: the pressure level is 'when the pull-down transistor is enabled, the first two rounds of the output end, when the second end of the body is output. "% 准系系hydroxyl pull down crystal 13. As claimed in the scope of the patent, wherein the first end of the pull-up transistor is used to receive the second circuit, the control end of the body is connected to the first Two: Phase: The second end of the body is output. The early system < the pull-up electric crystal 14. As claimed in the patent range > wherein the pull-up transistor and the rail-drop transistor change circuit, 15 · _ patent range of the 14th item of the pull-down transistor The second end of the circuit is purely the first circuit, and the control terminal of the pull-down transistor is coupled to the first reverse phase crying: = level 'when the pull-down transistor is enabled, 兮m °. The end of the wheel, the first end of the body output. The younger brother-subordinate system is subjected to the pull-down electron cell 16. As claimed in claim 14, the second end of the riser crystal is used to receive the second 'electricity: t:: the control end of the book crystal is light Connected to the second inverter, when the pull-up transistor is enabled, the second terminal is outputted by the second end of the body. +%% of the lifted crystals 19